2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
57 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
60 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
61 * @dwc: pointer to our context structure
62 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
64 * Caller should take care of locking. This function will
65 * return 0 on success or -EINVAL if wrong Test Selector
68 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
72 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
73 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
87 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
93 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
94 * @dwc: pointer to our context structure
95 * @state: the state to put link into
97 * Caller should take care of locking. This function will
98 * return 0 on success or -EINVAL.
100 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
105 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
106 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
108 /* set requested state */
109 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
110 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
112 /* wait for a change in DSTS */
114 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
116 /* in HS, means ON */
117 if (DWC3_DSTS_USBLNKST(reg
) == state
)
123 dev_vdbg(dwc
->dev
, "link state change request timed out\n");
128 void dwc3_map_buffer_to_dma(struct dwc3_request
*req
)
130 struct dwc3
*dwc
= req
->dep
->dwc
;
132 if (req
->request
.length
== 0) {
133 /* req->request.dma = dwc->setup_buf_addr; */
137 if (req
->request
.num_sgs
) {
140 mapped
= dma_map_sg(dwc
->dev
, req
->request
.sg
,
141 req
->request
.num_sgs
,
142 req
->direction
? DMA_TO_DEVICE
145 dev_err(dwc
->dev
, "failed to map SGs\n");
149 req
->request
.num_mapped_sgs
= mapped
;
153 if (req
->request
.dma
== DMA_ADDR_INVALID
) {
154 req
->request
.dma
= dma_map_single(dwc
->dev
, req
->request
.buf
,
155 req
->request
.length
, req
->direction
156 ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
161 void dwc3_unmap_buffer_from_dma(struct dwc3_request
*req
)
163 struct dwc3
*dwc
= req
->dep
->dwc
;
165 if (req
->request
.length
== 0) {
166 req
->request
.dma
= DMA_ADDR_INVALID
;
170 if (req
->request
.num_mapped_sgs
) {
171 req
->request
.dma
= DMA_ADDR_INVALID
;
172 dma_unmap_sg(dwc
->dev
, req
->request
.sg
,
173 req
->request
.num_mapped_sgs
,
174 req
->direction
? DMA_TO_DEVICE
177 req
->request
.num_mapped_sgs
= 0;
182 dma_unmap_single(dwc
->dev
, req
->request
.dma
,
183 req
->request
.length
, req
->direction
184 ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
186 req
->request
.dma
= DMA_ADDR_INVALID
;
190 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
193 struct dwc3
*dwc
= dep
->dwc
;
196 if (req
->request
.num_mapped_sgs
)
197 dep
->busy_slot
+= req
->request
.num_mapped_sgs
;
202 * Skip LINK TRB. We can't use req->trb and check for
203 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
204 * completed (not the LINK TRB).
206 if (((dep
->busy_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
207 usb_endpoint_xfer_isoc(dep
->desc
))
210 list_del(&req
->list
);
213 if (req
->request
.status
== -EINPROGRESS
)
214 req
->request
.status
= status
;
216 dwc3_unmap_buffer_from_dma(req
);
218 dev_dbg(dwc
->dev
, "request %p from %s completed %d/%d ===> %d\n",
219 req
, dep
->name
, req
->request
.actual
,
220 req
->request
.length
, status
);
222 spin_unlock(&dwc
->lock
);
223 req
->request
.complete(&req
->dep
->endpoint
, &req
->request
);
224 spin_lock(&dwc
->lock
);
227 static const char *dwc3_gadget_ep_cmd_string(u8 cmd
)
230 case DWC3_DEPCMD_DEPSTARTCFG
:
231 return "Start New Configuration";
232 case DWC3_DEPCMD_ENDTRANSFER
:
233 return "End Transfer";
234 case DWC3_DEPCMD_UPDATETRANSFER
:
235 return "Update Transfer";
236 case DWC3_DEPCMD_STARTTRANSFER
:
237 return "Start Transfer";
238 case DWC3_DEPCMD_CLEARSTALL
:
239 return "Clear Stall";
240 case DWC3_DEPCMD_SETSTALL
:
242 case DWC3_DEPCMD_GETSEQNUMBER
:
243 return "Get Data Sequence Number";
244 case DWC3_DEPCMD_SETTRANSFRESOURCE
:
245 return "Set Endpoint Transfer Resource";
246 case DWC3_DEPCMD_SETEPCONFIG
:
247 return "Set Endpoint Configuration";
249 return "UNKNOWN command";
253 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
254 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
256 struct dwc3_ep
*dep
= dwc
->eps
[ep
];
260 dev_vdbg(dwc
->dev
, "%s: cmd '%s' params %08x %08x %08x\n",
262 dwc3_gadget_ep_cmd_string(cmd
), params
->param0
,
263 params
->param1
, params
->param2
);
265 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
266 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
267 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
269 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
271 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
272 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
273 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
274 DWC3_DEPCMD_STATUS(reg
));
279 * We can't sleep here, because it is also called from
290 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
291 struct dwc3_trb_hw
*trb
)
293 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
295 return dep
->trb_pool_dma
+ offset
;
298 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
300 struct dwc3
*dwc
= dep
->dwc
;
305 if (dep
->number
== 0 || dep
->number
== 1)
308 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
309 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
310 &dep
->trb_pool_dma
, GFP_KERNEL
);
311 if (!dep
->trb_pool
) {
312 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
320 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
322 struct dwc3
*dwc
= dep
->dwc
;
324 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
325 dep
->trb_pool
, dep
->trb_pool_dma
);
327 dep
->trb_pool
= NULL
;
328 dep
->trb_pool_dma
= 0;
331 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
333 struct dwc3_gadget_ep_cmd_params params
;
336 memset(¶ms
, 0x00, sizeof(params
));
338 if (dep
->number
!= 1) {
339 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
340 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
341 if (dep
->number
> 1) {
342 if (dwc
->start_config_issued
)
344 dwc
->start_config_issued
= true;
345 cmd
|= DWC3_DEPCMD_PARAM(2);
348 return dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
354 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
355 const struct usb_endpoint_descriptor
*desc
,
356 const struct usb_ss_ep_comp_descriptor
*comp_desc
)
358 struct dwc3_gadget_ep_cmd_params params
;
360 memset(¶ms
, 0x00, sizeof(params
));
362 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
363 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
))
364 | DWC3_DEPCFG_BURST_SIZE(dep
->endpoint
.maxburst
);
366 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
367 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
369 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
370 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
371 | DWC3_DEPCFG_STREAM_EVENT_EN
;
372 dep
->stream_capable
= true;
375 if (usb_endpoint_xfer_isoc(desc
))
376 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
379 * We are doing 1:1 mapping for endpoints, meaning
380 * Physical Endpoints 2 maps to Logical Endpoint 2 and
381 * so on. We consider the direction bit as part of the physical
382 * endpoint number. So USB endpoint 0x81 is 0x03.
384 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
387 * We must use the lower 16 TX FIFOs even though
391 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
393 if (desc
->bInterval
) {
394 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
395 dep
->interval
= 1 << (desc
->bInterval
- 1);
398 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
399 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
402 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
404 struct dwc3_gadget_ep_cmd_params params
;
406 memset(¶ms
, 0x00, sizeof(params
));
408 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
410 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
411 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
415 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
416 * @dep: endpoint to be initialized
417 * @desc: USB Endpoint Descriptor
419 * Caller should take care of locking
421 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
422 const struct usb_endpoint_descriptor
*desc
,
423 const struct usb_ss_ep_comp_descriptor
*comp_desc
)
425 struct dwc3
*dwc
= dep
->dwc
;
429 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
430 ret
= dwc3_gadget_start_config(dwc
, dep
);
435 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
);
439 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
440 struct dwc3_trb_hw
*trb_st_hw
;
441 struct dwc3_trb_hw
*trb_link_hw
;
442 struct dwc3_trb trb_link
;
444 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
449 dep
->comp_desc
= comp_desc
;
450 dep
->type
= usb_endpoint_type(desc
);
451 dep
->flags
|= DWC3_EP_ENABLED
;
453 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
454 reg
|= DWC3_DALEPENA_EP(dep
->number
);
455 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
457 if (!usb_endpoint_xfer_isoc(desc
))
460 memset(&trb_link
, 0, sizeof(trb_link
));
462 /* Link TRB for ISOC. The HWO but is never reset */
463 trb_st_hw
= &dep
->trb_pool
[0];
465 trb_link
.bplh
= dwc3_trb_dma_offset(dep
, trb_st_hw
);
466 trb_link
.trbctl
= DWC3_TRBCTL_LINK_TRB
;
469 trb_link_hw
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
470 dwc3_trb_to_hw(&trb_link
, trb_link_hw
);
476 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
);
477 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
479 struct dwc3_request
*req
;
481 if (!list_empty(&dep
->req_queued
))
482 dwc3_stop_active_transfer(dwc
, dep
->number
);
484 while (!list_empty(&dep
->request_list
)) {
485 req
= next_request(&dep
->request_list
);
487 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
492 * __dwc3_gadget_ep_disable - Disables a HW endpoint
493 * @dep: the endpoint to disable
495 * This function also removes requests which are currently processed ny the
496 * hardware and those which are not yet scheduled.
497 * Caller should take care of locking.
499 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
501 struct dwc3
*dwc
= dep
->dwc
;
504 dwc3_remove_requests(dwc
, dep
);
506 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
507 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
508 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
510 dep
->stream_capable
= false;
512 dep
->comp_desc
= NULL
;
519 /* -------------------------------------------------------------------------- */
521 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
522 const struct usb_endpoint_descriptor
*desc
)
527 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
532 /* -------------------------------------------------------------------------- */
534 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
535 const struct usb_endpoint_descriptor
*desc
)
542 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
543 pr_debug("dwc3: invalid parameters\n");
547 if (!desc
->wMaxPacketSize
) {
548 pr_debug("dwc3: missing wMaxPacketSize\n");
552 dep
= to_dwc3_ep(ep
);
555 switch (usb_endpoint_type(desc
)) {
556 case USB_ENDPOINT_XFER_CONTROL
:
557 strncat(dep
->name
, "-control", sizeof(dep
->name
));
559 case USB_ENDPOINT_XFER_ISOC
:
560 strncat(dep
->name
, "-isoc", sizeof(dep
->name
));
562 case USB_ENDPOINT_XFER_BULK
:
563 strncat(dep
->name
, "-bulk", sizeof(dep
->name
));
565 case USB_ENDPOINT_XFER_INT
:
566 strncat(dep
->name
, "-int", sizeof(dep
->name
));
569 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
572 if (dep
->flags
& DWC3_EP_ENABLED
) {
573 dev_WARN_ONCE(dwc
->dev
, true, "%s is already enabled\n",
578 dev_vdbg(dwc
->dev
, "Enabling %s\n", dep
->name
);
580 spin_lock_irqsave(&dwc
->lock
, flags
);
581 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
);
582 spin_unlock_irqrestore(&dwc
->lock
, flags
);
587 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
595 pr_debug("dwc3: invalid parameters\n");
599 dep
= to_dwc3_ep(ep
);
602 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
603 dev_WARN_ONCE(dwc
->dev
, true, "%s is already disabled\n",
608 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
610 (dep
->number
& 1) ? "in" : "out");
612 spin_lock_irqsave(&dwc
->lock
, flags
);
613 ret
= __dwc3_gadget_ep_disable(dep
);
614 spin_unlock_irqrestore(&dwc
->lock
, flags
);
619 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
622 struct dwc3_request
*req
;
623 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
624 struct dwc3
*dwc
= dep
->dwc
;
626 req
= kzalloc(sizeof(*req
), gfp_flags
);
628 dev_err(dwc
->dev
, "not enough memory\n");
632 req
->epnum
= dep
->number
;
634 req
->request
.dma
= DMA_ADDR_INVALID
;
636 return &req
->request
;
639 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
640 struct usb_request
*request
)
642 struct dwc3_request
*req
= to_dwc3_request(request
);
648 * dwc3_prepare_one_trb - setup one TRB from one request
649 * @dep: endpoint for which this request is prepared
650 * @req: dwc3_request pointer
652 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
653 struct dwc3_request
*req
, dma_addr_t dma
,
654 unsigned length
, unsigned last
, unsigned chain
)
656 struct dwc3
*dwc
= dep
->dwc
;
657 struct dwc3_trb_hw
*trb_hw
;
660 unsigned int cur_slot
;
662 dev_vdbg(dwc
->dev
, "%s: req %p dma %08llx length %d%s%s\n",
663 dep
->name
, req
, (unsigned long long) dma
,
664 length
, last
? " last" : "",
665 chain
? " chain" : "");
667 trb_hw
= &dep
->trb_pool
[dep
->free_slot
& DWC3_TRB_MASK
];
668 cur_slot
= dep
->free_slot
;
671 /* Skip the LINK-TRB on ISOC */
672 if (((cur_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
673 usb_endpoint_xfer_isoc(dep
->desc
))
676 memset(&trb
, 0, sizeof(trb
));
678 dwc3_gadget_move_request_queued(req
);
680 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb_hw
);
683 if (usb_endpoint_xfer_isoc(dep
->desc
)) {
691 if (usb_endpoint_xfer_bulk(dep
->desc
) && dep
->stream_capable
)
692 trb
.sid_sofn
= req
->request
.stream_id
;
694 switch (usb_endpoint_type(dep
->desc
)) {
695 case USB_ENDPOINT_XFER_CONTROL
:
696 trb
.trbctl
= DWC3_TRBCTL_CONTROL_SETUP
;
699 case USB_ENDPOINT_XFER_ISOC
:
700 trb
.trbctl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
702 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
703 if (!(cur_slot
% (DWC3_TRB_NUM
/ 4)))
707 case USB_ENDPOINT_XFER_BULK
:
708 case USB_ENDPOINT_XFER_INT
:
709 trb
.trbctl
= DWC3_TRBCTL_NORMAL
;
713 * This is only possible with faulty memory because we
714 * checked it already :)
723 dwc3_trb_to_hw(&trb
, trb_hw
);
727 * dwc3_prepare_trbs - setup TRBs from requests
728 * @dep: endpoint for which requests are being prepared
729 * @starting: true if the endpoint is idle and no requests are queued.
731 * The functions goes through the requests list and setups TRBs for the
732 * transfers. The functions returns once there are not more TRBs available or
733 * it run out of requests.
735 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
737 struct dwc3_request
*req
, *n
;
739 unsigned int last_one
= 0;
741 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
743 /* the first request must not be queued */
744 trbs_left
= (dep
->busy_slot
- dep
->free_slot
) & DWC3_TRB_MASK
;
747 * if busy & slot are equal than it is either full or empty. If we are
748 * starting to proceed requests then we are empty. Otherwise we ar
749 * full and don't do anything
754 trbs_left
= DWC3_TRB_NUM
;
756 * In case we start from scratch, we queue the ISOC requests
757 * starting from slot 1. This is done because we use ring
758 * buffer and have no LST bit to stop us. Instead, we place
759 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
760 * after the first request so we start at slot 1 and have
761 * 7 requests proceed before we hit the first IOC.
762 * Other transfer types don't use the ring buffer and are
763 * processed from the first TRB until the last one. Since we
764 * don't wrap around we have to start at the beginning.
766 if (usb_endpoint_xfer_isoc(dep
->desc
)) {
775 /* The last TRB is a link TRB, not used for xfer */
776 if ((trbs_left
<= 1) && usb_endpoint_xfer_isoc(dep
->desc
))
779 list_for_each_entry_safe(req
, n
, &dep
->request_list
, list
) {
783 if (req
->request
.num_mapped_sgs
> 0) {
784 struct usb_request
*request
= &req
->request
;
785 struct scatterlist
*sg
= request
->sg
;
786 struct scatterlist
*s
;
789 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
790 unsigned chain
= true;
792 length
= sg_dma_len(s
);
793 dma
= sg_dma_address(s
);
795 if (i
== (request
->num_mapped_sgs
- 1)
808 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
815 dma
= req
->request
.dma
;
816 length
= req
->request
.length
;
822 /* Is this the last request? */
823 if (list_is_last(&req
->list
, &dep
->request_list
))
826 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
835 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
838 struct dwc3_gadget_ep_cmd_params params
;
839 struct dwc3_request
*req
;
840 struct dwc3
*dwc
= dep
->dwc
;
844 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
845 dev_vdbg(dwc
->dev
, "%s: endpoint busy\n", dep
->name
);
848 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
851 * If we are getting here after a short-out-packet we don't enqueue any
852 * new requests as we try to set the IOC bit only on the last request.
855 if (list_empty(&dep
->req_queued
))
856 dwc3_prepare_trbs(dep
, start_new
);
858 /* req points to the first request which will be sent */
859 req
= next_request(&dep
->req_queued
);
861 dwc3_prepare_trbs(dep
, start_new
);
864 * req points to the first request where HWO changed
867 req
= next_request(&dep
->req_queued
);
870 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
874 memset(¶ms
, 0, sizeof(params
));
875 params
.param0
= upper_32_bits(req
->trb_dma
);
876 params
.param1
= lower_32_bits(req
->trb_dma
);
879 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
881 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
883 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
884 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
886 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
889 * FIXME we need to iterate over the list of requests
890 * here and stop, unmap, free and del each of the linked
891 * requests instead of we do now.
893 dwc3_unmap_buffer_from_dma(req
);
894 list_del(&req
->list
);
898 dep
->flags
|= DWC3_EP_BUSY
;
899 dep
->res_trans_idx
= dwc3_gadget_ep_get_transfer_index(dwc
,
902 WARN_ON_ONCE(!dep
->res_trans_idx
);
907 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
909 req
->request
.actual
= 0;
910 req
->request
.status
= -EINPROGRESS
;
911 req
->direction
= dep
->direction
;
912 req
->epnum
= dep
->number
;
915 * We only add to our list of requests now and
916 * start consuming the list once we get XferNotReady
919 * That way, we avoid doing anything that we don't need
920 * to do now and defer it until the point we receive a
921 * particular token from the Host side.
923 * This will also avoid Host cancelling URBs due to too
926 dwc3_map_buffer_to_dma(req
);
927 list_add_tail(&req
->list
, &dep
->request_list
);
930 * There is one special case: XferNotReady with
931 * empty list of requests. We need to kick the
932 * transfer here in that situation, otherwise
933 * we will be NAKing forever.
935 * If we get XferNotReady before gadget driver
936 * has a chance to queue a request, we will ACK
937 * the IRQ but won't be able to receive the data
938 * until the next request is queued. The following
939 * code is handling exactly that.
941 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
946 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
947 dep
->flags
& DWC3_EP_BUSY
)
950 ret
= __dwc3_gadget_kick_transfer(dep
, 0, start_trans
);
951 if (ret
&& ret
!= -EBUSY
) {
952 struct dwc3
*dwc
= dep
->dwc
;
954 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
962 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
965 struct dwc3_request
*req
= to_dwc3_request(request
);
966 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
967 struct dwc3
*dwc
= dep
->dwc
;
974 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
979 dev_vdbg(dwc
->dev
, "queing request %p to %s length %d\n",
980 request
, ep
->name
, request
->length
);
982 spin_lock_irqsave(&dwc
->lock
, flags
);
983 ret
= __dwc3_gadget_ep_queue(dep
, req
);
984 spin_unlock_irqrestore(&dwc
->lock
, flags
);
989 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
990 struct usb_request
*request
)
992 struct dwc3_request
*req
= to_dwc3_request(request
);
993 struct dwc3_request
*r
= NULL
;
995 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
996 struct dwc3
*dwc
= dep
->dwc
;
1001 spin_lock_irqsave(&dwc
->lock
, flags
);
1003 list_for_each_entry(r
, &dep
->request_list
, list
) {
1009 list_for_each_entry(r
, &dep
->req_queued
, list
) {
1014 /* wait until it is processed */
1015 dwc3_stop_active_transfer(dwc
, dep
->number
);
1018 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1024 /* giveback the request */
1025 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1028 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1033 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
)
1035 struct dwc3_gadget_ep_cmd_params params
;
1036 struct dwc3
*dwc
= dep
->dwc
;
1039 memset(¶ms
, 0x00, sizeof(params
));
1042 if (dep
->number
== 0 || dep
->number
== 1) {
1044 * Whenever EP0 is stalled, we will restart
1045 * the state machine, thus moving back to
1048 dwc
->ep0state
= EP0_SETUP_PHASE
;
1051 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1052 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1054 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1055 value
? "set" : "clear",
1058 dep
->flags
|= DWC3_EP_STALL
;
1060 if (dep
->flags
& DWC3_EP_WEDGE
)
1063 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1064 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1066 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1067 value
? "set" : "clear",
1070 dep
->flags
&= ~DWC3_EP_STALL
;
1076 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1078 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1079 struct dwc3
*dwc
= dep
->dwc
;
1081 unsigned long flags
;
1085 spin_lock_irqsave(&dwc
->lock
, flags
);
1087 if (usb_endpoint_xfer_isoc(dep
->desc
)) {
1088 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1093 ret
= __dwc3_gadget_ep_set_halt(dep
, value
);
1095 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1100 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1102 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1104 dep
->flags
|= DWC3_EP_WEDGE
;
1106 return dwc3_gadget_ep_set_halt(ep
, 1);
1109 /* -------------------------------------------------------------------------- */
1111 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1112 .bLength
= USB_DT_ENDPOINT_SIZE
,
1113 .bDescriptorType
= USB_DT_ENDPOINT
,
1114 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1117 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1118 .enable
= dwc3_gadget_ep0_enable
,
1119 .disable
= dwc3_gadget_ep0_disable
,
1120 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1121 .free_request
= dwc3_gadget_ep_free_request
,
1122 .queue
= dwc3_gadget_ep0_queue
,
1123 .dequeue
= dwc3_gadget_ep_dequeue
,
1124 .set_halt
= dwc3_gadget_ep_set_halt
,
1125 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1128 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1129 .enable
= dwc3_gadget_ep_enable
,
1130 .disable
= dwc3_gadget_ep_disable
,
1131 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1132 .free_request
= dwc3_gadget_ep_free_request
,
1133 .queue
= dwc3_gadget_ep_queue
,
1134 .dequeue
= dwc3_gadget_ep_dequeue
,
1135 .set_halt
= dwc3_gadget_ep_set_halt
,
1136 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1139 /* -------------------------------------------------------------------------- */
1141 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1143 struct dwc3
*dwc
= gadget_to_dwc(g
);
1146 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1147 return DWC3_DSTS_SOFFN(reg
);
1150 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1152 struct dwc3
*dwc
= gadget_to_dwc(g
);
1154 unsigned long timeout
;
1155 unsigned long flags
;
1164 spin_lock_irqsave(&dwc
->lock
, flags
);
1167 * According to the Databook Remote wakeup request should
1168 * be issued only when the device is in early suspend state.
1170 * We can check that via USB Link State bits in DSTS register.
1172 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1174 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1175 if (speed
== DWC3_DSTS_SUPERSPEED
) {
1176 dev_dbg(dwc
->dev
, "no wakeup on SuperSpeed\n");
1181 link_state
= DWC3_DSTS_USBLNKST(reg
);
1183 switch (link_state
) {
1184 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1185 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1188 dev_dbg(dwc
->dev
, "can't wakeup from link state %d\n",
1194 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1196 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1200 /* write zeroes to Link Change Request */
1201 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1202 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1204 /* pool until Link State change to ON */
1205 timeout
= jiffies
+ msecs_to_jiffies(100);
1207 while (!(time_after(jiffies
, timeout
))) {
1208 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1210 /* in HS, means ON */
1211 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1215 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1216 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1221 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1226 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1229 struct dwc3
*dwc
= gadget_to_dwc(g
);
1231 dwc
->is_selfpowered
= !!is_selfpowered
;
1236 static void dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
)
1241 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1243 reg
|= DWC3_DCTL_RUN_STOP
;
1245 reg
&= ~DWC3_DCTL_RUN_STOP
;
1247 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1250 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1252 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1255 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1264 dev_vdbg(dwc
->dev
, "gadget %s data soft-%s\n",
1266 ? dwc
->gadget_driver
->function
: "no-function",
1267 is_on
? "connect" : "disconnect");
1270 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1272 struct dwc3
*dwc
= gadget_to_dwc(g
);
1273 unsigned long flags
;
1277 spin_lock_irqsave(&dwc
->lock
, flags
);
1278 dwc3_gadget_run_stop(dwc
, is_on
);
1279 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1284 static int dwc3_gadget_start(struct usb_gadget
*g
,
1285 struct usb_gadget_driver
*driver
)
1287 struct dwc3
*dwc
= gadget_to_dwc(g
);
1288 struct dwc3_ep
*dep
;
1289 unsigned long flags
;
1293 spin_lock_irqsave(&dwc
->lock
, flags
);
1295 if (dwc
->gadget_driver
) {
1296 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1298 dwc
->gadget_driver
->driver
.name
);
1303 dwc
->gadget_driver
= driver
;
1304 dwc
->gadget
.dev
.driver
= &driver
->driver
;
1306 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1307 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1308 reg
|= dwc
->maximum_speed
;
1309 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1311 dwc
->start_config_issued
= false;
1313 /* Start with SuperSpeed Default */
1314 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1317 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
1319 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1324 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
1326 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1330 /* begin to receive SETUP packets */
1331 dwc
->ep0state
= EP0_SETUP_PHASE
;
1332 dwc3_ep0_out_start(dwc
);
1334 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1339 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1342 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1347 static int dwc3_gadget_stop(struct usb_gadget
*g
,
1348 struct usb_gadget_driver
*driver
)
1350 struct dwc3
*dwc
= gadget_to_dwc(g
);
1351 unsigned long flags
;
1353 spin_lock_irqsave(&dwc
->lock
, flags
);
1355 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1356 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1358 dwc
->gadget_driver
= NULL
;
1359 dwc
->gadget
.dev
.driver
= NULL
;
1361 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1365 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1366 .get_frame
= dwc3_gadget_get_frame
,
1367 .wakeup
= dwc3_gadget_wakeup
,
1368 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1369 .pullup
= dwc3_gadget_pullup
,
1370 .udc_start
= dwc3_gadget_start
,
1371 .udc_stop
= dwc3_gadget_stop
,
1374 /* -------------------------------------------------------------------------- */
1376 static int __devinit
dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1378 struct dwc3_ep
*dep
;
1381 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1383 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1384 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1386 dev_err(dwc
->dev
, "can't allocate endpoint %d\n",
1392 dep
->number
= epnum
;
1393 dwc
->eps
[epnum
] = dep
;
1395 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1396 (epnum
& 1) ? "in" : "out");
1397 dep
->endpoint
.name
= dep
->name
;
1398 dep
->direction
= (epnum
& 1);
1400 if (epnum
== 0 || epnum
== 1) {
1401 dep
->endpoint
.maxpacket
= 512;
1402 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1404 dwc
->gadget
.ep0
= &dep
->endpoint
;
1408 dep
->endpoint
.maxpacket
= 1024;
1409 dep
->endpoint
.max_streams
= 15;
1410 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1411 list_add_tail(&dep
->endpoint
.ep_list
,
1412 &dwc
->gadget
.ep_list
);
1414 ret
= dwc3_alloc_trb_pool(dep
);
1419 INIT_LIST_HEAD(&dep
->request_list
);
1420 INIT_LIST_HEAD(&dep
->req_queued
);
1426 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1428 struct dwc3_ep
*dep
;
1431 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1432 dep
= dwc
->eps
[epnum
];
1433 dwc3_free_trb_pool(dep
);
1435 if (epnum
!= 0 && epnum
!= 1)
1436 list_del(&dep
->endpoint
.ep_list
);
1442 static void dwc3_gadget_release(struct device
*dev
)
1444 dev_dbg(dev
, "%s\n", __func__
);
1447 /* -------------------------------------------------------------------------- */
1448 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1449 const struct dwc3_event_depevt
*event
, int status
)
1451 struct dwc3_request
*req
;
1452 struct dwc3_trb trb
;
1454 unsigned int s_pkt
= 0;
1457 req
= next_request(&dep
->req_queued
);
1463 dwc3_trb_to_nat(req
->trb
, &trb
);
1465 if (trb
.hwo
&& status
!= -ESHUTDOWN
)
1467 * We continue despite the error. There is not much we
1468 * can do. If we don't clean in up we loop for ever. If
1469 * we skip the TRB than it gets overwritten reused after
1470 * a while since we use them in a ring buffer. a BUG()
1471 * would help. Lets hope that if this occures, someone
1472 * fixes the root cause instead of looking away :)
1474 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1475 dep
->name
, req
->trb
);
1478 if (dep
->direction
) {
1480 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1482 status
= -ECONNRESET
;
1485 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1490 * We assume here we will always receive the entire data block
1491 * which we should receive. Meaning, if we program RX to
1492 * receive 4K but we receive only 2K, we assume that's all we
1493 * should receive and we simply bounce the request back to the
1494 * gadget driver for further processing.
1496 req
->request
.actual
+= req
->request
.length
- count
;
1497 dwc3_gadget_giveback(dep
, req
, status
);
1500 if ((event
->status
& DEPEVT_STATUS_LST
) && trb
.lst
)
1502 if ((event
->status
& DEPEVT_STATUS_IOC
) && trb
.ioc
)
1506 if ((event
->status
& DEPEVT_STATUS_IOC
) && trb
.ioc
)
1511 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
1512 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
,
1515 unsigned status
= 0;
1518 if (event
->status
& DEPEVT_STATUS_BUSERR
)
1519 status
= -ECONNRESET
;
1521 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
1523 dep
->flags
&= ~DWC3_EP_BUSY
;
1524 dep
->res_trans_idx
= 0;
1528 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1529 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1531 if (dwc
->revision
< DWC3_REVISION_183A
) {
1535 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
1536 struct dwc3_ep
*dep
= dwc
->eps
[i
];
1538 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1541 if (!list_empty(&dep
->req_queued
))
1545 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1547 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1553 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1554 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1558 if (list_empty(&dep
->request_list
)) {
1559 dev_vdbg(dwc
->dev
, "ISOC ep %s run out for requests.\n",
1564 if (event
->parameters
) {
1567 mask
= ~(dep
->interval
- 1);
1568 uf
= event
->parameters
& mask
;
1569 /* 4 micro frames in the future */
1570 uf
+= dep
->interval
* 4;
1575 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
1578 static void dwc3_process_ep_cmd_complete(struct dwc3_ep
*dep
,
1579 const struct dwc3_event_depevt
*event
)
1581 struct dwc3
*dwc
= dep
->dwc
;
1582 struct dwc3_event_depevt mod_ev
= *event
;
1585 * We were asked to remove one requests. It is possible that this
1586 * request and a few other were started together and have the same
1587 * transfer index. Since we stopped the complete endpoint we don't
1588 * know how many requests were already completed (and not yet)
1589 * reported and how could be done (later). We purge them all until
1590 * the end of the list.
1592 mod_ev
.status
= DEPEVT_STATUS_LST
;
1593 dwc3_cleanup_done_reqs(dwc
, dep
, &mod_ev
, -ESHUTDOWN
);
1594 dep
->flags
&= ~DWC3_EP_BUSY
;
1595 /* pending requets are ignored and are queued on XferNotReady */
1598 static void dwc3_ep_cmd_compl(struct dwc3_ep
*dep
,
1599 const struct dwc3_event_depevt
*event
)
1601 u32 param
= event
->parameters
;
1602 u32 cmd_type
= (param
>> 8) & ((1 << 5) - 1);
1605 case DWC3_DEPCMD_ENDTRANSFER
:
1606 dwc3_process_ep_cmd_complete(dep
, event
);
1608 case DWC3_DEPCMD_STARTTRANSFER
:
1609 dep
->res_trans_idx
= param
& 0x7f;
1612 printk(KERN_ERR
"%s() unknown /unexpected type: %d\n",
1613 __func__
, cmd_type
);
1618 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
1619 const struct dwc3_event_depevt
*event
)
1621 struct dwc3_ep
*dep
;
1622 u8 epnum
= event
->endpoint_number
;
1624 dep
= dwc
->eps
[epnum
];
1626 dev_vdbg(dwc
->dev
, "%s: %s\n", dep
->name
,
1627 dwc3_ep_event_string(event
->endpoint_event
));
1629 if (epnum
== 0 || epnum
== 1) {
1630 dwc3_ep0_interrupt(dwc
, event
);
1634 switch (event
->endpoint_event
) {
1635 case DWC3_DEPEVT_XFERCOMPLETE
:
1636 if (usb_endpoint_xfer_isoc(dep
->desc
)) {
1637 dev_dbg(dwc
->dev
, "%s is an Isochronous endpoint\n",
1642 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 1);
1644 case DWC3_DEPEVT_XFERINPROGRESS
:
1645 if (!usb_endpoint_xfer_isoc(dep
->desc
)) {
1646 dev_dbg(dwc
->dev
, "%s is not an Isochronous endpoint\n",
1651 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 0);
1653 case DWC3_DEPEVT_XFERNOTREADY
:
1654 if (usb_endpoint_xfer_isoc(dep
->desc
)) {
1655 dwc3_gadget_start_isoc(dwc
, dep
, event
);
1659 dev_vdbg(dwc
->dev
, "%s: reason %s\n",
1660 dep
->name
, event
->status
1662 : "Transfer Not Active");
1664 ret
= __dwc3_gadget_kick_transfer(dep
, 0, 1);
1665 if (!ret
|| ret
== -EBUSY
)
1668 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1673 case DWC3_DEPEVT_STREAMEVT
:
1674 if (!usb_endpoint_xfer_bulk(dep
->desc
)) {
1675 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
1680 switch (event
->status
) {
1681 case DEPEVT_STREAMEVT_FOUND
:
1682 dev_vdbg(dwc
->dev
, "Stream %d found and started\n",
1686 case DEPEVT_STREAMEVT_NOTFOUND
:
1689 dev_dbg(dwc
->dev
, "Couldn't find suitable stream\n");
1692 case DWC3_DEPEVT_RXTXFIFOEVT
:
1693 dev_dbg(dwc
->dev
, "%s FIFO Overrun\n", dep
->name
);
1695 case DWC3_DEPEVT_EPCMDCMPLT
:
1696 dwc3_ep_cmd_compl(dep
, event
);
1701 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
1703 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
1704 spin_unlock(&dwc
->lock
);
1705 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
1706 spin_lock(&dwc
->lock
);
1710 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
)
1712 struct dwc3_ep
*dep
;
1713 struct dwc3_gadget_ep_cmd_params params
;
1717 dep
= dwc
->eps
[epnum
];
1719 WARN_ON(!dep
->res_trans_idx
);
1720 if (dep
->res_trans_idx
) {
1721 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1722 cmd
|= DWC3_DEPCMD_HIPRI_FORCERM
| DWC3_DEPCMD_CMDIOC
;
1723 cmd
|= DWC3_DEPCMD_PARAM(dep
->res_trans_idx
);
1724 memset(¶ms
, 0, sizeof(params
));
1725 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1727 dep
->res_trans_idx
= 0;
1731 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
1735 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1736 struct dwc3_ep
*dep
;
1738 dep
= dwc
->eps
[epnum
];
1739 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1742 dwc3_remove_requests(dwc
, dep
);
1746 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
1750 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1751 struct dwc3_ep
*dep
;
1752 struct dwc3_gadget_ep_cmd_params params
;
1755 dep
= dwc
->eps
[epnum
];
1757 if (!(dep
->flags
& DWC3_EP_STALL
))
1760 dep
->flags
&= ~DWC3_EP_STALL
;
1762 memset(¶ms
, 0, sizeof(params
));
1763 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1764 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1769 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
1771 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1774 U1
/U2 is powersave optimization
. Skip it
for now
. Anyway we need to
1775 enable it before we can disable it
.
1777 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1778 reg
&= ~DWC3_DCTL_INITU1ENA
;
1779 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1781 reg
&= ~DWC3_DCTL_INITU2ENA
;
1782 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1785 dwc3_stop_active_transfers(dwc
);
1786 dwc3_disconnect_gadget(dwc
);
1787 dwc
->start_config_issued
= false;
1789 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1790 dwc
->setup_packet_pending
= false;
1793 static void dwc3_gadget_usb3_phy_power(struct dwc3
*dwc
, int on
)
1797 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
1800 reg
&= ~DWC3_GUSB3PIPECTL_SUSPHY
;
1802 reg
|= DWC3_GUSB3PIPECTL_SUSPHY
;
1804 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
1807 static void dwc3_gadget_usb2_phy_power(struct dwc3
*dwc
, int on
)
1811 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
1814 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
1816 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
1818 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
1821 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
1825 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1828 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1829 * would cause a missing Disconnect Event if there's a
1830 * pending Setup Packet in the FIFO.
1832 * There's no suggested workaround on the official Bug
1833 * report, which states that "unless the driver/application
1834 * is doing any special handling of a disconnect event,
1835 * there is no functional issue".
1837 * Unfortunately, it turns out that we _do_ some special
1838 * handling of a disconnect event, namely complete all
1839 * pending transfers, notify gadget driver of the
1840 * disconnection, and so on.
1842 * Our suggested workaround is to follow the Disconnect
1843 * Event steps here, instead, based on a setup_packet_pending
1844 * flag. Such flag gets set whenever we have a XferNotReady
1845 * event on EP0 and gets cleared on XferComplete for the
1850 * STAR#9000466709: RTL: Device : Disconnect event not
1851 * generated if setup packet pending in FIFO
1853 if (dwc
->revision
< DWC3_REVISION_188A
) {
1854 if (dwc
->setup_packet_pending
)
1855 dwc3_gadget_disconnect_interrupt(dwc
);
1858 /* after reset -> Default State */
1859 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
1862 dwc3_gadget_usb2_phy_power(dwc
, true);
1863 dwc3_gadget_usb3_phy_power(dwc
, true);
1865 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
)
1866 dwc3_disconnect_gadget(dwc
);
1868 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1869 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
1870 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1872 dwc3_stop_active_transfers(dwc
);
1873 dwc3_clear_stall_all_ep(dwc
);
1874 dwc
->start_config_issued
= false;
1876 /* Reset device address to zero */
1877 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1878 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
1879 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1882 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
1885 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
1888 * We change the clock only at SS but I dunno why I would want to do
1889 * this. Maybe it becomes part of the power saving plan.
1892 if (speed
!= DWC3_DSTS_SUPERSPEED
)
1896 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1897 * each time on Connect Done.
1902 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
1903 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
1904 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
1907 static void dwc3_gadget_disable_phy(struct dwc3
*dwc
, u8 speed
)
1910 case USB_SPEED_SUPER
:
1911 dwc3_gadget_usb2_phy_power(dwc
, false);
1913 case USB_SPEED_HIGH
:
1914 case USB_SPEED_FULL
:
1916 dwc3_gadget_usb3_phy_power(dwc
, false);
1921 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
1923 struct dwc3_gadget_ep_cmd_params params
;
1924 struct dwc3_ep
*dep
;
1929 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1931 memset(¶ms
, 0x00, sizeof(params
));
1933 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1934 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1937 dwc3_update_ram_clk_sel(dwc
, speed
);
1940 case DWC3_DCFG_SUPERSPEED
:
1942 * WORKAROUND: DWC3 revisions <1.90a have an issue which
1943 * would cause a missing USB3 Reset event.
1945 * In such situations, we should force a USB3 Reset
1946 * event by calling our dwc3_gadget_reset_interrupt()
1951 * STAR#9000483510: RTL: SS : USB3 reset event may
1952 * not be generated always when the link enters poll
1954 if (dwc
->revision
< DWC3_REVISION_190A
)
1955 dwc3_gadget_reset_interrupt(dwc
);
1957 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1958 dwc
->gadget
.ep0
->maxpacket
= 512;
1959 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
1961 case DWC3_DCFG_HIGHSPEED
:
1962 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
1963 dwc
->gadget
.ep0
->maxpacket
= 64;
1964 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
1966 case DWC3_DCFG_FULLSPEED2
:
1967 case DWC3_DCFG_FULLSPEED1
:
1968 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
1969 dwc
->gadget
.ep0
->maxpacket
= 64;
1970 dwc
->gadget
.speed
= USB_SPEED_FULL
;
1972 case DWC3_DCFG_LOWSPEED
:
1973 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
1974 dwc
->gadget
.ep0
->maxpacket
= 8;
1975 dwc
->gadget
.speed
= USB_SPEED_LOW
;
1979 /* Disable unneded PHY */
1980 dwc3_gadget_disable_phy(dwc
, dwc
->gadget
.speed
);
1983 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
1985 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1990 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
1992 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1997 * Configure PHY via GUSB3PIPECTLn if required.
1999 * Update GTXFIFOSIZn
2001 * In both cases reset values should be sufficient.
2005 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2007 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2010 * TODO take core out of low power mode when that's
2014 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2017 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2018 unsigned int evtinfo
)
2020 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2023 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2024 * on the link partner, the USB session might do multiple entry/exit
2025 * of low power states before a transfer takes place.
2027 * Due to this problem, we might experience lower throughput. The
2028 * suggested workaround is to disable DCTL[12:9] bits if we're
2029 * transitioning from U1/U2 to U0 and enable those bits again
2030 * after a transfer completes and there are no pending transfers
2031 * on any of the enabled endpoints.
2033 * This is the first half of that workaround.
2037 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2038 * core send LGO_Ux entering U0
2040 if (dwc
->revision
< DWC3_REVISION_183A
) {
2041 if (next
== DWC3_LINK_STATE_U0
) {
2045 switch (dwc
->link_state
) {
2046 case DWC3_LINK_STATE_U1
:
2047 case DWC3_LINK_STATE_U2
:
2048 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2049 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2050 | DWC3_DCTL_ACCEPTU2ENA
2051 | DWC3_DCTL_INITU1ENA
2052 | DWC3_DCTL_ACCEPTU1ENA
);
2055 dwc
->u1u2
= reg
& u1u2
;
2059 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2068 dwc
->link_state
= next
;
2070 dev_vdbg(dwc
->dev
, "%s link %d\n", __func__
, dwc
->link_state
);
2073 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2074 const struct dwc3_event_devt
*event
)
2076 switch (event
->type
) {
2077 case DWC3_DEVICE_EVENT_DISCONNECT
:
2078 dwc3_gadget_disconnect_interrupt(dwc
);
2080 case DWC3_DEVICE_EVENT_RESET
:
2081 dwc3_gadget_reset_interrupt(dwc
);
2083 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2084 dwc3_gadget_conndone_interrupt(dwc
);
2086 case DWC3_DEVICE_EVENT_WAKEUP
:
2087 dwc3_gadget_wakeup_interrupt(dwc
);
2089 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2090 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2092 case DWC3_DEVICE_EVENT_EOPF
:
2093 dev_vdbg(dwc
->dev
, "End of Periodic Frame\n");
2095 case DWC3_DEVICE_EVENT_SOF
:
2096 dev_vdbg(dwc
->dev
, "Start of Periodic Frame\n");
2098 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2099 dev_vdbg(dwc
->dev
, "Erratic Error\n");
2101 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2102 dev_vdbg(dwc
->dev
, "Command Complete\n");
2104 case DWC3_DEVICE_EVENT_OVERFLOW
:
2105 dev_vdbg(dwc
->dev
, "Overflow\n");
2108 dev_dbg(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2112 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2113 const union dwc3_event
*event
)
2115 /* Endpoint IRQ, handle it and return early */
2116 if (event
->type
.is_devspec
== 0) {
2118 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2121 switch (event
->type
.type
) {
2122 case DWC3_EVENT_TYPE_DEV
:
2123 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2125 /* REVISIT what to do with Carkit and I2C events ? */
2127 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2131 static irqreturn_t
dwc3_process_event_buf(struct dwc3
*dwc
, u32 buf
)
2133 struct dwc3_event_buffer
*evt
;
2137 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(buf
));
2138 count
&= DWC3_GEVNTCOUNT_MASK
;
2142 evt
= dwc
->ev_buffs
[buf
];
2146 union dwc3_event event
;
2148 memcpy(&event
.raw
, (evt
->buf
+ evt
->lpos
), sizeof(event
.raw
));
2149 dwc3_process_event_entry(dwc
, &event
);
2151 * XXX we wrap around correctly to the next entry as almost all
2152 * entries are 4 bytes in size. There is one entry which has 12
2153 * bytes which is a regular entry followed by 8 bytes data. ATM
2154 * I don't know how things are organized if were get next to the
2155 * a boundary so I worry about that once we try to handle that.
2157 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2160 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(buf
), 4);
2166 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
)
2168 struct dwc3
*dwc
= _dwc
;
2170 irqreturn_t ret
= IRQ_NONE
;
2172 spin_lock(&dwc
->lock
);
2174 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2177 status
= dwc3_process_event_buf(dwc
, i
);
2178 if (status
== IRQ_HANDLED
)
2182 spin_unlock(&dwc
->lock
);
2188 * dwc3_gadget_init - Initializes gadget related registers
2189 * @dwc: Pointer to out controller context structure
2191 * Returns 0 on success otherwise negative errno.
2193 int __devinit
dwc3_gadget_init(struct dwc3
*dwc
)
2199 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2200 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2201 if (!dwc
->ctrl_req
) {
2202 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2207 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2208 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2209 if (!dwc
->ep0_trb
) {
2210 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2215 dwc
->setup_buf
= dma_alloc_coherent(dwc
->dev
,
2216 sizeof(*dwc
->setup_buf
) * 2,
2217 &dwc
->setup_buf_addr
, GFP_KERNEL
);
2218 if (!dwc
->setup_buf
) {
2219 dev_err(dwc
->dev
, "failed to allocate setup buffer\n");
2224 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2225 512, &dwc
->ep0_bounce_addr
, GFP_KERNEL
);
2226 if (!dwc
->ep0_bounce
) {
2227 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2232 dev_set_name(&dwc
->gadget
.dev
, "gadget");
2234 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2235 dwc
->gadget
.max_speed
= USB_SPEED_SUPER
;
2236 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2237 dwc
->gadget
.dev
.parent
= dwc
->dev
;
2238 dwc
->gadget
.sg_supported
= true;
2240 dma_set_coherent_mask(&dwc
->gadget
.dev
, dwc
->dev
->coherent_dma_mask
);
2242 dwc
->gadget
.dev
.dma_parms
= dwc
->dev
->dma_parms
;
2243 dwc
->gadget
.dev
.dma_mask
= dwc
->dev
->dma_mask
;
2244 dwc
->gadget
.dev
.release
= dwc3_gadget_release
;
2245 dwc
->gadget
.name
= "dwc3-gadget";
2248 * REVISIT: Here we should clear all pending IRQs to be
2249 * sure we're starting from a well known location.
2252 ret
= dwc3_gadget_init_endpoints(dwc
);
2256 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
2258 ret
= request_irq(irq
, dwc3_interrupt
, IRQF_SHARED
,
2261 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
2266 /* Enable all but Start and End of Frame IRQs */
2267 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
2268 DWC3_DEVTEN_EVNTOVERFLOWEN
|
2269 DWC3_DEVTEN_CMDCMPLTEN
|
2270 DWC3_DEVTEN_ERRTICERREN
|
2271 DWC3_DEVTEN_WKUPEVTEN
|
2272 DWC3_DEVTEN_ULSTCNGEN
|
2273 DWC3_DEVTEN_CONNECTDONEEN
|
2274 DWC3_DEVTEN_USBRSTEN
|
2275 DWC3_DEVTEN_DISCONNEVTEN
);
2276 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
2278 ret
= device_register(&dwc
->gadget
.dev
);
2280 dev_err(dwc
->dev
, "failed to register gadget device\n");
2281 put_device(&dwc
->gadget
.dev
);
2285 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2287 dev_err(dwc
->dev
, "failed to register udc\n");
2294 device_unregister(&dwc
->gadget
.dev
);
2297 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2301 dwc3_gadget_free_endpoints(dwc
);
2304 dma_free_coherent(dwc
->dev
, 512, dwc
->ep0_bounce
,
2305 dwc
->ep0_bounce_addr
);
2308 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->setup_buf
) * 2,
2309 dwc
->setup_buf
, dwc
->setup_buf_addr
);
2312 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2313 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2316 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2317 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2323 void dwc3_gadget_exit(struct dwc3
*dwc
)
2327 usb_del_gadget_udc(&dwc
->gadget
);
2328 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
2330 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2333 dwc3_gadget_free_endpoints(dwc
);
2335 dma_free_coherent(dwc
->dev
, 512, dwc
->ep0_bounce
,
2336 dwc
->ep0_bounce_addr
);
2338 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->setup_buf
) * 2,
2339 dwc
->setup_buf
, dwc
->setup_buf_addr
);
2341 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2342 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2344 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2345 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2347 device_unregister(&dwc
->gadget
.dev
);