2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
66 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
70 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
71 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
85 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
98 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
104 * Wait until device controller is ready. Only applies to 1.94a and
107 if (dwc
->revision
>= DWC3_REVISION_194A
) {
109 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
110 if (reg
& DWC3_DSTS_DCNRD
)
120 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
121 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
123 /* set requested state */
124 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
125 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
131 if (dwc
->revision
>= DWC3_REVISION_194A
)
134 /* wait for a change in DSTS */
137 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
139 if (DWC3_DSTS_USBLNKST(reg
) == state
)
145 dev_vdbg(dwc
->dev
, "link state change request timed out\n");
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
169 * Unfortunately, due to many variables that's not always the case.
171 int dwc3_gadget_resize_tx_fifos(struct dwc3
*dwc
)
173 int last_fifo_depth
= 0;
179 if (!dwc
->needs_fifo_resize
)
182 ram1_depth
= DWC3_RAM1_DEPTH(dwc
->hwparams
.hwparams7
);
183 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
185 /* MDWIDTH is represented in bits, we need it in bytes */
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
194 for (num
= 0; num
< DWC3_ENDPOINTS_NUM
; num
++) {
195 struct dwc3_ep
*dep
= dwc
->eps
[num
];
196 int fifo_number
= dep
->number
>> 1;
200 if (!(dep
->number
& 1))
203 if (!(dep
->flags
& DWC3_EP_ENABLED
))
206 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)
207 || usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
221 tmp
= mult
* (dep
->endpoint
.maxpacket
+ mdwidth
);
224 fifo_size
= DIV_ROUND_UP(tmp
, mdwidth
);
226 fifo_size
|= (last_fifo_depth
<< 16);
228 dev_vdbg(dwc
->dev
, "%s: Fifo Addr %04x Size %d\n",
229 dep
->name
, last_fifo_depth
, fifo_size
& 0xffff);
231 dwc3_writel(dwc
->regs
, DWC3_GTXFIFOSIZ(fifo_number
),
234 last_fifo_depth
+= (fifo_size
& 0xffff);
240 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
243 struct dwc3
*dwc
= dep
->dwc
;
246 if (req
->request
.num_mapped_sgs
)
247 dep
->busy_slot
+= req
->request
.num_mapped_sgs
;
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
256 if (((dep
->busy_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
257 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
260 list_del(&req
->list
);
263 if (req
->request
.status
== -EINPROGRESS
)
264 req
->request
.status
= status
;
266 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
269 dev_dbg(dwc
->dev
, "request %p from %s completed %d/%d ===> %d\n",
270 req
, dep
->name
, req
->request
.actual
,
271 req
->request
.length
, status
);
273 spin_unlock(&dwc
->lock
);
274 req
->request
.complete(&dep
->endpoint
, &req
->request
);
275 spin_lock(&dwc
->lock
);
278 static const char *dwc3_gadget_ep_cmd_string(u8 cmd
)
281 case DWC3_DEPCMD_DEPSTARTCFG
:
282 return "Start New Configuration";
283 case DWC3_DEPCMD_ENDTRANSFER
:
284 return "End Transfer";
285 case DWC3_DEPCMD_UPDATETRANSFER
:
286 return "Update Transfer";
287 case DWC3_DEPCMD_STARTTRANSFER
:
288 return "Start Transfer";
289 case DWC3_DEPCMD_CLEARSTALL
:
290 return "Clear Stall";
291 case DWC3_DEPCMD_SETSTALL
:
293 case DWC3_DEPCMD_GETEPSTATE
:
294 return "Get Endpoint State";
295 case DWC3_DEPCMD_SETTRANSFRESOURCE
:
296 return "Set Endpoint Transfer Resource";
297 case DWC3_DEPCMD_SETEPCONFIG
:
298 return "Set Endpoint Configuration";
300 return "UNKNOWN command";
304 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, int cmd
, u32 param
)
309 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
310 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
313 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
314 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
315 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
316 DWC3_DGCMD_STATUS(reg
));
321 * We can't sleep here, because it's also called from
331 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
332 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
334 struct dwc3_ep
*dep
= dwc
->eps
[ep
];
338 dev_vdbg(dwc
->dev
, "%s: cmd '%s' params %08x %08x %08x\n",
340 dwc3_gadget_ep_cmd_string(cmd
), params
->param0
,
341 params
->param1
, params
->param2
);
343 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
344 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
345 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
347 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
349 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
350 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
351 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
352 DWC3_DEPCMD_STATUS(reg
));
357 * We can't sleep here, because it is also called from
368 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
369 struct dwc3_trb
*trb
)
371 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
373 return dep
->trb_pool_dma
+ offset
;
376 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
378 struct dwc3
*dwc
= dep
->dwc
;
383 if (dep
->number
== 0 || dep
->number
== 1)
386 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
387 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
388 &dep
->trb_pool_dma
, GFP_KERNEL
);
389 if (!dep
->trb_pool
) {
390 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
398 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
400 struct dwc3
*dwc
= dep
->dwc
;
402 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
403 dep
->trb_pool
, dep
->trb_pool_dma
);
405 dep
->trb_pool
= NULL
;
406 dep
->trb_pool_dma
= 0;
409 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
411 struct dwc3_gadget_ep_cmd_params params
;
414 memset(¶ms
, 0x00, sizeof(params
));
416 if (dep
->number
!= 1) {
417 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
419 if (dep
->number
> 1) {
420 if (dwc
->start_config_issued
)
422 dwc
->start_config_issued
= true;
423 cmd
|= DWC3_DEPCMD_PARAM(2);
426 return dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
432 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
433 const struct usb_endpoint_descriptor
*desc
,
434 const struct usb_ss_ep_comp_descriptor
*comp_desc
)
436 struct dwc3_gadget_ep_cmd_params params
;
438 memset(¶ms
, 0x00, sizeof(params
));
440 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
441 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
))
442 | DWC3_DEPCFG_BURST_SIZE(dep
->endpoint
.maxburst
);
444 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
445 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
447 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
448 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
449 | DWC3_DEPCFG_STREAM_EVENT_EN
;
450 dep
->stream_capable
= true;
453 if (usb_endpoint_xfer_isoc(desc
))
454 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
457 * We are doing 1:1 mapping for endpoints, meaning
458 * Physical Endpoints 2 maps to Logical Endpoint 2 and
459 * so on. We consider the direction bit as part of the physical
460 * endpoint number. So USB endpoint 0x81 is 0x03.
462 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
465 * We must use the lower 16 TX FIFOs even though
469 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
471 if (desc
->bInterval
) {
472 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
473 dep
->interval
= 1 << (desc
->bInterval
- 1);
476 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
477 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
480 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
482 struct dwc3_gadget_ep_cmd_params params
;
484 memset(¶ms
, 0x00, sizeof(params
));
486 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
488 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
489 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
493 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
494 * @dep: endpoint to be initialized
495 * @desc: USB Endpoint Descriptor
497 * Caller should take care of locking
499 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
500 const struct usb_endpoint_descriptor
*desc
,
501 const struct usb_ss_ep_comp_descriptor
*comp_desc
)
503 struct dwc3
*dwc
= dep
->dwc
;
507 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
508 ret
= dwc3_gadget_start_config(dwc
, dep
);
513 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
);
517 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
518 struct dwc3_trb
*trb_st_hw
;
519 struct dwc3_trb
*trb_link
;
521 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
525 dep
->endpoint
.desc
= desc
;
526 dep
->comp_desc
= comp_desc
;
527 dep
->type
= usb_endpoint_type(desc
);
528 dep
->flags
|= DWC3_EP_ENABLED
;
530 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
531 reg
|= DWC3_DALEPENA_EP(dep
->number
);
532 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
534 if (!usb_endpoint_xfer_isoc(desc
))
537 memset(&trb_link
, 0, sizeof(trb_link
));
539 /* Link TRB for ISOC. The HWO bit is never reset */
540 trb_st_hw
= &dep
->trb_pool
[0];
542 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
544 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
545 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
546 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
547 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
553 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
);
554 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
556 struct dwc3_request
*req
;
558 if (!list_empty(&dep
->req_queued
)) {
559 dwc3_stop_active_transfer(dwc
, dep
->number
);
562 * NOTICE: We are violating what the Databook says about the
563 * EndTransfer command. Ideally we would _always_ wait for the
564 * EndTransfer Command Completion IRQ, but that's causing too
565 * much trouble synchronizing between us and gadget driver.
567 * We have discussed this with the IP Provider and it was
568 * suggested to giveback all requests here, but give HW some
569 * extra time to synchronize with the interconnect. We're using
570 * an arbitraty 100us delay for that.
572 * Note also that a similar handling was tested by Synopsys
573 * (thanks a lot Paul) and nothing bad has come out of it.
574 * In short, what we're doing is:
576 * - Issue EndTransfer WITH CMDIOC bit set
578 * - giveback all requests to gadget driver
582 while (!list_empty(&dep
->req_queued
)) {
583 req
= next_request(&dep
->req_queued
);
585 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
589 while (!list_empty(&dep
->request_list
)) {
590 req
= next_request(&dep
->request_list
);
592 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
597 * __dwc3_gadget_ep_disable - Disables a HW endpoint
598 * @dep: the endpoint to disable
600 * This function also removes requests which are currently processed ny the
601 * hardware and those which are not yet scheduled.
602 * Caller should take care of locking.
604 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
606 struct dwc3
*dwc
= dep
->dwc
;
609 dwc3_remove_requests(dwc
, dep
);
611 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
612 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
613 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
615 dep
->stream_capable
= false;
616 dep
->endpoint
.desc
= NULL
;
617 dep
->comp_desc
= NULL
;
624 /* -------------------------------------------------------------------------- */
626 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
627 const struct usb_endpoint_descriptor
*desc
)
632 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
637 /* -------------------------------------------------------------------------- */
639 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
640 const struct usb_endpoint_descriptor
*desc
)
647 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
648 pr_debug("dwc3: invalid parameters\n");
652 if (!desc
->wMaxPacketSize
) {
653 pr_debug("dwc3: missing wMaxPacketSize\n");
657 dep
= to_dwc3_ep(ep
);
660 switch (usb_endpoint_type(desc
)) {
661 case USB_ENDPOINT_XFER_CONTROL
:
662 strlcat(dep
->name
, "-control", sizeof(dep
->name
));
664 case USB_ENDPOINT_XFER_ISOC
:
665 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
667 case USB_ENDPOINT_XFER_BULK
:
668 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
670 case USB_ENDPOINT_XFER_INT
:
671 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
674 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
677 if (dep
->flags
& DWC3_EP_ENABLED
) {
678 dev_WARN_ONCE(dwc
->dev
, true, "%s is already enabled\n",
683 dev_vdbg(dwc
->dev
, "Enabling %s\n", dep
->name
);
685 spin_lock_irqsave(&dwc
->lock
, flags
);
686 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
);
687 spin_unlock_irqrestore(&dwc
->lock
, flags
);
692 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
700 pr_debug("dwc3: invalid parameters\n");
704 dep
= to_dwc3_ep(ep
);
707 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
708 dev_WARN_ONCE(dwc
->dev
, true, "%s is already disabled\n",
713 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
715 (dep
->number
& 1) ? "in" : "out");
717 spin_lock_irqsave(&dwc
->lock
, flags
);
718 ret
= __dwc3_gadget_ep_disable(dep
);
719 spin_unlock_irqrestore(&dwc
->lock
, flags
);
724 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
727 struct dwc3_request
*req
;
728 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
729 struct dwc3
*dwc
= dep
->dwc
;
731 req
= kzalloc(sizeof(*req
), gfp_flags
);
733 dev_err(dwc
->dev
, "not enough memory\n");
737 req
->epnum
= dep
->number
;
740 return &req
->request
;
743 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
744 struct usb_request
*request
)
746 struct dwc3_request
*req
= to_dwc3_request(request
);
752 * dwc3_prepare_one_trb - setup one TRB from one request
753 * @dep: endpoint for which this request is prepared
754 * @req: dwc3_request pointer
756 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
757 struct dwc3_request
*req
, dma_addr_t dma
,
758 unsigned length
, unsigned last
, unsigned chain
)
760 struct dwc3
*dwc
= dep
->dwc
;
761 struct dwc3_trb
*trb
;
763 unsigned int cur_slot
;
765 dev_vdbg(dwc
->dev
, "%s: req %p dma %08llx length %d%s%s\n",
766 dep
->name
, req
, (unsigned long long) dma
,
767 length
, last
? " last" : "",
768 chain
? " chain" : "");
770 trb
= &dep
->trb_pool
[dep
->free_slot
& DWC3_TRB_MASK
];
771 cur_slot
= dep
->free_slot
;
774 /* Skip the LINK-TRB on ISOC */
775 if (((cur_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
776 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
780 dwc3_gadget_move_request_queued(req
);
782 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
785 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
786 trb
->bpl
= lower_32_bits(dma
);
787 trb
->bph
= upper_32_bits(dma
);
789 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
790 case USB_ENDPOINT_XFER_CONTROL
:
791 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
794 case USB_ENDPOINT_XFER_ISOC
:
795 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
797 if (!req
->request
.no_interrupt
)
798 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
801 case USB_ENDPOINT_XFER_BULK
:
802 case USB_ENDPOINT_XFER_INT
:
803 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
807 * This is only possible with faulty memory because we
808 * checked it already :)
813 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
814 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
815 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
818 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
821 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
824 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
825 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
827 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
831 * dwc3_prepare_trbs - setup TRBs from requests
832 * @dep: endpoint for which requests are being prepared
833 * @starting: true if the endpoint is idle and no requests are queued.
835 * The function goes through the requests list and sets up TRBs for the
836 * transfers. The function returns once there are no more TRBs available or
837 * it runs out of requests.
839 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
841 struct dwc3_request
*req
, *n
;
844 unsigned int last_one
= 0;
846 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
848 /* the first request must not be queued */
849 trbs_left
= (dep
->busy_slot
- dep
->free_slot
) & DWC3_TRB_MASK
;
851 /* Can't wrap around on a non-isoc EP since there's no link TRB */
852 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
853 max
= DWC3_TRB_NUM
- (dep
->free_slot
& DWC3_TRB_MASK
);
859 * If busy & slot are equal than it is either full or empty. If we are
860 * starting to process requests then we are empty. Otherwise we are
861 * full and don't do anything
866 trbs_left
= DWC3_TRB_NUM
;
868 * In case we start from scratch, we queue the ISOC requests
869 * starting from slot 1. This is done because we use ring
870 * buffer and have no LST bit to stop us. Instead, we place
871 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
872 * after the first request so we start at slot 1 and have
873 * 7 requests proceed before we hit the first IOC.
874 * Other transfer types don't use the ring buffer and are
875 * processed from the first TRB until the last one. Since we
876 * don't wrap around we have to start at the beginning.
878 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
887 /* The last TRB is a link TRB, not used for xfer */
888 if ((trbs_left
<= 1) && usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
891 list_for_each_entry_safe(req
, n
, &dep
->request_list
, list
) {
895 if (req
->request
.num_mapped_sgs
> 0) {
896 struct usb_request
*request
= &req
->request
;
897 struct scatterlist
*sg
= request
->sg
;
898 struct scatterlist
*s
;
901 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
902 unsigned chain
= true;
904 length
= sg_dma_len(s
);
905 dma
= sg_dma_address(s
);
907 if (i
== (request
->num_mapped_sgs
- 1) ||
920 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
927 dma
= req
->request
.dma
;
928 length
= req
->request
.length
;
934 /* Is this the last request? */
935 if (list_is_last(&req
->list
, &dep
->request_list
))
938 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
947 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
950 struct dwc3_gadget_ep_cmd_params params
;
951 struct dwc3_request
*req
;
952 struct dwc3
*dwc
= dep
->dwc
;
956 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
957 dev_vdbg(dwc
->dev
, "%s: endpoint busy\n", dep
->name
);
960 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
963 * If we are getting here after a short-out-packet we don't enqueue any
964 * new requests as we try to set the IOC bit only on the last request.
967 if (list_empty(&dep
->req_queued
))
968 dwc3_prepare_trbs(dep
, start_new
);
970 /* req points to the first request which will be sent */
971 req
= next_request(&dep
->req_queued
);
973 dwc3_prepare_trbs(dep
, start_new
);
976 * req points to the first request where HWO changed from 0 to 1
978 req
= next_request(&dep
->req_queued
);
981 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
985 memset(¶ms
, 0, sizeof(params
));
986 params
.param0
= upper_32_bits(req
->trb_dma
);
987 params
.param1
= lower_32_bits(req
->trb_dma
);
990 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
992 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
994 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
995 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
997 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
1000 * FIXME we need to iterate over the list of requests
1001 * here and stop, unmap, free and del each of the linked
1002 * requests instead of what we do now.
1004 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
1006 list_del(&req
->list
);
1010 dep
->flags
|= DWC3_EP_BUSY
;
1013 dep
->res_trans_idx
= dwc3_gadget_ep_get_transfer_index(dwc
,
1015 WARN_ON_ONCE(!dep
->res_trans_idx
);
1021 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1022 struct dwc3_ep
*dep
, u32 cur_uf
)
1026 if (list_empty(&dep
->request_list
)) {
1027 dev_vdbg(dwc
->dev
, "ISOC ep %s run out for requests.\n",
1032 /* 4 micro frames in the future */
1033 uf
= cur_uf
+ dep
->interval
* 4;
1035 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
1038 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1039 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1043 mask
= ~(dep
->interval
- 1);
1044 cur_uf
= event
->parameters
& mask
;
1046 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1049 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1051 struct dwc3
*dwc
= dep
->dwc
;
1054 req
->request
.actual
= 0;
1055 req
->request
.status
= -EINPROGRESS
;
1056 req
->direction
= dep
->direction
;
1057 req
->epnum
= dep
->number
;
1060 * We only add to our list of requests now and
1061 * start consuming the list once we get XferNotReady
1064 * That way, we avoid doing anything that we don't need
1065 * to do now and defer it until the point we receive a
1066 * particular token from the Host side.
1068 * This will also avoid Host cancelling URBs due to too
1071 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1076 list_add_tail(&req
->list
, &dep
->request_list
);
1078 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1079 if (dep
->flags
& DWC3_EP_BUSY
) {
1080 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1081 } else if (dep
->flags
& DWC3_EP_MISSED_ISOC
) {
1082 __dwc3_gadget_start_isoc(dwc
, dep
, dep
->current_uf
);
1083 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1088 * There are two special cases:
1090 * 1. XferNotReady with empty list of requests. We need to kick the
1091 * transfer here in that situation, otherwise we will be NAKing
1092 * forever. If we get XferNotReady before gadget driver has a
1093 * chance to queue a request, we will ACK the IRQ but won't be
1094 * able to receive the data until the next request is queued.
1095 * The following code is handling exactly that.
1097 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1098 * kick the transfer here after queuing a request, otherwise the
1099 * core may not see the modified TRB(s).
1101 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1103 int start_trans
= 1;
1104 u8 trans_idx
= dep
->res_trans_idx
;
1106 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1107 (dep
->flags
& DWC3_EP_BUSY
)) {
1109 WARN_ON_ONCE(!trans_idx
);
1114 ret
= __dwc3_gadget_kick_transfer(dep
, trans_idx
, start_trans
);
1115 if (ret
&& ret
!= -EBUSY
) {
1116 struct dwc3
*dwc
= dep
->dwc
;
1118 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1126 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1129 struct dwc3_request
*req
= to_dwc3_request(request
);
1130 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1131 struct dwc3
*dwc
= dep
->dwc
;
1133 unsigned long flags
;
1137 if (!dep
->endpoint
.desc
) {
1138 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
1143 dev_vdbg(dwc
->dev
, "queing request %p to %s length %d\n",
1144 request
, ep
->name
, request
->length
);
1146 spin_lock_irqsave(&dwc
->lock
, flags
);
1147 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1148 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1153 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1154 struct usb_request
*request
)
1156 struct dwc3_request
*req
= to_dwc3_request(request
);
1157 struct dwc3_request
*r
= NULL
;
1159 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1160 struct dwc3
*dwc
= dep
->dwc
;
1162 unsigned long flags
;
1165 spin_lock_irqsave(&dwc
->lock
, flags
);
1167 list_for_each_entry(r
, &dep
->request_list
, list
) {
1173 list_for_each_entry(r
, &dep
->req_queued
, list
) {
1178 /* wait until it is processed */
1179 dwc3_stop_active_transfer(dwc
, dep
->number
);
1182 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1188 /* giveback the request */
1189 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1192 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1197 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
)
1199 struct dwc3_gadget_ep_cmd_params params
;
1200 struct dwc3
*dwc
= dep
->dwc
;
1203 memset(¶ms
, 0x00, sizeof(params
));
1206 if (dep
->number
== 0 || dep
->number
== 1) {
1208 * Whenever EP0 is stalled, we will restart
1209 * the state machine, thus moving back to
1212 dwc
->ep0state
= EP0_SETUP_PHASE
;
1215 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1216 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1218 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1219 value
? "set" : "clear",
1222 dep
->flags
|= DWC3_EP_STALL
;
1224 if (dep
->flags
& DWC3_EP_WEDGE
)
1227 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1228 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1230 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1231 value
? "set" : "clear",
1234 dep
->flags
&= ~DWC3_EP_STALL
;
1240 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1242 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1243 struct dwc3
*dwc
= dep
->dwc
;
1245 unsigned long flags
;
1249 spin_lock_irqsave(&dwc
->lock
, flags
);
1251 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1252 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1257 ret
= __dwc3_gadget_ep_set_halt(dep
, value
);
1259 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1264 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1266 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1267 struct dwc3
*dwc
= dep
->dwc
;
1268 unsigned long flags
;
1270 spin_lock_irqsave(&dwc
->lock
, flags
);
1271 dep
->flags
|= DWC3_EP_WEDGE
;
1272 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1274 return dwc3_gadget_ep_set_halt(ep
, 1);
1277 /* -------------------------------------------------------------------------- */
1279 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1280 .bLength
= USB_DT_ENDPOINT_SIZE
,
1281 .bDescriptorType
= USB_DT_ENDPOINT
,
1282 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1285 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1286 .enable
= dwc3_gadget_ep0_enable
,
1287 .disable
= dwc3_gadget_ep0_disable
,
1288 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1289 .free_request
= dwc3_gadget_ep_free_request
,
1290 .queue
= dwc3_gadget_ep0_queue
,
1291 .dequeue
= dwc3_gadget_ep_dequeue
,
1292 .set_halt
= dwc3_gadget_ep_set_halt
,
1293 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1296 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1297 .enable
= dwc3_gadget_ep_enable
,
1298 .disable
= dwc3_gadget_ep_disable
,
1299 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1300 .free_request
= dwc3_gadget_ep_free_request
,
1301 .queue
= dwc3_gadget_ep_queue
,
1302 .dequeue
= dwc3_gadget_ep_dequeue
,
1303 .set_halt
= dwc3_gadget_ep_set_halt
,
1304 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1307 /* -------------------------------------------------------------------------- */
1309 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1311 struct dwc3
*dwc
= gadget_to_dwc(g
);
1314 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1315 return DWC3_DSTS_SOFFN(reg
);
1318 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1320 struct dwc3
*dwc
= gadget_to_dwc(g
);
1322 unsigned long timeout
;
1323 unsigned long flags
;
1332 spin_lock_irqsave(&dwc
->lock
, flags
);
1335 * According to the Databook Remote wakeup request should
1336 * be issued only when the device is in early suspend state.
1338 * We can check that via USB Link State bits in DSTS register.
1340 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1342 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1343 if (speed
== DWC3_DSTS_SUPERSPEED
) {
1344 dev_dbg(dwc
->dev
, "no wakeup on SuperSpeed\n");
1349 link_state
= DWC3_DSTS_USBLNKST(reg
);
1351 switch (link_state
) {
1352 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1353 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1356 dev_dbg(dwc
->dev
, "can't wakeup from link state %d\n",
1362 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1364 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1368 /* Recent versions do this automatically */
1369 if (dwc
->revision
< DWC3_REVISION_194A
) {
1370 /* write zeroes to Link Change Request */
1371 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1372 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1373 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1376 /* poll until Link State changes to ON */
1377 timeout
= jiffies
+ msecs_to_jiffies(100);
1379 while (!time_after(jiffies
, timeout
)) {
1380 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1382 /* in HS, means ON */
1383 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1387 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1388 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1393 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1398 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1401 struct dwc3
*dwc
= gadget_to_dwc(g
);
1402 unsigned long flags
;
1404 spin_lock_irqsave(&dwc
->lock
, flags
);
1405 dwc
->is_selfpowered
= !!is_selfpowered
;
1406 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1411 static void dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
)
1416 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1418 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1419 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1420 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1423 if (dwc
->revision
>= DWC3_REVISION_194A
)
1424 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1425 reg
|= DWC3_DCTL_RUN_STOP
;
1427 reg
&= ~DWC3_DCTL_RUN_STOP
;
1430 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1433 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1435 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1438 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1447 dev_vdbg(dwc
->dev
, "gadget %s data soft-%s\n",
1449 ? dwc
->gadget_driver
->function
: "no-function",
1450 is_on
? "connect" : "disconnect");
1453 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1455 struct dwc3
*dwc
= gadget_to_dwc(g
);
1456 unsigned long flags
;
1460 spin_lock_irqsave(&dwc
->lock
, flags
);
1461 dwc3_gadget_run_stop(dwc
, is_on
);
1462 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1467 static int dwc3_gadget_start(struct usb_gadget
*g
,
1468 struct usb_gadget_driver
*driver
)
1470 struct dwc3
*dwc
= gadget_to_dwc(g
);
1471 struct dwc3_ep
*dep
;
1472 unsigned long flags
;
1476 spin_lock_irqsave(&dwc
->lock
, flags
);
1478 if (dwc
->gadget_driver
) {
1479 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1481 dwc
->gadget_driver
->driver
.name
);
1486 dwc
->gadget_driver
= driver
;
1487 dwc
->gadget
.dev
.driver
= &driver
->driver
;
1489 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1490 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1493 * WORKAROUND: DWC3 revision < 2.20a have an issue
1494 * which would cause metastability state on Run/Stop
1495 * bit if we try to force the IP to USB2-only mode.
1497 * Because of that, we cannot configure the IP to any
1498 * speed other than the SuperSpeed
1502 * STAR#9000525659: Clock Domain Crossing on DCTL in
1505 if (dwc
->revision
< DWC3_REVISION_220A
)
1506 reg
|= DWC3_DCFG_SUPERSPEED
;
1508 reg
|= dwc
->maximum_speed
;
1509 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1511 dwc
->start_config_issued
= false;
1513 /* Start with SuperSpeed Default */
1514 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1517 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
1519 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1524 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
1526 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1530 /* begin to receive SETUP packets */
1531 dwc
->ep0state
= EP0_SETUP_PHASE
;
1532 dwc3_ep0_out_start(dwc
);
1534 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1539 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1542 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1547 static int dwc3_gadget_stop(struct usb_gadget
*g
,
1548 struct usb_gadget_driver
*driver
)
1550 struct dwc3
*dwc
= gadget_to_dwc(g
);
1551 unsigned long flags
;
1553 spin_lock_irqsave(&dwc
->lock
, flags
);
1555 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1556 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1558 dwc
->gadget_driver
= NULL
;
1559 dwc
->gadget
.dev
.driver
= NULL
;
1561 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1566 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1567 .get_frame
= dwc3_gadget_get_frame
,
1568 .wakeup
= dwc3_gadget_wakeup
,
1569 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1570 .pullup
= dwc3_gadget_pullup
,
1571 .udc_start
= dwc3_gadget_start
,
1572 .udc_stop
= dwc3_gadget_stop
,
1575 /* -------------------------------------------------------------------------- */
1577 static int __devinit
dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1579 struct dwc3_ep
*dep
;
1582 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1584 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1585 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1587 dev_err(dwc
->dev
, "can't allocate endpoint %d\n",
1593 dep
->number
= epnum
;
1594 dwc
->eps
[epnum
] = dep
;
1596 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1597 (epnum
& 1) ? "in" : "out");
1598 dep
->endpoint
.name
= dep
->name
;
1599 dep
->direction
= (epnum
& 1);
1601 if (epnum
== 0 || epnum
== 1) {
1602 dep
->endpoint
.maxpacket
= 512;
1603 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1605 dwc
->gadget
.ep0
= &dep
->endpoint
;
1609 dep
->endpoint
.maxpacket
= 1024;
1610 dep
->endpoint
.max_streams
= 15;
1611 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1612 list_add_tail(&dep
->endpoint
.ep_list
,
1613 &dwc
->gadget
.ep_list
);
1615 ret
= dwc3_alloc_trb_pool(dep
);
1620 INIT_LIST_HEAD(&dep
->request_list
);
1621 INIT_LIST_HEAD(&dep
->req_queued
);
1627 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1629 struct dwc3_ep
*dep
;
1632 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1633 dep
= dwc
->eps
[epnum
];
1634 dwc3_free_trb_pool(dep
);
1636 if (epnum
!= 0 && epnum
!= 1)
1637 list_del(&dep
->endpoint
.ep_list
);
1643 static void dwc3_gadget_release(struct device
*dev
)
1645 dev_dbg(dev
, "%s\n", __func__
);
1648 /* -------------------------------------------------------------------------- */
1649 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1650 const struct dwc3_event_depevt
*event
, int status
)
1652 struct dwc3_request
*req
;
1653 struct dwc3_trb
*trb
;
1655 unsigned int s_pkt
= 0;
1656 unsigned int trb_status
;
1659 req
= next_request(&dep
->req_queued
);
1667 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1669 * We continue despite the error. There is not much we
1670 * can do. If we don't clean it up we loop forever. If
1671 * we skip the TRB then it gets overwritten after a
1672 * while since we use them in a ring buffer. A BUG()
1673 * would help. Lets hope that if this occurs, someone
1674 * fixes the root cause instead of looking away :)
1676 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1677 dep
->name
, req
->trb
);
1678 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1680 if (dep
->direction
) {
1682 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1683 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1684 dev_dbg(dwc
->dev
, "incomplete IN transfer %s\n",
1686 dep
->current_uf
= event
->parameters
&
1687 ~(dep
->interval
- 1);
1688 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1690 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1692 status
= -ECONNRESET
;
1696 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1701 * We assume here we will always receive the entire data block
1702 * which we should receive. Meaning, if we program RX to
1703 * receive 4K but we receive only 2K, we assume that's all we
1704 * should receive and we simply bounce the request back to the
1705 * gadget driver for further processing.
1707 req
->request
.actual
+= req
->request
.length
- count
;
1708 dwc3_gadget_giveback(dep
, req
, status
);
1711 if ((event
->status
& DEPEVT_STATUS_LST
) &&
1712 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
1713 DWC3_TRB_CTRL_HWO
)))
1715 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1716 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1720 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1721 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1726 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
1727 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
,
1730 unsigned status
= 0;
1733 if (event
->status
& DEPEVT_STATUS_BUSERR
)
1734 status
= -ECONNRESET
;
1736 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
1738 dep
->flags
&= ~DWC3_EP_BUSY
;
1741 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1742 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1744 if (dwc
->revision
< DWC3_REVISION_183A
) {
1748 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
1749 struct dwc3_ep
*dep
= dwc
->eps
[i
];
1751 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1754 if (!list_empty(&dep
->req_queued
))
1758 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1760 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1766 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
1767 const struct dwc3_event_depevt
*event
)
1769 struct dwc3_ep
*dep
;
1770 u8 epnum
= event
->endpoint_number
;
1772 dep
= dwc
->eps
[epnum
];
1774 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1777 dev_vdbg(dwc
->dev
, "%s: %s\n", dep
->name
,
1778 dwc3_ep_event_string(event
->endpoint_event
));
1780 if (epnum
== 0 || epnum
== 1) {
1781 dwc3_ep0_interrupt(dwc
, event
);
1785 switch (event
->endpoint_event
) {
1786 case DWC3_DEPEVT_XFERCOMPLETE
:
1787 dep
->res_trans_idx
= 0;
1789 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1790 dev_dbg(dwc
->dev
, "%s is an Isochronous endpoint\n",
1795 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 1);
1797 case DWC3_DEPEVT_XFERINPROGRESS
:
1798 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1799 dev_dbg(dwc
->dev
, "%s is not an Isochronous endpoint\n",
1804 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 0);
1806 case DWC3_DEPEVT_XFERNOTREADY
:
1807 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1808 dwc3_gadget_start_isoc(dwc
, dep
, event
);
1812 dev_vdbg(dwc
->dev
, "%s: reason %s\n",
1813 dep
->name
, event
->status
&
1814 DEPEVT_STATUS_TRANSFER_ACTIVE
1816 : "Transfer Not Active");
1818 ret
= __dwc3_gadget_kick_transfer(dep
, 0, 1);
1819 if (!ret
|| ret
== -EBUSY
)
1822 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1827 case DWC3_DEPEVT_STREAMEVT
:
1828 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
1829 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
1834 switch (event
->status
) {
1835 case DEPEVT_STREAMEVT_FOUND
:
1836 dev_vdbg(dwc
->dev
, "Stream %d found and started\n",
1840 case DEPEVT_STREAMEVT_NOTFOUND
:
1843 dev_dbg(dwc
->dev
, "Couldn't find suitable stream\n");
1846 case DWC3_DEPEVT_RXTXFIFOEVT
:
1847 dev_dbg(dwc
->dev
, "%s FIFO Overrun\n", dep
->name
);
1849 case DWC3_DEPEVT_EPCMDCMPLT
:
1850 dev_vdbg(dwc
->dev
, "Endpoint Command Complete\n");
1855 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
1857 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
1858 spin_unlock(&dwc
->lock
);
1859 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
1860 spin_lock(&dwc
->lock
);
1864 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
)
1866 struct dwc3_ep
*dep
;
1867 struct dwc3_gadget_ep_cmd_params params
;
1871 dep
= dwc
->eps
[epnum
];
1873 WARN_ON(!dep
->res_trans_idx
);
1874 if (dep
->res_trans_idx
) {
1875 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1876 cmd
|= DWC3_DEPCMD_HIPRI_FORCERM
| DWC3_DEPCMD_CMDIOC
;
1877 cmd
|= DWC3_DEPCMD_PARAM(dep
->res_trans_idx
);
1878 memset(¶ms
, 0, sizeof(params
));
1879 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1881 dep
->res_trans_idx
= 0;
1885 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
1889 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1890 struct dwc3_ep
*dep
;
1892 dep
= dwc
->eps
[epnum
];
1893 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1896 dwc3_remove_requests(dwc
, dep
);
1900 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
1904 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1905 struct dwc3_ep
*dep
;
1906 struct dwc3_gadget_ep_cmd_params params
;
1909 dep
= dwc
->eps
[epnum
];
1911 if (!(dep
->flags
& DWC3_EP_STALL
))
1914 dep
->flags
&= ~DWC3_EP_STALL
;
1916 memset(¶ms
, 0, sizeof(params
));
1917 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1918 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1923 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
1927 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1929 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1930 reg
&= ~DWC3_DCTL_INITU1ENA
;
1931 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1933 reg
&= ~DWC3_DCTL_INITU2ENA
;
1934 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1936 dwc3_disconnect_gadget(dwc
);
1937 dwc
->start_config_issued
= false;
1939 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1940 dwc
->setup_packet_pending
= false;
1943 static void dwc3_gadget_usb3_phy_suspend(struct dwc3
*dwc
, int suspend
)
1947 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
1950 reg
|= DWC3_GUSB3PIPECTL_SUSPHY
;
1952 reg
&= ~DWC3_GUSB3PIPECTL_SUSPHY
;
1954 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
1957 static void dwc3_gadget_usb2_phy_suspend(struct dwc3
*dwc
, int suspend
)
1961 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
1964 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
1966 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
1968 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
1971 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
1975 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1978 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1979 * would cause a missing Disconnect Event if there's a
1980 * pending Setup Packet in the FIFO.
1982 * There's no suggested workaround on the official Bug
1983 * report, which states that "unless the driver/application
1984 * is doing any special handling of a disconnect event,
1985 * there is no functional issue".
1987 * Unfortunately, it turns out that we _do_ some special
1988 * handling of a disconnect event, namely complete all
1989 * pending transfers, notify gadget driver of the
1990 * disconnection, and so on.
1992 * Our suggested workaround is to follow the Disconnect
1993 * Event steps here, instead, based on a setup_packet_pending
1994 * flag. Such flag gets set whenever we have a XferNotReady
1995 * event on EP0 and gets cleared on XferComplete for the
2000 * STAR#9000466709: RTL: Device : Disconnect event not
2001 * generated if setup packet pending in FIFO
2003 if (dwc
->revision
< DWC3_REVISION_188A
) {
2004 if (dwc
->setup_packet_pending
)
2005 dwc3_gadget_disconnect_interrupt(dwc
);
2008 /* after reset -> Default State */
2009 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
2011 /* Recent versions support automatic phy suspend and don't need this */
2012 if (dwc
->revision
< DWC3_REVISION_194A
) {
2014 dwc3_gadget_usb2_phy_suspend(dwc
, false);
2015 dwc3_gadget_usb3_phy_suspend(dwc
, false);
2018 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
)
2019 dwc3_disconnect_gadget(dwc
);
2021 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2022 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2023 reg
&= ~(DWC3_DCTL_INITU1ENA
| DWC3_DCTL_INITU2ENA
);
2024 reg
|= (DWC3_DCTL_ACCEPTU1ENA
| DWC3_DCTL_ACCEPTU2ENA
);
2025 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2026 dwc
->test_mode
= false;
2028 dwc3_stop_active_transfers(dwc
);
2029 dwc3_clear_stall_all_ep(dwc
);
2030 dwc
->start_config_issued
= false;
2032 /* Reset device address to zero */
2033 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2034 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2035 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2038 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2041 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2044 * We change the clock only at SS but I dunno why I would want to do
2045 * this. Maybe it becomes part of the power saving plan.
2048 if (speed
!= DWC3_DSTS_SUPERSPEED
)
2052 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2053 * each time on Connect Done.
2058 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2059 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2060 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2063 static void dwc3_gadget_phy_suspend(struct dwc3
*dwc
, u8 speed
)
2066 case USB_SPEED_SUPER
:
2067 dwc3_gadget_usb2_phy_suspend(dwc
, true);
2069 case USB_SPEED_HIGH
:
2070 case USB_SPEED_FULL
:
2072 dwc3_gadget_usb3_phy_suspend(dwc
, true);
2077 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2079 struct dwc3_gadget_ep_cmd_params params
;
2080 struct dwc3_ep
*dep
;
2085 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2087 memset(¶ms
, 0x00, sizeof(params
));
2089 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2090 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2093 dwc3_update_ram_clk_sel(dwc
, speed
);
2096 case DWC3_DCFG_SUPERSPEED
:
2098 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2099 * would cause a missing USB3 Reset event.
2101 * In such situations, we should force a USB3 Reset
2102 * event by calling our dwc3_gadget_reset_interrupt()
2107 * STAR#9000483510: RTL: SS : USB3 reset event may
2108 * not be generated always when the link enters poll
2110 if (dwc
->revision
< DWC3_REVISION_190A
)
2111 dwc3_gadget_reset_interrupt(dwc
);
2113 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2114 dwc
->gadget
.ep0
->maxpacket
= 512;
2115 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2117 case DWC3_DCFG_HIGHSPEED
:
2118 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2119 dwc
->gadget
.ep0
->maxpacket
= 64;
2120 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2122 case DWC3_DCFG_FULLSPEED2
:
2123 case DWC3_DCFG_FULLSPEED1
:
2124 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2125 dwc
->gadget
.ep0
->maxpacket
= 64;
2126 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2128 case DWC3_DCFG_LOWSPEED
:
2129 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2130 dwc
->gadget
.ep0
->maxpacket
= 8;
2131 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2135 /* Recent versions support automatic phy suspend and don't need this */
2136 if (dwc
->revision
< DWC3_REVISION_194A
) {
2137 /* Suspend unneeded PHY */
2138 dwc3_gadget_phy_suspend(dwc
, dwc
->gadget
.speed
);
2142 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
2144 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2149 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
2151 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2156 * Configure PHY via GUSB3PIPECTLn if required.
2158 * Update GTXFIFOSIZn
2160 * In both cases reset values should be sufficient.
2164 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2166 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2169 * TODO take core out of low power mode when that's
2173 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2176 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2177 unsigned int evtinfo
)
2179 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2182 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2183 * on the link partner, the USB session might do multiple entry/exit
2184 * of low power states before a transfer takes place.
2186 * Due to this problem, we might experience lower throughput. The
2187 * suggested workaround is to disable DCTL[12:9] bits if we're
2188 * transitioning from U1/U2 to U0 and enable those bits again
2189 * after a transfer completes and there are no pending transfers
2190 * on any of the enabled endpoints.
2192 * This is the first half of that workaround.
2196 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2197 * core send LGO_Ux entering U0
2199 if (dwc
->revision
< DWC3_REVISION_183A
) {
2200 if (next
== DWC3_LINK_STATE_U0
) {
2204 switch (dwc
->link_state
) {
2205 case DWC3_LINK_STATE_U1
:
2206 case DWC3_LINK_STATE_U2
:
2207 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2208 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2209 | DWC3_DCTL_ACCEPTU2ENA
2210 | DWC3_DCTL_INITU1ENA
2211 | DWC3_DCTL_ACCEPTU1ENA
);
2214 dwc
->u1u2
= reg
& u1u2
;
2218 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2227 dwc
->link_state
= next
;
2229 dev_vdbg(dwc
->dev
, "%s link %d\n", __func__
, dwc
->link_state
);
2232 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2233 const struct dwc3_event_devt
*event
)
2235 switch (event
->type
) {
2236 case DWC3_DEVICE_EVENT_DISCONNECT
:
2237 dwc3_gadget_disconnect_interrupt(dwc
);
2239 case DWC3_DEVICE_EVENT_RESET
:
2240 dwc3_gadget_reset_interrupt(dwc
);
2242 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2243 dwc3_gadget_conndone_interrupt(dwc
);
2245 case DWC3_DEVICE_EVENT_WAKEUP
:
2246 dwc3_gadget_wakeup_interrupt(dwc
);
2248 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2249 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2251 case DWC3_DEVICE_EVENT_EOPF
:
2252 dev_vdbg(dwc
->dev
, "End of Periodic Frame\n");
2254 case DWC3_DEVICE_EVENT_SOF
:
2255 dev_vdbg(dwc
->dev
, "Start of Periodic Frame\n");
2257 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2258 dev_vdbg(dwc
->dev
, "Erratic Error\n");
2260 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2261 dev_vdbg(dwc
->dev
, "Command Complete\n");
2263 case DWC3_DEVICE_EVENT_OVERFLOW
:
2264 dev_vdbg(dwc
->dev
, "Overflow\n");
2267 dev_dbg(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2271 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2272 const union dwc3_event
*event
)
2274 /* Endpoint IRQ, handle it and return early */
2275 if (event
->type
.is_devspec
== 0) {
2277 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2280 switch (event
->type
.type
) {
2281 case DWC3_EVENT_TYPE_DEV
:
2282 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2284 /* REVISIT what to do with Carkit and I2C events ? */
2286 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2290 static irqreturn_t
dwc3_process_event_buf(struct dwc3
*dwc
, u32 buf
)
2292 struct dwc3_event_buffer
*evt
;
2296 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(buf
));
2297 count
&= DWC3_GEVNTCOUNT_MASK
;
2301 evt
= dwc
->ev_buffs
[buf
];
2305 union dwc3_event event
;
2307 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2309 dwc3_process_event_entry(dwc
, &event
);
2311 * XXX we wrap around correctly to the next entry as almost all
2312 * entries are 4 bytes in size. There is one entry which has 12
2313 * bytes which is a regular entry followed by 8 bytes data. ATM
2314 * I don't know how things are organized if were get next to the
2315 * a boundary so I worry about that once we try to handle that.
2317 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2320 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(buf
), 4);
2326 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
)
2328 struct dwc3
*dwc
= _dwc
;
2330 irqreturn_t ret
= IRQ_NONE
;
2332 spin_lock(&dwc
->lock
);
2334 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2337 status
= dwc3_process_event_buf(dwc
, i
);
2338 if (status
== IRQ_HANDLED
)
2342 spin_unlock(&dwc
->lock
);
2348 * dwc3_gadget_init - Initializes gadget related registers
2349 * @dwc: pointer to our controller context structure
2351 * Returns 0 on success otherwise negative errno.
2353 int __devinit
dwc3_gadget_init(struct dwc3
*dwc
)
2359 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2360 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2361 if (!dwc
->ctrl_req
) {
2362 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2367 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2368 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2369 if (!dwc
->ep0_trb
) {
2370 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2375 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2376 if (!dwc
->setup_buf
) {
2377 dev_err(dwc
->dev
, "failed to allocate setup buffer\n");
2382 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2383 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2385 if (!dwc
->ep0_bounce
) {
2386 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2391 dev_set_name(&dwc
->gadget
.dev
, "gadget");
2393 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2394 dwc
->gadget
.max_speed
= USB_SPEED_SUPER
;
2395 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2396 dwc
->gadget
.dev
.parent
= dwc
->dev
;
2397 dwc
->gadget
.sg_supported
= true;
2399 dma_set_coherent_mask(&dwc
->gadget
.dev
, dwc
->dev
->coherent_dma_mask
);
2401 dwc
->gadget
.dev
.dma_parms
= dwc
->dev
->dma_parms
;
2402 dwc
->gadget
.dev
.dma_mask
= dwc
->dev
->dma_mask
;
2403 dwc
->gadget
.dev
.release
= dwc3_gadget_release
;
2404 dwc
->gadget
.name
= "dwc3-gadget";
2407 * REVISIT: Here we should clear all pending IRQs to be
2408 * sure we're starting from a well known location.
2411 ret
= dwc3_gadget_init_endpoints(dwc
);
2415 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
2417 ret
= request_irq(irq
, dwc3_interrupt
, IRQF_SHARED
,
2420 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
2425 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2426 reg
|= DWC3_DCFG_LPM_CAP
;
2427 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2429 /* Enable all but Start and End of Frame IRQs */
2430 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
2431 DWC3_DEVTEN_EVNTOVERFLOWEN
|
2432 DWC3_DEVTEN_CMDCMPLTEN
|
2433 DWC3_DEVTEN_ERRTICERREN
|
2434 DWC3_DEVTEN_WKUPEVTEN
|
2435 DWC3_DEVTEN_ULSTCNGEN
|
2436 DWC3_DEVTEN_CONNECTDONEEN
|
2437 DWC3_DEVTEN_USBRSTEN
|
2438 DWC3_DEVTEN_DISCONNEVTEN
);
2439 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
2441 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2442 if (dwc
->revision
>= DWC3_REVISION_194A
) {
2443 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2444 reg
|= DWC3_DCFG_LPM_CAP
;
2445 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2447 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2448 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2450 /* TODO: This should be configurable */
2451 reg
|= DWC3_DCTL_HIRD_THRES(31);
2453 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2455 dwc3_gadget_usb2_phy_suspend(dwc
, false);
2456 dwc3_gadget_usb3_phy_suspend(dwc
, false);
2459 ret
= device_register(&dwc
->gadget
.dev
);
2461 dev_err(dwc
->dev
, "failed to register gadget device\n");
2462 put_device(&dwc
->gadget
.dev
);
2466 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2468 dev_err(dwc
->dev
, "failed to register udc\n");
2475 device_unregister(&dwc
->gadget
.dev
);
2478 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2482 dwc3_gadget_free_endpoints(dwc
);
2485 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2486 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2489 kfree(dwc
->setup_buf
);
2492 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2493 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2496 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2497 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2503 void dwc3_gadget_exit(struct dwc3
*dwc
)
2507 usb_del_gadget_udc(&dwc
->gadget
);
2508 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
2510 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2513 dwc3_gadget_free_endpoints(dwc
);
2515 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2516 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2518 kfree(dwc
->setup_buf
);
2520 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2521 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2523 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2524 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2526 device_unregister(&dwc
->gadget
.dev
);