2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24 * can be used with gadget ether.
28 /* #define UDC_VERBOSE */
31 #define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
32 #define UDC_DRIVER_VERSION_STRING "01.00.0206"
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/ioport.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/errno.h>
43 #include <linux/init.h>
44 #include <linux/timer.h>
45 #include <linux/list.h>
46 #include <linux/interrupt.h>
47 #include <linux/ioctl.h>
49 #include <linux/dmapool.h>
50 #include <linux/moduleparam.h>
51 #include <linux/device.h>
53 #include <linux/irq.h>
54 #include <linux/prefetch.h>
56 #include <asm/byteorder.h>
57 #include <asm/unaligned.h>
60 #include <linux/usb/ch9.h>
61 #include <linux/usb/gadget.h>
64 #include "amd5536udc.h"
67 static void udc_tasklet_disconnect(unsigned long);
68 static void empty_req_queue(struct udc_ep
*);
69 static int udc_probe(struct udc
*dev
);
70 static void udc_basic_init(struct udc
*dev
);
71 static void udc_setup_endpoints(struct udc
*dev
);
72 static void udc_soft_reset(struct udc
*dev
);
73 static struct udc_request
*udc_alloc_bna_dummy(struct udc_ep
*ep
);
74 static void udc_free_request(struct usb_ep
*usbep
, struct usb_request
*usbreq
);
75 static int udc_free_dma_chain(struct udc
*dev
, struct udc_request
*req
);
76 static int udc_create_dma_chain(struct udc_ep
*ep
, struct udc_request
*req
,
77 unsigned long buf_len
, gfp_t gfp_flags
);
78 static int udc_remote_wakeup(struct udc
*dev
);
79 static int udc_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
);
80 static void udc_pci_remove(struct pci_dev
*pdev
);
83 static const char mod_desc
[] = UDC_MOD_DESCRIPTION
;
84 static const char name
[] = "amd5536udc";
86 /* structure to hold endpoint function pointers */
87 static const struct usb_ep_ops udc_ep_ops
;
89 /* received setup data */
90 static union udc_setup_data setup_data
;
92 /* pointer to device object */
93 static struct udc
*udc
;
95 /* irq spin lock for soft reset */
96 static DEFINE_SPINLOCK(udc_irq_spinlock
);
98 static DEFINE_SPINLOCK(udc_stall_spinlock
);
101 * slave mode: pending bytes in rx fifo after nyet,
102 * used if EPIN irq came but no req was available
104 static unsigned int udc_rxfifo_pending
;
106 /* count soft resets after suspend to avoid loop */
107 static int soft_reset_occured
;
108 static int soft_reset_after_usbreset_occured
;
111 static struct timer_list udc_timer
;
112 static int stop_timer
;
114 /* set_rde -- Is used to control enabling of RX DMA. Problem is
115 * that UDC has only one bit (RDE) to enable/disable RX DMA for
116 * all OUT endpoints. So we have to handle race conditions like
117 * when OUT data reaches the fifo but no request was queued yet.
118 * This cannot be solved by letting the RX DMA disabled until a
119 * request gets queued because there may be other OUT packets
120 * in the FIFO (important for not blocking control traffic).
121 * The value of set_rde controls the correspondig timer.
123 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
124 * set_rde 0 == do not touch RDE, do no start the RDE timer
125 * set_rde 1 == timer function will look whether FIFO has data
126 * set_rde 2 == set by timer function to enable RX DMA on next call
128 static int set_rde
= -1;
130 static DECLARE_COMPLETION(on_exit
);
131 static struct timer_list udc_pollstall_timer
;
132 static int stop_pollstall_timer
;
133 static DECLARE_COMPLETION(on_pollstall_exit
);
135 /* tasklet for usb disconnect */
136 static DECLARE_TASKLET(disconnect_tasklet
, udc_tasklet_disconnect
,
137 (unsigned long) &udc
);
140 /* endpoint names used for print */
141 static const char ep0_string
[] = "ep0in";
142 static const char *const ep_string
[] = {
144 "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
145 "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
146 "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
147 "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
148 "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
149 "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
150 "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
154 static bool use_dma
= 1;
155 /* packet per buffer dma */
156 static bool use_dma_ppb
= 1;
157 /* with per descr. update */
158 static bool use_dma_ppb_du
;
159 /* buffer fill mode */
160 static int use_dma_bufferfill_mode
;
161 /* full speed only mode */
162 static bool use_fullspeed
;
163 /* tx buffer size for high speed */
164 static unsigned long hs_tx_buf
= UDC_EPIN_BUFF_SIZE
;
166 /* module parameters */
167 module_param(use_dma
, bool, S_IRUGO
);
168 MODULE_PARM_DESC(use_dma
, "true for DMA");
169 module_param(use_dma_ppb
, bool, S_IRUGO
);
170 MODULE_PARM_DESC(use_dma_ppb
, "true for DMA in packet per buffer mode");
171 module_param(use_dma_ppb_du
, bool, S_IRUGO
);
172 MODULE_PARM_DESC(use_dma_ppb_du
,
173 "true for DMA in packet per buffer mode with descriptor update");
174 module_param(use_fullspeed
, bool, S_IRUGO
);
175 MODULE_PARM_DESC(use_fullspeed
, "true for fullspeed only");
177 /*---------------------------------------------------------------------------*/
178 /* Prints UDC device registers and endpoint irq registers */
179 static void print_regs(struct udc
*dev
)
181 DBG(dev
, "------- Device registers -------\n");
182 DBG(dev
, "dev config = %08x\n", readl(&dev
->regs
->cfg
));
183 DBG(dev
, "dev control = %08x\n", readl(&dev
->regs
->ctl
));
184 DBG(dev
, "dev status = %08x\n", readl(&dev
->regs
->sts
));
186 DBG(dev
, "dev int's = %08x\n", readl(&dev
->regs
->irqsts
));
187 DBG(dev
, "dev intmask = %08x\n", readl(&dev
->regs
->irqmsk
));
189 DBG(dev
, "dev ep int's = %08x\n", readl(&dev
->regs
->ep_irqsts
));
190 DBG(dev
, "dev ep intmask = %08x\n", readl(&dev
->regs
->ep_irqmsk
));
192 DBG(dev
, "USE DMA = %d\n", use_dma
);
193 if (use_dma
&& use_dma_ppb
&& !use_dma_ppb_du
) {
194 DBG(dev
, "DMA mode = PPBNDU (packet per buffer "
195 "WITHOUT desc. update)\n");
196 dev_info(&dev
->pdev
->dev
, "DMA mode (%s)\n", "PPBNDU");
197 } else if (use_dma
&& use_dma_ppb
&& use_dma_ppb_du
) {
198 DBG(dev
, "DMA mode = PPBDU (packet per buffer "
199 "WITH desc. update)\n");
200 dev_info(&dev
->pdev
->dev
, "DMA mode (%s)\n", "PPBDU");
202 if (use_dma
&& use_dma_bufferfill_mode
) {
203 DBG(dev
, "DMA mode = BF (buffer fill mode)\n");
204 dev_info(&dev
->pdev
->dev
, "DMA mode (%s)\n", "BF");
207 dev_info(&dev
->pdev
->dev
, "FIFO mode\n");
208 DBG(dev
, "-------------------------------------------------------\n");
211 /* Masks unused interrupts */
212 static int udc_mask_unused_interrupts(struct udc
*dev
)
216 /* mask all dev interrupts */
217 tmp
= AMD_BIT(UDC_DEVINT_SVC
) |
218 AMD_BIT(UDC_DEVINT_ENUM
) |
219 AMD_BIT(UDC_DEVINT_US
) |
220 AMD_BIT(UDC_DEVINT_UR
) |
221 AMD_BIT(UDC_DEVINT_ES
) |
222 AMD_BIT(UDC_DEVINT_SI
) |
223 AMD_BIT(UDC_DEVINT_SOF
)|
224 AMD_BIT(UDC_DEVINT_SC
);
225 writel(tmp
, &dev
->regs
->irqmsk
);
227 /* mask all ep interrupts */
228 writel(UDC_EPINT_MSK_DISABLE_ALL
, &dev
->regs
->ep_irqmsk
);
233 /* Enables endpoint 0 interrupts */
234 static int udc_enable_ep0_interrupts(struct udc
*dev
)
238 DBG(dev
, "udc_enable_ep0_interrupts()\n");
241 tmp
= readl(&dev
->regs
->ep_irqmsk
);
242 /* enable ep0 irq's */
243 tmp
&= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0
)
244 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0
);
245 writel(tmp
, &dev
->regs
->ep_irqmsk
);
250 /* Enables device interrupts for SET_INTF and SET_CONFIG */
251 static int udc_enable_dev_setup_interrupts(struct udc
*dev
)
255 DBG(dev
, "enable device interrupts for setup data\n");
258 tmp
= readl(&dev
->regs
->irqmsk
);
260 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
261 tmp
&= AMD_UNMASK_BIT(UDC_DEVINT_SI
)
262 & AMD_UNMASK_BIT(UDC_DEVINT_SC
)
263 & AMD_UNMASK_BIT(UDC_DEVINT_UR
)
264 & AMD_UNMASK_BIT(UDC_DEVINT_SVC
)
265 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM
);
266 writel(tmp
, &dev
->regs
->irqmsk
);
271 /* Calculates fifo start of endpoint based on preceding endpoints */
272 static int udc_set_txfifo_addr(struct udc_ep
*ep
)
278 if (!ep
|| !(ep
->in
))
282 ep
->txfifo
= dev
->txfifo
;
285 for (i
= 0; i
< ep
->num
; i
++) {
286 if (dev
->ep
[i
].regs
) {
288 tmp
= readl(&dev
->ep
[i
].regs
->bufin_framenum
);
289 tmp
= AMD_GETBITS(tmp
, UDC_EPIN_BUFF_SIZE
);
296 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
297 static u32 cnak_pending
;
299 static void UDC_QUEUE_CNAK(struct udc_ep
*ep
, unsigned num
)
301 if (readl(&ep
->regs
->ctl
) & AMD_BIT(UDC_EPCTL_NAK
)) {
302 DBG(ep
->dev
, "NAK could not be cleared for ep%d\n", num
);
303 cnak_pending
|= 1 << (num
);
306 cnak_pending
= cnak_pending
& (~(1 << (num
)));
310 /* Enables endpoint, is called by gadget driver */
312 udc_ep_enable(struct usb_ep
*usbep
, const struct usb_endpoint_descriptor
*desc
)
317 unsigned long iflags
;
322 || usbep
->name
== ep0_string
324 || desc
->bDescriptorType
!= USB_DT_ENDPOINT
)
327 ep
= container_of(usbep
, struct udc_ep
, ep
);
330 DBG(dev
, "udc_ep_enable() ep %d\n", ep
->num
);
332 if (!dev
->driver
|| dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)
335 spin_lock_irqsave(&dev
->lock
, iflags
);
340 /* set traffic type */
341 tmp
= readl(&dev
->ep
[ep
->num
].regs
->ctl
);
342 tmp
= AMD_ADDBITS(tmp
, desc
->bmAttributes
, UDC_EPCTL_ET
);
343 writel(tmp
, &dev
->ep
[ep
->num
].regs
->ctl
);
345 /* set max packet size */
346 maxpacket
= usb_endpoint_maxp(desc
);
347 tmp
= readl(&dev
->ep
[ep
->num
].regs
->bufout_maxpkt
);
348 tmp
= AMD_ADDBITS(tmp
, maxpacket
, UDC_EP_MAX_PKT_SIZE
);
349 ep
->ep
.maxpacket
= maxpacket
;
350 writel(tmp
, &dev
->ep
[ep
->num
].regs
->bufout_maxpkt
);
355 /* ep ix in UDC CSR register space */
356 udc_csr_epix
= ep
->num
;
358 /* set buffer size (tx fifo entries) */
359 tmp
= readl(&dev
->ep
[ep
->num
].regs
->bufin_framenum
);
360 /* double buffering: fifo size = 2 x max packet size */
363 maxpacket
* UDC_EPIN_BUFF_SIZE_MULT
366 writel(tmp
, &dev
->ep
[ep
->num
].regs
->bufin_framenum
);
368 /* calc. tx fifo base addr */
369 udc_set_txfifo_addr(ep
);
372 tmp
= readl(&ep
->regs
->ctl
);
373 tmp
|= AMD_BIT(UDC_EPCTL_F
);
374 writel(tmp
, &ep
->regs
->ctl
);
378 /* ep ix in UDC CSR register space */
379 udc_csr_epix
= ep
->num
- UDC_CSR_EP_OUT_IX_OFS
;
381 /* set max packet size UDC CSR */
382 tmp
= readl(&dev
->csr
->ne
[ep
->num
- UDC_CSR_EP_OUT_IX_OFS
]);
383 tmp
= AMD_ADDBITS(tmp
, maxpacket
,
385 writel(tmp
, &dev
->csr
->ne
[ep
->num
- UDC_CSR_EP_OUT_IX_OFS
]);
387 if (use_dma
&& !ep
->in
) {
388 /* alloc and init BNA dummy request */
389 ep
->bna_dummy_req
= udc_alloc_bna_dummy(ep
);
390 ep
->bna_occurred
= 0;
393 if (ep
->num
!= UDC_EP0OUT_IX
)
394 dev
->data_ep_enabled
= 1;
398 tmp
= readl(&dev
->csr
->ne
[udc_csr_epix
]);
400 tmp
= AMD_ADDBITS(tmp
, maxpacket
, UDC_CSR_NE_MAX_PKT
);
402 tmp
= AMD_ADDBITS(tmp
, desc
->bEndpointAddress
, UDC_CSR_NE_NUM
);
404 tmp
= AMD_ADDBITS(tmp
, ep
->in
, UDC_CSR_NE_DIR
);
406 tmp
= AMD_ADDBITS(tmp
, desc
->bmAttributes
, UDC_CSR_NE_TYPE
);
408 tmp
= AMD_ADDBITS(tmp
, ep
->dev
->cur_config
, UDC_CSR_NE_CFG
);
410 tmp
= AMD_ADDBITS(tmp
, ep
->dev
->cur_intf
, UDC_CSR_NE_INTF
);
412 tmp
= AMD_ADDBITS(tmp
, ep
->dev
->cur_alt
, UDC_CSR_NE_ALT
);
414 writel(tmp
, &dev
->csr
->ne
[udc_csr_epix
]);
417 tmp
= readl(&dev
->regs
->ep_irqmsk
);
418 tmp
&= AMD_UNMASK_BIT(ep
->num
);
419 writel(tmp
, &dev
->regs
->ep_irqmsk
);
422 * clear NAK by writing CNAK
423 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
425 if (!use_dma
|| ep
->in
) {
426 tmp
= readl(&ep
->regs
->ctl
);
427 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
428 writel(tmp
, &ep
->regs
->ctl
);
430 UDC_QUEUE_CNAK(ep
, ep
->num
);
432 tmp
= desc
->bEndpointAddress
;
433 DBG(dev
, "%s enabled\n", usbep
->name
);
435 spin_unlock_irqrestore(&dev
->lock
, iflags
);
439 /* Resets endpoint */
440 static void ep_init(struct udc_regs __iomem
*regs
, struct udc_ep
*ep
)
444 VDBG(ep
->dev
, "ep-%d reset\n", ep
->num
);
446 ep
->ep
.ops
= &udc_ep_ops
;
447 INIT_LIST_HEAD(&ep
->queue
);
449 ep
->ep
.maxpacket
= (u16
) ~0;
451 tmp
= readl(&ep
->regs
->ctl
);
452 tmp
|= AMD_BIT(UDC_EPCTL_SNAK
);
453 writel(tmp
, &ep
->regs
->ctl
);
456 /* disable interrupt */
457 tmp
= readl(®s
->ep_irqmsk
);
458 tmp
|= AMD_BIT(ep
->num
);
459 writel(tmp
, ®s
->ep_irqmsk
);
462 /* unset P and IN bit of potential former DMA */
463 tmp
= readl(&ep
->regs
->ctl
);
464 tmp
&= AMD_UNMASK_BIT(UDC_EPCTL_P
);
465 writel(tmp
, &ep
->regs
->ctl
);
467 tmp
= readl(&ep
->regs
->sts
);
468 tmp
|= AMD_BIT(UDC_EPSTS_IN
);
469 writel(tmp
, &ep
->regs
->sts
);
472 tmp
= readl(&ep
->regs
->ctl
);
473 tmp
|= AMD_BIT(UDC_EPCTL_F
);
474 writel(tmp
, &ep
->regs
->ctl
);
477 /* reset desc pointer */
478 writel(0, &ep
->regs
->desptr
);
481 /* Disables endpoint, is called by gadget driver */
482 static int udc_ep_disable(struct usb_ep
*usbep
)
484 struct udc_ep
*ep
= NULL
;
485 unsigned long iflags
;
490 ep
= container_of(usbep
, struct udc_ep
, ep
);
491 if (usbep
->name
== ep0_string
|| !ep
->ep
.desc
)
494 DBG(ep
->dev
, "Disable ep-%d\n", ep
->num
);
496 spin_lock_irqsave(&ep
->dev
->lock
, iflags
);
497 udc_free_request(&ep
->ep
, &ep
->bna_dummy_req
->req
);
499 ep_init(ep
->dev
->regs
, ep
);
500 spin_unlock_irqrestore(&ep
->dev
->lock
, iflags
);
505 /* Allocates request packet, called by gadget driver */
506 static struct usb_request
*
507 udc_alloc_request(struct usb_ep
*usbep
, gfp_t gfp
)
509 struct udc_request
*req
;
510 struct udc_data_dma
*dma_desc
;
516 ep
= container_of(usbep
, struct udc_ep
, ep
);
518 VDBG(ep
->dev
, "udc_alloc_req(): ep%d\n", ep
->num
);
519 req
= kzalloc(sizeof(struct udc_request
), gfp
);
523 req
->req
.dma
= DMA_DONT_USE
;
524 INIT_LIST_HEAD(&req
->queue
);
527 /* ep0 in requests are allocated from data pool here */
528 dma_desc
= pci_pool_alloc(ep
->dev
->data_requests
, gfp
,
535 VDBG(ep
->dev
, "udc_alloc_req: req = %p dma_desc = %p, "
538 (unsigned long)req
->td_phys
);
539 /* prevent from using desc. - set HOST BUSY */
540 dma_desc
->status
= AMD_ADDBITS(dma_desc
->status
,
541 UDC_DMA_STP_STS_BS_HOST_BUSY
,
543 dma_desc
->bufptr
= cpu_to_le32(DMA_DONT_USE
);
544 req
->td_data
= dma_desc
;
545 req
->td_data_last
= NULL
;
552 /* Frees request packet, called by gadget driver */
554 udc_free_request(struct usb_ep
*usbep
, struct usb_request
*usbreq
)
557 struct udc_request
*req
;
559 if (!usbep
|| !usbreq
)
562 ep
= container_of(usbep
, struct udc_ep
, ep
);
563 req
= container_of(usbreq
, struct udc_request
, req
);
564 VDBG(ep
->dev
, "free_req req=%p\n", req
);
565 BUG_ON(!list_empty(&req
->queue
));
567 VDBG(ep
->dev
, "req->td_data=%p\n", req
->td_data
);
569 /* free dma chain if created */
570 if (req
->chain_len
> 1)
571 udc_free_dma_chain(ep
->dev
, req
);
573 pci_pool_free(ep
->dev
->data_requests
, req
->td_data
,
579 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
580 static void udc_init_bna_dummy(struct udc_request
*req
)
584 req
->td_data
->status
|= AMD_BIT(UDC_DMA_IN_STS_L
);
585 /* set next pointer to itself */
586 req
->td_data
->next
= req
->td_phys
;
589 = AMD_ADDBITS(req
->td_data
->status
,
590 UDC_DMA_STP_STS_BS_DMA_DONE
,
593 pr_debug("bna desc = %p, sts = %08x\n",
594 req
->td_data
, req
->td_data
->status
);
599 /* Allocate BNA dummy descriptor */
600 static struct udc_request
*udc_alloc_bna_dummy(struct udc_ep
*ep
)
602 struct udc_request
*req
= NULL
;
603 struct usb_request
*_req
= NULL
;
605 /* alloc the dummy request */
606 _req
= udc_alloc_request(&ep
->ep
, GFP_ATOMIC
);
608 req
= container_of(_req
, struct udc_request
, req
);
609 ep
->bna_dummy_req
= req
;
610 udc_init_bna_dummy(req
);
615 /* Write data to TX fifo for IN packets */
617 udc_txfifo_write(struct udc_ep
*ep
, struct usb_request
*req
)
623 unsigned remaining
= 0;
628 req_buf
= req
->buf
+ req
->actual
;
630 remaining
= req
->length
- req
->actual
;
632 buf
= (u32
*) req_buf
;
634 bytes
= ep
->ep
.maxpacket
;
635 if (bytes
> remaining
)
639 for (i
= 0; i
< bytes
/ UDC_DWORD_BYTES
; i
++)
640 writel(*(buf
+ i
), ep
->txfifo
);
642 /* remaining bytes must be written by byte access */
643 for (j
= 0; j
< bytes
% UDC_DWORD_BYTES
; j
++) {
644 writeb((u8
)(*(buf
+ i
) >> (j
<< UDC_BITS_PER_BYTE_SHIFT
)),
648 /* dummy write confirm */
649 writel(0, &ep
->regs
->confirm
);
652 /* Read dwords from RX fifo for OUT transfers */
653 static int udc_rxfifo_read_dwords(struct udc
*dev
, u32
*buf
, int dwords
)
657 VDBG(dev
, "udc_read_dwords(): %d dwords\n", dwords
);
659 for (i
= 0; i
< dwords
; i
++)
660 *(buf
+ i
) = readl(dev
->rxfifo
);
664 /* Read bytes from RX fifo for OUT transfers */
665 static int udc_rxfifo_read_bytes(struct udc
*dev
, u8
*buf
, int bytes
)
670 VDBG(dev
, "udc_read_bytes(): %d bytes\n", bytes
);
673 for (i
= 0; i
< bytes
/ UDC_DWORD_BYTES
; i
++)
674 *((u32
*)(buf
+ (i
<<2))) = readl(dev
->rxfifo
);
676 /* remaining bytes must be read by byte access */
677 if (bytes
% UDC_DWORD_BYTES
) {
678 tmp
= readl(dev
->rxfifo
);
679 for (j
= 0; j
< bytes
% UDC_DWORD_BYTES
; j
++) {
680 *(buf
+ (i
<<2) + j
) = (u8
)(tmp
& UDC_BYTE_MASK
);
681 tmp
= tmp
>> UDC_BITS_PER_BYTE
;
688 /* Read data from RX fifo for OUT transfers */
690 udc_rxfifo_read(struct udc_ep
*ep
, struct udc_request
*req
)
695 unsigned finished
= 0;
697 /* received number bytes */
698 bytes
= readl(&ep
->regs
->sts
);
699 bytes
= AMD_GETBITS(bytes
, UDC_EPSTS_RX_PKT_SIZE
);
701 buf_space
= req
->req
.length
- req
->req
.actual
;
702 buf
= req
->req
.buf
+ req
->req
.actual
;
703 if (bytes
> buf_space
) {
704 if ((buf_space
% ep
->ep
.maxpacket
) != 0) {
706 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
707 ep
->ep
.name
, bytes
, buf_space
);
708 req
->req
.status
= -EOVERFLOW
;
712 req
->req
.actual
+= bytes
;
715 if (((bytes
% ep
->ep
.maxpacket
) != 0) || (!bytes
)
716 || ((req
->req
.actual
== req
->req
.length
) && !req
->req
.zero
))
719 /* read rx fifo bytes */
720 VDBG(ep
->dev
, "ep %s: rxfifo read %d bytes\n", ep
->ep
.name
, bytes
);
721 udc_rxfifo_read_bytes(ep
->dev
, buf
, bytes
);
726 /* create/re-init a DMA descriptor or a DMA descriptor chain */
727 static int prep_dma(struct udc_ep
*ep
, struct udc_request
*req
, gfp_t gfp
)
732 VDBG(ep
->dev
, "prep_dma\n");
733 VDBG(ep
->dev
, "prep_dma ep%d req->td_data=%p\n",
734 ep
->num
, req
->td_data
);
736 /* set buffer pointer */
737 req
->td_data
->bufptr
= req
->req
.dma
;
740 req
->td_data
->status
|= AMD_BIT(UDC_DMA_IN_STS_L
);
742 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
745 retval
= udc_create_dma_chain(ep
, req
, ep
->ep
.maxpacket
, gfp
);
747 if (retval
== -ENOMEM
)
748 DBG(ep
->dev
, "Out of DMA memory\n");
752 if (req
->req
.length
== ep
->ep
.maxpacket
) {
754 req
->td_data
->status
=
755 AMD_ADDBITS(req
->td_data
->status
,
757 UDC_DMA_IN_STS_TXBYTES
);
765 VDBG(ep
->dev
, "IN: use_dma_ppb=%d req->req.len=%d "
766 "maxpacket=%d ep%d\n",
767 use_dma_ppb
, req
->req
.length
,
768 ep
->ep
.maxpacket
, ep
->num
);
770 * if bytes < max packet then tx bytes must
771 * be written in packet per buffer mode
773 if (!use_dma_ppb
|| req
->req
.length
< ep
->ep
.maxpacket
774 || ep
->num
== UDC_EP0OUT_IX
775 || ep
->num
== UDC_EP0IN_IX
) {
777 req
->td_data
->status
=
778 AMD_ADDBITS(req
->td_data
->status
,
780 UDC_DMA_IN_STS_TXBYTES
);
781 /* reset frame num */
782 req
->td_data
->status
=
783 AMD_ADDBITS(req
->td_data
->status
,
785 UDC_DMA_IN_STS_FRAMENUM
);
788 req
->td_data
->status
=
789 AMD_ADDBITS(req
->td_data
->status
,
790 UDC_DMA_STP_STS_BS_HOST_BUSY
,
793 VDBG(ep
->dev
, "OUT set host ready\n");
795 req
->td_data
->status
=
796 AMD_ADDBITS(req
->td_data
->status
,
797 UDC_DMA_STP_STS_BS_HOST_READY
,
801 /* clear NAK by writing CNAK */
803 tmp
= readl(&ep
->regs
->ctl
);
804 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
805 writel(tmp
, &ep
->regs
->ctl
);
807 UDC_QUEUE_CNAK(ep
, ep
->num
);
815 /* Completes request packet ... caller MUST hold lock */
817 complete_req(struct udc_ep
*ep
, struct udc_request
*req
, int sts
)
818 __releases(ep
->dev
->lock
)
819 __acquires(ep
->dev
->lock
)
824 VDBG(ep
->dev
, "complete_req(): ep%d\n", ep
->num
);
829 usb_gadget_unmap_request(&dev
->gadget
, &req
->req
, ep
->in
);
834 /* set new status if pending */
835 if (req
->req
.status
== -EINPROGRESS
)
836 req
->req
.status
= sts
;
838 /* remove from ep queue */
839 list_del_init(&req
->queue
);
841 VDBG(ep
->dev
, "req %p => complete %d bytes at %s with sts %d\n",
842 &req
->req
, req
->req
.length
, ep
->ep
.name
, sts
);
844 spin_unlock(&dev
->lock
);
845 req
->req
.complete(&ep
->ep
, &req
->req
);
846 spin_lock(&dev
->lock
);
850 /* frees pci pool descriptors of a DMA chain */
851 static int udc_free_dma_chain(struct udc
*dev
, struct udc_request
*req
)
855 struct udc_data_dma
*td
;
856 struct udc_data_dma
*td_last
= NULL
;
859 DBG(dev
, "free chain req = %p\n", req
);
861 /* do not free first desc., will be done by free for request */
862 td_last
= req
->td_data
;
863 td
= phys_to_virt(td_last
->next
);
865 for (i
= 1; i
< req
->chain_len
; i
++) {
867 pci_pool_free(dev
->data_requests
, td
,
868 (dma_addr_t
) td_last
->next
);
870 td
= phys_to_virt(td_last
->next
);
876 /* Iterates to the end of a DMA chain and returns last descriptor */
877 static struct udc_data_dma
*udc_get_last_dma_desc(struct udc_request
*req
)
879 struct udc_data_dma
*td
;
882 while (td
&& !(td
->status
& AMD_BIT(UDC_DMA_IN_STS_L
)))
883 td
= phys_to_virt(td
->next
);
889 /* Iterates to the end of a DMA chain and counts bytes received */
890 static u32
udc_get_ppbdu_rxbytes(struct udc_request
*req
)
892 struct udc_data_dma
*td
;
896 /* received number bytes */
897 count
= AMD_GETBITS(td
->status
, UDC_DMA_OUT_STS_RXBYTES
);
899 while (td
&& !(td
->status
& AMD_BIT(UDC_DMA_IN_STS_L
))) {
900 td
= phys_to_virt(td
->next
);
901 /* received number bytes */
903 count
+= AMD_GETBITS(td
->status
,
904 UDC_DMA_OUT_STS_RXBYTES
);
912 /* Creates or re-inits a DMA chain */
913 static int udc_create_dma_chain(
915 struct udc_request
*req
,
916 unsigned long buf_len
, gfp_t gfp_flags
919 unsigned long bytes
= req
->req
.length
;
922 struct udc_data_dma
*td
= NULL
;
923 struct udc_data_dma
*last
= NULL
;
924 unsigned long txbytes
;
925 unsigned create_new_chain
= 0;
928 VDBG(ep
->dev
, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
930 dma_addr
= DMA_DONT_USE
;
932 /* unset L bit in first desc for OUT */
934 req
->td_data
->status
&= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L
);
936 /* alloc only new desc's if not already available */
937 len
= req
->req
.length
/ ep
->ep
.maxpacket
;
938 if (req
->req
.length
% ep
->ep
.maxpacket
)
941 if (len
> req
->chain_len
) {
942 /* shorter chain already allocated before */
943 if (req
->chain_len
> 1)
944 udc_free_dma_chain(ep
->dev
, req
);
945 req
->chain_len
= len
;
946 create_new_chain
= 1;
950 /* gen. required number of descriptors and buffers */
951 for (i
= buf_len
; i
< bytes
; i
+= buf_len
) {
952 /* create or determine next desc. */
953 if (create_new_chain
) {
955 td
= pci_pool_alloc(ep
->dev
->data_requests
,
956 gfp_flags
, &dma_addr
);
961 } else if (i
== buf_len
) {
963 td
= (struct udc_data_dma
*) phys_to_virt(
967 td
= (struct udc_data_dma
*) phys_to_virt(last
->next
);
973 td
->bufptr
= req
->req
.dma
+ i
; /* assign buffer */
978 if ((bytes
- i
) >= buf_len
) {
985 /* link td and assign tx bytes */
987 if (create_new_chain
)
988 req
->td_data
->next
= dma_addr
;
991 req->td_data->next = virt_to_phys(td);
996 req
->td_data
->status
=
997 AMD_ADDBITS(req
->td_data
->status
,
999 UDC_DMA_IN_STS_TXBYTES
);
1001 td
->status
= AMD_ADDBITS(td
->status
,
1003 UDC_DMA_IN_STS_TXBYTES
);
1006 if (create_new_chain
)
1007 last
->next
= dma_addr
;
1010 last->next = virt_to_phys(td);
1013 /* write tx bytes */
1014 td
->status
= AMD_ADDBITS(td
->status
,
1016 UDC_DMA_IN_STS_TXBYTES
);
1023 td
->status
|= AMD_BIT(UDC_DMA_IN_STS_L
);
1024 /* last desc. points to itself */
1025 req
->td_data_last
= td
;
1031 /* Enabling RX DMA */
1032 static void udc_set_rde(struct udc
*dev
)
1036 VDBG(dev
, "udc_set_rde()\n");
1037 /* stop RDE timer */
1038 if (timer_pending(&udc_timer
)) {
1040 mod_timer(&udc_timer
, jiffies
- 1);
1043 tmp
= readl(&dev
->regs
->ctl
);
1044 tmp
|= AMD_BIT(UDC_DEVCTL_RDE
);
1045 writel(tmp
, &dev
->regs
->ctl
);
1048 /* Queues a request packet, called by gadget driver */
1050 udc_queue(struct usb_ep
*usbep
, struct usb_request
*usbreq
, gfp_t gfp
)
1054 unsigned long iflags
;
1056 struct udc_request
*req
;
1060 /* check the inputs */
1061 req
= container_of(usbreq
, struct udc_request
, req
);
1063 if (!usbep
|| !usbreq
|| !usbreq
->complete
|| !usbreq
->buf
1064 || !list_empty(&req
->queue
))
1067 ep
= container_of(usbep
, struct udc_ep
, ep
);
1068 if (!ep
->ep
.desc
&& (ep
->num
!= 0 && ep
->num
!= UDC_EP0OUT_IX
))
1071 VDBG(ep
->dev
, "udc_queue(): ep%d-in=%d\n", ep
->num
, ep
->in
);
1074 if (!dev
->driver
|| dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1077 /* map dma (usually done before) */
1079 VDBG(dev
, "DMA map req %p\n", req
);
1080 retval
= usb_gadget_map_request(&udc
->gadget
, usbreq
, ep
->in
);
1085 VDBG(dev
, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1086 usbep
->name
, usbreq
, usbreq
->length
,
1087 req
->td_data
, usbreq
->buf
);
1089 spin_lock_irqsave(&dev
->lock
, iflags
);
1091 usbreq
->status
= -EINPROGRESS
;
1094 /* on empty queue just do first transfer */
1095 if (list_empty(&ep
->queue
)) {
1097 if (usbreq
->length
== 0) {
1098 /* IN zlp's are handled by hardware */
1099 complete_req(ep
, req
, 0);
1100 VDBG(dev
, "%s: zlp\n", ep
->ep
.name
);
1102 * if set_config or set_intf is waiting for ack by zlp
1105 if (dev
->set_cfg_not_acked
) {
1106 tmp
= readl(&dev
->regs
->ctl
);
1107 tmp
|= AMD_BIT(UDC_DEVCTL_CSR_DONE
);
1108 writel(tmp
, &dev
->regs
->ctl
);
1109 dev
->set_cfg_not_acked
= 0;
1111 /* setup command is ACK'ed now by zlp */
1112 if (dev
->waiting_zlp_ack_ep0in
) {
1113 /* clear NAK by writing CNAK in EP0_IN */
1114 tmp
= readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
1115 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
1116 writel(tmp
, &dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
1117 dev
->ep
[UDC_EP0IN_IX
].naking
= 0;
1118 UDC_QUEUE_CNAK(&dev
->ep
[UDC_EP0IN_IX
],
1120 dev
->waiting_zlp_ack_ep0in
= 0;
1125 retval
= prep_dma(ep
, req
, gfp
);
1128 /* write desc pointer to enable DMA */
1130 /* set HOST READY */
1131 req
->td_data
->status
=
1132 AMD_ADDBITS(req
->td_data
->status
,
1133 UDC_DMA_IN_STS_BS_HOST_READY
,
1137 /* disabled rx dma while descriptor update */
1139 /* stop RDE timer */
1140 if (timer_pending(&udc_timer
)) {
1142 mod_timer(&udc_timer
, jiffies
- 1);
1145 tmp
= readl(&dev
->regs
->ctl
);
1146 tmp
&= AMD_UNMASK_BIT(UDC_DEVCTL_RDE
);
1147 writel(tmp
, &dev
->regs
->ctl
);
1151 * if BNA occurred then let BNA dummy desc.
1152 * point to current desc.
1154 if (ep
->bna_occurred
) {
1155 VDBG(dev
, "copy to BNA dummy desc.\n");
1156 memcpy(ep
->bna_dummy_req
->td_data
,
1158 sizeof(struct udc_data_dma
));
1161 /* write desc pointer */
1162 writel(req
->td_phys
, &ep
->regs
->desptr
);
1164 /* clear NAK by writing CNAK */
1166 tmp
= readl(&ep
->regs
->ctl
);
1167 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
1168 writel(tmp
, &ep
->regs
->ctl
);
1170 UDC_QUEUE_CNAK(ep
, ep
->num
);
1175 tmp
= readl(&dev
->regs
->ep_irqmsk
);
1176 tmp
&= AMD_UNMASK_BIT(ep
->num
);
1177 writel(tmp
, &dev
->regs
->ep_irqmsk
);
1179 } else if (ep
->in
) {
1181 tmp
= readl(&dev
->regs
->ep_irqmsk
);
1182 tmp
&= AMD_UNMASK_BIT(ep
->num
);
1183 writel(tmp
, &dev
->regs
->ep_irqmsk
);
1186 } else if (ep
->dma
) {
1189 * prep_dma not used for OUT ep's, this is not possible
1190 * for PPB modes, because of chain creation reasons
1193 retval
= prep_dma(ep
, req
, gfp
);
1198 VDBG(dev
, "list_add\n");
1199 /* add request to ep queue */
1202 list_add_tail(&req
->queue
, &ep
->queue
);
1204 /* open rxfifo if out data queued */
1209 if (ep
->num
!= UDC_EP0OUT_IX
)
1210 dev
->data_ep_queued
= 1;
1212 /* stop OUT naking */
1214 if (!use_dma
&& udc_rxfifo_pending
) {
1215 DBG(dev
, "udc_queue(): pending bytes in "
1216 "rxfifo after nyet\n");
1218 * read pending bytes afer nyet:
1221 if (udc_rxfifo_read(ep
, req
)) {
1223 complete_req(ep
, req
, 0);
1225 udc_rxfifo_pending
= 0;
1232 spin_unlock_irqrestore(&dev
->lock
, iflags
);
1236 /* Empty request queue of an endpoint; caller holds spinlock */
1237 static void empty_req_queue(struct udc_ep
*ep
)
1239 struct udc_request
*req
;
1242 while (!list_empty(&ep
->queue
)) {
1243 req
= list_entry(ep
->queue
.next
,
1246 complete_req(ep
, req
, -ESHUTDOWN
);
1250 /* Dequeues a request packet, called by gadget driver */
1251 static int udc_dequeue(struct usb_ep
*usbep
, struct usb_request
*usbreq
)
1254 struct udc_request
*req
;
1256 unsigned long iflags
;
1258 ep
= container_of(usbep
, struct udc_ep
, ep
);
1259 if (!usbep
|| !usbreq
|| (!ep
->ep
.desc
&& (ep
->num
!= 0
1260 && ep
->num
!= UDC_EP0OUT_IX
)))
1263 req
= container_of(usbreq
, struct udc_request
, req
);
1265 spin_lock_irqsave(&ep
->dev
->lock
, iflags
);
1266 halted
= ep
->halted
;
1268 /* request in processing or next one */
1269 if (ep
->queue
.next
== &req
->queue
) {
1270 if (ep
->dma
&& req
->dma_going
) {
1272 ep
->cancel_transfer
= 1;
1276 /* stop potential receive DMA */
1277 tmp
= readl(&udc
->regs
->ctl
);
1278 writel(tmp
& AMD_UNMASK_BIT(UDC_DEVCTL_RDE
),
1281 * Cancel transfer later in ISR
1282 * if descriptor was touched.
1284 dma_sts
= AMD_GETBITS(req
->td_data
->status
,
1285 UDC_DMA_OUT_STS_BS
);
1286 if (dma_sts
!= UDC_DMA_OUT_STS_BS_HOST_READY
)
1287 ep
->cancel_transfer
= 1;
1289 udc_init_bna_dummy(ep
->req
);
1290 writel(ep
->bna_dummy_req
->td_phys
,
1293 writel(tmp
, &udc
->regs
->ctl
);
1297 complete_req(ep
, req
, -ECONNRESET
);
1298 ep
->halted
= halted
;
1300 spin_unlock_irqrestore(&ep
->dev
->lock
, iflags
);
1304 /* Halt or clear halt of endpoint */
1306 udc_set_halt(struct usb_ep
*usbep
, int halt
)
1310 unsigned long iflags
;
1316 pr_debug("set_halt %s: halt=%d\n", usbep
->name
, halt
);
1318 ep
= container_of(usbep
, struct udc_ep
, ep
);
1319 if (!ep
->ep
.desc
&& (ep
->num
!= 0 && ep
->num
!= UDC_EP0OUT_IX
))
1321 if (!ep
->dev
->driver
|| ep
->dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1324 spin_lock_irqsave(&udc_stall_spinlock
, iflags
);
1325 /* halt or clear halt */
1328 ep
->dev
->stall_ep0in
= 1;
1332 * rxfifo empty not taken into acount
1334 tmp
= readl(&ep
->regs
->ctl
);
1335 tmp
|= AMD_BIT(UDC_EPCTL_S
);
1336 writel(tmp
, &ep
->regs
->ctl
);
1339 /* setup poll timer */
1340 if (!timer_pending(&udc_pollstall_timer
)) {
1341 udc_pollstall_timer
.expires
= jiffies
+
1342 HZ
* UDC_POLLSTALL_TIMER_USECONDS
1344 if (!stop_pollstall_timer
) {
1345 DBG(ep
->dev
, "start polltimer\n");
1346 add_timer(&udc_pollstall_timer
);
1351 /* ep is halted by set_halt() before */
1353 tmp
= readl(&ep
->regs
->ctl
);
1354 /* clear stall bit */
1355 tmp
= tmp
& AMD_CLEAR_BIT(UDC_EPCTL_S
);
1356 /* clear NAK by writing CNAK */
1357 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
1358 writel(tmp
, &ep
->regs
->ctl
);
1360 UDC_QUEUE_CNAK(ep
, ep
->num
);
1363 spin_unlock_irqrestore(&udc_stall_spinlock
, iflags
);
1367 /* gadget interface */
1368 static const struct usb_ep_ops udc_ep_ops
= {
1369 .enable
= udc_ep_enable
,
1370 .disable
= udc_ep_disable
,
1372 .alloc_request
= udc_alloc_request
,
1373 .free_request
= udc_free_request
,
1376 .dequeue
= udc_dequeue
,
1378 .set_halt
= udc_set_halt
,
1379 /* fifo ops not implemented */
1382 /*-------------------------------------------------------------------------*/
1384 /* Get frame counter (not implemented) */
1385 static int udc_get_frame(struct usb_gadget
*gadget
)
1390 /* Remote wakeup gadget interface */
1391 static int udc_wakeup(struct usb_gadget
*gadget
)
1397 dev
= container_of(gadget
, struct udc
, gadget
);
1398 udc_remote_wakeup(dev
);
1403 static int amd5536_udc_start(struct usb_gadget
*g
,
1404 struct usb_gadget_driver
*driver
);
1405 static int amd5536_udc_stop(struct usb_gadget
*g
,
1406 struct usb_gadget_driver
*driver
);
1407 /* gadget operations */
1408 static const struct usb_gadget_ops udc_ops
= {
1409 .wakeup
= udc_wakeup
,
1410 .get_frame
= udc_get_frame
,
1411 .udc_start
= amd5536_udc_start
,
1412 .udc_stop
= amd5536_udc_stop
,
1415 /* Setups endpoint parameters, adds endpoints to linked list */
1416 static void make_ep_lists(struct udc
*dev
)
1418 /* make gadget ep lists */
1419 INIT_LIST_HEAD(&dev
->gadget
.ep_list
);
1420 list_add_tail(&dev
->ep
[UDC_EPIN_STATUS_IX
].ep
.ep_list
,
1421 &dev
->gadget
.ep_list
);
1422 list_add_tail(&dev
->ep
[UDC_EPIN_IX
].ep
.ep_list
,
1423 &dev
->gadget
.ep_list
);
1424 list_add_tail(&dev
->ep
[UDC_EPOUT_IX
].ep
.ep_list
,
1425 &dev
->gadget
.ep_list
);
1428 dev
->ep
[UDC_EPIN_STATUS_IX
].fifo_depth
= UDC_EPIN_SMALLINT_BUFF_SIZE
;
1429 if (dev
->gadget
.speed
== USB_SPEED_FULL
)
1430 dev
->ep
[UDC_EPIN_IX
].fifo_depth
= UDC_FS_EPIN_BUFF_SIZE
;
1431 else if (dev
->gadget
.speed
== USB_SPEED_HIGH
)
1432 dev
->ep
[UDC_EPIN_IX
].fifo_depth
= hs_tx_buf
;
1433 dev
->ep
[UDC_EPOUT_IX
].fifo_depth
= UDC_RXFIFO_SIZE
;
1436 /* init registers at driver load time */
1437 static int startup_registers(struct udc
*dev
)
1441 /* init controller by soft reset */
1442 udc_soft_reset(dev
);
1444 /* mask not needed interrupts */
1445 udc_mask_unused_interrupts(dev
);
1447 /* put into initial config */
1448 udc_basic_init(dev
);
1449 /* link up all endpoints */
1450 udc_setup_endpoints(dev
);
1453 tmp
= readl(&dev
->regs
->cfg
);
1455 tmp
= AMD_ADDBITS(tmp
, UDC_DEVCFG_SPD_FS
, UDC_DEVCFG_SPD
);
1457 tmp
= AMD_ADDBITS(tmp
, UDC_DEVCFG_SPD_HS
, UDC_DEVCFG_SPD
);
1458 writel(tmp
, &dev
->regs
->cfg
);
1463 /* Inits UDC context */
1464 static void udc_basic_init(struct udc
*dev
)
1468 DBG(dev
, "udc_basic_init()\n");
1470 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1472 /* stop RDE timer */
1473 if (timer_pending(&udc_timer
)) {
1475 mod_timer(&udc_timer
, jiffies
- 1);
1477 /* stop poll stall timer */
1478 if (timer_pending(&udc_pollstall_timer
))
1479 mod_timer(&udc_pollstall_timer
, jiffies
- 1);
1481 tmp
= readl(&dev
->regs
->ctl
);
1482 tmp
&= AMD_UNMASK_BIT(UDC_DEVCTL_RDE
);
1483 tmp
&= AMD_UNMASK_BIT(UDC_DEVCTL_TDE
);
1484 writel(tmp
, &dev
->regs
->ctl
);
1486 /* enable dynamic CSR programming */
1487 tmp
= readl(&dev
->regs
->cfg
);
1488 tmp
|= AMD_BIT(UDC_DEVCFG_CSR_PRG
);
1489 /* set self powered */
1490 tmp
|= AMD_BIT(UDC_DEVCFG_SP
);
1491 /* set remote wakeupable */
1492 tmp
|= AMD_BIT(UDC_DEVCFG_RWKP
);
1493 writel(tmp
, &dev
->regs
->cfg
);
1497 dev
->data_ep_enabled
= 0;
1498 dev
->data_ep_queued
= 0;
1501 /* Sets initial endpoint parameters */
1502 static void udc_setup_endpoints(struct udc
*dev
)
1508 DBG(dev
, "udc_setup_endpoints()\n");
1510 /* read enum speed */
1511 tmp
= readl(&dev
->regs
->sts
);
1512 tmp
= AMD_GETBITS(tmp
, UDC_DEVSTS_ENUM_SPEED
);
1513 if (tmp
== UDC_DEVSTS_ENUM_SPEED_HIGH
)
1514 dev
->gadget
.speed
= USB_SPEED_HIGH
;
1515 else if (tmp
== UDC_DEVSTS_ENUM_SPEED_FULL
)
1516 dev
->gadget
.speed
= USB_SPEED_FULL
;
1518 /* set basic ep parameters */
1519 for (tmp
= 0; tmp
< UDC_EP_NUM
; tmp
++) {
1522 ep
->ep
.name
= ep_string
[tmp
];
1524 /* txfifo size is calculated at enable time */
1525 ep
->txfifo
= dev
->txfifo
;
1528 if (tmp
< UDC_EPIN_NUM
) {
1529 ep
->fifo_depth
= UDC_TXFIFO_SIZE
;
1532 ep
->fifo_depth
= UDC_RXFIFO_SIZE
;
1536 ep
->regs
= &dev
->ep_regs
[tmp
];
1538 * ep will be reset only if ep was not enabled before to avoid
1539 * disabling ep interrupts when ENUM interrupt occurs but ep is
1540 * not enabled by gadget driver
1543 ep_init(dev
->regs
, ep
);
1547 * ep->dma is not really used, just to indicate that
1548 * DMA is active: remove this
1549 * dma regs = dev control regs
1551 ep
->dma
= &dev
->regs
->ctl
;
1553 /* nak OUT endpoints until enable - not for ep0 */
1554 if (tmp
!= UDC_EP0IN_IX
&& tmp
!= UDC_EP0OUT_IX
1555 && tmp
> UDC_EPIN_NUM
) {
1557 reg
= readl(&dev
->ep
[tmp
].regs
->ctl
);
1558 reg
|= AMD_BIT(UDC_EPCTL_SNAK
);
1559 writel(reg
, &dev
->ep
[tmp
].regs
->ctl
);
1560 dev
->ep
[tmp
].naking
= 1;
1565 /* EP0 max packet */
1566 if (dev
->gadget
.speed
== USB_SPEED_FULL
) {
1567 dev
->ep
[UDC_EP0IN_IX
].ep
.maxpacket
= UDC_FS_EP0IN_MAX_PKT_SIZE
;
1568 dev
->ep
[UDC_EP0OUT_IX
].ep
.maxpacket
=
1569 UDC_FS_EP0OUT_MAX_PKT_SIZE
;
1570 } else if (dev
->gadget
.speed
== USB_SPEED_HIGH
) {
1571 dev
->ep
[UDC_EP0IN_IX
].ep
.maxpacket
= UDC_EP0IN_MAX_PKT_SIZE
;
1572 dev
->ep
[UDC_EP0OUT_IX
].ep
.maxpacket
= UDC_EP0OUT_MAX_PKT_SIZE
;
1576 * with suspend bug workaround, ep0 params for gadget driver
1577 * are set at gadget driver bind() call
1579 dev
->gadget
.ep0
= &dev
->ep
[UDC_EP0IN_IX
].ep
;
1580 dev
->ep
[UDC_EP0IN_IX
].halted
= 0;
1581 INIT_LIST_HEAD(&dev
->gadget
.ep0
->ep_list
);
1583 /* init cfg/alt/int */
1584 dev
->cur_config
= 0;
1589 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1590 static void usb_connect(struct udc
*dev
)
1593 dev_info(&dev
->pdev
->dev
, "USB Connect\n");
1597 /* put into initial config */
1598 udc_basic_init(dev
);
1600 /* enable device setup interrupts */
1601 udc_enable_dev_setup_interrupts(dev
);
1605 * Calls gadget with disconnect event and resets the UDC and makes
1606 * initial bringup to be ready for ep0 events
1608 static void usb_disconnect(struct udc
*dev
)
1611 dev_info(&dev
->pdev
->dev
, "USB Disconnect\n");
1615 /* mask interrupts */
1616 udc_mask_unused_interrupts(dev
);
1618 /* REVISIT there doesn't seem to be a point to having this
1619 * talk to a tasklet ... do it directly, we already hold
1620 * the spinlock needed to process the disconnect.
1623 tasklet_schedule(&disconnect_tasklet
);
1626 /* Tasklet for disconnect to be outside of interrupt context */
1627 static void udc_tasklet_disconnect(unsigned long par
)
1629 struct udc
*dev
= (struct udc
*)(*((struct udc
**) par
));
1632 DBG(dev
, "Tasklet disconnect\n");
1633 spin_lock_irq(&dev
->lock
);
1636 spin_unlock(&dev
->lock
);
1637 dev
->driver
->disconnect(&dev
->gadget
);
1638 spin_lock(&dev
->lock
);
1641 for (tmp
= 0; tmp
< UDC_EP_NUM
; tmp
++)
1642 empty_req_queue(&dev
->ep
[tmp
]);
1648 &dev
->ep
[UDC_EP0IN_IX
]);
1651 if (!soft_reset_occured
) {
1652 /* init controller by soft reset */
1653 udc_soft_reset(dev
);
1654 soft_reset_occured
++;
1657 /* re-enable dev interrupts */
1658 udc_enable_dev_setup_interrupts(dev
);
1659 /* back to full speed ? */
1660 if (use_fullspeed
) {
1661 tmp
= readl(&dev
->regs
->cfg
);
1662 tmp
= AMD_ADDBITS(tmp
, UDC_DEVCFG_SPD_FS
, UDC_DEVCFG_SPD
);
1663 writel(tmp
, &dev
->regs
->cfg
);
1666 spin_unlock_irq(&dev
->lock
);
1669 /* Reset the UDC core */
1670 static void udc_soft_reset(struct udc
*dev
)
1672 unsigned long flags
;
1674 DBG(dev
, "Soft reset\n");
1676 * reset possible waiting interrupts, because int.
1677 * status is lost after soft reset,
1678 * ep int. status reset
1680 writel(UDC_EPINT_MSK_DISABLE_ALL
, &dev
->regs
->ep_irqsts
);
1681 /* device int. status reset */
1682 writel(UDC_DEV_MSK_DISABLE
, &dev
->regs
->irqsts
);
1684 spin_lock_irqsave(&udc_irq_spinlock
, flags
);
1685 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET
), &dev
->regs
->cfg
);
1686 readl(&dev
->regs
->cfg
);
1687 spin_unlock_irqrestore(&udc_irq_spinlock
, flags
);
1691 /* RDE timer callback to set RDE bit */
1692 static void udc_timer_function(unsigned long v
)
1696 spin_lock_irq(&udc_irq_spinlock
);
1700 * open the fifo if fifo was filled on last timer call
1704 /* set RDE to receive setup data */
1705 tmp
= readl(&udc
->regs
->ctl
);
1706 tmp
|= AMD_BIT(UDC_DEVCTL_RDE
);
1707 writel(tmp
, &udc
->regs
->ctl
);
1709 } else if (readl(&udc
->regs
->sts
)
1710 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY
)) {
1712 * if fifo empty setup polling, do not just
1715 udc_timer
.expires
= jiffies
+ HZ
/UDC_RDE_TIMER_DIV
;
1717 add_timer(&udc_timer
);
1720 * fifo contains data now, setup timer for opening
1721 * the fifo when timer expires to be able to receive
1722 * setup packets, when data packets gets queued by
1723 * gadget layer then timer will forced to expire with
1724 * set_rde=0 (RDE is set in udc_queue())
1727 /* debug: lhadmot_timer_start = 221070 */
1728 udc_timer
.expires
= jiffies
+ HZ
*UDC_RDE_TIMER_SECONDS
;
1730 add_timer(&udc_timer
);
1734 set_rde
= -1; /* RDE was set by udc_queue() */
1735 spin_unlock_irq(&udc_irq_spinlock
);
1741 /* Handle halt state, used in stall poll timer */
1742 static void udc_handle_halt_state(struct udc_ep
*ep
)
1745 /* set stall as long not halted */
1746 if (ep
->halted
== 1) {
1747 tmp
= readl(&ep
->regs
->ctl
);
1748 /* STALL cleared ? */
1749 if (!(tmp
& AMD_BIT(UDC_EPCTL_S
))) {
1751 * FIXME: MSC spec requires that stall remains
1752 * even on receivng of CLEAR_FEATURE HALT. So
1753 * we would set STALL again here to be compliant.
1754 * But with current mass storage drivers this does
1755 * not work (would produce endless host retries).
1756 * So we clear halt on CLEAR_FEATURE.
1758 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1759 tmp |= AMD_BIT(UDC_EPCTL_S);
1760 writel(tmp, &ep->regs->ctl);*/
1762 /* clear NAK by writing CNAK */
1763 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
1764 writel(tmp
, &ep
->regs
->ctl
);
1766 UDC_QUEUE_CNAK(ep
, ep
->num
);
1771 /* Stall timer callback to poll S bit and set it again after */
1772 static void udc_pollstall_timer_function(unsigned long v
)
1777 spin_lock_irq(&udc_stall_spinlock
);
1779 * only one IN and OUT endpoints are handled
1782 ep
= &udc
->ep
[UDC_EPIN_IX
];
1783 udc_handle_halt_state(ep
);
1786 /* OUT poll stall */
1787 ep
= &udc
->ep
[UDC_EPOUT_IX
];
1788 udc_handle_halt_state(ep
);
1792 /* setup timer again when still halted */
1793 if (!stop_pollstall_timer
&& halted
) {
1794 udc_pollstall_timer
.expires
= jiffies
+
1795 HZ
* UDC_POLLSTALL_TIMER_USECONDS
1797 add_timer(&udc_pollstall_timer
);
1799 spin_unlock_irq(&udc_stall_spinlock
);
1801 if (stop_pollstall_timer
)
1802 complete(&on_pollstall_exit
);
1805 /* Inits endpoint 0 so that SETUP packets are processed */
1806 static void activate_control_endpoints(struct udc
*dev
)
1810 DBG(dev
, "activate_control_endpoints\n");
1813 tmp
= readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
1814 tmp
|= AMD_BIT(UDC_EPCTL_F
);
1815 writel(tmp
, &dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
1817 /* set ep0 directions */
1818 dev
->ep
[UDC_EP0IN_IX
].in
= 1;
1819 dev
->ep
[UDC_EP0OUT_IX
].in
= 0;
1821 /* set buffer size (tx fifo entries) of EP0_IN */
1822 tmp
= readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->bufin_framenum
);
1823 if (dev
->gadget
.speed
== USB_SPEED_FULL
)
1824 tmp
= AMD_ADDBITS(tmp
, UDC_FS_EPIN0_BUFF_SIZE
,
1825 UDC_EPIN_BUFF_SIZE
);
1826 else if (dev
->gadget
.speed
== USB_SPEED_HIGH
)
1827 tmp
= AMD_ADDBITS(tmp
, UDC_EPIN0_BUFF_SIZE
,
1828 UDC_EPIN_BUFF_SIZE
);
1829 writel(tmp
, &dev
->ep
[UDC_EP0IN_IX
].regs
->bufin_framenum
);
1831 /* set max packet size of EP0_IN */
1832 tmp
= readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->bufout_maxpkt
);
1833 if (dev
->gadget
.speed
== USB_SPEED_FULL
)
1834 tmp
= AMD_ADDBITS(tmp
, UDC_FS_EP0IN_MAX_PKT_SIZE
,
1835 UDC_EP_MAX_PKT_SIZE
);
1836 else if (dev
->gadget
.speed
== USB_SPEED_HIGH
)
1837 tmp
= AMD_ADDBITS(tmp
, UDC_EP0IN_MAX_PKT_SIZE
,
1838 UDC_EP_MAX_PKT_SIZE
);
1839 writel(tmp
, &dev
->ep
[UDC_EP0IN_IX
].regs
->bufout_maxpkt
);
1841 /* set max packet size of EP0_OUT */
1842 tmp
= readl(&dev
->ep
[UDC_EP0OUT_IX
].regs
->bufout_maxpkt
);
1843 if (dev
->gadget
.speed
== USB_SPEED_FULL
)
1844 tmp
= AMD_ADDBITS(tmp
, UDC_FS_EP0OUT_MAX_PKT_SIZE
,
1845 UDC_EP_MAX_PKT_SIZE
);
1846 else if (dev
->gadget
.speed
== USB_SPEED_HIGH
)
1847 tmp
= AMD_ADDBITS(tmp
, UDC_EP0OUT_MAX_PKT_SIZE
,
1848 UDC_EP_MAX_PKT_SIZE
);
1849 writel(tmp
, &dev
->ep
[UDC_EP0OUT_IX
].regs
->bufout_maxpkt
);
1851 /* set max packet size of EP0 in UDC CSR */
1852 tmp
= readl(&dev
->csr
->ne
[0]);
1853 if (dev
->gadget
.speed
== USB_SPEED_FULL
)
1854 tmp
= AMD_ADDBITS(tmp
, UDC_FS_EP0OUT_MAX_PKT_SIZE
,
1855 UDC_CSR_NE_MAX_PKT
);
1856 else if (dev
->gadget
.speed
== USB_SPEED_HIGH
)
1857 tmp
= AMD_ADDBITS(tmp
, UDC_EP0OUT_MAX_PKT_SIZE
,
1858 UDC_CSR_NE_MAX_PKT
);
1859 writel(tmp
, &dev
->csr
->ne
[0]);
1862 dev
->ep
[UDC_EP0OUT_IX
].td
->status
|=
1863 AMD_BIT(UDC_DMA_OUT_STS_L
);
1864 /* write dma desc address */
1865 writel(dev
->ep
[UDC_EP0OUT_IX
].td_stp_dma
,
1866 &dev
->ep
[UDC_EP0OUT_IX
].regs
->subptr
);
1867 writel(dev
->ep
[UDC_EP0OUT_IX
].td_phys
,
1868 &dev
->ep
[UDC_EP0OUT_IX
].regs
->desptr
);
1869 /* stop RDE timer */
1870 if (timer_pending(&udc_timer
)) {
1872 mod_timer(&udc_timer
, jiffies
- 1);
1874 /* stop pollstall timer */
1875 if (timer_pending(&udc_pollstall_timer
))
1876 mod_timer(&udc_pollstall_timer
, jiffies
- 1);
1878 tmp
= readl(&dev
->regs
->ctl
);
1879 tmp
|= AMD_BIT(UDC_DEVCTL_MODE
)
1880 | AMD_BIT(UDC_DEVCTL_RDE
)
1881 | AMD_BIT(UDC_DEVCTL_TDE
);
1882 if (use_dma_bufferfill_mode
)
1883 tmp
|= AMD_BIT(UDC_DEVCTL_BF
);
1884 else if (use_dma_ppb_du
)
1885 tmp
|= AMD_BIT(UDC_DEVCTL_DU
);
1886 writel(tmp
, &dev
->regs
->ctl
);
1889 /* clear NAK by writing CNAK for EP0IN */
1890 tmp
= readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
1891 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
1892 writel(tmp
, &dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
1893 dev
->ep
[UDC_EP0IN_IX
].naking
= 0;
1894 UDC_QUEUE_CNAK(&dev
->ep
[UDC_EP0IN_IX
], UDC_EP0IN_IX
);
1896 /* clear NAK by writing CNAK for EP0OUT */
1897 tmp
= readl(&dev
->ep
[UDC_EP0OUT_IX
].regs
->ctl
);
1898 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
1899 writel(tmp
, &dev
->ep
[UDC_EP0OUT_IX
].regs
->ctl
);
1900 dev
->ep
[UDC_EP0OUT_IX
].naking
= 0;
1901 UDC_QUEUE_CNAK(&dev
->ep
[UDC_EP0OUT_IX
], UDC_EP0OUT_IX
);
1904 /* Make endpoint 0 ready for control traffic */
1905 static int setup_ep0(struct udc
*dev
)
1907 activate_control_endpoints(dev
);
1908 /* enable ep0 interrupts */
1909 udc_enable_ep0_interrupts(dev
);
1910 /* enable device setup interrupts */
1911 udc_enable_dev_setup_interrupts(dev
);
1916 /* Called by gadget driver to register itself */
1917 static int amd5536_udc_start(struct usb_gadget
*g
,
1918 struct usb_gadget_driver
*driver
)
1920 struct udc
*dev
= to_amd5536_udc(g
);
1923 driver
->driver
.bus
= NULL
;
1924 dev
->driver
= driver
;
1925 dev
->gadget
.dev
.driver
= &driver
->driver
;
1927 /* Some gadget drivers use both ep0 directions.
1928 * NOTE: to gadget driver, ep0 is just one endpoint...
1930 dev
->ep
[UDC_EP0OUT_IX
].ep
.driver_data
=
1931 dev
->ep
[UDC_EP0IN_IX
].ep
.driver_data
;
1933 /* get ready for ep0 traffic */
1937 tmp
= readl(&dev
->regs
->ctl
);
1938 tmp
= tmp
& AMD_CLEAR_BIT(UDC_DEVCTL_SD
);
1939 writel(tmp
, &dev
->regs
->ctl
);
1946 /* shutdown requests and disconnect from gadget */
1948 shutdown(struct udc
*dev
, struct usb_gadget_driver
*driver
)
1949 __releases(dev
->lock
)
1950 __acquires(dev
->lock
)
1954 /* empty queues and init hardware */
1955 udc_basic_init(dev
);
1957 for (tmp
= 0; tmp
< UDC_EP_NUM
; tmp
++)
1958 empty_req_queue(&dev
->ep
[tmp
]);
1960 udc_setup_endpoints(dev
);
1963 /* Called by gadget driver to unregister itself */
1964 static int amd5536_udc_stop(struct usb_gadget
*g
,
1965 struct usb_gadget_driver
*driver
)
1967 struct udc
*dev
= to_amd5536_udc(g
);
1968 unsigned long flags
;
1971 spin_lock_irqsave(&dev
->lock
, flags
);
1972 udc_mask_unused_interrupts(dev
);
1973 shutdown(dev
, driver
);
1974 spin_unlock_irqrestore(&dev
->lock
, flags
);
1976 dev
->gadget
.dev
.driver
= NULL
;
1980 tmp
= readl(&dev
->regs
->ctl
);
1981 tmp
|= AMD_BIT(UDC_DEVCTL_SD
);
1982 writel(tmp
, &dev
->regs
->ctl
);
1987 /* Clear pending NAK bits */
1988 static void udc_process_cnak_queue(struct udc
*dev
)
1994 DBG(dev
, "CNAK pending queue processing\n");
1995 for (tmp
= 0; tmp
< UDC_EPIN_NUM_USED
; tmp
++) {
1996 if (cnak_pending
& (1 << tmp
)) {
1997 DBG(dev
, "CNAK pending for ep%d\n", tmp
);
1998 /* clear NAK by writing CNAK */
1999 reg
= readl(&dev
->ep
[tmp
].regs
->ctl
);
2000 reg
|= AMD_BIT(UDC_EPCTL_CNAK
);
2001 writel(reg
, &dev
->ep
[tmp
].regs
->ctl
);
2002 dev
->ep
[tmp
].naking
= 0;
2003 UDC_QUEUE_CNAK(&dev
->ep
[tmp
], dev
->ep
[tmp
].num
);
2006 /* ... and ep0out */
2007 if (cnak_pending
& (1 << UDC_EP0OUT_IX
)) {
2008 DBG(dev
, "CNAK pending for ep%d\n", UDC_EP0OUT_IX
);
2009 /* clear NAK by writing CNAK */
2010 reg
= readl(&dev
->ep
[UDC_EP0OUT_IX
].regs
->ctl
);
2011 reg
|= AMD_BIT(UDC_EPCTL_CNAK
);
2012 writel(reg
, &dev
->ep
[UDC_EP0OUT_IX
].regs
->ctl
);
2013 dev
->ep
[UDC_EP0OUT_IX
].naking
= 0;
2014 UDC_QUEUE_CNAK(&dev
->ep
[UDC_EP0OUT_IX
],
2015 dev
->ep
[UDC_EP0OUT_IX
].num
);
2019 /* Enabling RX DMA after setup packet */
2020 static void udc_ep0_set_rde(struct udc
*dev
)
2024 * only enable RXDMA when no data endpoint enabled
2027 if (!dev
->data_ep_enabled
|| dev
->data_ep_queued
) {
2031 * setup timer for enabling RDE (to not enable
2032 * RXFIFO DMA for data endpoints to early)
2034 if (set_rde
!= 0 && !timer_pending(&udc_timer
)) {
2036 jiffies
+ HZ
/UDC_RDE_TIMER_DIV
;
2039 add_timer(&udc_timer
);
2046 /* Interrupt handler for data OUT traffic */
2047 static irqreturn_t
udc_data_out_isr(struct udc
*dev
, int ep_ix
)
2049 irqreturn_t ret_val
= IRQ_NONE
;
2052 struct udc_request
*req
;
2054 struct udc_data_dma
*td
= NULL
;
2057 VDBG(dev
, "ep%d irq\n", ep_ix
);
2058 ep
= &dev
->ep
[ep_ix
];
2060 tmp
= readl(&ep
->regs
->sts
);
2063 if (tmp
& AMD_BIT(UDC_EPSTS_BNA
)) {
2064 DBG(dev
, "BNA ep%dout occurred - DESPTR = %x\n",
2065 ep
->num
, readl(&ep
->regs
->desptr
));
2067 writel(tmp
| AMD_BIT(UDC_EPSTS_BNA
), &ep
->regs
->sts
);
2068 if (!ep
->cancel_transfer
)
2069 ep
->bna_occurred
= 1;
2071 ep
->cancel_transfer
= 0;
2072 ret_val
= IRQ_HANDLED
;
2077 if (tmp
& AMD_BIT(UDC_EPSTS_HE
)) {
2078 dev_err(&dev
->pdev
->dev
, "HE ep%dout occurred\n", ep
->num
);
2081 writel(tmp
| AMD_BIT(UDC_EPSTS_HE
), &ep
->regs
->sts
);
2082 ret_val
= IRQ_HANDLED
;
2086 if (!list_empty(&ep
->queue
)) {
2089 req
= list_entry(ep
->queue
.next
,
2090 struct udc_request
, queue
);
2093 udc_rxfifo_pending
= 1;
2095 VDBG(dev
, "req = %p\n", req
);
2100 if (req
&& udc_rxfifo_read(ep
, req
)) {
2101 ret_val
= IRQ_HANDLED
;
2104 complete_req(ep
, req
, 0);
2106 if (!list_empty(&ep
->queue
) && !ep
->halted
) {
2107 req
= list_entry(ep
->queue
.next
,
2108 struct udc_request
, queue
);
2114 } else if (!ep
->cancel_transfer
&& req
!= NULL
) {
2115 ret_val
= IRQ_HANDLED
;
2117 /* check for DMA done */
2119 dma_done
= AMD_GETBITS(req
->td_data
->status
,
2120 UDC_DMA_OUT_STS_BS
);
2121 /* packet per buffer mode - rx bytes */
2124 * if BNA occurred then recover desc. from
2127 if (ep
->bna_occurred
) {
2128 VDBG(dev
, "Recover desc. from BNA dummy\n");
2129 memcpy(req
->td_data
, ep
->bna_dummy_req
->td_data
,
2130 sizeof(struct udc_data_dma
));
2131 ep
->bna_occurred
= 0;
2132 udc_init_bna_dummy(ep
->req
);
2134 td
= udc_get_last_dma_desc(req
);
2135 dma_done
= AMD_GETBITS(td
->status
, UDC_DMA_OUT_STS_BS
);
2137 if (dma_done
== UDC_DMA_OUT_STS_BS_DMA_DONE
) {
2138 /* buffer fill mode - rx bytes */
2140 /* received number bytes */
2141 count
= AMD_GETBITS(req
->td_data
->status
,
2142 UDC_DMA_OUT_STS_RXBYTES
);
2143 VDBG(dev
, "rx bytes=%u\n", count
);
2144 /* packet per buffer mode - rx bytes */
2146 VDBG(dev
, "req->td_data=%p\n", req
->td_data
);
2147 VDBG(dev
, "last desc = %p\n", td
);
2148 /* received number bytes */
2149 if (use_dma_ppb_du
) {
2150 /* every desc. counts bytes */
2151 count
= udc_get_ppbdu_rxbytes(req
);
2153 /* last desc. counts bytes */
2154 count
= AMD_GETBITS(td
->status
,
2155 UDC_DMA_OUT_STS_RXBYTES
);
2156 if (!count
&& req
->req
.length
2157 == UDC_DMA_MAXPACKET
) {
2159 * on 64k packets the RXBYTES
2162 count
= UDC_DMA_MAXPACKET
;
2165 VDBG(dev
, "last desc rx bytes=%u\n", count
);
2168 tmp
= req
->req
.length
- req
->req
.actual
;
2170 if ((tmp
% ep
->ep
.maxpacket
) != 0) {
2171 DBG(dev
, "%s: rx %db, space=%db\n",
2172 ep
->ep
.name
, count
, tmp
);
2173 req
->req
.status
= -EOVERFLOW
;
2177 req
->req
.actual
+= count
;
2179 /* complete request */
2180 complete_req(ep
, req
, 0);
2183 if (!list_empty(&ep
->queue
) && !ep
->halted
) {
2184 req
= list_entry(ep
->queue
.next
,
2188 * DMA may be already started by udc_queue()
2189 * called by gadget drivers completion
2190 * routine. This happens when queue
2191 * holds one request only.
2193 if (req
->dma_going
== 0) {
2195 if (prep_dma(ep
, req
, GFP_ATOMIC
) != 0)
2197 /* write desc pointer */
2198 writel(req
->td_phys
,
2206 * implant BNA dummy descriptor to allow
2207 * RXFIFO opening by RDE
2209 if (ep
->bna_dummy_req
) {
2210 /* write desc pointer */
2211 writel(ep
->bna_dummy_req
->td_phys
,
2213 ep
->bna_occurred
= 0;
2217 * schedule timer for setting RDE if queue
2218 * remains empty to allow ep0 packets pass
2222 && !timer_pending(&udc_timer
)) {
2225 + HZ
*UDC_RDE_TIMER_SECONDS
;
2228 add_timer(&udc_timer
);
2230 if (ep
->num
!= UDC_EP0OUT_IX
)
2231 dev
->data_ep_queued
= 0;
2236 * RX DMA must be reenabled for each desc in PPBDU mode
2237 * and must be enabled for PPBNDU mode in case of BNA
2242 } else if (ep
->cancel_transfer
) {
2243 ret_val
= IRQ_HANDLED
;
2244 ep
->cancel_transfer
= 0;
2247 /* check pending CNAKS */
2249 /* CNAk processing when rxfifo empty only */
2250 if (readl(&dev
->regs
->sts
) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY
))
2251 udc_process_cnak_queue(dev
);
2254 /* clear OUT bits in ep status */
2255 writel(UDC_EPSTS_OUT_CLEAR
, &ep
->regs
->sts
);
2260 /* Interrupt handler for data IN traffic */
2261 static irqreturn_t
udc_data_in_isr(struct udc
*dev
, int ep_ix
)
2263 irqreturn_t ret_val
= IRQ_NONE
;
2267 struct udc_request
*req
;
2268 struct udc_data_dma
*td
;
2272 ep
= &dev
->ep
[ep_ix
];
2274 epsts
= readl(&ep
->regs
->sts
);
2277 if (epsts
& AMD_BIT(UDC_EPSTS_BNA
)) {
2278 dev_err(&dev
->pdev
->dev
,
2279 "BNA ep%din occurred - DESPTR = %08lx\n",
2281 (unsigned long) readl(&ep
->regs
->desptr
));
2284 writel(epsts
, &ep
->regs
->sts
);
2285 ret_val
= IRQ_HANDLED
;
2290 if (epsts
& AMD_BIT(UDC_EPSTS_HE
)) {
2291 dev_err(&dev
->pdev
->dev
,
2292 "HE ep%dn occurred - DESPTR = %08lx\n",
2293 ep
->num
, (unsigned long) readl(&ep
->regs
->desptr
));
2296 writel(epsts
| AMD_BIT(UDC_EPSTS_HE
), &ep
->regs
->sts
);
2297 ret_val
= IRQ_HANDLED
;
2301 /* DMA completion */
2302 if (epsts
& AMD_BIT(UDC_EPSTS_TDC
)) {
2303 VDBG(dev
, "TDC set- completion\n");
2304 ret_val
= IRQ_HANDLED
;
2305 if (!ep
->cancel_transfer
&& !list_empty(&ep
->queue
)) {
2306 req
= list_entry(ep
->queue
.next
,
2307 struct udc_request
, queue
);
2309 * length bytes transferred
2310 * check dma done of last desc. in PPBDU mode
2312 if (use_dma_ppb_du
) {
2313 td
= udc_get_last_dma_desc(req
);
2316 AMD_GETBITS(td
->status
,
2318 /* don't care DMA done */
2319 req
->req
.actual
= req
->req
.length
;
2322 /* assume all bytes transferred */
2323 req
->req
.actual
= req
->req
.length
;
2326 if (req
->req
.actual
== req
->req
.length
) {
2328 complete_req(ep
, req
, 0);
2330 /* further request available ? */
2331 if (list_empty(&ep
->queue
)) {
2332 /* disable interrupt */
2333 tmp
= readl(&dev
->regs
->ep_irqmsk
);
2334 tmp
|= AMD_BIT(ep
->num
);
2335 writel(tmp
, &dev
->regs
->ep_irqmsk
);
2339 ep
->cancel_transfer
= 0;
2343 * status reg has IN bit set and TDC not set (if TDC was handled,
2344 * IN must not be handled (UDC defect) ?
2346 if ((epsts
& AMD_BIT(UDC_EPSTS_IN
))
2347 && !(epsts
& AMD_BIT(UDC_EPSTS_TDC
))) {
2348 ret_val
= IRQ_HANDLED
;
2349 if (!list_empty(&ep
->queue
)) {
2351 req
= list_entry(ep
->queue
.next
,
2352 struct udc_request
, queue
);
2356 udc_txfifo_write(ep
, &req
->req
);
2357 len
= req
->req
.length
- req
->req
.actual
;
2358 if (len
> ep
->ep
.maxpacket
)
2359 len
= ep
->ep
.maxpacket
;
2360 req
->req
.actual
+= len
;
2361 if (req
->req
.actual
== req
->req
.length
2362 || (len
!= ep
->ep
.maxpacket
)) {
2364 complete_req(ep
, req
, 0);
2367 } else if (req
&& !req
->dma_going
) {
2368 VDBG(dev
, "IN DMA : req=%p req->td_data=%p\n",
2375 * unset L bit of first desc.
2378 if (use_dma_ppb
&& req
->req
.length
>
2380 req
->td_data
->status
&=
2385 /* write desc pointer */
2386 writel(req
->td_phys
, &ep
->regs
->desptr
);
2388 /* set HOST READY */
2389 req
->td_data
->status
=
2391 req
->td_data
->status
,
2392 UDC_DMA_IN_STS_BS_HOST_READY
,
2395 /* set poll demand bit */
2396 tmp
= readl(&ep
->regs
->ctl
);
2397 tmp
|= AMD_BIT(UDC_EPCTL_P
);
2398 writel(tmp
, &ep
->regs
->ctl
);
2402 } else if (!use_dma
&& ep
->in
) {
2403 /* disable interrupt */
2405 &dev
->regs
->ep_irqmsk
);
2406 tmp
|= AMD_BIT(ep
->num
);
2408 &dev
->regs
->ep_irqmsk
);
2411 /* clear status bits */
2412 writel(epsts
, &ep
->regs
->sts
);
2419 /* Interrupt handler for Control OUT traffic */
2420 static irqreturn_t
udc_control_out_isr(struct udc
*dev
)
2421 __releases(dev
->lock
)
2422 __acquires(dev
->lock
)
2424 irqreturn_t ret_val
= IRQ_NONE
;
2426 int setup_supported
;
2430 struct udc_ep
*ep_tmp
;
2432 ep
= &dev
->ep
[UDC_EP0OUT_IX
];
2435 writel(AMD_BIT(UDC_EPINT_OUT_EP0
), &dev
->regs
->ep_irqsts
);
2437 tmp
= readl(&dev
->ep
[UDC_EP0OUT_IX
].regs
->sts
);
2438 /* check BNA and clear if set */
2439 if (tmp
& AMD_BIT(UDC_EPSTS_BNA
)) {
2440 VDBG(dev
, "ep0: BNA set\n");
2441 writel(AMD_BIT(UDC_EPSTS_BNA
),
2442 &dev
->ep
[UDC_EP0OUT_IX
].regs
->sts
);
2443 ep
->bna_occurred
= 1;
2444 ret_val
= IRQ_HANDLED
;
2448 /* type of data: SETUP or DATA 0 bytes */
2449 tmp
= AMD_GETBITS(tmp
, UDC_EPSTS_OUT
);
2450 VDBG(dev
, "data_typ = %x\n", tmp
);
2453 if (tmp
== UDC_EPSTS_OUT_SETUP
) {
2454 ret_val
= IRQ_HANDLED
;
2456 ep
->dev
->stall_ep0in
= 0;
2457 dev
->waiting_zlp_ack_ep0in
= 0;
2459 /* set NAK for EP0_IN */
2460 tmp
= readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
2461 tmp
|= AMD_BIT(UDC_EPCTL_SNAK
);
2462 writel(tmp
, &dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
2463 dev
->ep
[UDC_EP0IN_IX
].naking
= 1;
2464 /* get setup data */
2467 /* clear OUT bits in ep status */
2468 writel(UDC_EPSTS_OUT_CLEAR
,
2469 &dev
->ep
[UDC_EP0OUT_IX
].regs
->sts
);
2471 setup_data
.data
[0] =
2472 dev
->ep
[UDC_EP0OUT_IX
].td_stp
->data12
;
2473 setup_data
.data
[1] =
2474 dev
->ep
[UDC_EP0OUT_IX
].td_stp
->data34
;
2475 /* set HOST READY */
2476 dev
->ep
[UDC_EP0OUT_IX
].td_stp
->status
=
2477 UDC_DMA_STP_STS_BS_HOST_READY
;
2480 udc_rxfifo_read_dwords(dev
, setup_data
.data
, 2);
2483 /* determine direction of control data */
2484 if ((setup_data
.request
.bRequestType
& USB_DIR_IN
) != 0) {
2485 dev
->gadget
.ep0
= &dev
->ep
[UDC_EP0IN_IX
].ep
;
2487 udc_ep0_set_rde(dev
);
2490 dev
->gadget
.ep0
= &dev
->ep
[UDC_EP0OUT_IX
].ep
;
2492 * implant BNA dummy descriptor to allow RXFIFO opening
2495 if (ep
->bna_dummy_req
) {
2496 /* write desc pointer */
2497 writel(ep
->bna_dummy_req
->td_phys
,
2498 &dev
->ep
[UDC_EP0OUT_IX
].regs
->desptr
);
2499 ep
->bna_occurred
= 0;
2503 dev
->ep
[UDC_EP0OUT_IX
].naking
= 1;
2505 * setup timer for enabling RDE (to not enable
2506 * RXFIFO DMA for data to early)
2509 if (!timer_pending(&udc_timer
)) {
2510 udc_timer
.expires
= jiffies
+
2511 HZ
/UDC_RDE_TIMER_DIV
;
2513 add_timer(&udc_timer
);
2518 * mass storage reset must be processed here because
2519 * next packet may be a CLEAR_FEATURE HALT which would not
2520 * clear the stall bit when no STALL handshake was received
2521 * before (autostall can cause this)
2523 if (setup_data
.data
[0] == UDC_MSCRES_DWORD0
2524 && setup_data
.data
[1] == UDC_MSCRES_DWORD1
) {
2525 DBG(dev
, "MSC Reset\n");
2528 * only one IN and OUT endpoints are handled
2530 ep_tmp
= &udc
->ep
[UDC_EPIN_IX
];
2531 udc_set_halt(&ep_tmp
->ep
, 0);
2532 ep_tmp
= &udc
->ep
[UDC_EPOUT_IX
];
2533 udc_set_halt(&ep_tmp
->ep
, 0);
2536 /* call gadget with setup data received */
2537 spin_unlock(&dev
->lock
);
2538 setup_supported
= dev
->driver
->setup(&dev
->gadget
,
2539 &setup_data
.request
);
2540 spin_lock(&dev
->lock
);
2542 tmp
= readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
2543 /* ep0 in returns data (not zlp) on IN phase */
2544 if (setup_supported
>= 0 && setup_supported
<
2545 UDC_EP0IN_MAXPACKET
) {
2546 /* clear NAK by writing CNAK in EP0_IN */
2547 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
2548 writel(tmp
, &dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
2549 dev
->ep
[UDC_EP0IN_IX
].naking
= 0;
2550 UDC_QUEUE_CNAK(&dev
->ep
[UDC_EP0IN_IX
], UDC_EP0IN_IX
);
2552 /* if unsupported request then stall */
2553 } else if (setup_supported
< 0) {
2554 tmp
|= AMD_BIT(UDC_EPCTL_S
);
2555 writel(tmp
, &dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
2557 dev
->waiting_zlp_ack_ep0in
= 1;
2560 /* clear NAK by writing CNAK in EP0_OUT */
2562 tmp
= readl(&dev
->ep
[UDC_EP0OUT_IX
].regs
->ctl
);
2563 tmp
|= AMD_BIT(UDC_EPCTL_CNAK
);
2564 writel(tmp
, &dev
->ep
[UDC_EP0OUT_IX
].regs
->ctl
);
2565 dev
->ep
[UDC_EP0OUT_IX
].naking
= 0;
2566 UDC_QUEUE_CNAK(&dev
->ep
[UDC_EP0OUT_IX
], UDC_EP0OUT_IX
);
2570 /* clear OUT bits in ep status */
2571 writel(UDC_EPSTS_OUT_CLEAR
,
2572 &dev
->ep
[UDC_EP0OUT_IX
].regs
->sts
);
2575 /* data packet 0 bytes */
2576 } else if (tmp
== UDC_EPSTS_OUT_DATA
) {
2577 /* clear OUT bits in ep status */
2578 writel(UDC_EPSTS_OUT_CLEAR
, &dev
->ep
[UDC_EP0OUT_IX
].regs
->sts
);
2580 /* get setup data: only 0 packet */
2582 /* no req if 0 packet, just reactivate */
2583 if (list_empty(&dev
->ep
[UDC_EP0OUT_IX
].queue
)) {
2586 /* set HOST READY */
2587 dev
->ep
[UDC_EP0OUT_IX
].td
->status
=
2589 dev
->ep
[UDC_EP0OUT_IX
].td
->status
,
2590 UDC_DMA_OUT_STS_BS_HOST_READY
,
2591 UDC_DMA_OUT_STS_BS
);
2593 udc_ep0_set_rde(dev
);
2594 ret_val
= IRQ_HANDLED
;
2598 ret_val
|= udc_data_out_isr(dev
, UDC_EP0OUT_IX
);
2599 /* re-program desc. pointer for possible ZLPs */
2600 writel(dev
->ep
[UDC_EP0OUT_IX
].td_phys
,
2601 &dev
->ep
[UDC_EP0OUT_IX
].regs
->desptr
);
2603 udc_ep0_set_rde(dev
);
2607 /* received number bytes */
2608 count
= readl(&dev
->ep
[UDC_EP0OUT_IX
].regs
->sts
);
2609 count
= AMD_GETBITS(count
, UDC_EPSTS_RX_PKT_SIZE
);
2610 /* out data for fifo mode not working */
2613 /* 0 packet or real data ? */
2615 ret_val
|= udc_data_out_isr(dev
, UDC_EP0OUT_IX
);
2617 /* dummy read confirm */
2618 readl(&dev
->ep
[UDC_EP0OUT_IX
].regs
->confirm
);
2619 ret_val
= IRQ_HANDLED
;
2624 /* check pending CNAKS */
2626 /* CNAk processing when rxfifo empty only */
2627 if (readl(&dev
->regs
->sts
) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY
))
2628 udc_process_cnak_queue(dev
);
2635 /* Interrupt handler for Control IN traffic */
2636 static irqreturn_t
udc_control_in_isr(struct udc
*dev
)
2638 irqreturn_t ret_val
= IRQ_NONE
;
2641 struct udc_request
*req
;
2644 ep
= &dev
->ep
[UDC_EP0IN_IX
];
2647 writel(AMD_BIT(UDC_EPINT_IN_EP0
), &dev
->regs
->ep_irqsts
);
2649 tmp
= readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->sts
);
2650 /* DMA completion */
2651 if (tmp
& AMD_BIT(UDC_EPSTS_TDC
)) {
2652 VDBG(dev
, "isr: TDC clear\n");
2653 ret_val
= IRQ_HANDLED
;
2656 writel(AMD_BIT(UDC_EPSTS_TDC
),
2657 &dev
->ep
[UDC_EP0IN_IX
].regs
->sts
);
2659 /* status reg has IN bit set ? */
2660 } else if (tmp
& AMD_BIT(UDC_EPSTS_IN
)) {
2661 ret_val
= IRQ_HANDLED
;
2665 writel(AMD_BIT(UDC_EPSTS_IN
),
2666 &dev
->ep
[UDC_EP0IN_IX
].regs
->sts
);
2668 if (dev
->stall_ep0in
) {
2669 DBG(dev
, "stall ep0in\n");
2671 tmp
= readl(&ep
->regs
->ctl
);
2672 tmp
|= AMD_BIT(UDC_EPCTL_S
);
2673 writel(tmp
, &ep
->regs
->ctl
);
2675 if (!list_empty(&ep
->queue
)) {
2677 req
= list_entry(ep
->queue
.next
,
2678 struct udc_request
, queue
);
2681 /* write desc pointer */
2682 writel(req
->td_phys
, &ep
->regs
->desptr
);
2683 /* set HOST READY */
2684 req
->td_data
->status
=
2686 req
->td_data
->status
,
2687 UDC_DMA_STP_STS_BS_HOST_READY
,
2688 UDC_DMA_STP_STS_BS
);
2690 /* set poll demand bit */
2692 readl(&dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
2693 tmp
|= AMD_BIT(UDC_EPCTL_P
);
2695 &dev
->ep
[UDC_EP0IN_IX
].regs
->ctl
);
2697 /* all bytes will be transferred */
2698 req
->req
.actual
= req
->req
.length
;
2701 complete_req(ep
, req
, 0);
2705 udc_txfifo_write(ep
, &req
->req
);
2707 /* lengh bytes transferred */
2708 len
= req
->req
.length
- req
->req
.actual
;
2709 if (len
> ep
->ep
.maxpacket
)
2710 len
= ep
->ep
.maxpacket
;
2712 req
->req
.actual
+= len
;
2713 if (req
->req
.actual
== req
->req
.length
2714 || (len
!= ep
->ep
.maxpacket
)) {
2716 complete_req(ep
, req
, 0);
2723 dev
->stall_ep0in
= 0;
2726 writel(AMD_BIT(UDC_EPSTS_IN
),
2727 &dev
->ep
[UDC_EP0IN_IX
].regs
->sts
);
2735 /* Interrupt handler for global device events */
2736 static irqreturn_t
udc_dev_isr(struct udc
*dev
, u32 dev_irq
)
2737 __releases(dev
->lock
)
2738 __acquires(dev
->lock
)
2740 irqreturn_t ret_val
= IRQ_NONE
;
2747 /* SET_CONFIG irq ? */
2748 if (dev_irq
& AMD_BIT(UDC_DEVINT_SC
)) {
2749 ret_val
= IRQ_HANDLED
;
2751 /* read config value */
2752 tmp
= readl(&dev
->regs
->sts
);
2753 cfg
= AMD_GETBITS(tmp
, UDC_DEVSTS_CFG
);
2754 DBG(dev
, "SET_CONFIG interrupt: config=%d\n", cfg
);
2755 dev
->cur_config
= cfg
;
2756 dev
->set_cfg_not_acked
= 1;
2758 /* make usb request for gadget driver */
2759 memset(&setup_data
, 0 , sizeof(union udc_setup_data
));
2760 setup_data
.request
.bRequest
= USB_REQ_SET_CONFIGURATION
;
2761 setup_data
.request
.wValue
= cpu_to_le16(dev
->cur_config
);
2763 /* programm the NE registers */
2764 for (i
= 0; i
< UDC_EP_NUM
; i
++) {
2768 /* ep ix in UDC CSR register space */
2769 udc_csr_epix
= ep
->num
;
2774 /* ep ix in UDC CSR register space */
2775 udc_csr_epix
= ep
->num
- UDC_CSR_EP_OUT_IX_OFS
;
2778 tmp
= readl(&dev
->csr
->ne
[udc_csr_epix
]);
2780 tmp
= AMD_ADDBITS(tmp
, ep
->dev
->cur_config
,
2783 writel(tmp
, &dev
->csr
->ne
[udc_csr_epix
]);
2785 /* clear stall bits */
2787 tmp
= readl(&ep
->regs
->ctl
);
2788 tmp
= tmp
& AMD_CLEAR_BIT(UDC_EPCTL_S
);
2789 writel(tmp
, &ep
->regs
->ctl
);
2791 /* call gadget zero with setup data received */
2792 spin_unlock(&dev
->lock
);
2793 tmp
= dev
->driver
->setup(&dev
->gadget
, &setup_data
.request
);
2794 spin_lock(&dev
->lock
);
2796 } /* SET_INTERFACE ? */
2797 if (dev_irq
& AMD_BIT(UDC_DEVINT_SI
)) {
2798 ret_val
= IRQ_HANDLED
;
2800 dev
->set_cfg_not_acked
= 1;
2801 /* read interface and alt setting values */
2802 tmp
= readl(&dev
->regs
->sts
);
2803 dev
->cur_alt
= AMD_GETBITS(tmp
, UDC_DEVSTS_ALT
);
2804 dev
->cur_intf
= AMD_GETBITS(tmp
, UDC_DEVSTS_INTF
);
2806 /* make usb request for gadget driver */
2807 memset(&setup_data
, 0 , sizeof(union udc_setup_data
));
2808 setup_data
.request
.bRequest
= USB_REQ_SET_INTERFACE
;
2809 setup_data
.request
.bRequestType
= USB_RECIP_INTERFACE
;
2810 setup_data
.request
.wValue
= cpu_to_le16(dev
->cur_alt
);
2811 setup_data
.request
.wIndex
= cpu_to_le16(dev
->cur_intf
);
2813 DBG(dev
, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2814 dev
->cur_alt
, dev
->cur_intf
);
2816 /* programm the NE registers */
2817 for (i
= 0; i
< UDC_EP_NUM
; i
++) {
2821 /* ep ix in UDC CSR register space */
2822 udc_csr_epix
= ep
->num
;
2827 /* ep ix in UDC CSR register space */
2828 udc_csr_epix
= ep
->num
- UDC_CSR_EP_OUT_IX_OFS
;
2833 tmp
= readl(&dev
->csr
->ne
[udc_csr_epix
]);
2835 tmp
= AMD_ADDBITS(tmp
, ep
->dev
->cur_intf
,
2837 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2839 tmp
= AMD_ADDBITS(tmp
, ep
->dev
->cur_alt
,
2842 writel(tmp
, &dev
->csr
->ne
[udc_csr_epix
]);
2844 /* clear stall bits */
2846 tmp
= readl(&ep
->regs
->ctl
);
2847 tmp
= tmp
& AMD_CLEAR_BIT(UDC_EPCTL_S
);
2848 writel(tmp
, &ep
->regs
->ctl
);
2851 /* call gadget zero with setup data received */
2852 spin_unlock(&dev
->lock
);
2853 tmp
= dev
->driver
->setup(&dev
->gadget
, &setup_data
.request
);
2854 spin_lock(&dev
->lock
);
2857 if (dev_irq
& AMD_BIT(UDC_DEVINT_UR
)) {
2858 DBG(dev
, "USB Reset interrupt\n");
2859 ret_val
= IRQ_HANDLED
;
2861 /* allow soft reset when suspend occurs */
2862 soft_reset_occured
= 0;
2864 dev
->waiting_zlp_ack_ep0in
= 0;
2865 dev
->set_cfg_not_acked
= 0;
2867 /* mask not needed interrupts */
2868 udc_mask_unused_interrupts(dev
);
2870 /* call gadget to resume and reset configs etc. */
2871 spin_unlock(&dev
->lock
);
2872 if (dev
->sys_suspended
&& dev
->driver
->resume
) {
2873 dev
->driver
->resume(&dev
->gadget
);
2874 dev
->sys_suspended
= 0;
2876 dev
->driver
->disconnect(&dev
->gadget
);
2877 spin_lock(&dev
->lock
);
2879 /* disable ep0 to empty req queue */
2880 empty_req_queue(&dev
->ep
[UDC_EP0IN_IX
]);
2881 ep_init(dev
->regs
, &dev
->ep
[UDC_EP0IN_IX
]);
2883 /* soft reset when rxfifo not empty */
2884 tmp
= readl(&dev
->regs
->sts
);
2885 if (!(tmp
& AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY
))
2886 && !soft_reset_after_usbreset_occured
) {
2887 udc_soft_reset(dev
);
2888 soft_reset_after_usbreset_occured
++;
2892 * DMA reset to kill potential old DMA hw hang,
2893 * POLL bit is already reset by ep_init() through
2896 DBG(dev
, "DMA machine reset\n");
2897 tmp
= readl(&dev
->regs
->cfg
);
2898 writel(tmp
| AMD_BIT(UDC_DEVCFG_DMARST
), &dev
->regs
->cfg
);
2899 writel(tmp
, &dev
->regs
->cfg
);
2901 /* put into initial config */
2902 udc_basic_init(dev
);
2904 /* enable device setup interrupts */
2905 udc_enable_dev_setup_interrupts(dev
);
2907 /* enable suspend interrupt */
2908 tmp
= readl(&dev
->regs
->irqmsk
);
2909 tmp
&= AMD_UNMASK_BIT(UDC_DEVINT_US
);
2910 writel(tmp
, &dev
->regs
->irqmsk
);
2913 if (dev_irq
& AMD_BIT(UDC_DEVINT_US
)) {
2914 DBG(dev
, "USB Suspend interrupt\n");
2915 ret_val
= IRQ_HANDLED
;
2916 if (dev
->driver
->suspend
) {
2917 spin_unlock(&dev
->lock
);
2918 dev
->sys_suspended
= 1;
2919 dev
->driver
->suspend(&dev
->gadget
);
2920 spin_lock(&dev
->lock
);
2923 if (dev_irq
& AMD_BIT(UDC_DEVINT_ENUM
)) {
2924 DBG(dev
, "ENUM interrupt\n");
2925 ret_val
= IRQ_HANDLED
;
2926 soft_reset_after_usbreset_occured
= 0;
2928 /* disable ep0 to empty req queue */
2929 empty_req_queue(&dev
->ep
[UDC_EP0IN_IX
]);
2930 ep_init(dev
->regs
, &dev
->ep
[UDC_EP0IN_IX
]);
2932 /* link up all endpoints */
2933 udc_setup_endpoints(dev
);
2934 dev_info(&dev
->pdev
->dev
, "Connect: %s\n",
2935 usb_speed_string(dev
->gadget
.speed
));
2938 activate_control_endpoints(dev
);
2940 /* enable ep0 interrupts */
2941 udc_enable_ep0_interrupts(dev
);
2943 /* session valid change interrupt */
2944 if (dev_irq
& AMD_BIT(UDC_DEVINT_SVC
)) {
2945 DBG(dev
, "USB SVC interrupt\n");
2946 ret_val
= IRQ_HANDLED
;
2948 /* check that session is not valid to detect disconnect */
2949 tmp
= readl(&dev
->regs
->sts
);
2950 if (!(tmp
& AMD_BIT(UDC_DEVSTS_SESSVLD
))) {
2951 /* disable suspend interrupt */
2952 tmp
= readl(&dev
->regs
->irqmsk
);
2953 tmp
|= AMD_BIT(UDC_DEVINT_US
);
2954 writel(tmp
, &dev
->regs
->irqmsk
);
2955 DBG(dev
, "USB Disconnect (session valid low)\n");
2956 /* cleanup on disconnect */
2957 usb_disconnect(udc
);
2965 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2966 static irqreturn_t
udc_irq(int irq
, void *pdev
)
2968 struct udc
*dev
= pdev
;
2972 irqreturn_t ret_val
= IRQ_NONE
;
2974 spin_lock(&dev
->lock
);
2976 /* check for ep irq */
2977 reg
= readl(&dev
->regs
->ep_irqsts
);
2979 if (reg
& AMD_BIT(UDC_EPINT_OUT_EP0
))
2980 ret_val
|= udc_control_out_isr(dev
);
2981 if (reg
& AMD_BIT(UDC_EPINT_IN_EP0
))
2982 ret_val
|= udc_control_in_isr(dev
);
2988 for (i
= 1; i
< UDC_EP_NUM
; i
++) {
2990 if (!(reg
& ep_irq
) || i
== UDC_EPINT_OUT_EP0
)
2993 /* clear irq status */
2994 writel(ep_irq
, &dev
->regs
->ep_irqsts
);
2996 /* irq for out ep ? */
2997 if (i
> UDC_EPIN_NUM
)
2998 ret_val
|= udc_data_out_isr(dev
, i
);
3000 ret_val
|= udc_data_in_isr(dev
, i
);
3006 /* check for dev irq */
3007 reg
= readl(&dev
->regs
->irqsts
);
3010 writel(reg
, &dev
->regs
->irqsts
);
3011 ret_val
|= udc_dev_isr(dev
, reg
);
3015 spin_unlock(&dev
->lock
);
3019 /* Tears down device */
3020 static void gadget_release(struct device
*pdev
)
3022 struct amd5536udc
*dev
= dev_get_drvdata(pdev
);
3026 /* Cleanup on device remove */
3027 static void udc_remove(struct udc
*dev
)
3031 if (timer_pending(&udc_timer
))
3032 wait_for_completion(&on_exit
);
3034 del_timer_sync(&udc_timer
);
3035 /* remove pollstall timer */
3036 stop_pollstall_timer
++;
3037 if (timer_pending(&udc_pollstall_timer
))
3038 wait_for_completion(&on_pollstall_exit
);
3039 if (udc_pollstall_timer
.data
)
3040 del_timer_sync(&udc_pollstall_timer
);
3044 /* Reset all pci context */
3045 static void udc_pci_remove(struct pci_dev
*pdev
)
3049 dev
= pci_get_drvdata(pdev
);
3051 usb_del_gadget_udc(&udc
->gadget
);
3052 /* gadget driver must not be registered */
3053 BUG_ON(dev
->driver
!= NULL
);
3055 /* dma pool cleanup */
3056 if (dev
->data_requests
)
3057 pci_pool_destroy(dev
->data_requests
);
3059 if (dev
->stp_requests
) {
3060 /* cleanup DMA desc's for ep0in */
3061 pci_pool_free(dev
->stp_requests
,
3062 dev
->ep
[UDC_EP0OUT_IX
].td_stp
,
3063 dev
->ep
[UDC_EP0OUT_IX
].td_stp_dma
);
3064 pci_pool_free(dev
->stp_requests
,
3065 dev
->ep
[UDC_EP0OUT_IX
].td
,
3066 dev
->ep
[UDC_EP0OUT_IX
].td_phys
);
3068 pci_pool_destroy(dev
->stp_requests
);
3071 /* reset controller */
3072 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET
), &dev
->regs
->cfg
);
3073 if (dev
->irq_registered
)
3074 free_irq(pdev
->irq
, dev
);
3077 if (dev
->mem_region
)
3078 release_mem_region(pci_resource_start(pdev
, 0),
3079 pci_resource_len(pdev
, 0));
3081 pci_disable_device(pdev
);
3083 device_unregister(&dev
->gadget
.dev
);
3084 pci_set_drvdata(pdev
, NULL
);
3089 /* create dma pools on init */
3090 static int init_dma_pools(struct udc
*dev
)
3092 struct udc_stp_dma
*td_stp
;
3093 struct udc_data_dma
*td_data
;
3096 /* consistent DMA mode setting ? */
3098 use_dma_bufferfill_mode
= 0;
3101 use_dma_bufferfill_mode
= 1;
3105 dev
->data_requests
= dma_pool_create("data_requests", NULL
,
3106 sizeof(struct udc_data_dma
), 0, 0);
3107 if (!dev
->data_requests
) {
3108 DBG(dev
, "can't get request data pool\n");
3113 /* EP0 in dma regs = dev control regs */
3114 dev
->ep
[UDC_EP0IN_IX
].dma
= &dev
->regs
->ctl
;
3116 /* dma desc for setup data */
3117 dev
->stp_requests
= dma_pool_create("setup requests", NULL
,
3118 sizeof(struct udc_stp_dma
), 0, 0);
3119 if (!dev
->stp_requests
) {
3120 DBG(dev
, "can't get stp request pool\n");
3125 td_stp
= dma_pool_alloc(dev
->stp_requests
, GFP_KERNEL
,
3126 &dev
->ep
[UDC_EP0OUT_IX
].td_stp_dma
);
3127 if (td_stp
== NULL
) {
3131 dev
->ep
[UDC_EP0OUT_IX
].td_stp
= td_stp
;
3133 /* data: 0 packets !? */
3134 td_data
= dma_pool_alloc(dev
->stp_requests
, GFP_KERNEL
,
3135 &dev
->ep
[UDC_EP0OUT_IX
].td_phys
);
3136 if (td_data
== NULL
) {
3140 dev
->ep
[UDC_EP0OUT_IX
].td
= td_data
;
3147 /* Called by pci bus driver to init pci context */
3148 static int udc_pci_probe(
3149 struct pci_dev
*pdev
,
3150 const struct pci_device_id
*id
3154 unsigned long resource
;
3160 dev_dbg(&pdev
->dev
, "already probed\n");
3165 dev
= kzalloc(sizeof(struct udc
), GFP_KERNEL
);
3172 if (pci_enable_device(pdev
) < 0) {
3180 /* PCI resource allocation */
3181 resource
= pci_resource_start(pdev
, 0);
3182 len
= pci_resource_len(pdev
, 0);
3184 if (!request_mem_region(resource
, len
, name
)) {
3185 dev_dbg(&pdev
->dev
, "pci device used already\n");
3191 dev
->mem_region
= 1;
3193 dev
->virt_addr
= ioremap_nocache(resource
, len
);
3194 if (dev
->virt_addr
== NULL
) {
3195 dev_dbg(&pdev
->dev
, "start address cannot be mapped\n");
3203 dev_err(&pdev
->dev
, "irq not set\n");
3210 spin_lock_init(&dev
->lock
);
3211 /* udc csr registers base */
3212 dev
->csr
= dev
->virt_addr
+ UDC_CSR_ADDR
;
3213 /* dev registers base */
3214 dev
->regs
= dev
->virt_addr
+ UDC_DEVCFG_ADDR
;
3215 /* ep registers base */
3216 dev
->ep_regs
= dev
->virt_addr
+ UDC_EPREGS_ADDR
;
3218 dev
->rxfifo
= (u32 __iomem
*)(dev
->virt_addr
+ UDC_RXFIFO_ADDR
);
3219 dev
->txfifo
= (u32 __iomem
*)(dev
->virt_addr
+ UDC_TXFIFO_ADDR
);
3221 if (request_irq(pdev
->irq
, udc_irq
, IRQF_SHARED
, name
, dev
) != 0) {
3222 dev_dbg(&pdev
->dev
, "request_irq(%d) fail\n", pdev
->irq
);
3228 dev
->irq_registered
= 1;
3230 pci_set_drvdata(pdev
, dev
);
3232 /* chip revision for Hs AMD5536 */
3233 dev
->chiprev
= pdev
->revision
;
3235 pci_set_master(pdev
);
3236 pci_try_set_mwi(pdev
);
3238 /* init dma pools */
3240 retval
= init_dma_pools(dev
);
3245 dev
->phys_addr
= resource
;
3246 dev
->irq
= pdev
->irq
;
3248 dev
->gadget
.dev
.parent
= &pdev
->dev
;
3249 dev
->gadget
.dev
.dma_mask
= pdev
->dev
.dma_mask
;
3251 /* general probing */
3252 if (udc_probe(dev
) == 0)
3257 udc_pci_remove(pdev
);
3262 static int udc_probe(struct udc
*dev
)
3268 /* mark timer as not initialized */
3270 udc_pollstall_timer
.data
= 0;
3272 /* device struct setup */
3273 dev
->gadget
.ops
= &udc_ops
;
3275 dev_set_name(&dev
->gadget
.dev
, "gadget");
3276 dev
->gadget
.dev
.release
= gadget_release
;
3277 dev
->gadget
.name
= name
;
3278 dev
->gadget
.max_speed
= USB_SPEED_HIGH
;
3280 /* init registers, interrupts, ... */
3281 startup_registers(dev
);
3283 dev_info(&dev
->pdev
->dev
, "%s\n", mod_desc
);
3285 snprintf(tmp
, sizeof tmp
, "%d", dev
->irq
);
3286 dev_info(&dev
->pdev
->dev
,
3287 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3288 tmp
, dev
->phys_addr
, dev
->chiprev
,
3289 (dev
->chiprev
== UDC_HSA0_REV
) ? "A0" : "B1");
3290 strcpy(tmp
, UDC_DRIVER_VERSION_STRING
);
3291 if (dev
->chiprev
== UDC_HSA0_REV
) {
3292 dev_err(&dev
->pdev
->dev
, "chip revision is A0; too old\n");
3296 dev_info(&dev
->pdev
->dev
,
3297 "driver version: %s(for Geode5536 B1)\n", tmp
);
3300 retval
= usb_add_gadget_udc(&udc
->pdev
->dev
, &dev
->gadget
);
3304 retval
= device_register(&dev
->gadget
.dev
);
3306 usb_del_gadget_udc(&dev
->gadget
);
3307 put_device(&dev
->gadget
.dev
);
3312 init_timer(&udc_timer
);
3313 udc_timer
.function
= udc_timer_function
;
3315 /* timer pollstall init */
3316 init_timer(&udc_pollstall_timer
);
3317 udc_pollstall_timer
.function
= udc_pollstall_timer_function
;
3318 udc_pollstall_timer
.data
= 1;
3321 reg
= readl(&dev
->regs
->ctl
);
3322 reg
|= AMD_BIT(UDC_DEVCTL_SD
);
3323 writel(reg
, &dev
->regs
->ctl
);
3325 /* print dev register info */
3334 /* Initiates a remote wakeup */
3335 static int udc_remote_wakeup(struct udc
*dev
)
3337 unsigned long flags
;
3340 DBG(dev
, "UDC initiates remote wakeup\n");
3342 spin_lock_irqsave(&dev
->lock
, flags
);
3344 tmp
= readl(&dev
->regs
->ctl
);
3345 tmp
|= AMD_BIT(UDC_DEVCTL_RES
);
3346 writel(tmp
, &dev
->regs
->ctl
);
3347 tmp
&= AMD_CLEAR_BIT(UDC_DEVCTL_RES
);
3348 writel(tmp
, &dev
->regs
->ctl
);
3350 spin_unlock_irqrestore(&dev
->lock
, flags
);
3354 /* PCI device parameters */
3355 static DEFINE_PCI_DEVICE_TABLE(pci_id
) = {
3357 PCI_DEVICE(PCI_VENDOR_ID_AMD
, 0x2096),
3358 .class = (PCI_CLASS_SERIAL_USB
<< 8) | 0xfe,
3359 .class_mask
= 0xffffffff,
3363 MODULE_DEVICE_TABLE(pci
, pci_id
);
3366 static struct pci_driver udc_pci_driver
= {
3367 .name
= (char *) name
,
3369 .probe
= udc_pci_probe
,
3370 .remove
= udc_pci_remove
,
3373 module_pci_driver(udc_pci_driver
);
3375 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION
);
3376 MODULE_AUTHOR("Thomas Dahlmann");
3377 MODULE_LICENSE("GPL");