USB: Gadget: MIPS CI13xxx UDC bugfixes
[deliverable/linux.git] / drivers / usb / gadget / ci13xxx_udc.c
1 /*
2 * ci13xxx_udc.c - MIPS USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
16 *
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
20 * - UTIL: utilities
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
25 * - PCI: PCI core interface and PCI resources (interrupts, memory...)
26 *
27 * Compile Options
28 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
29 * - STALL_IN: non-empty bulk-in pipes cannot be halted
30 * if defined mass storage compliance succeeds but with warnings
31 * => case 4: Hi > Dn
32 * => case 5: Hi > Di
33 * => case 8: Hi <> Do
34 * if undefined usbtest 13 fails
35 * - TRACE: enable function tracing (depends on DEBUG)
36 *
37 * Main Features
38 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
39 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
40 * - Normal & LPM support
41 *
42 * USBTEST Report
43 * - OK: 0-12, 13 (STALL_IN defined) & 14
44 * - Not Supported: 15 & 16 (ISO)
45 *
46 * TODO List
47 * - OTG
48 * - Isochronous & Interrupt Traffic
49 * - Handle requests which spawns into several TDs
50 * - GET_STATUS(device) - always reports 0
51 * - Gadget API (majority of optional features)
52 * - Suspend & Remote Wakeup
53 */
54 #include <linux/device.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/init.h>
58 #include <linux/interrupt.h>
59 #include <linux/io.h>
60 #include <linux/irq.h>
61 #include <linux/kernel.h>
62 #include <linux/module.h>
63 #include <linux/pci.h>
64 #include <linux/usb/ch9.h>
65 #include <linux/usb/gadget.h>
66
67 #include "ci13xxx_udc.h"
68
69
70 /******************************************************************************
71 * DEFINE
72 *****************************************************************************/
73 /* ctrl register bank access */
74 static DEFINE_SPINLOCK(udc_lock);
75
76 /* driver name */
77 #define UDC_DRIVER_NAME "ci13xxx_udc"
78
79 /* control endpoint description */
80 static const struct usb_endpoint_descriptor
81 ctrl_endpt_desc = {
82 .bLength = USB_DT_ENDPOINT_SIZE,
83 .bDescriptorType = USB_DT_ENDPOINT,
84
85 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
86 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
87 };
88
89 /* UDC descriptor */
90 static struct ci13xxx *_udc;
91
92 /* Interrupt statistics */
93 #define ISR_MASK 0x1F
94 static struct {
95 u32 test;
96 u32 ui;
97 u32 uei;
98 u32 pci;
99 u32 uri;
100 u32 sli;
101 u32 none;
102 struct {
103 u32 cnt;
104 u32 buf[ISR_MASK+1];
105 u32 idx;
106 } hndl;
107 } isr_statistics;
108
109 /**
110 * ffs_nr: find first (least significant) bit set
111 * @x: the word to search
112 *
113 * This function returns bit number (instead of position)
114 */
115 static int ffs_nr(u32 x)
116 {
117 int n = ffs(x);
118
119 return n ? n-1 : 32;
120 }
121
122 /******************************************************************************
123 * HW block
124 *****************************************************************************/
125 /* register bank descriptor */
126 static struct {
127 unsigned lpm; /* is LPM? */
128 void __iomem *abs; /* bus map offset */
129 void __iomem *cap; /* bus map offset + CAP offset + CAP data */
130 size_t size; /* bank size */
131 } hw_bank;
132
133 /* UDC register map */
134 #define ABS_CAPLENGTH (0x100UL)
135 #define ABS_HCCPARAMS (0x108UL)
136 #define ABS_DCCPARAMS (0x124UL)
137 #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
138 /* offset to CAPLENTGH (addr + data) */
139 #define CAP_USBCMD (0x000UL)
140 #define CAP_USBSTS (0x004UL)
141 #define CAP_USBINTR (0x008UL)
142 #define CAP_DEVICEADDR (0x014UL)
143 #define CAP_ENDPTLISTADDR (0x018UL)
144 #define CAP_PORTSC (0x044UL)
145 #define CAP_DEVLC (0x084UL)
146 #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
147 #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
148 #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
149 #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
150 #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
151 #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
152 #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
153 #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
154
155 /* maximum number of enpoints: valid only after hw_device_reset() */
156 static unsigned hw_ep_max;
157
158 /**
159 * hw_ep_bit: calculates the bit number
160 * @num: endpoint number
161 * @dir: endpoint direction
162 *
163 * This function returns bit number
164 */
165 static inline int hw_ep_bit(int num, int dir)
166 {
167 return num + (dir ? 16 : 0);
168 }
169
170 /**
171 * hw_aread: reads from register bitfield
172 * @addr: address relative to bus map
173 * @mask: bitfield mask
174 *
175 * This function returns register bitfield data
176 */
177 static u32 hw_aread(u32 addr, u32 mask)
178 {
179 return ioread32(addr + hw_bank.abs) & mask;
180 }
181
182 /**
183 * hw_awrite: writes to register bitfield
184 * @addr: address relative to bus map
185 * @mask: bitfield mask
186 * @data: new data
187 */
188 static void hw_awrite(u32 addr, u32 mask, u32 data)
189 {
190 iowrite32(hw_aread(addr, ~mask) | (data & mask),
191 addr + hw_bank.abs);
192 }
193
194 /**
195 * hw_cread: reads from register bitfield
196 * @addr: address relative to CAP offset plus content
197 * @mask: bitfield mask
198 *
199 * This function returns register bitfield data
200 */
201 static u32 hw_cread(u32 addr, u32 mask)
202 {
203 return ioread32(addr + hw_bank.cap) & mask;
204 }
205
206 /**
207 * hw_cwrite: writes to register bitfield
208 * @addr: address relative to CAP offset plus content
209 * @mask: bitfield mask
210 * @data: new data
211 */
212 static void hw_cwrite(u32 addr, u32 mask, u32 data)
213 {
214 iowrite32(hw_cread(addr, ~mask) | (data & mask),
215 addr + hw_bank.cap);
216 }
217
218 /**
219 * hw_ctest_and_clear: tests & clears register bitfield
220 * @addr: address relative to CAP offset plus content
221 * @mask: bitfield mask
222 *
223 * This function returns register bitfield data
224 */
225 static u32 hw_ctest_and_clear(u32 addr, u32 mask)
226 {
227 u32 reg = hw_cread(addr, mask);
228
229 iowrite32(reg, addr + hw_bank.cap);
230 return reg;
231 }
232
233 /**
234 * hw_ctest_and_write: tests & writes register bitfield
235 * @addr: address relative to CAP offset plus content
236 * @mask: bitfield mask
237 * @data: new data
238 *
239 * This function returns register bitfield data
240 */
241 static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
242 {
243 u32 reg = hw_cread(addr, ~0);
244
245 iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
246 return (reg & mask) >> ffs_nr(mask);
247 }
248
249 /**
250 * hw_device_reset: resets chip (execute without interruption)
251 * @base: register base address
252 *
253 * This function returns an error code
254 */
255 static int hw_device_reset(void __iomem *base)
256 {
257 u32 reg;
258
259 /* bank is a module variable */
260 hw_bank.abs = base;
261
262 hw_bank.cap = hw_bank.abs;
263 hw_bank.cap += ABS_CAPLENGTH;
264 hw_bank.cap += ioread8(hw_bank.cap);
265
266 reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
267 hw_bank.lpm = reg;
268 hw_bank.size = hw_bank.cap - hw_bank.abs;
269 hw_bank.size += CAP_LAST;
270 hw_bank.size /= sizeof(u32);
271
272 /* should flush & stop before reset */
273 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
274 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
275
276 hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
277 while (hw_cread(CAP_USBCMD, USBCMD_RST))
278 udelay(10); /* not RTOS friendly */
279
280 /* USBMODE should be configured step by step */
281 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
282 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
283 hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
284
285 if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
286 pr_err("cannot enter in device mode");
287 pr_err("lpm = %i", hw_bank.lpm);
288 return -ENODEV;
289 }
290
291 reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
292 if (reg == 0 || reg > ENDPT_MAX)
293 return -ENODEV;
294
295 hw_ep_max = reg; /* cache hw ENDPT_MAX */
296
297 /* setup lock mode ? */
298
299 /* ENDPTSETUPSTAT is '0' by default */
300
301 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
302
303 return 0;
304 }
305
306 /**
307 * hw_device_state: enables/disables interrupts & starts/stops device (execute
308 * without interruption)
309 * @dma: 0 => disable, !0 => enable and set dma engine
310 *
311 * This function returns an error code
312 */
313 static int hw_device_state(u32 dma)
314 {
315 if (dma) {
316 hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
317 /* interrupt, error, port change, reset, sleep/suspend */
318 hw_cwrite(CAP_USBINTR, ~0,
319 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
320 hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
321 } else {
322 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
323 hw_cwrite(CAP_USBINTR, ~0, 0);
324 }
325 return 0;
326 }
327
328 /**
329 * hw_ep_flush: flush endpoint fifo (execute without interruption)
330 * @num: endpoint number
331 * @dir: endpoint direction
332 *
333 * This function returns an error code
334 */
335 static int hw_ep_flush(int num, int dir)
336 {
337 int n = hw_ep_bit(num, dir);
338
339 do {
340 /* flush any pending transfer */
341 hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
342 while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
343 cpu_relax();
344 } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
345
346 return 0;
347 }
348
349 /**
350 * hw_ep_disable: disables endpoint (execute without interruption)
351 * @num: endpoint number
352 * @dir: endpoint direction
353 *
354 * This function returns an error code
355 */
356 static int hw_ep_disable(int num, int dir)
357 {
358 hw_ep_flush(num, dir);
359 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
360 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
361 return 0;
362 }
363
364 /**
365 * hw_ep_enable: enables endpoint (execute without interruption)
366 * @num: endpoint number
367 * @dir: endpoint direction
368 * @type: endpoint type
369 *
370 * This function returns an error code
371 */
372 static int hw_ep_enable(int num, int dir, int type)
373 {
374 u32 mask, data;
375
376 if (dir) {
377 mask = ENDPTCTRL_TXT; /* type */
378 data = type << ffs_nr(mask);
379
380 mask |= ENDPTCTRL_TXS; /* unstall */
381 mask |= ENDPTCTRL_TXR; /* reset data toggle */
382 data |= ENDPTCTRL_TXR;
383 mask |= ENDPTCTRL_TXE; /* enable */
384 data |= ENDPTCTRL_TXE;
385 } else {
386 mask = ENDPTCTRL_RXT; /* type */
387 data = type << ffs_nr(mask);
388
389 mask |= ENDPTCTRL_RXS; /* unstall */
390 mask |= ENDPTCTRL_RXR; /* reset data toggle */
391 data |= ENDPTCTRL_RXR;
392 mask |= ENDPTCTRL_RXE; /* enable */
393 data |= ENDPTCTRL_RXE;
394 }
395 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
396 return 0;
397 }
398
399 /**
400 * hw_ep_get_halt: return endpoint halt status
401 * @num: endpoint number
402 * @dir: endpoint direction
403 *
404 * This function returns 1 if endpoint halted
405 */
406 static int hw_ep_get_halt(int num, int dir)
407 {
408 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
409
410 return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
411 }
412
413 /**
414 * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
415 * @num: endpoint number
416 * @dir: endpoint direction
417 *
418 * This function returns true if endpoint primed
419 */
420 static int hw_ep_is_primed(int num, int dir)
421 {
422 u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
423
424 return test_bit(hw_ep_bit(num, dir), (void *)&reg);
425 }
426
427 /**
428 * hw_test_and_clear_setup_status: test & clear setup status (execute without
429 * interruption)
430 * @n: bit number (endpoint)
431 *
432 * This function returns setup status
433 */
434 static int hw_test_and_clear_setup_status(int n)
435 {
436 return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
437 }
438
439 /**
440 * hw_ep_prime: primes endpoint (execute without interruption)
441 * @num: endpoint number
442 * @dir: endpoint direction
443 * @is_ctrl: true if control endpoint
444 *
445 * This function returns an error code
446 */
447 static int hw_ep_prime(int num, int dir, int is_ctrl)
448 {
449 int n = hw_ep_bit(num, dir);
450
451 /* the caller should flush first */
452 if (hw_ep_is_primed(num, dir))
453 return -EBUSY;
454
455 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
456 return -EAGAIN;
457
458 hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
459
460 while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
461 cpu_relax();
462 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
463 return -EAGAIN;
464
465 /* status shoult be tested according with manual but it doesn't work */
466 return 0;
467 }
468
469 /**
470 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
471 * without interruption)
472 * @num: endpoint number
473 * @dir: endpoint direction
474 * @value: true => stall, false => unstall
475 *
476 * This function returns an error code
477 */
478 static int hw_ep_set_halt(int num, int dir, int value)
479 {
480 if (value != 0 && value != 1)
481 return -EINVAL;
482
483 do {
484 u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
485 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
486 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
487
488 /* data toggle - reserved for EP0 but it's in ESS */
489 hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
490
491 } while (value != hw_ep_get_halt(num, dir));
492
493 return 0;
494 }
495
496 /**
497 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
498 * interruption)
499 * @n: interrupt bit
500 *
501 * This function returns an error code
502 */
503 static int hw_intr_clear(int n)
504 {
505 if (n >= REG_BITS)
506 return -EINVAL;
507
508 hw_cwrite(CAP_USBINTR, BIT(n), 0);
509 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
510 return 0;
511 }
512
513 /**
514 * hw_intr_force: enables interrupt & forces interrupt status (execute without
515 * interruption)
516 * @n: interrupt bit
517 *
518 * This function returns an error code
519 */
520 static int hw_intr_force(int n)
521 {
522 if (n >= REG_BITS)
523 return -EINVAL;
524
525 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
526 hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
527 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
528 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
529 return 0;
530 }
531
532 /**
533 * hw_is_port_high_speed: test if port is high speed
534 *
535 * This function returns true if high speed port
536 */
537 static int hw_port_is_high_speed(void)
538 {
539 return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
540 hw_cread(CAP_PORTSC, PORTSC_HSP);
541 }
542
543 /**
544 * hw_port_test_get: reads port test mode value
545 *
546 * This function returns port test mode value
547 */
548 static u8 hw_port_test_get(void)
549 {
550 return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
551 }
552
553 /**
554 * hw_port_test_set: writes port test mode (execute without interruption)
555 * @mode: new value
556 *
557 * This function returns an error code
558 */
559 static int hw_port_test_set(u8 mode)
560 {
561 const u8 TEST_MODE_MAX = 7;
562
563 if (mode > TEST_MODE_MAX)
564 return -EINVAL;
565
566 hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
567 return 0;
568 }
569
570 /**
571 * hw_read_intr_enable: returns interrupt enable register
572 *
573 * This function returns register data
574 */
575 static u32 hw_read_intr_enable(void)
576 {
577 return hw_cread(CAP_USBINTR, ~0);
578 }
579
580 /**
581 * hw_read_intr_status: returns interrupt status register
582 *
583 * This function returns register data
584 */
585 static u32 hw_read_intr_status(void)
586 {
587 return hw_cread(CAP_USBSTS, ~0);
588 }
589
590 /**
591 * hw_register_read: reads all device registers (execute without interruption)
592 * @buf: destination buffer
593 * @size: buffer size
594 *
595 * This function returns number of registers read
596 */
597 static size_t hw_register_read(u32 *buf, size_t size)
598 {
599 unsigned i;
600
601 if (size > hw_bank.size)
602 size = hw_bank.size;
603
604 for (i = 0; i < size; i++)
605 buf[i] = hw_aread(i * sizeof(u32), ~0);
606
607 return size;
608 }
609
610 /**
611 * hw_register_write: writes to register
612 * @addr: register address
613 * @data: register value
614 *
615 * This function returns an error code
616 */
617 static int hw_register_write(u16 addr, u32 data)
618 {
619 /* align */
620 addr /= sizeof(u32);
621
622 if (addr >= hw_bank.size)
623 return -EINVAL;
624
625 /* align */
626 addr *= sizeof(u32);
627
628 hw_awrite(addr, ~0, data);
629 return 0;
630 }
631
632 /**
633 * hw_test_and_clear_complete: test & clear complete status (execute without
634 * interruption)
635 * @n: bit number (endpoint)
636 *
637 * This function returns complete status
638 */
639 static int hw_test_and_clear_complete(int n)
640 {
641 return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
642 }
643
644 /**
645 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
646 * without interruption)
647 *
648 * This function returns active interrutps
649 */
650 static u32 hw_test_and_clear_intr_active(void)
651 {
652 u32 reg = hw_read_intr_status() & hw_read_intr_enable();
653
654 hw_cwrite(CAP_USBSTS, ~0, reg);
655 return reg;
656 }
657
658 /**
659 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
660 * interruption)
661 *
662 * This function returns guard value
663 */
664 static int hw_test_and_clear_setup_guard(void)
665 {
666 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
667 }
668
669 /**
670 * hw_test_and_set_setup_guard: test & set setup guard (execute without
671 * interruption)
672 *
673 * This function returns guard value
674 */
675 static int hw_test_and_set_setup_guard(void)
676 {
677 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
678 }
679
680 /**
681 * hw_usb_set_address: configures USB address (execute without interruption)
682 * @value: new USB address
683 *
684 * This function returns an error code
685 */
686 static int hw_usb_set_address(u8 value)
687 {
688 /* advance */
689 hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
690 value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
691 return 0;
692 }
693
694 /**
695 * hw_usb_reset: restart device after a bus reset (execute without
696 * interruption)
697 *
698 * This function returns an error code
699 */
700 static int hw_usb_reset(void)
701 {
702 hw_usb_set_address(0);
703
704 /* ESS flushes only at end?!? */
705 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
706
707 /* clear setup token semaphores */
708 hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
709
710 /* clear complete status */
711 hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
712
713 /* wait until all bits cleared */
714 while (hw_cread(CAP_ENDPTPRIME, ~0))
715 udelay(10); /* not RTOS friendly */
716
717 /* reset all endpoints ? */
718
719 /* reset internal status and wait for further instructions
720 no need to verify the port reset status (ESS does it) */
721
722 return 0;
723 }
724
725 /******************************************************************************
726 * DBG block
727 *****************************************************************************/
728 /**
729 * show_device: prints information about device capabilities and status
730 *
731 * Check "device.h" for details
732 */
733 static ssize_t show_device(struct device *dev, struct device_attribute *attr,
734 char *buf)
735 {
736 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
737 struct usb_gadget *gadget = &udc->gadget;
738 int n = 0;
739
740 dbg_trace("[%s] %p\n", __func__, buf);
741 if (attr == NULL || buf == NULL) {
742 dev_err(dev, "[%s] EINVAL\n", __func__);
743 return 0;
744 }
745
746 n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
747 gadget->speed);
748 n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
749 gadget->is_dualspeed);
750 n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
751 gadget->is_otg);
752 n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
753 gadget->is_a_peripheral);
754 n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
755 gadget->b_hnp_enable);
756 n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
757 gadget->a_hnp_support);
758 n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
759 gadget->a_alt_hnp_support);
760 n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
761 (gadget->name ? gadget->name : ""));
762
763 return n;
764 }
765 static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
766
767 /**
768 * show_driver: prints information about attached gadget (if any)
769 *
770 * Check "device.h" for details
771 */
772 static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
773 char *buf)
774 {
775 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
776 struct usb_gadget_driver *driver = udc->driver;
777 int n = 0;
778
779 dbg_trace("[%s] %p\n", __func__, buf);
780 if (attr == NULL || buf == NULL) {
781 dev_err(dev, "[%s] EINVAL\n", __func__);
782 return 0;
783 }
784
785 if (driver == NULL)
786 return scnprintf(buf, PAGE_SIZE,
787 "There is no gadget attached!\n");
788
789 n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
790 (driver->function ? driver->function : ""));
791 n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
792 driver->speed);
793
794 return n;
795 }
796 static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
797
798 /* Maximum event message length */
799 #define DBG_DATA_MSG 64UL
800
801 /* Maximum event messages */
802 #define DBG_DATA_MAX 128UL
803
804 /* Event buffer descriptor */
805 static struct {
806 char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
807 unsigned idx; /* index */
808 unsigned tty; /* print to console? */
809 rwlock_t lck; /* lock */
810 } dbg_data = {
811 .idx = 0,
812 .tty = 0,
813 .lck = __RW_LOCK_UNLOCKED(lck)
814 };
815
816 /**
817 * dbg_dec: decrements debug event index
818 * @idx: buffer index
819 */
820 static void dbg_dec(unsigned *idx)
821 {
822 *idx = (*idx - 1) & (DBG_DATA_MAX-1);
823 }
824
825 /**
826 * dbg_inc: increments debug event index
827 * @idx: buffer index
828 */
829 static void dbg_inc(unsigned *idx)
830 {
831 *idx = (*idx + 1) & (DBG_DATA_MAX-1);
832 }
833
834 /**
835 * dbg_print: prints the common part of the event
836 * @addr: endpoint address
837 * @name: event name
838 * @status: status
839 * @extra: extra information
840 */
841 static void dbg_print(u8 addr, const char *name, int status, const char *extra)
842 {
843 struct timeval tval;
844 unsigned int stamp;
845 unsigned long flags;
846
847 write_lock_irqsave(&dbg_data.lck, flags);
848
849 do_gettimeofday(&tval);
850 stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
851 stamp = stamp * 1000000 + tval.tv_usec;
852
853 scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
854 "%04X\t» %02X %-7.7s %4i «\t%s\n",
855 stamp, addr, name, status, extra);
856
857 dbg_inc(&dbg_data.idx);
858
859 write_unlock_irqrestore(&dbg_data.lck, flags);
860
861 if (dbg_data.tty != 0)
862 pr_notice("%04X\t» %02X %-7.7s %4i «\t%s\n",
863 stamp, addr, name, status, extra);
864 }
865
866 /**
867 * dbg_done: prints a DONE event
868 * @addr: endpoint address
869 * @td: transfer descriptor
870 * @status: status
871 */
872 static void dbg_done(u8 addr, const u32 token, int status)
873 {
874 char msg[DBG_DATA_MSG];
875
876 scnprintf(msg, sizeof(msg), "%d %02X",
877 (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
878 (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
879 dbg_print(addr, "DONE", status, msg);
880 }
881
882 /**
883 * dbg_event: prints a generic event
884 * @addr: endpoint address
885 * @name: event name
886 * @status: status
887 */
888 static void dbg_event(u8 addr, const char *name, int status)
889 {
890 if (name != NULL)
891 dbg_print(addr, name, status, "");
892 }
893
894 /*
895 * dbg_queue: prints a QUEUE event
896 * @addr: endpoint address
897 * @req: USB request
898 * @status: status
899 */
900 static void dbg_queue(u8 addr, const struct usb_request *req, int status)
901 {
902 char msg[DBG_DATA_MSG];
903
904 if (req != NULL) {
905 scnprintf(msg, sizeof(msg),
906 "%d %d", !req->no_interrupt, req->length);
907 dbg_print(addr, "QUEUE", status, msg);
908 }
909 }
910
911 /**
912 * dbg_setup: prints a SETUP event
913 * @addr: endpoint address
914 * @req: setup request
915 */
916 static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
917 {
918 char msg[DBG_DATA_MSG];
919
920 if (req != NULL) {
921 scnprintf(msg, sizeof(msg),
922 "%02X %02X %04X %04X %d", req->bRequestType,
923 req->bRequest, le16_to_cpu(req->wValue),
924 le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
925 dbg_print(addr, "SETUP", 0, msg);
926 }
927 }
928
929 /**
930 * show_events: displays the event buffer
931 *
932 * Check "device.h" for details
933 */
934 static ssize_t show_events(struct device *dev, struct device_attribute *attr,
935 char *buf)
936 {
937 unsigned long flags;
938 unsigned i, j, n = 0;
939
940 dbg_trace("[%s] %p\n", __func__, buf);
941 if (attr == NULL || buf == NULL) {
942 dev_err(dev, "[%s] EINVAL\n", __func__);
943 return 0;
944 }
945
946 read_lock_irqsave(&dbg_data.lck, flags);
947
948 i = dbg_data.idx;
949 for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
950 n += strlen(dbg_data.buf[i]);
951 if (n >= PAGE_SIZE) {
952 n -= strlen(dbg_data.buf[i]);
953 break;
954 }
955 }
956 for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
957 j += scnprintf(buf + j, PAGE_SIZE - j,
958 "%s", dbg_data.buf[i]);
959
960 read_unlock_irqrestore(&dbg_data.lck, flags);
961
962 return n;
963 }
964
965 /**
966 * store_events: configure if events are going to be also printed to console
967 *
968 * Check "device.h" for details
969 */
970 static ssize_t store_events(struct device *dev, struct device_attribute *attr,
971 const char *buf, size_t count)
972 {
973 unsigned tty;
974
975 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
976 if (attr == NULL || buf == NULL) {
977 dev_err(dev, "[%s] EINVAL\n", __func__);
978 goto done;
979 }
980
981 if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
982 dev_err(dev, "<1|0>: enable|disable console log\n");
983 goto done;
984 }
985
986 dbg_data.tty = tty;
987 dev_info(dev, "tty = %u", dbg_data.tty);
988
989 done:
990 return count;
991 }
992 static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
993
994 /**
995 * show_inters: interrupt status, enable status and historic
996 *
997 * Check "device.h" for details
998 */
999 static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
1000 char *buf)
1001 {
1002 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1003 unsigned long flags;
1004 u32 intr;
1005 unsigned i, j, n = 0;
1006
1007 dbg_trace("[%s] %p\n", __func__, buf);
1008 if (attr == NULL || buf == NULL) {
1009 dev_err(dev, "[%s] EINVAL\n", __func__);
1010 return 0;
1011 }
1012
1013 spin_lock_irqsave(udc->lock, flags);
1014
1015 n += scnprintf(buf + n, PAGE_SIZE - n,
1016 "status = %08x\n", hw_read_intr_status());
1017 n += scnprintf(buf + n, PAGE_SIZE - n,
1018 "enable = %08x\n", hw_read_intr_enable());
1019
1020 n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
1021 isr_statistics.test);
1022 n += scnprintf(buf + n, PAGE_SIZE - n, "» ui = %d\n",
1023 isr_statistics.ui);
1024 n += scnprintf(buf + n, PAGE_SIZE - n, "» uei = %d\n",
1025 isr_statistics.uei);
1026 n += scnprintf(buf + n, PAGE_SIZE - n, "» pci = %d\n",
1027 isr_statistics.pci);
1028 n += scnprintf(buf + n, PAGE_SIZE - n, "» uri = %d\n",
1029 isr_statistics.uri);
1030 n += scnprintf(buf + n, PAGE_SIZE - n, "» sli = %d\n",
1031 isr_statistics.sli);
1032 n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
1033 isr_statistics.none);
1034 n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
1035 isr_statistics.hndl.cnt);
1036
1037 for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
1038 i &= ISR_MASK;
1039 intr = isr_statistics.hndl.buf[i];
1040
1041 if (USBi_UI & intr)
1042 n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
1043 intr &= ~USBi_UI;
1044 if (USBi_UEI & intr)
1045 n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
1046 intr &= ~USBi_UEI;
1047 if (USBi_PCI & intr)
1048 n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
1049 intr &= ~USBi_PCI;
1050 if (USBi_URI & intr)
1051 n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
1052 intr &= ~USBi_URI;
1053 if (USBi_SLI & intr)
1054 n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
1055 intr &= ~USBi_SLI;
1056 if (intr)
1057 n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
1058 if (isr_statistics.hndl.buf[i])
1059 n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
1060 }
1061
1062 spin_unlock_irqrestore(udc->lock, flags);
1063
1064 return n;
1065 }
1066
1067 /**
1068 * store_inters: enable & force or disable an individual interrutps
1069 * (to be used for test purposes only)
1070 *
1071 * Check "device.h" for details
1072 */
1073 static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
1074 const char *buf, size_t count)
1075 {
1076 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1077 unsigned long flags;
1078 unsigned en, bit;
1079
1080 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1081 if (attr == NULL || buf == NULL) {
1082 dev_err(dev, "[%s] EINVAL\n", __func__);
1083 goto done;
1084 }
1085
1086 if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
1087 dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
1088 goto done;
1089 }
1090
1091 spin_lock_irqsave(udc->lock, flags);
1092 if (en) {
1093 if (hw_intr_force(bit))
1094 dev_err(dev, "invalid bit number\n");
1095 else
1096 isr_statistics.test++;
1097 } else {
1098 if (hw_intr_clear(bit))
1099 dev_err(dev, "invalid bit number\n");
1100 }
1101 spin_unlock_irqrestore(udc->lock, flags);
1102
1103 done:
1104 return count;
1105 }
1106 static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
1107
1108 /**
1109 * show_port_test: reads port test mode
1110 *
1111 * Check "device.h" for details
1112 */
1113 static ssize_t show_port_test(struct device *dev,
1114 struct device_attribute *attr, char *buf)
1115 {
1116 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1117 unsigned long flags;
1118 unsigned mode;
1119
1120 dbg_trace("[%s] %p\n", __func__, buf);
1121 if (attr == NULL || buf == NULL) {
1122 dev_err(dev, "[%s] EINVAL\n", __func__);
1123 return 0;
1124 }
1125
1126 spin_lock_irqsave(udc->lock, flags);
1127 mode = hw_port_test_get();
1128 spin_unlock_irqrestore(udc->lock, flags);
1129
1130 return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
1131 }
1132
1133 /**
1134 * store_port_test: writes port test mode
1135 *
1136 * Check "device.h" for details
1137 */
1138 static ssize_t store_port_test(struct device *dev,
1139 struct device_attribute *attr,
1140 const char *buf, size_t count)
1141 {
1142 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1143 unsigned long flags;
1144 unsigned mode;
1145
1146 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1147 if (attr == NULL || buf == NULL) {
1148 dev_err(dev, "[%s] EINVAL\n", __func__);
1149 goto done;
1150 }
1151
1152 if (sscanf(buf, "%u", &mode) != 1) {
1153 dev_err(dev, "<mode>: set port test mode");
1154 goto done;
1155 }
1156
1157 spin_lock_irqsave(udc->lock, flags);
1158 if (hw_port_test_set(mode))
1159 dev_err(dev, "invalid mode\n");
1160 spin_unlock_irqrestore(udc->lock, flags);
1161
1162 done:
1163 return count;
1164 }
1165 static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
1166 show_port_test, store_port_test);
1167
1168 /**
1169 * show_qheads: DMA contents of all queue heads
1170 *
1171 * Check "device.h" for details
1172 */
1173 static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
1174 char *buf)
1175 {
1176 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1177 unsigned long flags;
1178 unsigned i, j, n = 0;
1179
1180 dbg_trace("[%s] %p\n", __func__, buf);
1181 if (attr == NULL || buf == NULL) {
1182 dev_err(dev, "[%s] EINVAL\n", __func__);
1183 return 0;
1184 }
1185
1186 spin_lock_irqsave(udc->lock, flags);
1187 for (i = 0; i < hw_ep_max; i++) {
1188 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
1189 n += scnprintf(buf + n, PAGE_SIZE - n,
1190 "EP=%02i: RX=%08X TX=%08X\n",
1191 i, (u32)mEp->qh[RX].dma, (u32)mEp->qh[TX].dma);
1192 for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
1193 n += scnprintf(buf + n, PAGE_SIZE - n,
1194 " %04X: %08X %08X\n", j,
1195 *((u32 *)mEp->qh[RX].ptr + j),
1196 *((u32 *)mEp->qh[TX].ptr + j));
1197 }
1198 }
1199 spin_unlock_irqrestore(udc->lock, flags);
1200
1201 return n;
1202 }
1203 static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
1204
1205 /**
1206 * show_registers: dumps all registers
1207 *
1208 * Check "device.h" for details
1209 */
1210 static ssize_t show_registers(struct device *dev,
1211 struct device_attribute *attr, char *buf)
1212 {
1213 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1214 unsigned long flags;
1215 u32 dump[512];
1216 unsigned i, k, n = 0;
1217
1218 dbg_trace("[%s] %p\n", __func__, buf);
1219 if (attr == NULL || buf == NULL) {
1220 dev_err(dev, "[%s] EINVAL\n", __func__);
1221 return 0;
1222 }
1223
1224 spin_lock_irqsave(udc->lock, flags);
1225 k = hw_register_read(dump, sizeof(dump)/sizeof(u32));
1226 spin_unlock_irqrestore(udc->lock, flags);
1227
1228 for (i = 0; i < k; i++) {
1229 n += scnprintf(buf + n, PAGE_SIZE - n,
1230 "reg[0x%04X] = 0x%08X\n",
1231 i * (unsigned)sizeof(u32), dump[i]);
1232 }
1233
1234 return n;
1235 }
1236
1237 /**
1238 * store_registers: writes value to register address
1239 *
1240 * Check "device.h" for details
1241 */
1242 static ssize_t store_registers(struct device *dev,
1243 struct device_attribute *attr,
1244 const char *buf, size_t count)
1245 {
1246 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1247 unsigned long addr, data, flags;
1248
1249 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1250 if (attr == NULL || buf == NULL) {
1251 dev_err(dev, "[%s] EINVAL\n", __func__);
1252 goto done;
1253 }
1254
1255 if (sscanf(buf, "%li %li", &addr, &data) != 2) {
1256 dev_err(dev, "<addr> <data>: write data to register address");
1257 goto done;
1258 }
1259
1260 spin_lock_irqsave(udc->lock, flags);
1261 if (hw_register_write(addr, data))
1262 dev_err(dev, "invalid address range\n");
1263 spin_unlock_irqrestore(udc->lock, flags);
1264
1265 done:
1266 return count;
1267 }
1268 static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
1269 show_registers, store_registers);
1270
1271 /**
1272 * show_requests: DMA contents of all requests currently queued (all endpts)
1273 *
1274 * Check "device.h" for details
1275 */
1276 static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
1277 char *buf)
1278 {
1279 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1280 unsigned long flags;
1281 struct list_head *ptr = NULL;
1282 struct ci13xxx_req *req = NULL;
1283 unsigned i, j, k, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
1284
1285 dbg_trace("[%s] %p\n", __func__, buf);
1286 if (attr == NULL || buf == NULL) {
1287 dev_err(dev, "[%s] EINVAL\n", __func__);
1288 return 0;
1289 }
1290
1291 spin_lock_irqsave(udc->lock, flags);
1292 for (i = 0; i < hw_ep_max; i++)
1293 for (k = RX; k <= TX; k++)
1294 list_for_each(ptr, &udc->ci13xxx_ep[i].qh[k].queue)
1295 {
1296 req = list_entry(ptr,
1297 struct ci13xxx_req, queue);
1298
1299 n += scnprintf(buf + n, PAGE_SIZE - n,
1300 "EP=%02i: TD=%08X %s\n",
1301 i, (u32)req->dma,
1302 ((k == RX) ? "RX" : "TX"));
1303
1304 for (j = 0; j < qSize; j++)
1305 n += scnprintf(buf + n, PAGE_SIZE - n,
1306 " %04X: %08X\n", j,
1307 *((u32 *)req->ptr + j));
1308 }
1309 spin_unlock_irqrestore(udc->lock, flags);
1310
1311 return n;
1312 }
1313 static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
1314
1315 /**
1316 * dbg_create_files: initializes the attribute interface
1317 * @dev: device
1318 *
1319 * This function returns an error code
1320 */
1321 __maybe_unused static int dbg_create_files(struct device *dev)
1322 {
1323 int retval = 0;
1324
1325 if (dev == NULL)
1326 return -EINVAL;
1327 retval = device_create_file(dev, &dev_attr_device);
1328 if (retval)
1329 goto done;
1330 retval = device_create_file(dev, &dev_attr_driver);
1331 if (retval)
1332 goto rm_device;
1333 retval = device_create_file(dev, &dev_attr_events);
1334 if (retval)
1335 goto rm_driver;
1336 retval = device_create_file(dev, &dev_attr_inters);
1337 if (retval)
1338 goto rm_events;
1339 retval = device_create_file(dev, &dev_attr_port_test);
1340 if (retval)
1341 goto rm_inters;
1342 retval = device_create_file(dev, &dev_attr_qheads);
1343 if (retval)
1344 goto rm_port_test;
1345 retval = device_create_file(dev, &dev_attr_registers);
1346 if (retval)
1347 goto rm_qheads;
1348 retval = device_create_file(dev, &dev_attr_requests);
1349 if (retval)
1350 goto rm_registers;
1351 return 0;
1352
1353 rm_registers:
1354 device_remove_file(dev, &dev_attr_registers);
1355 rm_qheads:
1356 device_remove_file(dev, &dev_attr_qheads);
1357 rm_port_test:
1358 device_remove_file(dev, &dev_attr_port_test);
1359 rm_inters:
1360 device_remove_file(dev, &dev_attr_inters);
1361 rm_events:
1362 device_remove_file(dev, &dev_attr_events);
1363 rm_driver:
1364 device_remove_file(dev, &dev_attr_driver);
1365 rm_device:
1366 device_remove_file(dev, &dev_attr_device);
1367 done:
1368 return retval;
1369 }
1370
1371 /**
1372 * dbg_remove_files: destroys the attribute interface
1373 * @dev: device
1374 *
1375 * This function returns an error code
1376 */
1377 __maybe_unused static int dbg_remove_files(struct device *dev)
1378 {
1379 if (dev == NULL)
1380 return -EINVAL;
1381 device_remove_file(dev, &dev_attr_requests);
1382 device_remove_file(dev, &dev_attr_registers);
1383 device_remove_file(dev, &dev_attr_qheads);
1384 device_remove_file(dev, &dev_attr_port_test);
1385 device_remove_file(dev, &dev_attr_inters);
1386 device_remove_file(dev, &dev_attr_events);
1387 device_remove_file(dev, &dev_attr_driver);
1388 device_remove_file(dev, &dev_attr_device);
1389 return 0;
1390 }
1391
1392 /******************************************************************************
1393 * UTIL block
1394 *****************************************************************************/
1395 /**
1396 * _usb_addr: calculates endpoint address from direction & number
1397 * @ep: endpoint
1398 */
1399 static inline u8 _usb_addr(struct ci13xxx_ep *ep)
1400 {
1401 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
1402 }
1403
1404 /**
1405 * _hardware_queue: configures a request at hardware level
1406 * @gadget: gadget
1407 * @mEp: endpoint
1408 *
1409 * This function returns an error code
1410 */
1411 static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1412 {
1413 unsigned i;
1414
1415 trace("%p, %p", mEp, mReq);
1416
1417 /* don't queue twice */
1418 if (mReq->req.status == -EALREADY)
1419 return -EALREADY;
1420
1421 if (hw_ep_is_primed(mEp->num, mEp->dir))
1422 return -EBUSY;
1423
1424 mReq->req.status = -EALREADY;
1425
1426 if (mReq->req.length && !mReq->req.dma) {
1427 mReq->req.dma = \
1428 dma_map_single(mEp->device, mReq->req.buf,
1429 mReq->req.length, mEp->dir ?
1430 DMA_TO_DEVICE : DMA_FROM_DEVICE);
1431 if (mReq->req.dma == 0)
1432 return -ENOMEM;
1433
1434 mReq->map = 1;
1435 }
1436
1437 /*
1438 * TD configuration
1439 * TODO - handle requests which spawns into several TDs
1440 */
1441 memset(mReq->ptr, 0, sizeof(*mReq->ptr));
1442 mReq->ptr->next |= TD_TERMINATE;
1443 mReq->ptr->token = mReq->req.length << ffs_nr(TD_TOTAL_BYTES);
1444 mReq->ptr->token &= TD_TOTAL_BYTES;
1445 mReq->ptr->token |= TD_IOC;
1446 mReq->ptr->token |= TD_STATUS_ACTIVE;
1447 mReq->ptr->page[0] = mReq->req.dma;
1448 for (i = 1; i < 5; i++)
1449 mReq->ptr->page[i] =
1450 (mReq->req.dma + i * PAGE_SIZE) & ~TD_RESERVED_MASK;
1451
1452 /*
1453 * QH configuration
1454 * At this point it's guaranteed exclusive access to qhead
1455 * (endpt is not primed) so it's no need to use tripwire
1456 */
1457 mEp->qh[mEp->dir].ptr->td.next = mReq->dma; /* TERMINATE = 0 */
1458 mEp->qh[mEp->dir].ptr->td.token &= ~TD_STATUS; /* clear status */
1459 if (mReq->req.zero == 0)
1460 mEp->qh[mEp->dir].ptr->cap |= QH_ZLT;
1461 else
1462 mEp->qh[mEp->dir].ptr->cap &= ~QH_ZLT;
1463
1464 wmb(); /* synchronize before ep prime */
1465
1466 return hw_ep_prime(mEp->num, mEp->dir,
1467 mEp->type == USB_ENDPOINT_XFER_CONTROL);
1468 }
1469
1470 /**
1471 * _hardware_dequeue: handles a request at hardware level
1472 * @gadget: gadget
1473 * @mEp: endpoint
1474 *
1475 * This function returns an error code
1476 */
1477 static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1478 {
1479 trace("%p, %p", mEp, mReq);
1480
1481 if (mReq->req.status != -EALREADY)
1482 return -EINVAL;
1483
1484 if (hw_ep_is_primed(mEp->num, mEp->dir))
1485 hw_ep_flush(mEp->num, mEp->dir);
1486
1487 mReq->req.status = 0;
1488
1489 if (mReq->map) {
1490 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
1491 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1492 mReq->req.dma = 0;
1493 mReq->map = 0;
1494 }
1495
1496 mReq->req.status = mReq->ptr->token & TD_STATUS;
1497 if ((TD_STATUS_ACTIVE & mReq->req.status) != 0)
1498 mReq->req.status = -ECONNRESET;
1499 else if ((TD_STATUS_HALTED & mReq->req.status) != 0)
1500 mReq->req.status = -1;
1501 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
1502 mReq->req.status = -1;
1503 else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
1504 mReq->req.status = -1;
1505
1506 mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
1507 mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
1508 mReq->req.actual = mReq->req.length - mReq->req.actual;
1509 mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
1510
1511 return mReq->req.actual;
1512 }
1513
1514 /**
1515 * _ep_nuke: dequeues all endpoint requests
1516 * @mEp: endpoint
1517 *
1518 * This function returns an error code
1519 * Caller must hold lock
1520 */
1521 static int _ep_nuke(struct ci13xxx_ep *mEp)
1522 __releases(mEp->lock)
1523 __acquires(mEp->lock)
1524 {
1525 trace("%p", mEp);
1526
1527 if (mEp == NULL)
1528 return -EINVAL;
1529
1530 hw_ep_flush(mEp->num, mEp->dir);
1531
1532 while (!list_empty(&mEp->qh[mEp->dir].queue)) {
1533
1534 /* pop oldest request */
1535 struct ci13xxx_req *mReq = \
1536 list_entry(mEp->qh[mEp->dir].queue.next,
1537 struct ci13xxx_req, queue);
1538 list_del_init(&mReq->queue);
1539 mReq->req.status = -ESHUTDOWN;
1540
1541 if (!mReq->req.no_interrupt && mReq->req.complete != NULL) {
1542 spin_unlock(mEp->lock);
1543 mReq->req.complete(&mEp->ep, &mReq->req);
1544 spin_lock(mEp->lock);
1545 }
1546 }
1547 return 0;
1548 }
1549
1550 /**
1551 * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
1552 * @gadget: gadget
1553 *
1554 * This function returns an error code
1555 * Caller must hold lock
1556 */
1557 static int _gadget_stop_activity(struct usb_gadget *gadget)
1558 __releases(udc->lock)
1559 __acquires(udc->lock)
1560 {
1561 struct usb_ep *ep;
1562 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
1563 struct ci13xxx_ep *mEp = container_of(gadget->ep0,
1564 struct ci13xxx_ep, ep);
1565
1566 trace("%p", gadget);
1567
1568 if (gadget == NULL)
1569 return -EINVAL;
1570
1571 spin_unlock(udc->lock);
1572
1573 /* flush all endpoints */
1574 gadget_for_each_ep(ep, gadget) {
1575 usb_ep_fifo_flush(ep);
1576 }
1577 usb_ep_fifo_flush(gadget->ep0);
1578
1579 udc->driver->disconnect(gadget);
1580
1581 /* make sure to disable all endpoints */
1582 gadget_for_each_ep(ep, gadget) {
1583 usb_ep_disable(ep);
1584 }
1585 usb_ep_disable(gadget->ep0);
1586
1587 if (mEp->status != NULL) {
1588 usb_ep_free_request(gadget->ep0, mEp->status);
1589 mEp->status = NULL;
1590 }
1591
1592 spin_lock(udc->lock);
1593
1594 return 0;
1595 }
1596
1597 /******************************************************************************
1598 * ISR block
1599 *****************************************************************************/
1600 /**
1601 * isr_reset_handler: USB reset interrupt handler
1602 * @udc: UDC device
1603 *
1604 * This function resets USB engine after a bus reset occurred
1605 */
1606 static void isr_reset_handler(struct ci13xxx *udc)
1607 __releases(udc->lock)
1608 __acquires(udc->lock)
1609 {
1610 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[0];
1611 int retval;
1612
1613 trace("%p", udc);
1614
1615 if (udc == NULL) {
1616 err("EINVAL");
1617 return;
1618 }
1619
1620 dbg_event(0xFF, "BUS RST", 0);
1621
1622 retval = _gadget_stop_activity(&udc->gadget);
1623 if (retval)
1624 goto done;
1625
1626 retval = hw_usb_reset();
1627 if (retval)
1628 goto done;
1629
1630 spin_unlock(udc->lock);
1631 retval = usb_ep_enable(&mEp->ep, &ctrl_endpt_desc);
1632 if (!retval) {
1633 mEp->status = usb_ep_alloc_request(&mEp->ep, GFP_KERNEL);
1634 if (mEp->status == NULL) {
1635 usb_ep_disable(&mEp->ep);
1636 retval = -ENOMEM;
1637 }
1638 }
1639 spin_lock(udc->lock);
1640
1641 done:
1642 if (retval)
1643 err("error: %i", retval);
1644 }
1645
1646 /**
1647 * isr_get_status_complete: get_status request complete function
1648 * @ep: endpoint
1649 * @req: request handled
1650 *
1651 * Caller must release lock
1652 */
1653 static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
1654 {
1655 trace("%p, %p", ep, req);
1656
1657 if (ep == NULL || req == NULL) {
1658 err("EINVAL");
1659 return;
1660 }
1661
1662 kfree(req->buf);
1663 usb_ep_free_request(ep, req);
1664 }
1665
1666 /**
1667 * isr_get_status_response: get_status request response
1668 * @ep: endpoint
1669 * @setup: setup request packet
1670 *
1671 * This function returns an error code
1672 */
1673 static int isr_get_status_response(struct ci13xxx_ep *mEp,
1674 struct usb_ctrlrequest *setup)
1675 __releases(mEp->lock)
1676 __acquires(mEp->lock)
1677 {
1678 struct usb_request *req = NULL;
1679 gfp_t gfp_flags = GFP_ATOMIC;
1680 int dir, num, retval;
1681
1682 trace("%p, %p", mEp, setup);
1683
1684 if (mEp == NULL || setup == NULL)
1685 return -EINVAL;
1686
1687 spin_unlock(mEp->lock);
1688 req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
1689 spin_lock(mEp->lock);
1690 if (req == NULL)
1691 return -ENOMEM;
1692
1693 req->complete = isr_get_status_complete;
1694 req->length = 2;
1695 req->buf = kzalloc(req->length, gfp_flags);
1696 if (req->buf == NULL) {
1697 retval = -ENOMEM;
1698 goto err_free_req;
1699 }
1700
1701 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1702 /* TODO: D1 - Remote Wakeup; D0 - Self Powered */
1703 retval = 0;
1704 } else if ((setup->bRequestType & USB_RECIP_MASK) \
1705 == USB_RECIP_ENDPOINT) {
1706 dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
1707 TX : RX;
1708 num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
1709 *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
1710 }
1711 /* else do nothing; reserved for future use */
1712
1713 spin_unlock(mEp->lock);
1714 retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
1715 spin_lock(mEp->lock);
1716 if (retval)
1717 goto err_free_buf;
1718
1719 return 0;
1720
1721 err_free_buf:
1722 kfree(req->buf);
1723 err_free_req:
1724 spin_unlock(mEp->lock);
1725 usb_ep_free_request(&mEp->ep, req);
1726 spin_lock(mEp->lock);
1727 return retval;
1728 }
1729
1730 /**
1731 * isr_setup_status_phase: queues the status phase of a setup transation
1732 * @mEp: endpoint
1733 *
1734 * This function returns an error code
1735 */
1736 static int isr_setup_status_phase(struct ci13xxx_ep *mEp)
1737 __releases(mEp->lock)
1738 __acquires(mEp->lock)
1739 {
1740 int retval;
1741
1742 trace("%p", mEp);
1743
1744 /* mEp is always valid & configured */
1745
1746 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1747 mEp->dir = (mEp->dir == TX) ? RX : TX;
1748
1749 mEp->status->no_interrupt = 1;
1750
1751 spin_unlock(mEp->lock);
1752 retval = usb_ep_queue(&mEp->ep, mEp->status, GFP_ATOMIC);
1753 spin_lock(mEp->lock);
1754
1755 return retval;
1756 }
1757
1758 /**
1759 * isr_tr_complete_low: transaction complete low level handler
1760 * @mEp: endpoint
1761 *
1762 * This function returns an error code
1763 * Caller must hold lock
1764 */
1765 static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
1766 __releases(mEp->lock)
1767 __acquires(mEp->lock)
1768 {
1769 struct ci13xxx_req *mReq;
1770 int retval;
1771
1772 trace("%p", mEp);
1773
1774 if (list_empty(&mEp->qh[mEp->dir].queue))
1775 return -EINVAL;
1776
1777 /* pop oldest request */
1778 mReq = list_entry(mEp->qh[mEp->dir].queue.next,
1779 struct ci13xxx_req, queue);
1780 list_del_init(&mReq->queue);
1781
1782 retval = _hardware_dequeue(mEp, mReq);
1783 if (retval < 0) {
1784 dbg_event(_usb_addr(mEp), "DONE", retval);
1785 goto done;
1786 }
1787
1788 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
1789
1790 if (!mReq->req.no_interrupt && mReq->req.complete != NULL) {
1791 spin_unlock(mEp->lock);
1792 mReq->req.complete(&mEp->ep, &mReq->req);
1793 spin_lock(mEp->lock);
1794 }
1795
1796 if (!list_empty(&mEp->qh[mEp->dir].queue)) {
1797 mReq = list_entry(mEp->qh[mEp->dir].queue.next,
1798 struct ci13xxx_req, queue);
1799 _hardware_enqueue(mEp, mReq);
1800 }
1801
1802 done:
1803 return retval;
1804 }
1805
1806 /**
1807 * isr_tr_complete_handler: transaction complete interrupt handler
1808 * @udc: UDC descriptor
1809 *
1810 * This function handles traffic events
1811 */
1812 static void isr_tr_complete_handler(struct ci13xxx *udc)
1813 __releases(udc->lock)
1814 __acquires(udc->lock)
1815 {
1816 unsigned i;
1817
1818 trace("%p", udc);
1819
1820 if (udc == NULL) {
1821 err("EINVAL");
1822 return;
1823 }
1824
1825 for (i = 0; i < hw_ep_max; i++) {
1826 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
1827 int type, num, err = -EINVAL;
1828 struct usb_ctrlrequest req;
1829
1830
1831 if (mEp->desc == NULL)
1832 continue; /* not configured */
1833
1834 if ((mEp->dir == RX && hw_test_and_clear_complete(i)) ||
1835 (mEp->dir == TX && hw_test_and_clear_complete(i + 16))) {
1836 err = isr_tr_complete_low(mEp);
1837 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
1838 if (err > 0) /* needs status phase */
1839 err = isr_setup_status_phase(mEp);
1840 if (err < 0) {
1841 dbg_event(_usb_addr(mEp),
1842 "ERROR", err);
1843 spin_unlock(udc->lock);
1844 if (usb_ep_set_halt(&mEp->ep))
1845 err("error: ep_set_halt");
1846 spin_lock(udc->lock);
1847 }
1848 }
1849 }
1850
1851 if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
1852 !hw_test_and_clear_setup_status(i))
1853 continue;
1854
1855 if (i != 0) {
1856 warn("ctrl traffic received at endpoint");
1857 continue;
1858 }
1859
1860 /* read_setup_packet */
1861 do {
1862 hw_test_and_set_setup_guard();
1863 memcpy(&req, &mEp->qh[RX].ptr->setup, sizeof(req));
1864 } while (!hw_test_and_clear_setup_guard());
1865
1866 type = req.bRequestType;
1867
1868 mEp->dir = (type & USB_DIR_IN) ? TX : RX;
1869
1870 dbg_setup(_usb_addr(mEp), &req);
1871
1872 switch (req.bRequest) {
1873 case USB_REQ_CLEAR_FEATURE:
1874 if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1875 le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
1876 goto delegate;
1877 if (req.wLength != 0)
1878 break;
1879 num = le16_to_cpu(req.wIndex);
1880 num &= USB_ENDPOINT_NUMBER_MASK;
1881 if (!udc->ci13xxx_ep[num].wedge) {
1882 spin_unlock(udc->lock);
1883 err = usb_ep_clear_halt(
1884 &udc->ci13xxx_ep[num].ep);
1885 spin_lock(udc->lock);
1886 if (err)
1887 break;
1888 }
1889 err = isr_setup_status_phase(mEp);
1890 break;
1891 case USB_REQ_GET_STATUS:
1892 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
1893 type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
1894 type != (USB_DIR_IN|USB_RECIP_INTERFACE))
1895 goto delegate;
1896 if (le16_to_cpu(req.wLength) != 2 ||
1897 le16_to_cpu(req.wValue) != 0)
1898 break;
1899 err = isr_get_status_response(mEp, &req);
1900 break;
1901 case USB_REQ_SET_ADDRESS:
1902 if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
1903 goto delegate;
1904 if (le16_to_cpu(req.wLength) != 0 ||
1905 le16_to_cpu(req.wIndex) != 0)
1906 break;
1907 err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
1908 if (err)
1909 break;
1910 err = isr_setup_status_phase(mEp);
1911 break;
1912 case USB_REQ_SET_FEATURE:
1913 if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1914 le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
1915 goto delegate;
1916 if (req.wLength != 0)
1917 break;
1918 num = le16_to_cpu(req.wIndex);
1919 num &= USB_ENDPOINT_NUMBER_MASK;
1920
1921 spin_unlock(udc->lock);
1922 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
1923 spin_lock(udc->lock);
1924 if (err)
1925 break;
1926 err = isr_setup_status_phase(mEp);
1927 break;
1928 default:
1929 delegate:
1930 if (req.wLength == 0) /* no data phase */
1931 mEp->dir = TX;
1932
1933 spin_unlock(udc->lock);
1934 err = udc->driver->setup(&udc->gadget, &req);
1935 spin_lock(udc->lock);
1936 break;
1937 }
1938
1939 if (err < 0) {
1940 dbg_event(_usb_addr(mEp), "ERROR", err);
1941
1942 spin_unlock(udc->lock);
1943 if (usb_ep_set_halt(&mEp->ep))
1944 err("error: ep_set_halt");
1945 spin_lock(udc->lock);
1946 }
1947 }
1948 }
1949
1950 /******************************************************************************
1951 * ENDPT block
1952 *****************************************************************************/
1953 /**
1954 * ep_enable: configure endpoint, making it usable
1955 *
1956 * Check usb_ep_enable() at "usb_gadget.h" for details
1957 */
1958 static int ep_enable(struct usb_ep *ep,
1959 const struct usb_endpoint_descriptor *desc)
1960 {
1961 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1962 int direction, retval = 0;
1963 unsigned long flags;
1964
1965 trace("%p, %p", ep, desc);
1966
1967 if (ep == NULL || desc == NULL)
1968 return -EINVAL;
1969
1970 spin_lock_irqsave(mEp->lock, flags);
1971
1972 /* only internal SW should enable ctrl endpts */
1973
1974 mEp->desc = desc;
1975
1976 if (!list_empty(&mEp->qh[mEp->dir].queue))
1977 warn("enabling a non-empty endpoint!");
1978
1979 mEp->dir = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? TX : RX;
1980 mEp->num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
1981 mEp->type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1982
1983 mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
1984
1985 direction = mEp->dir;
1986 do {
1987 dbg_event(_usb_addr(mEp), "ENABLE", 0);
1988
1989 mEp->qh[mEp->dir].ptr->cap = 0;
1990
1991 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1992 mEp->qh[mEp->dir].ptr->cap |= QH_IOS;
1993 else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
1994 mEp->qh[mEp->dir].ptr->cap &= ~QH_MULT;
1995 else
1996 mEp->qh[mEp->dir].ptr->cap &= ~QH_ZLT;
1997
1998 mEp->qh[mEp->dir].ptr->cap |=
1999 (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
2000 mEp->qh[mEp->dir].ptr->td.next |= TD_TERMINATE; /* needed? */
2001
2002 retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
2003
2004 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2005 mEp->dir = (mEp->dir == TX) ? RX : TX;
2006
2007 } while (mEp->dir != direction);
2008
2009 spin_unlock_irqrestore(mEp->lock, flags);
2010 return retval;
2011 }
2012
2013 /**
2014 * ep_disable: endpoint is no longer usable
2015 *
2016 * Check usb_ep_disable() at "usb_gadget.h" for details
2017 */
2018 static int ep_disable(struct usb_ep *ep)
2019 {
2020 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2021 int direction, retval = 0;
2022 unsigned long flags;
2023
2024 trace("%p", ep);
2025
2026 if (ep == NULL)
2027 return -EINVAL;
2028 else if (mEp->desc == NULL)
2029 return -EBUSY;
2030
2031 spin_lock_irqsave(mEp->lock, flags);
2032
2033 /* only internal SW should disable ctrl endpts */
2034
2035 direction = mEp->dir;
2036 do {
2037 dbg_event(_usb_addr(mEp), "DISABLE", 0);
2038
2039 retval |= _ep_nuke(mEp);
2040 retval |= hw_ep_disable(mEp->num, mEp->dir);
2041
2042 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2043 mEp->dir = (mEp->dir == TX) ? RX : TX;
2044
2045 } while (mEp->dir != direction);
2046
2047 mEp->desc = NULL;
2048
2049 spin_unlock_irqrestore(mEp->lock, flags);
2050 return retval;
2051 }
2052
2053 /**
2054 * ep_alloc_request: allocate a request object to use with this endpoint
2055 *
2056 * Check usb_ep_alloc_request() at "usb_gadget.h" for details
2057 */
2058 static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
2059 {
2060 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2061 struct ci13xxx_req *mReq = NULL;
2062 unsigned long flags;
2063
2064 trace("%p, %i", ep, gfp_flags);
2065
2066 if (ep == NULL) {
2067 err("EINVAL");
2068 return NULL;
2069 }
2070
2071 spin_lock_irqsave(mEp->lock, flags);
2072
2073 mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
2074 if (mReq != NULL) {
2075 INIT_LIST_HEAD(&mReq->queue);
2076
2077 mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
2078 &mReq->dma);
2079 if (mReq->ptr == NULL) {
2080 kfree(mReq);
2081 mReq = NULL;
2082 }
2083 }
2084
2085 dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
2086
2087 spin_unlock_irqrestore(mEp->lock, flags);
2088
2089 return (mReq == NULL) ? NULL : &mReq->req;
2090 }
2091
2092 /**
2093 * ep_free_request: frees a request object
2094 *
2095 * Check usb_ep_free_request() at "usb_gadget.h" for details
2096 */
2097 static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
2098 {
2099 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2100 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2101 unsigned long flags;
2102
2103 trace("%p, %p", ep, req);
2104
2105 if (ep == NULL || req == NULL) {
2106 err("EINVAL");
2107 return;
2108 } else if (!list_empty(&mReq->queue)) {
2109 err("EBUSY");
2110 return;
2111 }
2112
2113 spin_lock_irqsave(mEp->lock, flags);
2114
2115 if (mReq->ptr)
2116 dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
2117 kfree(mReq);
2118
2119 dbg_event(_usb_addr(mEp), "FREE", 0);
2120
2121 spin_unlock_irqrestore(mEp->lock, flags);
2122 }
2123
2124 /**
2125 * ep_queue: queues (submits) an I/O request to an endpoint
2126 *
2127 * Check usb_ep_queue()* at usb_gadget.h" for details
2128 */
2129 static int ep_queue(struct usb_ep *ep, struct usb_request *req,
2130 gfp_t __maybe_unused gfp_flags)
2131 {
2132 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2133 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2134 int retval = 0;
2135 unsigned long flags;
2136
2137 trace("%p, %p, %X", ep, req, gfp_flags);
2138
2139 if (ep == NULL || req == NULL || mEp->desc == NULL)
2140 return -EINVAL;
2141
2142 spin_lock_irqsave(mEp->lock, flags);
2143
2144 if (mEp->type == USB_ENDPOINT_XFER_CONTROL &&
2145 !list_empty(&mEp->qh[mEp->dir].queue)) {
2146 _ep_nuke(mEp);
2147 retval = -EOVERFLOW;
2148 warn("endpoint ctrl %X nuked", _usb_addr(mEp));
2149 }
2150
2151 /* first nuke then test link, e.g. previous status has not sent */
2152 if (!list_empty(&mReq->queue)) {
2153 retval = -EBUSY;
2154 err("request already in queue");
2155 goto done;
2156 }
2157
2158 if (req->length > (4 * PAGE_SIZE)) {
2159 req->length = (4 * PAGE_SIZE);
2160 retval = -EMSGSIZE;
2161 warn("request length truncated");
2162 }
2163
2164 dbg_queue(_usb_addr(mEp), req, retval);
2165
2166 /* push request */
2167 mReq->req.status = -EINPROGRESS;
2168 mReq->req.actual = 0;
2169 list_add_tail(&mReq->queue, &mEp->qh[mEp->dir].queue);
2170
2171 retval = _hardware_enqueue(mEp, mReq);
2172 if (retval == -EALREADY || retval == -EBUSY) {
2173 dbg_event(_usb_addr(mEp), "QUEUE", retval);
2174 retval = 0;
2175 }
2176
2177 done:
2178 spin_unlock_irqrestore(mEp->lock, flags);
2179 return retval;
2180 }
2181
2182 /**
2183 * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
2184 *
2185 * Check usb_ep_dequeue() at "usb_gadget.h" for details
2186 */
2187 static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2188 {
2189 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2190 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2191 unsigned long flags;
2192
2193 trace("%p, %p", ep, req);
2194
2195 if (ep == NULL || req == NULL || mEp->desc == NULL ||
2196 list_empty(&mReq->queue) || list_empty(&mEp->qh[mEp->dir].queue))
2197 return -EINVAL;
2198
2199 spin_lock_irqsave(mEp->lock, flags);
2200
2201 dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
2202
2203 if (mReq->req.status == -EALREADY)
2204 _hardware_dequeue(mEp, mReq);
2205
2206 /* pop request */
2207 list_del_init(&mReq->queue);
2208 req->status = -ECONNRESET;
2209
2210 if (!mReq->req.no_interrupt && mReq->req.complete != NULL) {
2211 spin_unlock(mEp->lock);
2212 mReq->req.complete(&mEp->ep, &mReq->req);
2213 spin_lock(mEp->lock);
2214 }
2215
2216 spin_unlock_irqrestore(mEp->lock, flags);
2217 return 0;
2218 }
2219
2220 /**
2221 * ep_set_halt: sets the endpoint halt feature
2222 *
2223 * Check usb_ep_set_halt() at "usb_gadget.h" for details
2224 */
2225 static int ep_set_halt(struct usb_ep *ep, int value)
2226 {
2227 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2228 int direction, retval = 0;
2229 unsigned long flags;
2230
2231 trace("%p, %i", ep, value);
2232
2233 if (ep == NULL || mEp->desc == NULL)
2234 return -EINVAL;
2235
2236 spin_lock_irqsave(mEp->lock, flags);
2237
2238 #ifndef STALL_IN
2239 /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
2240 if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
2241 !list_empty(&mEp->qh[mEp->dir].queue)) {
2242 spin_unlock_irqrestore(mEp->lock, flags);
2243 return -EAGAIN;
2244 }
2245 #endif
2246
2247 direction = mEp->dir;
2248 do {
2249 dbg_event(_usb_addr(mEp), "HALT", value);
2250 retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
2251
2252 if (!value)
2253 mEp->wedge = 0;
2254
2255 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2256 mEp->dir = (mEp->dir == TX) ? RX : TX;
2257
2258 } while (mEp->dir != direction);
2259
2260 spin_unlock_irqrestore(mEp->lock, flags);
2261 return retval;
2262 }
2263
2264 /**
2265 * ep_set_wedge: sets the halt feature and ignores clear requests
2266 *
2267 * Check usb_ep_set_wedge() at "usb_gadget.h" for details
2268 */
2269 static int ep_set_wedge(struct usb_ep *ep)
2270 {
2271 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2272 unsigned long flags;
2273
2274 trace("%p", ep);
2275
2276 if (ep == NULL || mEp->desc == NULL)
2277 return -EINVAL;
2278
2279 spin_lock_irqsave(mEp->lock, flags);
2280
2281 dbg_event(_usb_addr(mEp), "WEDGE", 0);
2282 mEp->wedge = 1;
2283
2284 spin_unlock_irqrestore(mEp->lock, flags);
2285
2286 return usb_ep_set_halt(ep);
2287 }
2288
2289 /**
2290 * ep_fifo_flush: flushes contents of a fifo
2291 *
2292 * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
2293 */
2294 static void ep_fifo_flush(struct usb_ep *ep)
2295 {
2296 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2297 unsigned long flags;
2298
2299 trace("%p", ep);
2300
2301 if (ep == NULL) {
2302 err("%02X: -EINVAL", _usb_addr(mEp));
2303 return;
2304 }
2305
2306 spin_lock_irqsave(mEp->lock, flags);
2307
2308 dbg_event(_usb_addr(mEp), "FFLUSH", 0);
2309 hw_ep_flush(mEp->num, mEp->dir);
2310
2311 spin_unlock_irqrestore(mEp->lock, flags);
2312 }
2313
2314 /**
2315 * Endpoint-specific part of the API to the USB controller hardware
2316 * Check "usb_gadget.h" for details
2317 */
2318 static const struct usb_ep_ops usb_ep_ops = {
2319 .enable = ep_enable,
2320 .disable = ep_disable,
2321 .alloc_request = ep_alloc_request,
2322 .free_request = ep_free_request,
2323 .queue = ep_queue,
2324 .dequeue = ep_dequeue,
2325 .set_halt = ep_set_halt,
2326 .set_wedge = ep_set_wedge,
2327 .fifo_flush = ep_fifo_flush,
2328 };
2329
2330 /******************************************************************************
2331 * GADGET block
2332 *****************************************************************************/
2333 /**
2334 * Device operations part of the API to the USB controller hardware,
2335 * which don't involve endpoints (or i/o)
2336 * Check "usb_gadget.h" for details
2337 */
2338 static const struct usb_gadget_ops usb_gadget_ops;
2339
2340 /**
2341 * usb_gadget_register_driver: register a gadget driver
2342 *
2343 * Check usb_gadget_register_driver() at "usb_gadget.h" for details
2344 * Interrupts are enabled here
2345 */
2346 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2347 {
2348 struct ci13xxx *udc = _udc;
2349 unsigned long i, k, flags;
2350 int retval = -ENOMEM;
2351
2352 trace("%p", driver);
2353
2354 if (driver == NULL ||
2355 driver->bind == NULL ||
2356 driver->unbind == NULL ||
2357 driver->setup == NULL ||
2358 driver->disconnect == NULL ||
2359 driver->suspend == NULL ||
2360 driver->resume == NULL)
2361 return -EINVAL;
2362 else if (udc == NULL)
2363 return -ENODEV;
2364 else if (udc->driver != NULL)
2365 return -EBUSY;
2366
2367 /* alloc resources */
2368 udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
2369 sizeof(struct ci13xxx_qh),
2370 64, PAGE_SIZE);
2371 if (udc->qh_pool == NULL)
2372 return -ENOMEM;
2373
2374 udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
2375 sizeof(struct ci13xxx_td),
2376 64, PAGE_SIZE);
2377 if (udc->td_pool == NULL) {
2378 dma_pool_destroy(udc->qh_pool);
2379 udc->qh_pool = NULL;
2380 return -ENOMEM;
2381 }
2382
2383 spin_lock_irqsave(udc->lock, flags);
2384
2385 info("hw_ep_max = %d", hw_ep_max);
2386
2387 udc->driver = driver;
2388 udc->gadget.ops = NULL;
2389 udc->gadget.dev.driver = NULL;
2390
2391 retval = 0;
2392 for (i = 0; i < hw_ep_max; i++) {
2393 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
2394
2395 scnprintf(mEp->name, sizeof(mEp->name), "ep%i", (int)i);
2396
2397 mEp->lock = udc->lock;
2398 mEp->device = &udc->gadget.dev;
2399 mEp->td_pool = udc->td_pool;
2400
2401 mEp->ep.name = mEp->name;
2402 mEp->ep.ops = &usb_ep_ops;
2403 mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
2404
2405 /* this allocation cannot be random */
2406 for (k = RX; k <= TX; k++) {
2407 INIT_LIST_HEAD(&mEp->qh[k].queue);
2408 mEp->qh[k].ptr = dma_pool_alloc(udc->qh_pool,
2409 GFP_KERNEL,
2410 &mEp->qh[k].dma);
2411 if (mEp->qh[k].ptr == NULL)
2412 retval = -ENOMEM;
2413 else
2414 memset(mEp->qh[k].ptr, 0,
2415 sizeof(*mEp->qh[k].ptr));
2416 }
2417 if (i == 0)
2418 udc->gadget.ep0 = &mEp->ep;
2419 else
2420 list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
2421 }
2422 if (retval)
2423 goto done;
2424
2425 /* bind gadget */
2426 driver->driver.bus = NULL;
2427 udc->gadget.ops = &usb_gadget_ops;
2428 udc->gadget.dev.driver = &driver->driver;
2429
2430 spin_unlock_irqrestore(udc->lock, flags);
2431 retval = driver->bind(&udc->gadget); /* MAY SLEEP */
2432 spin_lock_irqsave(udc->lock, flags);
2433
2434 if (retval) {
2435 udc->gadget.ops = NULL;
2436 udc->gadget.dev.driver = NULL;
2437 goto done;
2438 }
2439
2440 retval = hw_device_state(udc->ci13xxx_ep[0].qh[RX].dma);
2441
2442 done:
2443 spin_unlock_irqrestore(udc->lock, flags);
2444 if (retval)
2445 usb_gadget_unregister_driver(driver);
2446 return retval;
2447 }
2448 EXPORT_SYMBOL(usb_gadget_register_driver);
2449
2450 /**
2451 * usb_gadget_unregister_driver: unregister a gadget driver
2452 *
2453 * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
2454 */
2455 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2456 {
2457 struct ci13xxx *udc = _udc;
2458 unsigned long i, k, flags;
2459
2460 trace("%p", driver);
2461
2462 if (driver == NULL ||
2463 driver->bind == NULL ||
2464 driver->unbind == NULL ||
2465 driver->setup == NULL ||
2466 driver->disconnect == NULL ||
2467 driver->suspend == NULL ||
2468 driver->resume == NULL ||
2469 driver != udc->driver)
2470 return -EINVAL;
2471
2472 spin_lock_irqsave(udc->lock, flags);
2473
2474 hw_device_state(0);
2475
2476 /* unbind gadget */
2477 if (udc->gadget.ops != NULL) {
2478 _gadget_stop_activity(&udc->gadget);
2479
2480 spin_unlock_irqrestore(udc->lock, flags);
2481 driver->unbind(&udc->gadget); /* MAY SLEEP */
2482 spin_lock_irqsave(udc->lock, flags);
2483
2484 udc->gadget.ops = NULL;
2485 udc->gadget.dev.driver = NULL;
2486 }
2487
2488 /* free resources */
2489 for (i = 0; i < hw_ep_max; i++) {
2490 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
2491
2492 if (i == 0)
2493 udc->gadget.ep0 = NULL;
2494 else if (!list_empty(&mEp->ep.ep_list))
2495 list_del_init(&mEp->ep.ep_list);
2496
2497 for (k = RX; k <= TX; k++)
2498 if (mEp->qh[k].ptr != NULL)
2499 dma_pool_free(udc->qh_pool,
2500 mEp->qh[k].ptr, mEp->qh[k].dma);
2501 }
2502
2503 udc->driver = NULL;
2504
2505 spin_unlock_irqrestore(udc->lock, flags);
2506
2507 if (udc->td_pool != NULL) {
2508 dma_pool_destroy(udc->td_pool);
2509 udc->td_pool = NULL;
2510 }
2511 if (udc->qh_pool != NULL) {
2512 dma_pool_destroy(udc->qh_pool);
2513 udc->qh_pool = NULL;
2514 }
2515
2516 return 0;
2517 }
2518 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2519
2520 /******************************************************************************
2521 * BUS block
2522 *****************************************************************************/
2523 /**
2524 * udc_irq: global interrupt handler
2525 *
2526 * This function returns IRQ_HANDLED if the IRQ has been handled
2527 * It locks access to registers
2528 */
2529 static irqreturn_t udc_irq(void)
2530 {
2531 struct ci13xxx *udc = _udc;
2532 irqreturn_t retval;
2533 u32 intr;
2534
2535 trace();
2536
2537 if (udc == NULL) {
2538 err("ENODEV");
2539 return IRQ_HANDLED;
2540 }
2541
2542 spin_lock(udc->lock);
2543 intr = hw_test_and_clear_intr_active();
2544 if (intr) {
2545 isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
2546 isr_statistics.hndl.idx &= ISR_MASK;
2547 isr_statistics.hndl.cnt++;
2548
2549 /* order defines priority - do NOT change it */
2550 if (USBi_URI & intr) {
2551 isr_statistics.uri++;
2552 isr_reset_handler(udc);
2553 }
2554 if (USBi_PCI & intr) {
2555 isr_statistics.pci++;
2556 udc->gadget.speed = hw_port_is_high_speed() ?
2557 USB_SPEED_HIGH : USB_SPEED_FULL;
2558 }
2559 if (USBi_UEI & intr)
2560 isr_statistics.uei++;
2561 if (USBi_UI & intr) {
2562 isr_statistics.ui++;
2563 isr_tr_complete_handler(udc);
2564 }
2565 if (USBi_SLI & intr)
2566 isr_statistics.sli++;
2567 retval = IRQ_HANDLED;
2568 } else {
2569 isr_statistics.none++;
2570 retval = IRQ_NONE;
2571 }
2572 spin_unlock(udc->lock);
2573
2574 return retval;
2575 }
2576
2577 /**
2578 * udc_release: driver release function
2579 * @dev: device
2580 *
2581 * Currently does nothing
2582 */
2583 static void udc_release(struct device *dev)
2584 {
2585 trace("%p", dev);
2586
2587 if (dev == NULL)
2588 err("EINVAL");
2589 }
2590
2591 /**
2592 * udc_probe: parent probe must call this to initialize UDC
2593 * @dev: parent device
2594 * @regs: registers base address
2595 * @name: driver name
2596 *
2597 * This function returns an error code
2598 * No interrupts active, the IRQ has not been requested yet
2599 * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
2600 */
2601 static int udc_probe(struct device *dev, void __iomem *regs, const char *name)
2602 {
2603 struct ci13xxx *udc;
2604 int retval = 0;
2605
2606 trace("%p, %p, %p", dev, regs, name);
2607
2608 if (dev == NULL || regs == NULL || name == NULL)
2609 return -EINVAL;
2610
2611 udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
2612 if (udc == NULL)
2613 return -ENOMEM;
2614
2615 udc->lock = &udc_lock;
2616
2617 retval = hw_device_reset(regs);
2618 if (retval)
2619 goto done;
2620
2621 udc->gadget.ops = NULL;
2622 udc->gadget.speed = USB_SPEED_UNKNOWN;
2623 udc->gadget.is_dualspeed = 1;
2624 udc->gadget.is_otg = 0;
2625 udc->gadget.name = name;
2626
2627 INIT_LIST_HEAD(&udc->gadget.ep_list);
2628 udc->gadget.ep0 = NULL;
2629
2630 dev_set_name(&udc->gadget.dev, "gadget");
2631 udc->gadget.dev.dma_mask = dev->dma_mask;
2632 udc->gadget.dev.parent = dev;
2633 udc->gadget.dev.release = udc_release;
2634
2635 retval = device_register(&udc->gadget.dev);
2636 if (retval)
2637 goto done;
2638
2639 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2640 retval = dbg_create_files(&udc->gadget.dev);
2641 #endif
2642 if (retval) {
2643 device_unregister(&udc->gadget.dev);
2644 goto done;
2645 }
2646
2647 _udc = udc;
2648 return retval;
2649
2650 done:
2651 err("error = %i", retval);
2652 kfree(udc);
2653 _udc = NULL;
2654 return retval;
2655 }
2656
2657 /**
2658 * udc_remove: parent remove must call this to remove UDC
2659 *
2660 * No interrupts active, the IRQ has been released
2661 */
2662 static void udc_remove(void)
2663 {
2664 struct ci13xxx *udc = _udc;
2665
2666 if (udc == NULL) {
2667 err("EINVAL");
2668 return;
2669 }
2670
2671 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2672 dbg_remove_files(&udc->gadget.dev);
2673 #endif
2674 device_unregister(&udc->gadget.dev);
2675
2676 kfree(udc);
2677 _udc = NULL;
2678 }
2679
2680 /******************************************************************************
2681 * PCI block
2682 *****************************************************************************/
2683 /**
2684 * ci13xxx_pci_irq: interrut handler
2685 * @irq: irq number
2686 * @pdev: USB Device Controller interrupt source
2687 *
2688 * This function returns IRQ_HANDLED if the IRQ has been handled
2689 * This is an ISR don't trace, use attribute interface instead
2690 */
2691 static irqreturn_t ci13xxx_pci_irq(int irq, void *pdev)
2692 {
2693 if (irq == 0) {
2694 dev_err(&((struct pci_dev *)pdev)->dev, "Invalid IRQ0 usage!");
2695 return IRQ_HANDLED;
2696 }
2697 return udc_irq();
2698 }
2699
2700 /**
2701 * ci13xxx_pci_probe: PCI probe
2702 * @pdev: USB device controller being probed
2703 * @id: PCI hotplug ID connecting controller to UDC framework
2704 *
2705 * This function returns an error code
2706 * Allocates basic PCI resources for this USB device controller, and then
2707 * invokes the udc_probe() method to start the UDC associated with it
2708 */
2709 static int __devinit ci13xxx_pci_probe(struct pci_dev *pdev,
2710 const struct pci_device_id *id)
2711 {
2712 void __iomem *regs = NULL;
2713 int retval = 0;
2714
2715 if (id == NULL)
2716 return -EINVAL;
2717
2718 retval = pci_enable_device(pdev);
2719 if (retval)
2720 goto done;
2721
2722 if (!pdev->irq) {
2723 dev_err(&pdev->dev, "No IRQ, check BIOS/PCI setup!");
2724 retval = -ENODEV;
2725 goto disable_device;
2726 }
2727
2728 retval = pci_request_regions(pdev, UDC_DRIVER_NAME);
2729 if (retval)
2730 goto disable_device;
2731
2732 /* BAR 0 holds all the registers */
2733 regs = pci_iomap(pdev, 0, 0);
2734 if (!regs) {
2735 dev_err(&pdev->dev, "Error mapping memory!");
2736 retval = -EFAULT;
2737 goto release_regions;
2738 }
2739 pci_set_drvdata(pdev, (__force void *)regs);
2740
2741 pci_set_master(pdev);
2742 pci_try_set_mwi(pdev);
2743
2744 retval = udc_probe(&pdev->dev, regs, UDC_DRIVER_NAME);
2745 if (retval)
2746 goto iounmap;
2747
2748 /* our device does not have MSI capability */
2749
2750 retval = request_irq(pdev->irq, ci13xxx_pci_irq, IRQF_SHARED,
2751 UDC_DRIVER_NAME, pdev);
2752 if (retval)
2753 goto gadget_remove;
2754
2755 return 0;
2756
2757 gadget_remove:
2758 udc_remove();
2759 iounmap:
2760 pci_iounmap(pdev, regs);
2761 release_regions:
2762 pci_release_regions(pdev);
2763 disable_device:
2764 pci_disable_device(pdev);
2765 done:
2766 return retval;
2767 }
2768
2769 /**
2770 * ci13xxx_pci_remove: PCI remove
2771 * @pdev: USB Device Controller being removed
2772 *
2773 * Reverses the effect of ci13xxx_pci_probe(),
2774 * first invoking the udc_remove() and then releases
2775 * all PCI resources allocated for this USB device controller
2776 */
2777 static void __devexit ci13xxx_pci_remove(struct pci_dev *pdev)
2778 {
2779 free_irq(pdev->irq, pdev);
2780 udc_remove();
2781 pci_iounmap(pdev, (__force void __iomem *)pci_get_drvdata(pdev));
2782 pci_release_regions(pdev);
2783 pci_disable_device(pdev);
2784 }
2785
2786 /**
2787 * PCI device table
2788 * PCI device structure
2789 *
2790 * Check "pci.h" for details
2791 */
2792 static DEFINE_PCI_DEVICE_TABLE(ci13xxx_pci_id_table) = {
2793 { PCI_DEVICE(0x153F, 0x1004) },
2794 { PCI_DEVICE(0x153F, 0x1006) },
2795 { 0, 0, 0, 0, 0, 0, 0 /* end: all zeroes */ }
2796 };
2797 MODULE_DEVICE_TABLE(pci, ci13xxx_pci_id_table);
2798
2799 static struct pci_driver ci13xxx_pci_driver = {
2800 .name = UDC_DRIVER_NAME,
2801 .id_table = ci13xxx_pci_id_table,
2802 .probe = ci13xxx_pci_probe,
2803 .remove = __devexit_p(ci13xxx_pci_remove),
2804 };
2805
2806 /**
2807 * ci13xxx_pci_init: module init
2808 *
2809 * Driver load
2810 */
2811 static int __init ci13xxx_pci_init(void)
2812 {
2813 return pci_register_driver(&ci13xxx_pci_driver);
2814 }
2815 module_init(ci13xxx_pci_init);
2816
2817 /**
2818 * ci13xxx_pci_exit: module exit
2819 *
2820 * Driver unload
2821 */
2822 static void __exit ci13xxx_pci_exit(void)
2823 {
2824 pci_unregister_driver(&ci13xxx_pci_driver);
2825 }
2826 module_exit(ci13xxx_pci_exit);
2827
2828 MODULE_AUTHOR("MIPS - David Lopo <dlopo@chipidea.mips.com>");
2829 MODULE_DESCRIPTION("MIPS CI13XXX USB Peripheral Controller");
2830 MODULE_LICENSE("GPL");
2831 MODULE_VERSION("June 2008");
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