2 * USB Gadget driver for LPC32xx
5 * Kevin Wells <kevin.wells@nxp.com>
7 * Roland Stigge <stigge@antcom.de>
9 * Copyright (C) 2006 Philips Semiconductors
10 * Copyright (C) 2009 NXP Semiconductors
11 * Copyright (C) 2012 Roland Stigge
13 * Note: This driver is based on original work done by Mike James for
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/delay.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/init.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/proc_fs.h>
42 #include <linux/clk.h>
43 #include <linux/usb/ch9.h>
44 #include <linux/usb/gadget.h>
45 #include <linux/i2c.h>
46 #include <linux/kthread.h>
47 #include <linux/freezer.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/dmapool.h>
50 #include <linux/workqueue.h>
52 #include <linux/usb/isp1301.h>
54 #include <asm/byteorder.h>
55 #include <mach/hardware.h>
58 #include <asm/system.h>
60 #include <mach/platform.h>
61 #include <mach/irqs.h>
62 #include <mach/board.h>
63 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
64 #include <linux/debugfs.h>
65 #include <linux/seq_file.h>
69 * USB device configuration structure
71 typedef void (*usc_chg_event
)(int);
72 struct lpc32xx_usbd_cfg
{
73 int vbus_drv_pol
; /* 0=active low drive for VBUS via ISP1301 */
74 usc_chg_event conn_chgb
; /* Connection change event (optional) */
75 usc_chg_event susp_chgb
; /* Suspend/resume event (optional) */
76 usc_chg_event rmwk_chgb
; /* Enable/disable remote wakeup */
80 * controller driver data structures
83 /* 16 endpoints (not to be confused with 32 hardware endpoints) */
84 #define NUM_ENDPOINTS 16
87 * IRQ indices make reading the code a little easier
91 #define IRQ_USB_DEVDMA 2
94 #define EP_OUT 0 /* RX (from host) */
95 #define EP_IN 1 /* TX (to host) */
97 /* Returns the interrupt mask for the selected hardware endpoint */
98 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
100 #define EP_INT_TYPE 0
101 #define EP_ISO_TYPE 1
102 #define EP_BLK_TYPE 2
103 #define EP_CTL_TYPE 3
106 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
107 #define DATA_IN 1 /* Expect dev->host transfer */
108 #define DATA_OUT 2 /* Expect host->dev transfer */
110 /* DD (DMA Descriptor) structure, requires word alignment, this is already
111 * defined in the LPC32XX USB device header file, but this version is slightly
112 * modified to tag some work data with each DMA descriptor. */
113 struct lpc32xx_usbd_dd_gad
{
118 u32 dd_iso_ps_mem_addr
;
120 u32 iso_status
[6]; /* 5 spare */
125 * Logical endpoint structure
129 struct list_head queue
;
130 struct lpc32xx_udc
*udc
;
132 u32 hwep_num_base
; /* Physical hardware EP */
133 u32 hwep_num
; /* Maps to hardware endpoint */
145 const struct usb_endpoint_descriptor
*desc
;
149 * Common UDC structure
152 struct usb_gadget gadget
;
153 struct usb_gadget_driver
*driver
;
154 struct platform_device
*pdev
;
158 struct i2c_client
*isp1301_i2c_client
;
160 /* Board and device specific */
161 struct lpc32xx_usbd_cfg
*board
;
164 void __iomem
*udp_baseaddr
;
166 struct clk
*usb_pll_clk
;
167 struct clk
*usb_slv_clk
;
172 struct dma_pool
*dd_cache
;
174 /* Common EP and control data */
176 u32 enabled_hwepints
;
180 /* VBUS detection, pullup, and power flags */
186 /* Work queues related to I2C support */
187 struct work_struct pullup_job
;
188 struct work_struct vbus_job
;
189 struct work_struct power_job
;
191 /* USB device peripheral - various */
192 struct lpc32xx_ep ep
[NUM_ENDPOINTS
];
198 atomic_t enabled_ep_cnt
;
199 wait_queue_head_t ep_disable_wait_queue
;
205 struct lpc32xx_request
{
206 struct usb_request req
;
207 struct list_head queue
;
208 struct lpc32xx_usbd_dd_gad
*dd_desc_ptr
;
213 static inline struct lpc32xx_udc
*to_udc(struct usb_gadget
*g
)
215 return container_of(g
, struct lpc32xx_udc
, gadget
);
218 #define ep_dbg(epp, fmt, arg...) \
219 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
220 #define ep_err(epp, fmt, arg...) \
221 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
222 #define ep_info(epp, fmt, arg...) \
223 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
224 #define ep_warn(epp, fmt, arg...) \
225 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
227 #define UDCA_BUFF_SIZE (128)
229 /* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
230 * be replaced with an inremap()ed pointer, see USB_OTG_CLK_CTRL()
232 #define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
233 #define USB_CLOCK_MASK (AHB_M_CLOCK_ON | OTG_CLOCK_ON | \
234 DEV_CLOCK_ON | I2C_CLOCK_ON)
236 /* USB_CTRL bit defines */
237 #define USB_SLAVE_HCLK_EN (1 << 24)
238 #define USB_HOST_NEED_CLK_EN (1 << 21)
239 #define USB_DEV_NEED_CLK_EN (1 << 22)
241 #define USB_OTG_CLK_CTRL(udc) ((udc)->udp_baseaddr + 0xFF4)
242 #define USB_OTG_CLK_STAT(udc) ((udc)->udp_baseaddr + 0xFF8)
244 /* USB_OTG_CLK_CTRL bit defines */
245 #define AHB_M_CLOCK_ON (1 << 4)
246 #define OTG_CLOCK_ON (1 << 3)
247 #define I2C_CLOCK_ON (1 << 2)
248 #define DEV_CLOCK_ON (1 << 1)
249 #define HOST_CLOCK_ON (1 << 0)
251 #define USB_OTG_STAT_CONTROL(udc) (udc->udp_baseaddr + 0x110)
253 /* USB_OTG_STAT_CONTROL bit defines */
254 #define TRANSPARENT_I2C_EN (1 << 7)
255 #define HOST_EN (1 << 0)
257 /**********************************************************************
258 * USB device controller register offsets
259 **********************************************************************/
261 #define USBD_DEVINTST(x) ((x) + 0x200)
262 #define USBD_DEVINTEN(x) ((x) + 0x204)
263 #define USBD_DEVINTCLR(x) ((x) + 0x208)
264 #define USBD_DEVINTSET(x) ((x) + 0x20C)
265 #define USBD_CMDCODE(x) ((x) + 0x210)
266 #define USBD_CMDDATA(x) ((x) + 0x214)
267 #define USBD_RXDATA(x) ((x) + 0x218)
268 #define USBD_TXDATA(x) ((x) + 0x21C)
269 #define USBD_RXPLEN(x) ((x) + 0x220)
270 #define USBD_TXPLEN(x) ((x) + 0x224)
271 #define USBD_CTRL(x) ((x) + 0x228)
272 #define USBD_DEVINTPRI(x) ((x) + 0x22C)
273 #define USBD_EPINTST(x) ((x) + 0x230)
274 #define USBD_EPINTEN(x) ((x) + 0x234)
275 #define USBD_EPINTCLR(x) ((x) + 0x238)
276 #define USBD_EPINTSET(x) ((x) + 0x23C)
277 #define USBD_EPINTPRI(x) ((x) + 0x240)
278 #define USBD_REEP(x) ((x) + 0x244)
279 #define USBD_EPIND(x) ((x) + 0x248)
280 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
281 /* DMA support registers only below */
282 /* Set, clear, or get enabled state of the DMA request status. If
283 * enabled, an IN or OUT token will start a DMA transfer for the EP */
284 #define USBD_DMARST(x) ((x) + 0x250)
285 #define USBD_DMARCLR(x) ((x) + 0x254)
286 #define USBD_DMARSET(x) ((x) + 0x258)
287 /* DMA UDCA head pointer */
288 #define USBD_UDCAH(x) ((x) + 0x280)
289 /* EP DMA status, enable, and disable. This is used to specifically
290 * enabled or disable DMA for a specific EP */
291 #define USBD_EPDMAST(x) ((x) + 0x284)
292 #define USBD_EPDMAEN(x) ((x) + 0x288)
293 #define USBD_EPDMADIS(x) ((x) + 0x28C)
294 /* DMA master interrupts enable and pending interrupts */
295 #define USBD_DMAINTST(x) ((x) + 0x290)
296 #define USBD_DMAINTEN(x) ((x) + 0x294)
297 /* DMA end of transfer interrupt enable, disable, status */
298 #define USBD_EOTINTST(x) ((x) + 0x2A0)
299 #define USBD_EOTINTCLR(x) ((x) + 0x2A4)
300 #define USBD_EOTINTSET(x) ((x) + 0x2A8)
301 /* New DD request interrupt enable, disable, status */
302 #define USBD_NDDRTINTST(x) ((x) + 0x2AC)
303 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
304 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
305 /* DMA error interrupt enable, disable, status */
306 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
307 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
308 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
310 /**********************************************************************
311 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
312 * USBD_DEVINTPRI register definitions
313 **********************************************************************/
314 #define USBD_ERR_INT (1 << 9)
315 #define USBD_EP_RLZED (1 << 8)
316 #define USBD_TXENDPKT (1 << 7)
317 #define USBD_RXENDPKT (1 << 6)
318 #define USBD_CDFULL (1 << 5)
319 #define USBD_CCEMPTY (1 << 4)
320 #define USBD_DEV_STAT (1 << 3)
321 #define USBD_EP_SLOW (1 << 2)
322 #define USBD_EP_FAST (1 << 1)
323 #define USBD_FRAME (1 << 0)
325 /**********************************************************************
326 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
327 * USBD_EPINTPRI register definitions
328 **********************************************************************/
329 /* End point selection macro (RX) */
330 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
332 /* End point selection macro (TX) */
333 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
335 /**********************************************************************
336 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
337 * USBD_EPDMAEN/USBD_EPDMADIS/
338 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
339 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
340 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
341 * register definitions
342 **********************************************************************/
343 /* Endpoint selection macro */
344 #define USBD_EP_SEL(e) (1 << (e))
346 /**********************************************************************
347 * SBD_DMAINTST/USBD_DMAINTEN
348 **********************************************************************/
349 #define USBD_SYS_ERR_INT (1 << 2)
350 #define USBD_NEW_DD_INT (1 << 1)
351 #define USBD_EOT_INT (1 << 0)
353 /**********************************************************************
354 * USBD_RXPLEN register definitions
355 **********************************************************************/
356 #define USBD_PKT_RDY (1 << 11)
357 #define USBD_DV (1 << 10)
358 #define USBD_PK_LEN_MASK 0x3FF
360 /**********************************************************************
361 * USBD_CTRL register definitions
362 **********************************************************************/
363 #define USBD_LOG_ENDPOINT(e) ((e) << 2)
364 #define USBD_WR_EN (1 << 1)
365 #define USBD_RD_EN (1 << 0)
367 /**********************************************************************
368 * USBD_CMDCODE register definitions
369 **********************************************************************/
370 #define USBD_CMD_CODE(c) ((c) << 16)
371 #define USBD_CMD_PHASE(p) ((p) << 8)
373 /**********************************************************************
374 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
375 **********************************************************************/
376 #define USBD_DMAEP(e) (1 << (e))
378 /* DD (DMA Descriptor) structure, requires word alignment */
379 struct lpc32xx_usbd_dd
{
384 u32 dd_iso_ps_mem_addr
;
387 /* dd_setup bit defines */
388 #define DD_SETUP_ATLE_DMA_MODE 0x01
389 #define DD_SETUP_NEXT_DD_VALID 0x04
390 #define DD_SETUP_ISO_EP 0x10
391 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
392 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
394 /* dd_status bit defines */
395 #define DD_STATUS_DD_RETIRED 0x01
396 #define DD_STATUS_STS_MASK 0x1E
397 #define DD_STATUS_STS_NS 0x00 /* Not serviced */
398 #define DD_STATUS_STS_BS 0x02 /* Being serviced */
399 #define DD_STATUS_STS_NC 0x04 /* Normal completion */
400 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
401 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */
402 #define DD_STATUS_STS_SE 0x12 /* System error */
403 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
404 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
405 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
406 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
407 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
411 * Protocol engine bits below
414 /* Device Interrupt Bit Definitions */
415 #define FRAME_INT 0x00000001
416 #define EP_FAST_INT 0x00000002
417 #define EP_SLOW_INT 0x00000004
418 #define DEV_STAT_INT 0x00000008
419 #define CCEMTY_INT 0x00000010
420 #define CDFULL_INT 0x00000020
421 #define RxENDPKT_INT 0x00000040
422 #define TxENDPKT_INT 0x00000080
423 #define EP_RLZED_INT 0x00000100
424 #define ERR_INT 0x00000200
426 /* Rx & Tx Packet Length Definitions */
427 #define PKT_LNGTH_MASK 0x000003FF
428 #define PKT_DV 0x00000400
429 #define PKT_RDY 0x00000800
431 /* USB Control Definitions */
432 #define CTRL_RD_EN 0x00000001
433 #define CTRL_WR_EN 0x00000002
436 #define CMD_SET_ADDR 0x00D00500
437 #define CMD_CFG_DEV 0x00D80500
438 #define CMD_SET_MODE 0x00F30500
439 #define CMD_RD_FRAME 0x00F50500
440 #define DAT_RD_FRAME 0x00F50200
441 #define CMD_RD_TEST 0x00FD0500
442 #define DAT_RD_TEST 0x00FD0200
443 #define CMD_SET_DEV_STAT 0x00FE0500
444 #define CMD_GET_DEV_STAT 0x00FE0500
445 #define DAT_GET_DEV_STAT 0x00FE0200
446 #define CMD_GET_ERR_CODE 0x00FF0500
447 #define DAT_GET_ERR_CODE 0x00FF0200
448 #define CMD_RD_ERR_STAT 0x00FB0500
449 #define DAT_RD_ERR_STAT 0x00FB0200
450 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
451 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
452 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
453 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
454 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
455 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
456 #define CMD_CLR_BUF 0x00F20500
457 #define DAT_CLR_BUF 0x00F20200
458 #define CMD_VALID_BUF 0x00FA0500
460 /* Device Address Register Definitions */
461 #define DEV_ADDR_MASK 0x7F
464 /* Device Configure Register Definitions */
465 #define CONF_DVICE 0x01
467 /* Device Mode Register Definitions */
476 /* Device Status Register Definitions */
478 #define DEV_CON_CH 0x02
480 #define DEV_SUS_CH 0x08
483 /* Error Code Register Definitions */
484 #define ERR_EC_MASK 0x0F
487 /* Error Status Register Definitions */
489 #define ERR_UEPKT 0x02
490 #define ERR_DCRC 0x04
491 #define ERR_TIMOUT 0x08
493 #define ERR_B_OVRN 0x20
494 #define ERR_BTSTF 0x40
497 /* Endpoint Select Register Definitions */
498 #define EP_SEL_F 0x01
499 #define EP_SEL_ST 0x02
500 #define EP_SEL_STP 0x04
501 #define EP_SEL_PO 0x08
502 #define EP_SEL_EPN 0x10
503 #define EP_SEL_B_1_FULL 0x20
504 #define EP_SEL_B_2_FULL 0x40
506 /* Endpoint Status Register Definitions */
507 #define EP_STAT_ST 0x01
508 #define EP_STAT_DA 0x20
509 #define EP_STAT_RF_MO 0x40
510 #define EP_STAT_CND_ST 0x80
512 /* Clear Buffer Register Definitions */
513 #define CLR_BUF_PO 0x01
515 /* DMA Interrupt Bit Definitions */
517 #define NDD_REQ_INT 0x02
518 #define SYS_ERR_INT 0x04
520 #define DRIVER_VERSION "1.03"
521 static const char driver_name
[] = "lpc32xx_udc";
525 * proc interface support
528 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
529 static char *epnames
[] = {"INT", "ISO", "BULK", "CTRL"};
530 static const char debug_filename
[] = "driver/udc";
532 static void proc_ep_show(struct seq_file
*s
, struct lpc32xx_ep
*ep
)
534 struct lpc32xx_request
*req
;
537 seq_printf(s
, "%12s, maxpacket %4d %3s",
538 ep
->ep
.name
, ep
->ep
.maxpacket
,
539 ep
->is_in
? "in" : "out");
540 seq_printf(s
, " type %4s", epnames
[ep
->eptype
]);
541 seq_printf(s
, " ints: %12d", ep
->totalints
);
543 if (list_empty(&ep
->queue
))
544 seq_printf(s
, "\t(queue empty)\n");
546 list_for_each_entry(req
, &ep
->queue
, queue
) {
547 u32 length
= req
->req
.actual
;
549 seq_printf(s
, "\treq %p len %d/%d buf %p\n",
551 req
->req
.length
, req
->req
.buf
);
556 static int proc_udc_show(struct seq_file
*s
, void *unused
)
558 struct lpc32xx_udc
*udc
= s
->private;
559 struct lpc32xx_ep
*ep
;
562 seq_printf(s
, "%s: version %s\n", driver_name
, DRIVER_VERSION
);
564 spin_lock_irqsave(&udc
->lock
, flags
);
566 seq_printf(s
, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
567 udc
->vbus
? "present" : "off",
568 udc
->enabled
? (udc
->vbus
? "active" : "enabled") :
570 udc
->selfpowered
? "self" : "VBUS",
571 udc
->suspended
? ", suspended" : "",
572 udc
->driver
? udc
->driver
->driver
.name
: "(none)");
574 if (udc
->enabled
&& udc
->vbus
) {
575 proc_ep_show(s
, &udc
->ep
[0]);
576 list_for_each_entry(ep
, &udc
->gadget
.ep_list
, ep
.ep_list
) {
582 spin_unlock_irqrestore(&udc
->lock
, flags
);
587 static int proc_udc_open(struct inode
*inode
, struct file
*file
)
589 return single_open(file
, proc_udc_show
, PDE(inode
)->data
);
592 static const struct file_operations proc_ops
= {
593 .owner
= THIS_MODULE
,
594 .open
= proc_udc_open
,
597 .release
= single_release
,
600 static void create_debug_file(struct lpc32xx_udc
*udc
)
602 udc
->pde
= debugfs_create_file(debug_filename
, 0, NULL
, udc
, &proc_ops
);
605 static void remove_debug_file(struct lpc32xx_udc
*udc
)
608 debugfs_remove(udc
->pde
);
612 static inline void create_debug_file(struct lpc32xx_udc
*udc
) {}
613 static inline void remove_debug_file(struct lpc32xx_udc
*udc
) {}
616 /* Primary initialization sequence for the ISP1301 transceiver */
617 static void isp1301_udc_configure(struct lpc32xx_udc
*udc
)
619 /* LPC32XX only supports DAT_SE0 USB mode */
620 /* This sequence is important */
622 /* Disable transparent UART mode first */
623 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
624 (ISP1301_I2C_MODE_CONTROL_1
| ISP1301_I2C_REG_CLEAR_ADDR
),
627 /* Set full speed and SE0 mode */
628 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
629 (ISP1301_I2C_MODE_CONTROL_1
| ISP1301_I2C_REG_CLEAR_ADDR
), ~0);
630 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
631 ISP1301_I2C_MODE_CONTROL_1
, (MC1_SPEED_REG
| MC1_DAT_SE0
));
634 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
636 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
637 (ISP1301_I2C_MODE_CONTROL_2
| ISP1301_I2C_REG_CLEAR_ADDR
), ~0);
638 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
639 ISP1301_I2C_MODE_CONTROL_2
, (MC2_BI_DI
| MC2_SPD_SUSP_CTRL
));
641 /* Driver VBUS_DRV high or low depending on board setup */
642 if (udc
->board
->vbus_drv_pol
!= 0)
643 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
644 ISP1301_I2C_OTG_CONTROL_1
, OTG1_VBUS_DRV
);
646 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
647 ISP1301_I2C_OTG_CONTROL_1
| ISP1301_I2C_REG_CLEAR_ADDR
,
650 /* Bi-directional mode with suspend control
651 * Enable both pulldowns for now - the pullup will be enable when VBUS
653 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
654 (ISP1301_I2C_OTG_CONTROL_1
| ISP1301_I2C_REG_CLEAR_ADDR
), ~0);
655 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
656 ISP1301_I2C_OTG_CONTROL_1
,
657 (0 | OTG1_DM_PULLDOWN
| OTG1_DP_PULLDOWN
));
659 /* Discharge VBUS (just in case) */
660 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
661 ISP1301_I2C_OTG_CONTROL_1
, OTG1_VBUS_DISCHRG
);
663 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
664 (ISP1301_I2C_OTG_CONTROL_1
| ISP1301_I2C_REG_CLEAR_ADDR
),
667 /* Clear and enable VBUS high edge interrupt */
668 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
669 ISP1301_I2C_INTERRUPT_LATCH
| ISP1301_I2C_REG_CLEAR_ADDR
, ~0);
670 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
671 ISP1301_I2C_INTERRUPT_FALLING
| ISP1301_I2C_REG_CLEAR_ADDR
, ~0);
672 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
673 ISP1301_I2C_INTERRUPT_FALLING
, INT_VBUS_VLD
);
674 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
675 ISP1301_I2C_INTERRUPT_RISING
| ISP1301_I2C_REG_CLEAR_ADDR
, ~0);
676 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
677 ISP1301_I2C_INTERRUPT_RISING
, INT_VBUS_VLD
);
679 /* Enable usb_need_clk clock after transceiver is initialized */
680 writel((readl(USB_CTRL
) | (1 << 22)), USB_CTRL
);
682 dev_info(udc
->dev
, "ISP1301 Vendor ID : 0x%04x\n",
683 i2c_smbus_read_word_data(udc
->isp1301_i2c_client
, 0x00));
684 dev_info(udc
->dev
, "ISP1301 Product ID : 0x%04x\n",
685 i2c_smbus_read_word_data(udc
->isp1301_i2c_client
, 0x02));
686 dev_info(udc
->dev
, "ISP1301 Version ID : 0x%04x\n",
687 i2c_smbus_read_word_data(udc
->isp1301_i2c_client
, 0x14));
690 /* Enables or disables the USB device pullup via the ISP1301 transceiver */
691 static void isp1301_pullup_set(struct lpc32xx_udc
*udc
)
694 /* Enable pullup for bus signalling */
695 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
696 ISP1301_I2C_OTG_CONTROL_1
, OTG1_DP_PULLUP
);
698 /* Enable pullup for bus signalling */
699 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
700 ISP1301_I2C_OTG_CONTROL_1
| ISP1301_I2C_REG_CLEAR_ADDR
,
704 static void pullup_work(struct work_struct
*work
)
706 struct lpc32xx_udc
*udc
=
707 container_of(work
, struct lpc32xx_udc
, pullup_job
);
709 isp1301_pullup_set(udc
);
712 static void isp1301_pullup_enable(struct lpc32xx_udc
*udc
, int en_pullup
,
715 if (en_pullup
== udc
->pullup
)
718 udc
->pullup
= en_pullup
;
720 isp1301_pullup_set(udc
);
722 /* defer slow i2c pull up setting */
723 schedule_work(&udc
->pullup_job
);
727 /* Powers up or down the ISP1301 transceiver */
728 static void isp1301_set_powerstate(struct lpc32xx_udc
*udc
, int enable
)
731 /* Power up ISP1301 - this ISP1301 will automatically wakeup
732 when VBUS is detected */
733 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
734 ISP1301_I2C_MODE_CONTROL_2
| ISP1301_I2C_REG_CLEAR_ADDR
,
737 /* Power down ISP1301 */
738 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
739 ISP1301_I2C_MODE_CONTROL_2
, MC2_GLOBAL_PWR_DN
);
742 static void power_work(struct work_struct
*work
)
744 struct lpc32xx_udc
*udc
=
745 container_of(work
, struct lpc32xx_udc
, power_job
);
747 isp1301_set_powerstate(udc
, udc
->poweron
);
753 * USB protocol engine command/data read/write helper functions
756 /* Issues a single command to the USB device state machine */
757 static void udc_protocol_cmd_w(struct lpc32xx_udc
*udc
, u32 cmd
)
762 /* EP may lock on CLRI if this read isn't done */
763 u32 tmp
= readl(USBD_DEVINTST(udc
->udp_baseaddr
));
767 writel(USBD_CCEMPTY
, USBD_DEVINTCLR(udc
->udp_baseaddr
));
769 /* Write command code */
770 writel(cmd
, USBD_CMDCODE(udc
->udp_baseaddr
));
772 while (((readl(USBD_DEVINTST(udc
->udp_baseaddr
)) &
773 USBD_CCEMPTY
) == 0) && (to
> 0)) {
784 /* Issues 2 commands (or command and data) to the USB device state machine */
785 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc
*udc
, u32 cmd
,
788 udc_protocol_cmd_w(udc
, cmd
);
789 udc_protocol_cmd_w(udc
, data
);
792 /* Issues a single command to the USB device state machine and reads
794 static u32
udc_protocol_cmd_r(struct lpc32xx_udc
*udc
, u32 cmd
)
799 /* Write a command and read data from the protocol engine */
800 writel((USBD_CDFULL
| USBD_CCEMPTY
),
801 USBD_DEVINTCLR(udc
->udp_baseaddr
));
803 /* Write command code */
804 udc_protocol_cmd_w(udc
, cmd
);
806 tmp
= readl(USBD_DEVINTST(udc
->udp_baseaddr
));
807 while ((!(readl(USBD_DEVINTST(udc
->udp_baseaddr
)) & USBD_CDFULL
))
812 "Protocol engine didn't receive response (CDFULL)\n");
814 return readl(USBD_CMDDATA(udc
->udp_baseaddr
));
819 * USB device interrupt mask support functions
822 /* Enable one or more USB device interrupts */
823 static inline void uda_enable_devint(struct lpc32xx_udc
*udc
, u32 devmask
)
825 udc
->enabled_devints
|= devmask
;
826 writel(udc
->enabled_devints
, USBD_DEVINTEN(udc
->udp_baseaddr
));
829 /* Disable one or more USB device interrupts */
830 static inline void uda_disable_devint(struct lpc32xx_udc
*udc
, u32 mask
)
832 udc
->enabled_devints
&= ~mask
;
833 writel(udc
->enabled_devints
, USBD_DEVINTEN(udc
->udp_baseaddr
));
836 /* Clear one or more USB device interrupts */
837 static inline void uda_clear_devint(struct lpc32xx_udc
*udc
, u32 mask
)
839 writel(mask
, USBD_DEVINTCLR(udc
->udp_baseaddr
));
844 * Endpoint interrupt disable/enable functions
847 /* Enable one or more USB endpoint interrupts */
848 static void uda_enable_hwepint(struct lpc32xx_udc
*udc
, u32 hwep
)
850 udc
->enabled_hwepints
|= (1 << hwep
);
851 writel(udc
->enabled_hwepints
, USBD_EPINTEN(udc
->udp_baseaddr
));
854 /* Disable one or more USB endpoint interrupts */
855 static void uda_disable_hwepint(struct lpc32xx_udc
*udc
, u32 hwep
)
857 udc
->enabled_hwepints
&= ~(1 << hwep
);
858 writel(udc
->enabled_hwepints
, USBD_EPINTEN(udc
->udp_baseaddr
));
861 /* Clear one or more USB endpoint interrupts */
862 static inline void uda_clear_hwepint(struct lpc32xx_udc
*udc
, u32 hwep
)
864 writel((1 << hwep
), USBD_EPINTCLR(udc
->udp_baseaddr
));
867 /* Enable DMA for the HW channel */
868 static inline void udc_ep_dma_enable(struct lpc32xx_udc
*udc
, u32 hwep
)
870 writel((1 << hwep
), USBD_EPDMAEN(udc
->udp_baseaddr
));
873 /* Disable DMA for the HW channel */
874 static inline void udc_ep_dma_disable(struct lpc32xx_udc
*udc
, u32 hwep
)
876 writel((1 << hwep
), USBD_EPDMADIS(udc
->udp_baseaddr
));
881 * Endpoint realize/unrealize functions
884 /* Before an endpoint can be used, it needs to be realized
885 * in the USB protocol engine - this realizes the endpoint.
886 * The interrupt (FIFO or DMA) is not enabled with this function */
887 static void udc_realize_hwep(struct lpc32xx_udc
*udc
, u32 hwep
,
892 writel(USBD_EP_RLZED
, USBD_DEVINTCLR(udc
->udp_baseaddr
));
893 writel(hwep
, USBD_EPIND(udc
->udp_baseaddr
));
894 udc
->realized_eps
|= (1 << hwep
);
895 writel(udc
->realized_eps
, USBD_REEP(udc
->udp_baseaddr
));
896 writel(maxpacket
, USBD_EPMAXPSIZE(udc
->udp_baseaddr
));
898 /* Wait until endpoint is realized in hardware */
899 while ((!(readl(USBD_DEVINTST(udc
->udp_baseaddr
)) &
900 USBD_EP_RLZED
)) && (to
> 0))
903 dev_dbg(udc
->dev
, "EP not correctly realized in hardware\n");
905 writel(USBD_EP_RLZED
, USBD_DEVINTCLR(udc
->udp_baseaddr
));
908 /* Unrealize an EP */
909 static void udc_unrealize_hwep(struct lpc32xx_udc
*udc
, u32 hwep
)
911 udc
->realized_eps
&= ~(1 << hwep
);
912 writel(udc
->realized_eps
, USBD_REEP(udc
->udp_baseaddr
));
917 * Endpoint support functions
920 /* Select and clear endpoint interrupt */
921 static u32
udc_selep_clrint(struct lpc32xx_udc
*udc
, u32 hwep
)
923 udc_protocol_cmd_w(udc
, CMD_SEL_EP_CLRI(hwep
));
924 return udc_protocol_cmd_r(udc
, DAT_SEL_EP_CLRI(hwep
));
927 /* Disables the endpoint in the USB protocol engine */
928 static void udc_disable_hwep(struct lpc32xx_udc
*udc
, u32 hwep
)
930 udc_protocol_cmd_data_w(udc
, CMD_SET_EP_STAT(hwep
),
931 DAT_WR_BYTE(EP_STAT_DA
));
934 /* Stalls the endpoint - endpoint will return STALL */
935 static void udc_stall_hwep(struct lpc32xx_udc
*udc
, u32 hwep
)
937 udc_protocol_cmd_data_w(udc
, CMD_SET_EP_STAT(hwep
),
938 DAT_WR_BYTE(EP_STAT_ST
));
941 /* Clear stall or reset endpoint */
942 static void udc_clrstall_hwep(struct lpc32xx_udc
*udc
, u32 hwep
)
944 udc_protocol_cmd_data_w(udc
, CMD_SET_EP_STAT(hwep
),
948 /* Select an endpoint for endpoint status, clear, validate */
949 static void udc_select_hwep(struct lpc32xx_udc
*udc
, u32 hwep
)
951 udc_protocol_cmd_w(udc
, CMD_SEL_EP(hwep
));
956 * Endpoint buffer management functions
959 /* Clear the current endpoint's buffer */
960 static void udc_clr_buffer_hwep(struct lpc32xx_udc
*udc
, u32 hwep
)
962 udc_select_hwep(udc
, hwep
);
963 udc_protocol_cmd_w(udc
, CMD_CLR_BUF
);
966 /* Validate the current endpoint's buffer */
967 static void udc_val_buffer_hwep(struct lpc32xx_udc
*udc
, u32 hwep
)
969 udc_select_hwep(udc
, hwep
);
970 udc_protocol_cmd_w(udc
, CMD_VALID_BUF
);
973 static inline u32
udc_clearep_getsts(struct lpc32xx_udc
*udc
, u32 hwep
)
975 /* Clear EP interrupt */
976 uda_clear_hwepint(udc
, hwep
);
977 return udc_selep_clrint(udc
, hwep
);
985 /* Allocate a DMA Descriptor */
986 static struct lpc32xx_usbd_dd_gad
*udc_dd_alloc(struct lpc32xx_udc
*udc
)
989 struct lpc32xx_usbd_dd_gad
*dd
;
991 dd
= (struct lpc32xx_usbd_dd_gad
*) dma_pool_alloc(
992 udc
->dd_cache
, (GFP_KERNEL
| GFP_DMA
), &dma
);
999 /* Free a DMA Descriptor */
1000 static void udc_dd_free(struct lpc32xx_udc
*udc
, struct lpc32xx_usbd_dd_gad
*dd
)
1002 dma_pool_free(udc
->dd_cache
, dd
, dd
->this_dma
);
1007 * USB setup and shutdown functions
1010 /* Enables or disables most of the USB system clocks when low power mode is
1011 * needed. Clocks are typically started on a connection event, and disabled
1012 * when a cable is disconnected */
1013 #define OTGOFF_CLK_MASK (AHB_M_CLOCK_ON | I2C_CLOCK_ON)
1014 static void udc_clk_set(struct lpc32xx_udc
*udc
, int enable
)
1025 clk_enable(udc
->usb_pll_clk
);
1027 /* Enable the USB device clock */
1028 writel(readl(USB_CTRL
) | USB_DEV_NEED_CLK_EN
,
1031 /* Set to enable all needed USB OTG clocks */
1032 writel(USB_CLOCK_MASK
, USB_OTG_CLK_CTRL(udc
));
1034 while (((readl(USB_OTG_CLK_STAT(udc
)) & USB_CLOCK_MASK
) !=
1035 USB_CLOCK_MASK
) && (to
> 0))
1038 dev_dbg(udc
->dev
, "Cannot enable USB OTG clocking\n");
1045 /* Never disable the USB_HCLK during normal operation */
1047 /* 48MHz PLL dpwn */
1048 clk_disable(udc
->usb_pll_clk
);
1050 /* Enable the USB device clock */
1051 writel(readl(USB_CTRL
) & ~USB_DEV_NEED_CLK_EN
,
1054 /* Set to enable all needed USB OTG clocks */
1055 writel(OTGOFF_CLK_MASK
, USB_OTG_CLK_CTRL(udc
));
1057 while (((readl(USB_OTG_CLK_STAT(udc
)) &
1059 OTGOFF_CLK_MASK
) && (to
> 0))
1062 dev_dbg(udc
->dev
, "Cannot disable USB OTG clocking\n");
1066 /* Set/reset USB device address */
1067 static void udc_set_address(struct lpc32xx_udc
*udc
, u32 addr
)
1069 /* Address will be latched at the end of the status phase, or
1070 latched immediately if function is called twice */
1071 udc_protocol_cmd_data_w(udc
, CMD_SET_ADDR
,
1072 DAT_WR_BYTE(DEV_EN
| addr
));
1075 /* Setup up a IN request for DMA transfer - this consists of determining the
1076 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1077 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1078 static int udc_ep_in_req_dma(struct lpc32xx_udc
*udc
, struct lpc32xx_ep
*ep
)
1080 struct lpc32xx_request
*req
;
1081 u32 hwep
= ep
->hwep_num
;
1083 ep
->req_pending
= 1;
1085 /* There will always be a request waiting here */
1086 req
= list_entry(ep
->queue
.next
, struct lpc32xx_request
, queue
);
1088 /* Place the DD Descriptor into the UDCA */
1089 udc
->udca_v_base
[hwep
] = req
->dd_desc_ptr
->this_dma
;
1091 /* Enable DMA and interrupt for the HW EP */
1092 udc_ep_dma_enable(udc
, hwep
);
1094 /* Clear ZLP if last packet is not of MAXP size */
1095 if (req
->req
.length
% ep
->ep
.maxpacket
)
1101 /* Setup up a OUT request for DMA transfer - this consists of determining the
1102 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1103 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1104 static int udc_ep_out_req_dma(struct lpc32xx_udc
*udc
, struct lpc32xx_ep
*ep
)
1106 struct lpc32xx_request
*req
;
1107 u32 hwep
= ep
->hwep_num
;
1109 ep
->req_pending
= 1;
1111 /* There will always be a request waiting here */
1112 req
= list_entry(ep
->queue
.next
, struct lpc32xx_request
, queue
);
1114 /* Place the DD Descriptor into the UDCA */
1115 udc
->udca_v_base
[hwep
] = req
->dd_desc_ptr
->this_dma
;
1117 /* Enable DMA and interrupt for the HW EP */
1118 udc_ep_dma_enable(udc
, hwep
);
1122 static void udc_disable(struct lpc32xx_udc
*udc
)
1126 /* Disable device */
1127 udc_protocol_cmd_data_w(udc
, CMD_CFG_DEV
, DAT_WR_BYTE(0));
1128 udc_protocol_cmd_data_w(udc
, CMD_SET_DEV_STAT
, DAT_WR_BYTE(0));
1130 /* Disable all device interrupts (including EP0) */
1131 uda_disable_devint(udc
, 0x3FF);
1133 /* Disable and reset all endpoint interrupts */
1134 for (i
= 0; i
< 32; i
++) {
1135 uda_disable_hwepint(udc
, i
);
1136 uda_clear_hwepint(udc
, i
);
1137 udc_disable_hwep(udc
, i
);
1138 udc_unrealize_hwep(udc
, i
);
1139 udc
->udca_v_base
[i
] = 0;
1141 /* Disable and clear all interrupts and DMA */
1142 udc_ep_dma_disable(udc
, i
);
1143 writel((1 << i
), USBD_EOTINTCLR(udc
->udp_baseaddr
));
1144 writel((1 << i
), USBD_NDDRTINTCLR(udc
->udp_baseaddr
));
1145 writel((1 << i
), USBD_SYSERRTINTCLR(udc
->udp_baseaddr
));
1146 writel((1 << i
), USBD_DMARCLR(udc
->udp_baseaddr
));
1149 /* Disable DMA interrupts */
1150 writel(0, USBD_DMAINTEN(udc
->udp_baseaddr
));
1152 writel(0, USBD_UDCAH(udc
->udp_baseaddr
));
1155 static void udc_enable(struct lpc32xx_udc
*udc
)
1158 struct lpc32xx_ep
*ep
= &udc
->ep
[0];
1160 /* Start with known state */
1164 udc_protocol_cmd_data_w(udc
, CMD_SET_DEV_STAT
, DAT_WR_BYTE(DEV_CON
));
1166 /* EP interrupts on high priority, FRAME interrupt on low priority */
1167 writel(USBD_EP_FAST
, USBD_DEVINTPRI(udc
->udp_baseaddr
));
1168 writel(0xFFFF, USBD_EPINTPRI(udc
->udp_baseaddr
));
1170 /* Clear any pending device interrupts */
1171 writel(0x3FF, USBD_DEVINTCLR(udc
->udp_baseaddr
));
1173 /* Setup UDCA - not yet used (DMA) */
1174 writel(udc
->udca_p_base
, USBD_UDCAH(udc
->udp_baseaddr
));
1176 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1177 for (i
= 0; i
<= 1; i
++) {
1178 udc_realize_hwep(udc
, i
, ep
->ep
.maxpacket
);
1179 uda_enable_hwepint(udc
, i
);
1180 udc_select_hwep(udc
, i
);
1181 udc_clrstall_hwep(udc
, i
);
1182 udc_clr_buffer_hwep(udc
, i
);
1185 /* Device interrupt setup */
1186 uda_clear_devint(udc
, (USBD_ERR_INT
| USBD_DEV_STAT
| USBD_EP_SLOW
|
1188 uda_enable_devint(udc
, (USBD_ERR_INT
| USBD_DEV_STAT
| USBD_EP_SLOW
|
1191 /* Set device address to 0 - called twice to force a latch in the USB
1192 engine without the need of a setup packet status closure */
1193 udc_set_address(udc
, 0);
1194 udc_set_address(udc
, 0);
1196 /* Enable master DMA interrupts */
1197 writel((USBD_SYS_ERR_INT
| USBD_EOT_INT
),
1198 USBD_DMAINTEN(udc
->udp_baseaddr
));
1200 udc
->dev_status
= 0;
1205 * USB device board specific events handled via callbacks
1208 /* Connection change event - notify board function of change */
1209 static void uda_power_event(struct lpc32xx_udc
*udc
, u32 conn
)
1211 /* Just notify of a connection change event (optional) */
1212 if (udc
->board
->conn_chgb
!= NULL
)
1213 udc
->board
->conn_chgb(conn
);
1216 /* Suspend/resume event - notify board function of change */
1217 static void uda_resm_susp_event(struct lpc32xx_udc
*udc
, u32 conn
)
1219 /* Just notify of a Suspend/resume change event (optional) */
1220 if (udc
->board
->susp_chgb
!= NULL
)
1221 udc
->board
->susp_chgb(conn
);
1229 /* Remote wakeup enable/disable - notify board function of change */
1230 static void uda_remwkp_cgh(struct lpc32xx_udc
*udc
)
1232 if (udc
->board
->rmwk_chgb
!= NULL
)
1233 udc
->board
->rmwk_chgb(udc
->dev_status
&
1234 (1 << USB_DEVICE_REMOTE_WAKEUP
));
1237 /* Reads data from FIFO, adjusts for alignment and data size */
1238 static void udc_pop_fifo(struct lpc32xx_udc
*udc
, u8
*data
, u32 bytes
)
1242 u32
*p32
, tmp
, cbytes
;
1244 /* Use optimal data transfer method based on source address and size */
1245 switch (((u32
) data
) & 0x3) {
1246 case 0: /* 32-bit aligned */
1248 cbytes
= (bytes
& ~0x3);
1250 /* Copy 32-bit aligned data first */
1251 for (n
= 0; n
< cbytes
; n
+= 4)
1252 *p32
++ = readl(USBD_RXDATA(udc
->udp_baseaddr
));
1254 /* Handle any remaining bytes */
1255 bl
= bytes
- cbytes
;
1257 tmp
= readl(USBD_RXDATA(udc
->udp_baseaddr
));
1258 for (n
= 0; n
< bl
; n
++)
1259 data
[cbytes
+ n
] = ((tmp
>> (n
* 8)) & 0xFF);
1264 case 1: /* 8-bit aligned */
1266 /* Each byte has to be handled independently */
1267 for (n
= 0; n
< bytes
; n
+= 4) {
1268 tmp
= readl(USBD_RXDATA(udc
->udp_baseaddr
));
1274 for (i
= 0; i
< bl
; i
++)
1275 data
[n
+ i
] = (u8
) ((tmp
>> (n
* 8)) & 0xFF);
1279 case 2: /* 16-bit aligned */
1281 cbytes
= (bytes
& ~0x3);
1283 /* Copy 32-bit sized objects first with 16-bit alignment */
1284 for (n
= 0; n
< cbytes
; n
+= 4) {
1285 tmp
= readl(USBD_RXDATA(udc
->udp_baseaddr
));
1286 *p16
++ = (u16
)(tmp
& 0xFFFF);
1287 *p16
++ = (u16
)((tmp
>> 16) & 0xFFFF);
1290 /* Handle any remaining bytes */
1291 bl
= bytes
- cbytes
;
1293 tmp
= readl(USBD_RXDATA(udc
->udp_baseaddr
));
1294 for (n
= 0; n
< bl
; n
++)
1295 data
[cbytes
+ n
] = ((tmp
>> (n
* 8)) & 0xFF);
1301 /* Read data from the FIFO for an endpoint. This function is for endpoints (such
1302 * as EP0) that don't use DMA. This function should only be called if a packet
1303 * is known to be ready to read for the endpoint. Note that the endpoint must
1304 * be selected in the protocol engine prior to this call. */
1305 static u32
udc_read_hwep(struct lpc32xx_udc
*udc
, u32 hwep
, u32
*data
,
1310 u32 tmp
, hwrep
= ((hwep
& 0x1E) << 1) | CTRL_RD_EN
;
1312 /* Setup read of endpoint */
1313 writel(hwrep
, USBD_CTRL(udc
->udp_baseaddr
));
1315 /* Wait until packet is ready */
1316 while ((((tmpv
= readl(USBD_RXPLEN(udc
->udp_baseaddr
))) &
1317 PKT_RDY
) == 0) && (to
> 0))
1320 dev_dbg(udc
->dev
, "No packet ready on FIFO EP read\n");
1322 /* Mask out count */
1323 tmp
= tmpv
& PKT_LNGTH_MASK
;
1327 if ((tmp
> 0) && (data
!= NULL
))
1328 udc_pop_fifo(udc
, (u8
*) data
, tmp
);
1330 writel(((hwep
& 0x1E) << 1), USBD_CTRL(udc
->udp_baseaddr
));
1332 /* Clear the buffer */
1333 udc_clr_buffer_hwep(udc
, hwep
);
1338 /* Stuffs data into the FIFO, adjusts for alignment and data size */
1339 static void udc_stuff_fifo(struct lpc32xx_udc
*udc
, u8
*data
, u32 bytes
)
1343 u32
*p32
, tmp
, cbytes
;
1345 /* Use optimal data transfer method based on source address and size */
1346 switch (((u32
) data
) & 0x3) {
1347 case 0: /* 32-bit aligned */
1349 cbytes
= (bytes
& ~0x3);
1351 /* Copy 32-bit aligned data first */
1352 for (n
= 0; n
< cbytes
; n
+= 4)
1353 writel(*p32
++, USBD_TXDATA(udc
->udp_baseaddr
));
1355 /* Handle any remaining bytes */
1356 bl
= bytes
- cbytes
;
1359 for (n
= 0; n
< bl
; n
++)
1360 tmp
|= data
[cbytes
+ n
] << (n
* 8);
1362 writel(tmp
, USBD_TXDATA(udc
->udp_baseaddr
));
1366 case 1: /* 8-bit aligned */
1368 /* Each byte has to be handled independently */
1369 for (n
= 0; n
< bytes
; n
+= 4) {
1375 for (i
= 0; i
< bl
; i
++)
1376 tmp
|= data
[n
+ i
] << (i
* 8);
1378 writel(tmp
, USBD_TXDATA(udc
->udp_baseaddr
));
1382 case 2: /* 16-bit aligned */
1384 cbytes
= (bytes
& ~0x3);
1386 /* Copy 32-bit aligned data first */
1387 for (n
= 0; n
< cbytes
; n
+= 4) {
1388 tmp
= *p16
++ & 0xFFFF;
1389 tmp
|= (*p16
++ & 0xFFFF) << 16;
1390 writel(tmp
, USBD_TXDATA(udc
->udp_baseaddr
));
1393 /* Handle any remaining bytes */
1394 bl
= bytes
- cbytes
;
1397 for (n
= 0; n
< bl
; n
++)
1398 tmp
|= data
[cbytes
+ n
] << (n
* 8);
1400 writel(tmp
, USBD_TXDATA(udc
->udp_baseaddr
));
1406 /* Write data to the FIFO for an endpoint. This function is for endpoints (such
1407 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1408 * protocol engine prior to this call. */
1409 static void udc_write_hwep(struct lpc32xx_udc
*udc
, u32 hwep
, u32
*data
,
1412 u32 hwwep
= ((hwep
& 0x1E) << 1) | CTRL_WR_EN
;
1414 if ((bytes
> 0) && (data
== NULL
))
1417 /* Setup write of endpoint */
1418 writel(hwwep
, USBD_CTRL(udc
->udp_baseaddr
));
1420 writel(bytes
, USBD_TXPLEN(udc
->udp_baseaddr
));
1422 /* Need at least 1 byte to trigger TX */
1424 writel(0, USBD_TXDATA(udc
->udp_baseaddr
));
1426 udc_stuff_fifo(udc
, (u8
*) data
, bytes
);
1428 writel(((hwep
& 0x1E) << 1), USBD_CTRL(udc
->udp_baseaddr
));
1430 udc_val_buffer_hwep(udc
, hwep
);
1433 /* USB device reset - resets USB to a default state with just EP0
1435 static void uda_usb_reset(struct lpc32xx_udc
*udc
)
1438 /* Re-init device controller and EP0 */
1440 udc
->gadget
.speed
= USB_SPEED_FULL
;
1442 for (i
= 1; i
< NUM_ENDPOINTS
; i
++) {
1443 struct lpc32xx_ep
*ep
= &udc
->ep
[i
];
1444 ep
->req_pending
= 0;
1448 /* Send a ZLP on EP0 */
1449 static void udc_ep0_send_zlp(struct lpc32xx_udc
*udc
)
1451 udc_write_hwep(udc
, EP_IN
, NULL
, 0);
1454 /* Get current frame number */
1455 static u16
udc_get_current_frame(struct lpc32xx_udc
*udc
)
1459 udc_protocol_cmd_w(udc
, CMD_RD_FRAME
);
1460 flo
= (u16
) udc_protocol_cmd_r(udc
, DAT_RD_FRAME
);
1461 fhi
= (u16
) udc_protocol_cmd_r(udc
, DAT_RD_FRAME
);
1463 return (fhi
<< 8) | flo
;
1466 /* Set the device as configured - enables all endpoints */
1467 static inline void udc_set_device_configured(struct lpc32xx_udc
*udc
)
1469 udc_protocol_cmd_data_w(udc
, CMD_CFG_DEV
, DAT_WR_BYTE(CONF_DVICE
));
1472 /* Set the device as unconfigured - disables all endpoints */
1473 static inline void udc_set_device_unconfigured(struct lpc32xx_udc
*udc
)
1475 udc_protocol_cmd_data_w(udc
, CMD_CFG_DEV
, DAT_WR_BYTE(0));
1478 /* reinit == restore initial software state */
1479 static void udc_reinit(struct lpc32xx_udc
*udc
)
1483 INIT_LIST_HEAD(&udc
->gadget
.ep_list
);
1484 INIT_LIST_HEAD(&udc
->gadget
.ep0
->ep_list
);
1486 for (i
= 0; i
< NUM_ENDPOINTS
; i
++) {
1487 struct lpc32xx_ep
*ep
= &udc
->ep
[i
];
1490 list_add_tail(&ep
->ep
.ep_list
, &udc
->gadget
.ep_list
);
1492 ep
->ep
.maxpacket
= ep
->maxpacket
;
1493 INIT_LIST_HEAD(&ep
->queue
);
1494 ep
->req_pending
= 0;
1497 udc
->ep0state
= WAIT_FOR_SETUP
;
1500 /* Must be called with lock */
1501 static void done(struct lpc32xx_ep
*ep
, struct lpc32xx_request
*req
, int status
)
1503 struct lpc32xx_udc
*udc
= ep
->udc
;
1505 list_del_init(&req
->queue
);
1506 if (req
->req
.status
== -EINPROGRESS
)
1507 req
->req
.status
= status
;
1509 status
= req
->req
.status
;
1512 enum dma_data_direction direction
;
1515 direction
= DMA_TO_DEVICE
;
1517 direction
= DMA_FROM_DEVICE
;
1520 dma_unmap_single(ep
->udc
->gadget
.dev
.parent
,
1521 req
->req
.dma
, req
->req
.length
,
1526 dma_sync_single_for_cpu(ep
->udc
->gadget
.dev
.parent
,
1527 req
->req
.dma
, req
->req
.length
,
1531 udc_dd_free(udc
, req
->dd_desc_ptr
);
1534 if (status
&& status
!= -ESHUTDOWN
)
1535 ep_dbg(ep
, "%s done %p, status %d\n", ep
->ep
.name
, req
, status
);
1537 ep
->req_pending
= 0;
1538 spin_unlock(&udc
->lock
);
1539 req
->req
.complete(&ep
->ep
, &req
->req
);
1540 spin_lock(&udc
->lock
);
1543 /* Must be called with lock */
1544 static void nuke(struct lpc32xx_ep
*ep
, int status
)
1546 struct lpc32xx_request
*req
;
1548 while (!list_empty(&ep
->queue
)) {
1549 req
= list_entry(ep
->queue
.next
, struct lpc32xx_request
, queue
);
1550 done(ep
, req
, status
);
1553 if (ep
->desc
&& status
== -ESHUTDOWN
) {
1554 uda_disable_hwepint(ep
->udc
, ep
->hwep_num
);
1555 udc_disable_hwep(ep
->udc
, ep
->hwep_num
);
1559 /* IN endpoint 0 transfer */
1560 static int udc_ep0_in_req(struct lpc32xx_udc
*udc
)
1562 struct lpc32xx_request
*req
;
1563 struct lpc32xx_ep
*ep0
= &udc
->ep
[0];
1566 if (list_empty(&ep0
->queue
))
1567 /* Nothing to send */
1570 req
= list_entry(ep0
->queue
.next
, struct lpc32xx_request
,
1573 tsend
= ts
= req
->req
.length
- req
->req
.actual
;
1576 udc_ep0_send_zlp(udc
);
1579 } else if (ts
> ep0
->ep
.maxpacket
)
1580 ts
= ep0
->ep
.maxpacket
; /* Just send what we can */
1582 /* Write data to the EP0 FIFO and start transfer */
1583 udc_write_hwep(udc
, EP_IN
, (req
->req
.buf
+ req
->req
.actual
), ts
);
1585 /* Increment data pointer */
1586 req
->req
.actual
+= ts
;
1588 if (tsend
>= ep0
->ep
.maxpacket
)
1589 return 0; /* Stay in data transfer state */
1591 /* Transfer request is complete */
1592 udc
->ep0state
= WAIT_FOR_SETUP
;
1597 /* OUT endpoint 0 transfer */
1598 static int udc_ep0_out_req(struct lpc32xx_udc
*udc
)
1600 struct lpc32xx_request
*req
;
1601 struct lpc32xx_ep
*ep0
= &udc
->ep
[0];
1602 u32 tr
, bufferspace
;
1604 if (list_empty(&ep0
->queue
))
1607 req
= list_entry(ep0
->queue
.next
, struct lpc32xx_request
,
1611 if (req
->req
.length
== 0) {
1612 /* Just dequeue request */
1614 udc
->ep0state
= WAIT_FOR_SETUP
;
1618 /* Get data from FIFO */
1619 bufferspace
= req
->req
.length
- req
->req
.actual
;
1620 if (bufferspace
> ep0
->ep
.maxpacket
)
1621 bufferspace
= ep0
->ep
.maxpacket
;
1623 /* Copy data to buffer */
1624 prefetchw(req
->req
.buf
+ req
->req
.actual
);
1625 tr
= udc_read_hwep(udc
, EP_OUT
, req
->req
.buf
+ req
->req
.actual
,
1627 req
->req
.actual
+= bufferspace
;
1629 if (tr
< ep0
->ep
.maxpacket
) {
1630 /* This is the last packet */
1632 udc
->ep0state
= WAIT_FOR_SETUP
;
1640 /* Must be called with lock */
1641 static void stop_activity(struct lpc32xx_udc
*udc
)
1643 struct usb_gadget_driver
*driver
= udc
->driver
;
1646 if (udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1649 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1652 for (i
= 0; i
< NUM_ENDPOINTS
; i
++) {
1653 struct lpc32xx_ep
*ep
= &udc
->ep
[i
];
1654 nuke(ep
, -ESHUTDOWN
);
1657 spin_unlock(&udc
->lock
);
1658 driver
->disconnect(&udc
->gadget
);
1659 spin_lock(&udc
->lock
);
1662 isp1301_pullup_enable(udc
, 0, 0);
1668 * Activate or kill host pullup
1669 * Can be called with or without lock
1671 static void pullup(struct lpc32xx_udc
*udc
, int is_on
)
1676 if (!udc
->enabled
|| !udc
->vbus
)
1679 if (is_on
!= udc
->pullup
)
1680 isp1301_pullup_enable(udc
, is_on
, 0);
1683 /* Must be called without lock */
1684 static int lpc32xx_ep_disable(struct usb_ep
*_ep
)
1686 struct lpc32xx_ep
*ep
= container_of(_ep
, struct lpc32xx_ep
, ep
);
1687 struct lpc32xx_udc
*udc
= ep
->udc
;
1688 unsigned long flags
;
1690 if ((ep
->hwep_num_base
== 0) || (ep
->hwep_num
== 0))
1692 spin_lock_irqsave(&udc
->lock
, flags
);
1694 nuke(ep
, -ESHUTDOWN
);
1696 /* restore the endpoint's pristine config */
1699 /* Clear all DMA statuses for this EP */
1700 udc_ep_dma_disable(udc
, ep
->hwep_num
);
1701 writel(1 << ep
->hwep_num
, USBD_EOTINTCLR(udc
->udp_baseaddr
));
1702 writel(1 << ep
->hwep_num
, USBD_NDDRTINTCLR(udc
->udp_baseaddr
));
1703 writel(1 << ep
->hwep_num
, USBD_SYSERRTINTCLR(udc
->udp_baseaddr
));
1704 writel(1 << ep
->hwep_num
, USBD_DMARCLR(udc
->udp_baseaddr
));
1706 /* Remove the DD pointer in the UDCA */
1707 udc
->udca_v_base
[ep
->hwep_num
] = 0;
1709 /* Disable and reset endpoint and interrupt */
1710 uda_clear_hwepint(udc
, ep
->hwep_num
);
1711 udc_unrealize_hwep(udc
, ep
->hwep_num
);
1715 spin_unlock_irqrestore(&udc
->lock
, flags
);
1717 atomic_dec(&udc
->enabled_ep_cnt
);
1718 wake_up(&udc
->ep_disable_wait_queue
);
1723 /* Must be called without lock */
1724 static int lpc32xx_ep_enable(struct usb_ep
*_ep
,
1725 const struct usb_endpoint_descriptor
*desc
)
1727 struct lpc32xx_ep
*ep
= container_of(_ep
, struct lpc32xx_ep
, ep
);
1728 struct lpc32xx_udc
*udc
= ep
->udc
;
1731 unsigned long flags
;
1733 /* Verify EP data */
1734 if ((!_ep
) || (!ep
) || (!desc
) || (ep
->desc
) ||
1735 (desc
->bDescriptorType
!= USB_DT_ENDPOINT
)) {
1736 dev_dbg(udc
->dev
, "bad ep or descriptor\n");
1739 maxpacket
= usb_endpoint_maxp(desc
);
1740 if ((maxpacket
== 0) || (maxpacket
> ep
->maxpacket
)) {
1741 dev_dbg(udc
->dev
, "bad ep descriptor's packet size\n");
1745 /* Don't touch EP0 */
1746 if (ep
->hwep_num_base
== 0) {
1747 dev_dbg(udc
->dev
, "Can't re-enable EP0!!!\n");
1751 /* Is driver ready? */
1752 if ((!udc
->driver
) || (udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)) {
1753 dev_dbg(udc
->dev
, "bogus device state\n");
1757 tmp
= desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
;
1759 case USB_ENDPOINT_XFER_CONTROL
:
1762 case USB_ENDPOINT_XFER_INT
:
1763 if (maxpacket
> ep
->maxpacket
) {
1765 "Bad INT endpoint maxpacket %d\n", maxpacket
);
1770 case USB_ENDPOINT_XFER_BULK
:
1771 switch (maxpacket
) {
1780 "Bad BULK endpoint maxpacket %d\n", maxpacket
);
1785 case USB_ENDPOINT_XFER_ISOC
:
1788 spin_lock_irqsave(&udc
->lock
, flags
);
1790 /* Initialize endpoint to match the selected descriptor */
1791 ep
->is_in
= (desc
->bEndpointAddress
& USB_DIR_IN
) != 0;
1793 ep
->ep
.maxpacket
= maxpacket
;
1795 /* Map hardware endpoint from base and direction */
1797 /* IN endpoints are offset 1 from the OUT endpoint */
1798 ep
->hwep_num
= ep
->hwep_num_base
+ EP_IN
;
1800 ep
->hwep_num
= ep
->hwep_num_base
;
1802 ep_dbg(ep
, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep
->ep
.name
,
1803 ep
->hwep_num
, maxpacket
, (ep
->is_in
== 1));
1805 /* Realize the endpoint, interrupt is enabled later when
1806 * buffers are queued, IN EPs will NAK until buffers are ready */
1807 udc_realize_hwep(udc
, ep
->hwep_num
, ep
->ep
.maxpacket
);
1808 udc_clr_buffer_hwep(udc
, ep
->hwep_num
);
1809 uda_disable_hwepint(udc
, ep
->hwep_num
);
1810 udc_clrstall_hwep(udc
, ep
->hwep_num
);
1812 /* Clear all DMA statuses for this EP */
1813 udc_ep_dma_disable(udc
, ep
->hwep_num
);
1814 writel(1 << ep
->hwep_num
, USBD_EOTINTCLR(udc
->udp_baseaddr
));
1815 writel(1 << ep
->hwep_num
, USBD_NDDRTINTCLR(udc
->udp_baseaddr
));
1816 writel(1 << ep
->hwep_num
, USBD_SYSERRTINTCLR(udc
->udp_baseaddr
));
1817 writel(1 << ep
->hwep_num
, USBD_DMARCLR(udc
->udp_baseaddr
));
1819 spin_unlock_irqrestore(&udc
->lock
, flags
);
1821 atomic_inc(&udc
->enabled_ep_cnt
);
1826 * Allocate a USB request list
1827 * Can be called with or without lock
1829 static struct usb_request
*lpc32xx_ep_alloc_request(struct usb_ep
*_ep
,
1832 struct lpc32xx_request
*req
;
1834 req
= kzalloc(sizeof(struct lpc32xx_request
), gfp_flags
);
1838 INIT_LIST_HEAD(&req
->queue
);
1843 * De-allocate a USB request list
1844 * Can be called with or without lock
1846 static void lpc32xx_ep_free_request(struct usb_ep
*_ep
,
1847 struct usb_request
*_req
)
1849 struct lpc32xx_request
*req
;
1851 req
= container_of(_req
, struct lpc32xx_request
, req
);
1852 BUG_ON(!list_empty(&req
->queue
));
1856 /* Must be called without lock */
1857 static int lpc32xx_ep_queue(struct usb_ep
*_ep
,
1858 struct usb_request
*_req
, gfp_t gfp_flags
)
1860 struct lpc32xx_request
*req
;
1861 struct lpc32xx_ep
*ep
;
1862 struct lpc32xx_udc
*udc
;
1863 unsigned long flags
;
1866 req
= container_of(_req
, struct lpc32xx_request
, req
);
1867 ep
= container_of(_ep
, struct lpc32xx_ep
, ep
);
1869 if (!_req
|| !_req
->complete
|| !_req
->buf
||
1870 !list_empty(&req
->queue
))
1875 if (!_ep
|| (!ep
->desc
&& ep
->hwep_num_base
!= 0)) {
1876 dev_dbg(udc
->dev
, "invalid ep\n");
1881 if ((!udc
) || (!udc
->driver
) ||
1882 (udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)) {
1883 dev_dbg(udc
->dev
, "invalid device\n");
1888 enum dma_data_direction direction
;
1889 struct lpc32xx_usbd_dd_gad
*dd
;
1891 /* Map DMA pointer */
1893 direction
= DMA_TO_DEVICE
;
1895 direction
= DMA_FROM_DEVICE
;
1897 if (req
->req
.dma
== 0) {
1898 req
->req
.dma
= dma_map_single(
1899 ep
->udc
->gadget
.dev
.parent
,
1900 req
->req
.buf
, req
->req
.length
, direction
);
1903 dma_sync_single_for_device(
1904 ep
->udc
->gadget
.dev
.parent
, req
->req
.dma
,
1905 req
->req
.length
, direction
);
1909 /* For the request, build a list of DDs */
1910 dd
= udc_dd_alloc(udc
);
1912 /* Error allocating DD */
1915 req
->dd_desc_ptr
= dd
;
1917 /* Setup the DMA descriptor */
1918 dd
->dd_next_phy
= dd
->dd_next_v
= 0;
1919 dd
->dd_buffer_addr
= req
->req
.dma
;
1922 /* Special handling for ISO EPs */
1923 if (ep
->eptype
== EP_ISO_TYPE
) {
1924 dd
->dd_setup
= DD_SETUP_ISO_EP
|
1925 DD_SETUP_PACKETLEN(0) |
1926 DD_SETUP_DMALENBYTES(1);
1927 dd
->dd_iso_ps_mem_addr
= dd
->this_dma
+ 24;
1929 dd
->iso_status
[0] = req
->req
.length
;
1931 dd
->iso_status
[0] = 0;
1933 dd
->dd_setup
= DD_SETUP_PACKETLEN(ep
->ep
.maxpacket
) |
1934 DD_SETUP_DMALENBYTES(req
->req
.length
);
1937 ep_dbg(ep
, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep
->name
,
1938 _req
, _req
->length
, _req
->buf
, ep
->is_in
, _req
->zero
);
1940 spin_lock_irqsave(&udc
->lock
, flags
);
1942 _req
->status
= -EINPROGRESS
;
1944 req
->send_zlp
= _req
->zero
;
1946 /* Kickstart empty queues */
1947 if (list_empty(&ep
->queue
)) {
1948 list_add_tail(&req
->queue
, &ep
->queue
);
1950 if (ep
->hwep_num_base
== 0) {
1951 /* Handle expected data direction */
1953 /* IN packet to host */
1954 udc
->ep0state
= DATA_IN
;
1955 status
= udc_ep0_in_req(udc
);
1957 /* OUT packet from host */
1958 udc
->ep0state
= DATA_OUT
;
1959 status
= udc_ep0_out_req(udc
);
1961 } else if (ep
->is_in
) {
1962 /* IN packet to host and kick off transfer */
1963 if (!ep
->req_pending
)
1964 udc_ep_in_req_dma(udc
, ep
);
1966 /* OUT packet from host and kick off list */
1967 if (!ep
->req_pending
)
1968 udc_ep_out_req_dma(udc
, ep
);
1970 list_add_tail(&req
->queue
, &ep
->queue
);
1972 spin_unlock_irqrestore(&udc
->lock
, flags
);
1974 return (status
< 0) ? status
: 0;
1977 /* Must be called without lock */
1978 static int lpc32xx_ep_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
1980 struct lpc32xx_ep
*ep
;
1981 struct lpc32xx_request
*req
;
1982 unsigned long flags
;
1984 ep
= container_of(_ep
, struct lpc32xx_ep
, ep
);
1985 if (!_ep
|| ep
->hwep_num_base
== 0)
1988 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
1990 /* make sure it's actually queued on this endpoint */
1991 list_for_each_entry(req
, &ep
->queue
, queue
) {
1992 if (&req
->req
== _req
)
1995 if (&req
->req
!= _req
) {
1996 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
2000 done(ep
, req
, -ECONNRESET
);
2002 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
2007 /* Must be called without lock */
2008 static int lpc32xx_ep_set_halt(struct usb_ep
*_ep
, int value
)
2010 struct lpc32xx_ep
*ep
= container_of(_ep
, struct lpc32xx_ep
, ep
);
2011 struct lpc32xx_udc
*udc
= ep
->udc
;
2012 unsigned long flags
;
2014 if ((!ep
) || (ep
->desc
== NULL
) || (ep
->hwep_num
<= 1))
2017 /* Don't halt an IN EP */
2021 spin_lock_irqsave(&udc
->lock
, flags
);
2025 udc_protocol_cmd_data_w(udc
, CMD_SET_EP_STAT(ep
->hwep_num
),
2026 DAT_WR_BYTE(EP_STAT_ST
));
2030 udc_protocol_cmd_data_w(udc
, CMD_SET_EP_STAT(ep
->hwep_num
),
2034 spin_unlock_irqrestore(&udc
->lock
, flags
);
2039 /* set the halt feature and ignores clear requests */
2040 static int lpc32xx_ep_set_wedge(struct usb_ep
*_ep
)
2042 struct lpc32xx_ep
*ep
= container_of(_ep
, struct lpc32xx_ep
, ep
);
2044 if (!_ep
|| !ep
->udc
)
2049 return usb_ep_set_halt(_ep
);
2052 static const struct usb_ep_ops lpc32xx_ep_ops
= {
2053 .enable
= lpc32xx_ep_enable
,
2054 .disable
= lpc32xx_ep_disable
,
2055 .alloc_request
= lpc32xx_ep_alloc_request
,
2056 .free_request
= lpc32xx_ep_free_request
,
2057 .queue
= lpc32xx_ep_queue
,
2058 .dequeue
= lpc32xx_ep_dequeue
,
2059 .set_halt
= lpc32xx_ep_set_halt
,
2060 .set_wedge
= lpc32xx_ep_set_wedge
,
2063 /* Send a ZLP on a non-0 IN EP */
2064 void udc_send_in_zlp(struct lpc32xx_udc
*udc
, struct lpc32xx_ep
*ep
)
2066 /* Clear EP status */
2067 udc_clearep_getsts(udc
, ep
->hwep_num
);
2069 /* Send ZLP via FIFO mechanism */
2070 udc_write_hwep(udc
, ep
->hwep_num
, NULL
, 0);
2074 * Handle EP completion for ZLP
2075 * This function will only be called when a delayed ZLP needs to be sent out
2076 * after a DMA transfer has filled both buffers.
2078 void udc_handle_eps(struct lpc32xx_udc
*udc
, struct lpc32xx_ep
*ep
)
2081 struct lpc32xx_request
*req
;
2083 if (ep
->hwep_num
<= 0)
2086 uda_clear_hwepint(udc
, ep
->hwep_num
);
2088 /* If this interrupt isn't enabled, return now */
2089 if (!(udc
->enabled_hwepints
& (1 << ep
->hwep_num
)))
2092 /* Get endpoint status */
2093 epstatus
= udc_clearep_getsts(udc
, ep
->hwep_num
);
2096 * This should never happen, but protect against writing to the
2099 if (epstatus
& EP_SEL_F
)
2103 udc_send_in_zlp(udc
, ep
);
2104 uda_disable_hwepint(udc
, ep
->hwep_num
);
2108 /* If there isn't a request waiting, something went wrong */
2109 req
= list_entry(ep
->queue
.next
, struct lpc32xx_request
, queue
);
2113 /* Start another request if ready */
2114 if (!list_empty(&ep
->queue
)) {
2116 udc_ep_in_req_dma(udc
, ep
);
2118 udc_ep_out_req_dma(udc
, ep
);
2120 ep
->req_pending
= 0;
2125 /* DMA end of transfer completion */
2126 static void udc_handle_dma_ep(struct lpc32xx_udc
*udc
, struct lpc32xx_ep
*ep
)
2128 u32 status
, epstatus
;
2129 struct lpc32xx_request
*req
;
2130 struct lpc32xx_usbd_dd_gad
*dd
;
2132 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2136 req
= list_entry(ep
->queue
.next
, struct lpc32xx_request
, queue
);
2138 ep_err(ep
, "DMA interrupt on no req!\n");
2141 dd
= req
->dd_desc_ptr
;
2143 /* DMA descriptor should always be retired for this call */
2144 if (!(dd
->dd_status
& DD_STATUS_DD_RETIRED
))
2145 ep_warn(ep
, "DMA descriptor did not retire\n");
2148 udc_ep_dma_disable(udc
, ep
->hwep_num
);
2149 writel((1 << ep
->hwep_num
), USBD_EOTINTCLR(udc
->udp_baseaddr
));
2150 writel((1 << ep
->hwep_num
), USBD_NDDRTINTCLR(udc
->udp_baseaddr
));
2153 if (readl(USBD_SYSERRTINTST(udc
->udp_baseaddr
)) &
2154 (1 << ep
->hwep_num
)) {
2155 writel((1 << ep
->hwep_num
),
2156 USBD_SYSERRTINTCLR(udc
->udp_baseaddr
));
2157 ep_err(ep
, "AHB critical error!\n");
2158 ep
->req_pending
= 0;
2160 /* The error could have occurred on a packet of a multipacket
2161 * transfer, so recovering the transfer is not possible. Close
2162 * the request with an error */
2163 done(ep
, req
, -ECONNABORTED
);
2167 /* Handle the current DD's status */
2168 status
= dd
->dd_status
;
2169 switch (status
& DD_STATUS_STS_MASK
) {
2170 case DD_STATUS_STS_NS
:
2171 /* DD not serviced? This shouldn't happen! */
2172 ep
->req_pending
= 0;
2173 ep_err(ep
, "DMA critical EP error: DD not serviced (0x%x)!\n",
2176 done(ep
, req
, -ECONNABORTED
);
2179 case DD_STATUS_STS_BS
:
2180 /* Interrupt only fires on EOT - This shouldn't happen! */
2181 ep
->req_pending
= 0;
2182 ep_err(ep
, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2184 done(ep
, req
, -ECONNABORTED
);
2187 case DD_STATUS_STS_NC
:
2188 case DD_STATUS_STS_DUR
:
2189 /* Really just a short packet, not an underrun */
2190 /* This is a good status and what we expect */
2194 /* Data overrun, system error, or unknown */
2195 ep
->req_pending
= 0;
2196 ep_err(ep
, "DMA critical EP error: System error (0x%x)!\n",
2198 done(ep
, req
, -ECONNABORTED
);
2202 /* ISO endpoints are handled differently */
2203 if (ep
->eptype
== EP_ISO_TYPE
) {
2205 req
->req
.actual
= req
->req
.length
;
2207 req
->req
.actual
= dd
->iso_status
[0] & 0xFFFF;
2209 req
->req
.actual
+= DD_STATUS_CURDMACNT(status
);
2211 /* Send a ZLP if necessary. This will be done for non-int
2212 * packets which have a size that is a divisor of MAXP */
2213 if (req
->send_zlp
) {
2215 * If at least 1 buffer is available, send the ZLP now.
2216 * Otherwise, the ZLP send needs to be deferred until a
2217 * buffer is available.
2219 if (udc_clearep_getsts(udc
, ep
->hwep_num
) & EP_SEL_F
) {
2220 udc_clearep_getsts(udc
, ep
->hwep_num
);
2221 uda_enable_hwepint(udc
, ep
->hwep_num
);
2222 epstatus
= udc_clearep_getsts(udc
, ep
->hwep_num
);
2224 /* Let the EP interrupt handle the ZLP */
2227 udc_send_in_zlp(udc
, ep
);
2230 /* Transfer request is complete */
2233 /* Start another request if ready */
2234 udc_clearep_getsts(udc
, ep
->hwep_num
);
2235 if (!list_empty((&ep
->queue
))) {
2237 udc_ep_in_req_dma(udc
, ep
);
2239 udc_ep_out_req_dma(udc
, ep
);
2241 ep
->req_pending
= 0;
2247 * Endpoint 0 functions
2250 static void udc_handle_dev(struct lpc32xx_udc
*udc
)
2254 udc_protocol_cmd_w(udc
, CMD_GET_DEV_STAT
);
2255 tmp
= udc_protocol_cmd_r(udc
, DAT_GET_DEV_STAT
);
2259 else if (tmp
& DEV_CON_CH
)
2260 uda_power_event(udc
, (tmp
& DEV_CON
));
2261 else if (tmp
& DEV_SUS_CH
) {
2262 if (tmp
& DEV_SUS
) {
2265 else if ((udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) &&
2267 /* Power down transceiver */
2269 schedule_work(&udc
->pullup_job
);
2270 uda_resm_susp_event(udc
, 1);
2272 } else if ((udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) &&
2273 udc
->driver
&& udc
->vbus
) {
2274 uda_resm_susp_event(udc
, 0);
2275 /* Power up transceiver */
2277 schedule_work(&udc
->pullup_job
);
2282 static int udc_get_status(struct lpc32xx_udc
*udc
, u16 reqtype
, u16 wIndex
)
2284 struct lpc32xx_ep
*ep
;
2285 u32 ep0buff
= 0, tmp
;
2287 switch (reqtype
& USB_RECIP_MASK
) {
2288 case USB_RECIP_INTERFACE
:
2289 break; /* Not supported */
2291 case USB_RECIP_DEVICE
:
2292 ep0buff
= (udc
->selfpowered
<< USB_DEVICE_SELF_POWERED
);
2293 if (udc
->dev_status
& (1 << USB_DEVICE_REMOTE_WAKEUP
))
2294 ep0buff
|= (1 << USB_DEVICE_REMOTE_WAKEUP
);
2297 case USB_RECIP_ENDPOINT
:
2298 tmp
= wIndex
& USB_ENDPOINT_NUMBER_MASK
;
2300 if ((tmp
== 0) || (tmp
>= NUM_ENDPOINTS
) || (tmp
&& !ep
->desc
))
2303 if (wIndex
& USB_DIR_IN
) {
2305 return -EOPNOTSUPP
; /* Something's wrong */
2306 } else if (ep
->is_in
)
2307 return -EOPNOTSUPP
; /* Not an IN endpoint */
2309 /* Get status of the endpoint */
2310 udc_protocol_cmd_w(udc
, CMD_SEL_EP(ep
->hwep_num
));
2311 tmp
= udc_protocol_cmd_r(udc
, DAT_SEL_EP(ep
->hwep_num
));
2313 if (tmp
& EP_SEL_ST
)
2314 ep0buff
= (1 << USB_ENDPOINT_HALT
);
2324 udc_write_hwep(udc
, EP_IN
, &ep0buff
, 2);
2329 static void udc_handle_ep0_setup(struct lpc32xx_udc
*udc
)
2331 struct lpc32xx_ep
*ep
, *ep0
= &udc
->ep
[0];
2332 struct usb_ctrlrequest ctrlpkt
;
2334 u16 wIndex
, wValue
, wLength
, reqtype
, req
, tmp
;
2336 /* Nuke previous transfers */
2339 /* Get setup packet */
2340 bytes
= udc_read_hwep(udc
, EP_OUT
, (u32
*) &ctrlpkt
, 8);
2342 ep_warn(ep0
, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2347 /* Native endianness */
2348 wIndex
= le16_to_cpu(ctrlpkt
.wIndex
);
2349 wValue
= le16_to_cpu(ctrlpkt
.wValue
);
2350 wLength
= le16_to_cpu(ctrlpkt
.wLength
);
2351 reqtype
= le16_to_cpu(ctrlpkt
.bRequestType
);
2353 /* Set direction of EP0 */
2354 if (likely(reqtype
& USB_DIR_IN
))
2359 /* Handle SETUP packet */
2360 req
= le16_to_cpu(ctrlpkt
.bRequest
);
2362 case USB_REQ_CLEAR_FEATURE
:
2363 case USB_REQ_SET_FEATURE
:
2365 case (USB_TYPE_STANDARD
| USB_RECIP_DEVICE
):
2366 if (wValue
!= USB_DEVICE_REMOTE_WAKEUP
)
2367 goto stall
; /* Nothing else handled */
2369 /* Tell board about event */
2370 if (req
== USB_REQ_CLEAR_FEATURE
)
2372 ~(1 << USB_DEVICE_REMOTE_WAKEUP
);
2375 (1 << USB_DEVICE_REMOTE_WAKEUP
);
2376 uda_remwkp_cgh(udc
);
2379 case (USB_TYPE_STANDARD
| USB_RECIP_ENDPOINT
):
2380 tmp
= wIndex
& USB_ENDPOINT_NUMBER_MASK
;
2381 if ((wValue
!= USB_ENDPOINT_HALT
) ||
2382 (tmp
>= NUM_ENDPOINTS
))
2385 /* Find hardware endpoint from logical endpoint */
2391 if (req
== USB_REQ_SET_FEATURE
)
2392 udc_stall_hwep(udc
, tmp
);
2393 else if (!ep
->wedge
)
2394 udc_clrstall_hwep(udc
, tmp
);
2403 case USB_REQ_SET_ADDRESS
:
2404 if (reqtype
== (USB_TYPE_STANDARD
| USB_RECIP_DEVICE
)) {
2405 udc_set_address(udc
, wValue
);
2410 case USB_REQ_GET_STATUS
:
2411 udc_get_status(udc
, reqtype
, wIndex
);
2415 break; /* Let GadgetFS handle the descriptor instead */
2418 if (likely(udc
->driver
)) {
2419 /* device-2-host (IN) or no data setup command, process
2421 spin_unlock(&udc
->lock
);
2422 i
= udc
->driver
->setup(&udc
->gadget
, &ctrlpkt
);
2424 spin_lock(&udc
->lock
);
2425 if (req
== USB_REQ_SET_CONFIGURATION
) {
2426 /* Configuration is set after endpoints are realized */
2428 /* Set configuration */
2429 udc_set_device_configured(udc
);
2431 udc_protocol_cmd_data_w(udc
, CMD_SET_MODE
,
2432 DAT_WR_BYTE(AP_CLK
|
2433 INAK_BI
| INAK_II
));
2435 /* Clear configuration */
2436 udc_set_device_unconfigured(udc
);
2438 /* Disable NAK interrupts */
2439 udc_protocol_cmd_data_w(udc
, CMD_SET_MODE
,
2440 DAT_WR_BYTE(AP_CLK
));
2445 /* setup processing failed, force stall */
2447 "req %02x.%02x protocol STALL; stat %d\n",
2449 udc
->ep0state
= WAIT_FOR_SETUP
;
2455 udc_ep0_send_zlp(udc
); /* ZLP IN packet on data phase */
2460 udc_stall_hwep(udc
, EP_IN
);
2464 udc_ep0_send_zlp(udc
);
2468 /* IN endpoint 0 transfer */
2469 static void udc_handle_ep0_in(struct lpc32xx_udc
*udc
)
2471 struct lpc32xx_ep
*ep0
= &udc
->ep
[0];
2474 /* Clear EP interrupt */
2475 epstatus
= udc_clearep_getsts(udc
, EP_IN
);
2477 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2481 /* Stalled? Clear stall and reset buffers */
2482 if (epstatus
& EP_SEL_ST
) {
2483 udc_clrstall_hwep(udc
, EP_IN
);
2484 nuke(ep0
, -ECONNABORTED
);
2485 udc
->ep0state
= WAIT_FOR_SETUP
;
2489 /* Is a buffer available? */
2490 if (!(epstatus
& EP_SEL_F
)) {
2491 /* Handle based on current state */
2492 if (udc
->ep0state
== DATA_IN
)
2493 udc_ep0_in_req(udc
);
2495 /* Unknown state for EP0 oe end of DATA IN phase */
2496 nuke(ep0
, -ECONNABORTED
);
2497 udc
->ep0state
= WAIT_FOR_SETUP
;
2502 /* OUT endpoint 0 transfer */
2503 static void udc_handle_ep0_out(struct lpc32xx_udc
*udc
)
2505 struct lpc32xx_ep
*ep0
= &udc
->ep
[0];
2508 /* Clear EP interrupt */
2509 epstatus
= udc_clearep_getsts(udc
, EP_OUT
);
2512 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2517 if (epstatus
& EP_SEL_ST
) {
2518 udc_clrstall_hwep(udc
, EP_OUT
);
2519 nuke(ep0
, -ECONNABORTED
);
2520 udc
->ep0state
= WAIT_FOR_SETUP
;
2524 /* A NAK may occur if a packet couldn't be received yet */
2525 if (epstatus
& EP_SEL_EPN
)
2527 /* Setup packet incoming? */
2528 if (epstatus
& EP_SEL_STP
) {
2530 udc
->ep0state
= WAIT_FOR_SETUP
;
2533 /* Data available? */
2534 if (epstatus
& EP_SEL_F
)
2535 /* Handle based on current state */
2536 switch (udc
->ep0state
) {
2537 case WAIT_FOR_SETUP
:
2538 udc_handle_ep0_setup(udc
);
2542 udc_ep0_out_req(udc
);
2546 /* Unknown state for EP0 */
2547 nuke(ep0
, -ECONNABORTED
);
2548 udc
->ep0state
= WAIT_FOR_SETUP
;
2552 /* Must be called without lock */
2553 static int lpc32xx_get_frame(struct usb_gadget
*gadget
)
2556 unsigned long flags
;
2557 struct lpc32xx_udc
*udc
= to_udc(gadget
);
2562 spin_lock_irqsave(&udc
->lock
, flags
);
2564 frame
= (int) udc_get_current_frame(udc
);
2566 spin_unlock_irqrestore(&udc
->lock
, flags
);
2571 static int lpc32xx_wakeup(struct usb_gadget
*gadget
)
2576 static int lpc32xx_set_selfpowered(struct usb_gadget
*gadget
, int is_on
)
2578 struct lpc32xx_udc
*udc
= to_udc(gadget
);
2580 /* Always self-powered */
2581 udc
->selfpowered
= (is_on
!= 0);
2587 * vbus is here! turn everything on that's ready
2588 * Must be called without lock
2590 static int lpc32xx_vbus_session(struct usb_gadget
*gadget
, int is_active
)
2592 unsigned long flags
;
2593 struct lpc32xx_udc
*udc
= to_udc(gadget
);
2595 spin_lock_irqsave(&udc
->lock
, flags
);
2597 /* Doesn't need lock */
2599 udc_clk_set(udc
, 1);
2601 pullup(udc
, is_active
);
2606 spin_unlock_irqrestore(&udc
->lock
, flags
);
2608 * Wait for all the endpoints to disable,
2609 * before disabling clocks. Don't wait if
2610 * endpoints are not enabled.
2612 if (atomic_read(&udc
->enabled_ep_cnt
))
2613 wait_event_interruptible(udc
->ep_disable_wait_queue
,
2614 (atomic_read(&udc
->enabled_ep_cnt
) == 0));
2616 spin_lock_irqsave(&udc
->lock
, flags
);
2618 udc_clk_set(udc
, 0);
2621 spin_unlock_irqrestore(&udc
->lock
, flags
);
2626 /* Can be called with or without lock */
2627 static int lpc32xx_pullup(struct usb_gadget
*gadget
, int is_on
)
2629 struct lpc32xx_udc
*udc
= to_udc(gadget
);
2631 /* Doesn't need lock */
2637 static int lpc32xx_start(struct usb_gadget_driver
*driver
,
2638 int (*bind
)(struct usb_gadget
*));
2639 static int lpc32xx_stop(struct usb_gadget_driver
*driver
);
2641 static const struct usb_gadget_ops lpc32xx_udc_ops
= {
2642 .get_frame
= lpc32xx_get_frame
,
2643 .wakeup
= lpc32xx_wakeup
,
2644 .set_selfpowered
= lpc32xx_set_selfpowered
,
2645 .vbus_session
= lpc32xx_vbus_session
,
2646 .pullup
= lpc32xx_pullup
,
2647 .start
= lpc32xx_start
,
2648 .stop
= lpc32xx_stop
,
2651 static void nop_release(struct device
*dev
)
2653 /* nothing to free */
2656 static struct lpc32xx_udc controller
= {
2658 .ops
= &lpc32xx_udc_ops
,
2659 .ep0
= &controller
.ep
[0].ep
,
2660 .name
= driver_name
,
2662 .init_name
= "gadget",
2663 .release
= nop_release
,
2669 .ops
= &lpc32xx_ep_ops
,
2674 .hwep_num
= 0, /* Can be 0 or 1, has special handling */
2676 .eptype
= EP_CTL_TYPE
,
2681 .ops
= &lpc32xx_ep_ops
,
2686 .hwep_num
= 0, /* 2 or 3, will be set later */
2688 .eptype
= EP_INT_TYPE
,
2693 .ops
= &lpc32xx_ep_ops
,
2698 .hwep_num
= 0, /* 4 or 5, will be set later */
2700 .eptype
= EP_BLK_TYPE
,
2705 .ops
= &lpc32xx_ep_ops
,
2710 .hwep_num
= 0, /* 6 or 7, will be set later */
2712 .eptype
= EP_ISO_TYPE
,
2717 .ops
= &lpc32xx_ep_ops
,
2722 .hwep_num
= 0, /* 8 or 9, will be set later */
2724 .eptype
= EP_INT_TYPE
,
2729 .ops
= &lpc32xx_ep_ops
,
2733 .hwep_num_base
= 10,
2734 .hwep_num
= 0, /* 10 or 11, will be set later */
2736 .eptype
= EP_BLK_TYPE
,
2741 .ops
= &lpc32xx_ep_ops
,
2745 .hwep_num_base
= 12,
2746 .hwep_num
= 0, /* 12 or 13, will be set later */
2748 .eptype
= EP_ISO_TYPE
,
2753 .ops
= &lpc32xx_ep_ops
,
2757 .hwep_num_base
= 14,
2760 .eptype
= EP_INT_TYPE
,
2765 .ops
= &lpc32xx_ep_ops
,
2769 .hwep_num_base
= 16,
2772 .eptype
= EP_BLK_TYPE
,
2777 .ops
= &lpc32xx_ep_ops
,
2781 .hwep_num_base
= 18,
2784 .eptype
= EP_ISO_TYPE
,
2789 .ops
= &lpc32xx_ep_ops
,
2793 .hwep_num_base
= 20,
2796 .eptype
= EP_INT_TYPE
,
2800 .name
= "ep11-bulk",
2801 .ops
= &lpc32xx_ep_ops
,
2805 .hwep_num_base
= 22,
2808 .eptype
= EP_BLK_TYPE
,
2813 .ops
= &lpc32xx_ep_ops
,
2817 .hwep_num_base
= 24,
2820 .eptype
= EP_ISO_TYPE
,
2825 .ops
= &lpc32xx_ep_ops
,
2829 .hwep_num_base
= 26,
2832 .eptype
= EP_INT_TYPE
,
2836 .name
= "ep14-bulk",
2837 .ops
= &lpc32xx_ep_ops
,
2841 .hwep_num_base
= 28,
2844 .eptype
= EP_BLK_TYPE
,
2848 .name
= "ep15-bulk",
2849 .ops
= &lpc32xx_ep_ops
,
2853 .hwep_num_base
= 30,
2856 .eptype
= EP_BLK_TYPE
,
2860 /* ISO and status interrupts */
2861 static irqreturn_t
lpc32xx_usb_lp_irq(int irq
, void *_udc
)
2864 struct lpc32xx_udc
*udc
= _udc
;
2866 spin_lock(&udc
->lock
);
2868 /* Read the device status register */
2869 devstat
= readl(USBD_DEVINTST(udc
->udp_baseaddr
));
2871 devstat
&= ~USBD_EP_FAST
;
2872 writel(devstat
, USBD_DEVINTCLR(udc
->udp_baseaddr
));
2873 devstat
= devstat
& udc
->enabled_devints
;
2875 /* Device specific handling needed? */
2876 if (devstat
& USBD_DEV_STAT
)
2877 udc_handle_dev(udc
);
2879 /* Start of frame? (devstat & FRAME_INT):
2880 * The frame interrupt isn't really needed for ISO support,
2881 * as the driver will queue the necessary packets */
2884 if (devstat
& ERR_INT
) {
2885 /* All types of errors, from cable removal during transfer to
2886 * misc protocol and bit errors. These are mostly for just info,
2887 * as the USB hardware will work around these. If these errors
2888 * happen alot, something is wrong. */
2889 udc_protocol_cmd_w(udc
, CMD_RD_ERR_STAT
);
2890 tmp
= udc_protocol_cmd_r(udc
, DAT_RD_ERR_STAT
);
2891 dev_dbg(udc
->dev
, "Device error (0x%x)!\n", tmp
);
2894 spin_unlock(&udc
->lock
);
2900 static irqreturn_t
lpc32xx_usb_hp_irq(int irq
, void *_udc
)
2903 struct lpc32xx_udc
*udc
= _udc
;
2905 spin_lock(&udc
->lock
);
2907 /* Read the device status register */
2908 writel(USBD_EP_FAST
, USBD_DEVINTCLR(udc
->udp_baseaddr
));
2911 tmp
= readl(USBD_EPINTST(udc
->udp_baseaddr
));
2913 /* Special handling for EP0 */
2914 if (tmp
& (EP_MASK_SEL(0, EP_OUT
) | EP_MASK_SEL(0, EP_IN
))) {
2916 if (tmp
& (EP_MASK_SEL(0, EP_IN
)))
2917 udc_handle_ep0_in(udc
);
2919 /* Handle EP0 OUT */
2920 if (tmp
& (EP_MASK_SEL(0, EP_OUT
)))
2921 udc_handle_ep0_out(udc
);
2925 if (tmp
& ~(EP_MASK_SEL(0, EP_OUT
) | EP_MASK_SEL(0, EP_IN
))) {
2928 /* Handle other EP interrupts */
2929 for (i
= 1; i
< NUM_ENDPOINTS
; i
++) {
2930 if (tmp
& (1 << udc
->ep
[i
].hwep_num
))
2931 udc_handle_eps(udc
, &udc
->ep
[i
]);
2935 spin_unlock(&udc
->lock
);
2940 static irqreturn_t
lpc32xx_usb_devdma_irq(int irq
, void *_udc
)
2942 struct lpc32xx_udc
*udc
= _udc
;
2947 spin_lock(&udc
->lock
);
2949 /* Handle EP DMA EOT interrupts */
2950 tmp
= readl(USBD_EOTINTST(udc
->udp_baseaddr
)) |
2951 (readl(USBD_EPDMAST(udc
->udp_baseaddr
)) &
2952 readl(USBD_NDDRTINTST(udc
->udp_baseaddr
))) |
2953 readl(USBD_SYSERRTINTST(udc
->udp_baseaddr
));
2954 for (i
= 1; i
< NUM_ENDPOINTS
; i
++) {
2955 if (tmp
& (1 << udc
->ep
[i
].hwep_num
))
2956 udc_handle_dma_ep(udc
, &udc
->ep
[i
]);
2959 spin_unlock(&udc
->lock
);
2966 * VBUS detection, pullup handler, and Gadget cable state notification
2969 static void vbus_work(struct work_struct
*work
)
2972 struct lpc32xx_udc
*udc
= container_of(work
, struct lpc32xx_udc
,
2975 if (udc
->enabled
!= 0) {
2976 /* Discharge VBUS real quick */
2977 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
2978 ISP1301_I2C_OTG_CONTROL_1
, OTG1_VBUS_DISCHRG
);
2980 /* Give VBUS some time (100mS) to discharge */
2983 /* Disable VBUS discharge resistor */
2984 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
2985 ISP1301_I2C_OTG_CONTROL_1
| ISP1301_I2C_REG_CLEAR_ADDR
,
2988 /* Clear interrupt */
2989 i2c_smbus_write_byte_data(udc
->isp1301_i2c_client
,
2990 ISP1301_I2C_INTERRUPT_LATCH
|
2991 ISP1301_I2C_REG_CLEAR_ADDR
, ~0);
2993 /* Get the VBUS status from the transceiver */
2994 value
= i2c_smbus_read_byte_data(udc
->isp1301_i2c_client
,
2995 ISP1301_I2C_OTG_CONTROL_2
);
2997 /* VBUS on or off? */
2998 if (value
& OTG_B_SESS_VLD
)
3004 if (udc
->last_vbus
!= udc
->vbus
) {
3005 udc
->last_vbus
= udc
->vbus
;
3006 lpc32xx_vbus_session(&udc
->gadget
, udc
->vbus
);
3010 /* Re-enable after completion */
3011 enable_irq(udc
->udp_irq
[IRQ_USB_ATX
]);
3014 static irqreturn_t
lpc32xx_usb_vbus_irq(int irq
, void *_udc
)
3016 struct lpc32xx_udc
*udc
= _udc
;
3018 /* Defer handling of VBUS IRQ to work queue */
3019 disable_irq_nosync(udc
->udp_irq
[IRQ_USB_ATX
]);
3020 schedule_work(&udc
->vbus_job
);
3025 static int lpc32xx_start(struct usb_gadget_driver
*driver
,
3026 int (*bind
)(struct usb_gadget
*))
3028 struct lpc32xx_udc
*udc
= &controller
;
3031 if (!driver
|| driver
->max_speed
< USB_SPEED_FULL
||
3032 !bind
|| !driver
->setup
) {
3033 dev_err(udc
->dev
, "bad parameter.\n");
3038 dev_err(udc
->dev
, "UDC already has a gadget driver\n");
3042 udc
->driver
= driver
;
3043 udc
->gadget
.dev
.driver
= &driver
->driver
;
3045 udc
->selfpowered
= 1;
3048 retval
= bind(&udc
->gadget
);
3050 dev_err(udc
->dev
, "bind() returned %d\n", retval
);
3052 udc
->selfpowered
= 0;
3054 udc
->gadget
.dev
.driver
= NULL
;
3058 dev_dbg(udc
->dev
, "bound to %s\n", driver
->driver
.name
);
3060 /* Force VBUS process once to check for cable insertion */
3061 udc
->last_vbus
= udc
->vbus
= 0;
3062 schedule_work(&udc
->vbus_job
);
3064 /* Do not re-enable ATX IRQ (3) */
3065 for (i
= IRQ_USB_LP
; i
< IRQ_USB_ATX
; i
++)
3066 enable_irq(udc
->udp_irq
[i
]);
3071 static int lpc32xx_stop(struct usb_gadget_driver
*driver
)
3074 struct lpc32xx_udc
*udc
= &controller
;
3076 if (!driver
|| driver
!= udc
->driver
|| !driver
->unbind
)
3079 /* Disable USB pullup */
3080 isp1301_pullup_enable(udc
, 0, 1);
3082 for (i
= IRQ_USB_LP
; i
<= IRQ_USB_ATX
; i
++)
3083 disable_irq(udc
->udp_irq
[i
]);
3087 spin_lock(&udc
->lock
);
3089 spin_unlock(&udc
->lock
);
3092 * Wait for all the endpoints to disable,
3093 * before disabling clocks. Don't wait if
3094 * endpoints are not enabled.
3096 if (atomic_read(&udc
->enabled_ep_cnt
))
3097 wait_event_interruptible(udc
->ep_disable_wait_queue
,
3098 (atomic_read(&udc
->enabled_ep_cnt
) == 0));
3100 spin_lock(&udc
->lock
);
3101 udc_clk_set(udc
, 0);
3102 spin_unlock(&udc
->lock
);
3108 driver
->unbind(&udc
->gadget
);
3109 udc
->gadget
.dev
.driver
= NULL
;
3112 dev_dbg(udc
->dev
, "unbound from %s\n", driver
->driver
.name
);
3116 static void lpc32xx_udc_shutdown(struct platform_device
*dev
)
3118 /* Force disconnect on reboot */
3119 struct lpc32xx_udc
*udc
= &controller
;
3125 * Callbacks to be overridden by options passed via OF (TODO)
3128 static void lpc32xx_usbd_conn_chg(int conn
)
3130 /* Do nothing, it might be nice to enable an LED
3131 * based on conn state being !0 */
3134 static void lpc32xx_usbd_susp_chg(int susp
)
3136 /* Device suspend if susp != 0 */
3139 static void lpc32xx_rmwkup_chg(int remote_wakup_enable
)
3141 /* Enable or disable USB remote wakeup */
3144 struct lpc32xx_usbd_cfg lpc32xx_usbddata
= {
3146 .conn_chgb
= &lpc32xx_usbd_conn_chg
,
3147 .susp_chgb
= &lpc32xx_usbd_susp_chg
,
3148 .rmwk_chgb
= &lpc32xx_rmwkup_chg
,
3152 static u64 lpc32xx_usbd_dmamask
= ~(u32
) 0x7F;
3154 static int __init
lpc32xx_udc_probe(struct platform_device
*pdev
)
3156 struct device
*dev
= &pdev
->dev
;
3157 struct lpc32xx_udc
*udc
= &controller
;
3159 struct resource
*res
;
3160 dma_addr_t dma_handle
;
3161 struct device_node
*isp1301_node
;
3163 /* init software state */
3164 udc
->gadget
.dev
.parent
= dev
;
3166 udc
->dev
= &pdev
->dev
;
3169 if (pdev
->dev
.of_node
) {
3170 isp1301_node
= of_parse_phandle(pdev
->dev
.of_node
,
3173 isp1301_node
= NULL
;
3176 udc
->isp1301_i2c_client
= isp1301_get_client(isp1301_node
);
3177 if (!udc
->isp1301_i2c_client
)
3178 return -EPROBE_DEFER
;
3180 dev_info(udc
->dev
, "ISP1301 I2C device at address 0x%x\n",
3181 udc
->isp1301_i2c_client
->addr
);
3183 pdev
->dev
.dma_mask
= &lpc32xx_usbd_dmamask
;
3184 pdev
->dev
.coherent_dma_mask
= DMA_BIT_MASK(32);
3186 udc
->board
= &lpc32xx_usbddata
;
3189 * Resources are mapped as follows:
3190 * IORESOURCE_MEM, base address and size of USB space
3191 * IORESOURCE_IRQ, USB device low priority interrupt number
3192 * IORESOURCE_IRQ, USB device high priority interrupt number
3193 * IORESOURCE_IRQ, USB device interrupt number
3194 * IORESOURCE_IRQ, USB transceiver interrupt number
3196 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3200 spin_lock_init(&udc
->lock
);
3203 for (i
= 0; i
< 4; i
++) {
3204 udc
->udp_irq
[i
] = platform_get_irq(pdev
, i
);
3205 if (udc
->udp_irq
[i
] < 0) {
3207 "irq resource %d not available!\n", i
);
3208 return udc
->udp_irq
[i
];
3212 udc
->io_p_start
= res
->start
;
3213 udc
->io_p_size
= resource_size(res
);
3214 if (!request_mem_region(udc
->io_p_start
, udc
->io_p_size
, driver_name
)) {
3215 dev_err(udc
->dev
, "someone's using UDC memory\n");
3219 udc
->udp_baseaddr
= ioremap(udc
->io_p_start
, udc
->io_p_size
);
3220 if (!udc
->udp_baseaddr
) {
3222 dev_err(udc
->dev
, "IO map failure\n");
3226 /* Enable AHB slave USB clock, needed for further USB clock control */
3227 writel(USB_SLAVE_HCLK_EN
| (1 << 19), USB_CTRL
);
3229 /* Get required clocks */
3230 udc
->usb_pll_clk
= clk_get(&pdev
->dev
, "ck_pll5");
3231 if (IS_ERR(udc
->usb_pll_clk
)) {
3232 dev_err(udc
->dev
, "failed to acquire USB PLL\n");
3233 retval
= PTR_ERR(udc
->usb_pll_clk
);
3236 udc
->usb_slv_clk
= clk_get(&pdev
->dev
, "ck_usbd");
3237 if (IS_ERR(udc
->usb_slv_clk
)) {
3238 dev_err(udc
->dev
, "failed to acquire USB device clock\n");
3239 retval
= PTR_ERR(udc
->usb_slv_clk
);
3240 goto usb_clk_get_fail
;
3243 /* Setup PLL clock to 48MHz */
3244 retval
= clk_enable(udc
->usb_pll_clk
);
3246 dev_err(udc
->dev
, "failed to start USB PLL\n");
3247 goto pll_enable_fail
;
3250 retval
= clk_set_rate(udc
->usb_pll_clk
, 48000);
3252 dev_err(udc
->dev
, "failed to set USB clock rate\n");
3256 writel(readl(USB_CTRL
) | USB_DEV_NEED_CLK_EN
, USB_CTRL
);
3258 /* Enable USB device clock */
3259 retval
= clk_enable(udc
->usb_slv_clk
);
3261 dev_err(udc
->dev
, "failed to start USB device clock\n");
3262 goto usb_clk_enable_fail
;
3265 /* Set to enable all needed USB OTG clocks */
3266 writel(USB_CLOCK_MASK
, USB_OTG_CLK_CTRL(udc
));
3269 while (((readl(USB_OTG_CLK_STAT(udc
)) & USB_CLOCK_MASK
) !=
3270 USB_CLOCK_MASK
) && (i
> 0))
3273 dev_dbg(udc
->dev
, "USB OTG clocks not correctly enabled\n");
3275 /* Setup deferred workqueue data */
3276 udc
->poweron
= udc
->pullup
= 0;
3277 INIT_WORK(&udc
->pullup_job
, pullup_work
);
3278 INIT_WORK(&udc
->vbus_job
, vbus_work
);
3280 INIT_WORK(&udc
->power_job
, power_work
);
3283 /* All clocks are now on */
3286 isp1301_udc_configure(udc
);
3287 /* Allocate memory for the UDCA */
3288 udc
->udca_v_base
= dma_alloc_coherent(&pdev
->dev
, UDCA_BUFF_SIZE
,
3290 (GFP_KERNEL
| GFP_DMA
));
3291 if (!udc
->udca_v_base
) {
3292 dev_err(udc
->dev
, "error getting UDCA region\n");
3296 udc
->udca_p_base
= dma_handle
;
3297 dev_dbg(udc
->dev
, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3298 UDCA_BUFF_SIZE
, udc
->udca_p_base
, udc
->udca_v_base
);
3300 /* Setup the DD DMA memory pool */
3301 udc
->dd_cache
= dma_pool_create("udc_dd", udc
->dev
,
3302 sizeof(struct lpc32xx_usbd_dd_gad
),
3304 if (!udc
->dd_cache
) {
3305 dev_err(udc
->dev
, "error getting DD DMA region\n");
3307 goto dma_alloc_fail
;
3310 /* Clear USB peripheral and initialize gadget endpoints */
3314 retval
= device_register(&udc
->gadget
.dev
);
3316 dev_err(udc
->dev
, "Device registration failure\n");
3317 goto dev_register_fail
;
3320 /* Request IRQs - low and high priority USB device IRQs are routed to
3321 * the same handler, while the DMA interrupt is routed elsewhere */
3322 retval
= request_irq(udc
->udp_irq
[IRQ_USB_LP
], lpc32xx_usb_lp_irq
,
3325 dev_err(udc
->dev
, "LP request irq %d failed\n",
3326 udc
->udp_irq
[IRQ_USB_LP
]);
3329 retval
= request_irq(udc
->udp_irq
[IRQ_USB_HP
], lpc32xx_usb_hp_irq
,
3332 dev_err(udc
->dev
, "HP request irq %d failed\n",
3333 udc
->udp_irq
[IRQ_USB_HP
]);
3337 retval
= request_irq(udc
->udp_irq
[IRQ_USB_DEVDMA
],
3338 lpc32xx_usb_devdma_irq
, 0, "udc_dma", udc
);
3340 dev_err(udc
->dev
, "DEV request irq %d failed\n",
3341 udc
->udp_irq
[IRQ_USB_DEVDMA
]);
3345 /* The transceiver interrupt is used for VBUS detection and will
3346 kick off the VBUS handler function */
3347 retval
= request_irq(udc
->udp_irq
[IRQ_USB_ATX
], lpc32xx_usb_vbus_irq
,
3350 dev_err(udc
->dev
, "VBUS request irq %d failed\n",
3351 udc
->udp_irq
[IRQ_USB_ATX
]);
3355 /* Initialize wait queue */
3356 init_waitqueue_head(&udc
->ep_disable_wait_queue
);
3357 atomic_set(&udc
->enabled_ep_cnt
, 0);
3359 /* Keep all IRQs disabled until GadgetFS starts up */
3360 for (i
= IRQ_USB_LP
; i
<= IRQ_USB_ATX
; i
++)
3361 disable_irq(udc
->udp_irq
[i
]);
3363 retval
= usb_add_gadget_udc(dev
, &udc
->gadget
);
3365 goto add_gadget_fail
;
3367 dev_set_drvdata(dev
, udc
);
3368 device_init_wakeup(dev
, 1);
3369 create_debug_file(udc
);
3371 /* Disable clocks for now */
3372 udc_clk_set(udc
, 0);
3374 dev_info(udc
->dev
, "%s version %s\n", driver_name
, DRIVER_VERSION
);
3378 free_irq(udc
->udp_irq
[IRQ_USB_ATX
], udc
);
3380 free_irq(udc
->udp_irq
[IRQ_USB_DEVDMA
], udc
);
3382 free_irq(udc
->udp_irq
[IRQ_USB_HP
], udc
);
3384 free_irq(udc
->udp_irq
[IRQ_USB_LP
], udc
);
3386 device_unregister(&udc
->gadget
.dev
);
3388 dma_pool_destroy(udc
->dd_cache
);
3390 dma_free_coherent(&pdev
->dev
, UDCA_BUFF_SIZE
,
3391 udc
->udca_v_base
, udc
->udca_p_base
);
3393 clk_disable(udc
->usb_slv_clk
);
3394 usb_clk_enable_fail
:
3396 clk_disable(udc
->usb_pll_clk
);
3398 clk_put(udc
->usb_slv_clk
);
3400 clk_put(udc
->usb_pll_clk
);
3402 iounmap(udc
->udp_baseaddr
);
3404 release_mem_region(udc
->io_p_start
, udc
->io_p_size
);
3405 dev_err(udc
->dev
, "%s probe failed, %d\n", driver_name
, retval
);
3410 static int __devexit
lpc32xx_udc_remove(struct platform_device
*pdev
)
3412 struct lpc32xx_udc
*udc
= platform_get_drvdata(pdev
);
3414 usb_del_gadget_udc(&udc
->gadget
);
3418 udc_clk_set(udc
, 1);
3422 free_irq(udc
->udp_irq
[IRQ_USB_ATX
], udc
);
3424 device_init_wakeup(&pdev
->dev
, 0);
3425 remove_debug_file(udc
);
3427 dma_pool_destroy(udc
->dd_cache
);
3428 dma_free_coherent(&pdev
->dev
, UDCA_BUFF_SIZE
,
3429 udc
->udca_v_base
, udc
->udca_p_base
);
3430 free_irq(udc
->udp_irq
[IRQ_USB_DEVDMA
], udc
);
3431 free_irq(udc
->udp_irq
[IRQ_USB_HP
], udc
);
3432 free_irq(udc
->udp_irq
[IRQ_USB_LP
], udc
);
3434 device_unregister(&udc
->gadget
.dev
);
3436 clk_disable(udc
->usb_slv_clk
);
3437 clk_put(udc
->usb_slv_clk
);
3438 clk_disable(udc
->usb_pll_clk
);
3439 clk_put(udc
->usb_pll_clk
);
3440 iounmap(udc
->udp_baseaddr
);
3441 release_mem_region(udc
->io_p_start
, udc
->io_p_size
);
3447 static int lpc32xx_udc_suspend(struct platform_device
*pdev
, pm_message_t mesg
)
3450 struct lpc32xx_udc
*udc
= platform_get_drvdata(pdev
);
3453 /* Power down ISP */
3455 isp1301_set_powerstate(udc
, 0);
3457 /* Disable clocking */
3458 udc_clk_set(udc
, 0);
3460 /* Keep clock flag on, so we know to re-enable clocks
3464 /* Kill OTG and I2C clocks */
3465 writel(0, USB_OTG_CLK_CTRL(udc
));
3466 while (((readl(USB_OTG_CLK_STAT(udc
)) & OTGOFF_CLK_MASK
) !=
3467 OTGOFF_CLK_MASK
) && (to
> 0))
3471 "USB OTG clocks not correctly enabled\n");
3473 /* Kill global USB clock */
3474 clk_disable(udc
->usb_slv_clk
);
3480 static int lpc32xx_udc_resume(struct platform_device
*pdev
)
3482 struct lpc32xx_udc
*udc
= platform_get_drvdata(pdev
);
3485 /* Enable global USB clock */
3486 clk_enable(udc
->usb_slv_clk
);
3488 /* Enable clocking */
3489 udc_clk_set(udc
, 1);
3491 /* ISP back to normal power mode */
3493 isp1301_set_powerstate(udc
, 1);
3499 #define lpc32xx_udc_suspend NULL
3500 #define lpc32xx_udc_resume NULL
3504 static struct of_device_id lpc32xx_udc_of_match
[] = {
3505 { .compatible
= "nxp,lpc3220-udc", },
3508 MODULE_DEVICE_TABLE(of
, lpc32xx_udc_of_match
);
3511 static struct platform_driver lpc32xx_udc_driver
= {
3512 .remove
= __devexit_p(lpc32xx_udc_remove
),
3513 .shutdown
= lpc32xx_udc_shutdown
,
3514 .suspend
= lpc32xx_udc_suspend
,
3515 .resume
= lpc32xx_udc_resume
,
3517 .name
= (char *) driver_name
,
3518 .owner
= THIS_MODULE
,
3519 .of_match_table
= of_match_ptr(lpc32xx_udc_of_match
),
3523 static int __init
udc_init_module(void)
3525 return platform_driver_probe(&lpc32xx_udc_driver
, lpc32xx_udc_probe
);
3527 module_init(udc_init_module
);
3529 static void __exit
udc_exit_module(void)
3531 platform_driver_unregister(&lpc32xx_udc_driver
);
3533 module_exit(udc_exit_module
);
3535 MODULE_DESCRIPTION("LPC32XX udc driver");
3536 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3537 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3538 MODULE_LICENSE("GPL");
3539 MODULE_ALIAS("platform:lpc32xx_udc");