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usb: gadget: mv_udc: replace some debug info
[deliverable/linux.git] / drivers / usb / gadget / mv_udc_core.c
1 /*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmapool.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/ioport.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/timer.h>
24 #include <linux/list.h>
25 #include <linux/interrupt.h>
26 #include <linux/moduleparam.h>
27 #include <linux/device.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/otg.h>
31 #include <linux/pm.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36 #include <linux/platform_data/mv_usb.h>
37 #include <asm/system.h>
38 #include <asm/unaligned.h>
39
40 #include "mv_udc.h"
41
42 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
43 #define DRIVER_VERSION "8 Nov 2010"
44
45 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
46 ((ep)->udc->ep0_dir) : ((ep)->direction))
47
48 /* timeout value -- usec */
49 #define RESET_TIMEOUT 10000
50 #define FLUSH_TIMEOUT 10000
51 #define EPSTATUS_TIMEOUT 10000
52 #define PRIME_TIMEOUT 10000
53 #define READSAFE_TIMEOUT 1000
54 #define DTD_TIMEOUT 1000
55
56 #define LOOPS_USEC_SHIFT 4
57 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
58 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
59
60 static DECLARE_COMPLETION(release_done);
61
62 static const char driver_name[] = "mv_udc";
63 static const char driver_desc[] = DRIVER_DESC;
64
65 /* controller device global variable */
66 static struct mv_udc *the_controller;
67 int mv_usb_otgsc;
68
69 static void nuke(struct mv_ep *ep, int status);
70 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
71
72 /* for endpoint 0 operations */
73 static const struct usb_endpoint_descriptor mv_ep0_desc = {
74 .bLength = USB_DT_ENDPOINT_SIZE,
75 .bDescriptorType = USB_DT_ENDPOINT,
76 .bEndpointAddress = 0,
77 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
78 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
79 };
80
81 static void ep0_reset(struct mv_udc *udc)
82 {
83 struct mv_ep *ep;
84 u32 epctrlx;
85 int i = 0;
86
87 /* ep0 in and out */
88 for (i = 0; i < 2; i++) {
89 ep = &udc->eps[i];
90 ep->udc = udc;
91
92 /* ep0 dQH */
93 ep->dqh = &udc->ep_dqh[i];
94
95 /* configure ep0 endpoint capabilities in dQH */
96 ep->dqh->max_packet_length =
97 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
98 | EP_QUEUE_HEAD_IOS;
99
100 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
101
102 epctrlx = readl(&udc->op_regs->epctrlx[0]);
103 if (i) { /* TX */
104 epctrlx |= EPCTRL_TX_ENABLE
105 | (USB_ENDPOINT_XFER_CONTROL
106 << EPCTRL_TX_EP_TYPE_SHIFT);
107
108 } else { /* RX */
109 epctrlx |= EPCTRL_RX_ENABLE
110 | (USB_ENDPOINT_XFER_CONTROL
111 << EPCTRL_RX_EP_TYPE_SHIFT);
112 }
113
114 writel(epctrlx, &udc->op_regs->epctrlx[0]);
115 }
116 }
117
118 /* protocol ep0 stall, will automatically be cleared on new transaction */
119 static void ep0_stall(struct mv_udc *udc)
120 {
121 u32 epctrlx;
122
123 /* set TX and RX to stall */
124 epctrlx = readl(&udc->op_regs->epctrlx[0]);
125 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
126 writel(epctrlx, &udc->op_regs->epctrlx[0]);
127
128 /* update ep0 state */
129 udc->ep0_state = WAIT_FOR_SETUP;
130 udc->ep0_dir = EP_DIR_OUT;
131 }
132
133 static int process_ep_req(struct mv_udc *udc, int index,
134 struct mv_req *curr_req)
135 {
136 struct mv_dtd *curr_dtd;
137 struct mv_dqh *curr_dqh;
138 int td_complete, actual, remaining_length;
139 int i, direction;
140 int retval = 0;
141 u32 errors;
142 u32 bit_pos;
143
144 curr_dqh = &udc->ep_dqh[index];
145 direction = index % 2;
146
147 curr_dtd = curr_req->head;
148 td_complete = 0;
149 actual = curr_req->req.length;
150
151 for (i = 0; i < curr_req->dtd_count; i++) {
152 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
153 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
154 udc->eps[index].name);
155 return 1;
156 }
157
158 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
159 if (!errors) {
160 remaining_length =
161 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
162 >> DTD_LENGTH_BIT_POS;
163 actual -= remaining_length;
164
165 if (remaining_length) {
166 if (direction) {
167 dev_dbg(&udc->dev->dev,
168 "TX dTD remains data\n");
169 retval = -EPROTO;
170 break;
171 } else
172 break;
173 }
174 } else {
175 dev_info(&udc->dev->dev,
176 "complete_tr error: ep=%d %s: error = 0x%x\n",
177 index >> 1, direction ? "SEND" : "RECV",
178 errors);
179 if (errors & DTD_STATUS_HALTED) {
180 /* Clear the errors and Halt condition */
181 curr_dqh->size_ioc_int_sts &= ~errors;
182 retval = -EPIPE;
183 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
184 retval = -EPROTO;
185 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
186 retval = -EILSEQ;
187 }
188 }
189 if (i != curr_req->dtd_count - 1)
190 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
191 }
192 if (retval)
193 return retval;
194
195 if (direction == EP_DIR_OUT)
196 bit_pos = 1 << curr_req->ep->ep_num;
197 else
198 bit_pos = 1 << (16 + curr_req->ep->ep_num);
199
200 while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
201 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
202 while (readl(&udc->op_regs->epstatus) & bit_pos)
203 udelay(1);
204 break;
205 }
206 udelay(1);
207 }
208
209 curr_req->req.actual = actual;
210
211 return 0;
212 }
213
214 /*
215 * done() - retire a request; caller blocked irqs
216 * @status : request status to be set, only works when
217 * request is still in progress.
218 */
219 static void done(struct mv_ep *ep, struct mv_req *req, int status)
220 {
221 struct mv_udc *udc = NULL;
222 unsigned char stopped = ep->stopped;
223 struct mv_dtd *curr_td, *next_td;
224 int j;
225
226 udc = (struct mv_udc *)ep->udc;
227 /* Removed the req from fsl_ep->queue */
228 list_del_init(&req->queue);
229
230 /* req.status should be set as -EINPROGRESS in ep_queue() */
231 if (req->req.status == -EINPROGRESS)
232 req->req.status = status;
233 else
234 status = req->req.status;
235
236 /* Free dtd for the request */
237 next_td = req->head;
238 for (j = 0; j < req->dtd_count; j++) {
239 curr_td = next_td;
240 if (j != req->dtd_count - 1)
241 next_td = curr_td->next_dtd_virt;
242 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
243 }
244
245 if (req->mapped) {
246 dma_unmap_single(ep->udc->gadget.dev.parent,
247 req->req.dma, req->req.length,
248 ((ep_dir(ep) == EP_DIR_IN) ?
249 DMA_TO_DEVICE : DMA_FROM_DEVICE));
250 req->req.dma = DMA_ADDR_INVALID;
251 req->mapped = 0;
252 } else
253 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
254 req->req.dma, req->req.length,
255 ((ep_dir(ep) == EP_DIR_IN) ?
256 DMA_TO_DEVICE : DMA_FROM_DEVICE));
257
258 if (status && (status != -ESHUTDOWN))
259 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
260 ep->ep.name, &req->req, status,
261 req->req.actual, req->req.length);
262
263 ep->stopped = 1;
264
265 spin_unlock(&ep->udc->lock);
266 /*
267 * complete() is from gadget layer,
268 * eg fsg->bulk_in_complete()
269 */
270 if (req->req.complete)
271 req->req.complete(&ep->ep, &req->req);
272
273 spin_lock(&ep->udc->lock);
274 ep->stopped = stopped;
275 }
276
277 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
278 {
279 u32 tmp, epstatus, bit_pos, direction;
280 struct mv_udc *udc;
281 struct mv_dqh *dqh;
282 unsigned int loops;
283 int readsafe, retval = 0;
284
285 udc = ep->udc;
286 direction = ep_dir(ep);
287 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
288 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
289
290 /* check if the pipe is empty */
291 if (!(list_empty(&ep->queue))) {
292 struct mv_req *lastreq;
293 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
294 lastreq->tail->dtd_next =
295 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
296 if (readl(&udc->op_regs->epprime) & bit_pos) {
297 loops = LOOPS(PRIME_TIMEOUT);
298 while (readl(&udc->op_regs->epprime) & bit_pos) {
299 if (loops == 0) {
300 retval = -ETIME;
301 goto done;
302 }
303 udelay(LOOPS_USEC);
304 loops--;
305 }
306 if (readl(&udc->op_regs->epstatus) & bit_pos)
307 goto done;
308 }
309 readsafe = 0;
310 loops = LOOPS(READSAFE_TIMEOUT);
311 while (readsafe == 0) {
312 if (loops == 0) {
313 retval = -ETIME;
314 goto done;
315 }
316 /* start with setting the semaphores */
317 tmp = readl(&udc->op_regs->usbcmd);
318 tmp |= USBCMD_ATDTW_TRIPWIRE_SET;
319 writel(tmp, &udc->op_regs->usbcmd);
320
321 /* read the endpoint status */
322 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
323
324 /*
325 * Reread the ATDTW semaphore bit to check if it is
326 * cleared. When hardware see a hazard, it will clear
327 * the bit or else we remain set to 1 and we can
328 * proceed with priming of endpoint if not already
329 * primed.
330 */
331 if (readl(&udc->op_regs->usbcmd)
332 & USBCMD_ATDTW_TRIPWIRE_SET) {
333 readsafe = 1;
334 }
335 loops--;
336 udelay(LOOPS_USEC);
337 }
338
339 /* Clear the semaphore */
340 tmp = readl(&udc->op_regs->usbcmd);
341 tmp &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
342 writel(tmp, &udc->op_regs->usbcmd);
343
344 /* If endpoint is not active, we activate it now. */
345 if (!epstatus) {
346 if (direction == EP_DIR_IN) {
347 struct mv_dtd *curr_dtd = dma_to_virt(
348 &udc->dev->dev, dqh->curr_dtd_ptr);
349
350 loops = LOOPS(DTD_TIMEOUT);
351 while (curr_dtd->size_ioc_sts
352 & DTD_STATUS_ACTIVE) {
353 if (loops == 0) {
354 retval = -ETIME;
355 goto done;
356 }
357 loops--;
358 udelay(LOOPS_USEC);
359 }
360 }
361 /* No other transfers on the queue */
362
363 /* Write dQH next pointer and terminate bit to 0 */
364 dqh->next_dtd_ptr = req->head->td_dma
365 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
366 dqh->size_ioc_int_sts = 0;
367
368 /*
369 * Ensure that updates to the QH will
370 * occur before priming.
371 */
372 wmb();
373
374 /* Prime the Endpoint */
375 writel(bit_pos, &udc->op_regs->epprime);
376 }
377 } else {
378 /* Write dQH next pointer and terminate bit to 0 */
379 dqh->next_dtd_ptr = req->head->td_dma
380 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
381 dqh->size_ioc_int_sts = 0;
382
383 /* Ensure that updates to the QH will occur before priming. */
384 wmb();
385
386 /* Prime the Endpoint */
387 writel(bit_pos, &udc->op_regs->epprime);
388
389 if (direction == EP_DIR_IN) {
390 /* FIXME add status check after prime the IN ep */
391 int prime_again;
392 u32 curr_dtd_ptr = dqh->curr_dtd_ptr;
393
394 loops = LOOPS(DTD_TIMEOUT);
395 prime_again = 0;
396 while ((curr_dtd_ptr != req->head->td_dma)) {
397 curr_dtd_ptr = dqh->curr_dtd_ptr;
398 if (loops == 0) {
399 dev_err(&udc->dev->dev,
400 "failed to prime %s\n",
401 ep->name);
402 retval = -ETIME;
403 goto done;
404 }
405 loops--;
406 udelay(LOOPS_USEC);
407
408 if (loops == (LOOPS(DTD_TIMEOUT) >> 2)) {
409 if (prime_again)
410 goto done;
411 dev_info(&udc->dev->dev,
412 "prime again\n");
413 writel(bit_pos,
414 &udc->op_regs->epprime);
415 prime_again = 1;
416 }
417 }
418 }
419 }
420 done:
421 return retval;
422 }
423
424 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
425 dma_addr_t *dma, int *is_last)
426 {
427 u32 temp;
428 struct mv_dtd *dtd;
429 struct mv_udc *udc;
430
431 /* how big will this transfer be? */
432 *length = min(req->req.length - req->req.actual,
433 (unsigned)EP_MAX_LENGTH_TRANSFER);
434
435 udc = req->ep->udc;
436
437 /*
438 * Be careful that no _GFP_HIGHMEM is set,
439 * or we can not use dma_to_virt
440 */
441 dtd = dma_pool_alloc(udc->dtd_pool, GFP_KERNEL, dma);
442 if (dtd == NULL)
443 return dtd;
444
445 dtd->td_dma = *dma;
446 /* initialize buffer page pointers */
447 temp = (u32)(req->req.dma + req->req.actual);
448 dtd->buff_ptr0 = cpu_to_le32(temp);
449 temp &= ~0xFFF;
450 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
451 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
452 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
453 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
454
455 req->req.actual += *length;
456
457 /* zlp is needed if req->req.zero is set */
458 if (req->req.zero) {
459 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
460 *is_last = 1;
461 else
462 *is_last = 0;
463 } else if (req->req.length == req->req.actual)
464 *is_last = 1;
465 else
466 *is_last = 0;
467
468 /* Fill in the transfer size; set active bit */
469 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
470
471 /* Enable interrupt for the last dtd of a request */
472 if (*is_last && !req->req.no_interrupt)
473 temp |= DTD_IOC;
474
475 dtd->size_ioc_sts = temp;
476
477 mb();
478
479 return dtd;
480 }
481
482 /* generate dTD linked list for a request */
483 static int req_to_dtd(struct mv_req *req)
484 {
485 unsigned count;
486 int is_last, is_first = 1;
487 struct mv_dtd *dtd, *last_dtd = NULL;
488 struct mv_udc *udc;
489 dma_addr_t dma;
490
491 udc = req->ep->udc;
492
493 do {
494 dtd = build_dtd(req, &count, &dma, &is_last);
495 if (dtd == NULL)
496 return -ENOMEM;
497
498 if (is_first) {
499 is_first = 0;
500 req->head = dtd;
501 } else {
502 last_dtd->dtd_next = dma;
503 last_dtd->next_dtd_virt = dtd;
504 }
505 last_dtd = dtd;
506 req->dtd_count++;
507 } while (!is_last);
508
509 /* set terminate bit to 1 for the last dTD */
510 dtd->dtd_next = DTD_NEXT_TERMINATE;
511
512 req->tail = dtd;
513
514 return 0;
515 }
516
517 static int mv_ep_enable(struct usb_ep *_ep,
518 const struct usb_endpoint_descriptor *desc)
519 {
520 struct mv_udc *udc;
521 struct mv_ep *ep;
522 struct mv_dqh *dqh;
523 u16 max = 0;
524 u32 bit_pos, epctrlx, direction;
525 unsigned char zlt = 0, ios = 0, mult = 0;
526 unsigned long flags;
527
528 ep = container_of(_ep, struct mv_ep, ep);
529 udc = ep->udc;
530
531 if (!_ep || !desc || ep->desc
532 || desc->bDescriptorType != USB_DT_ENDPOINT)
533 return -EINVAL;
534
535 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
536 return -ESHUTDOWN;
537
538 direction = ep_dir(ep);
539 max = usb_endpoint_maxp(desc);
540
541 /*
542 * disable HW zero length termination select
543 * driver handles zero length packet through req->req.zero
544 */
545 zlt = 1;
546
547 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
548
549 /* Check if the Endpoint is Primed */
550 if ((readl(&udc->op_regs->epprime) & bit_pos)
551 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
552 dev_info(&udc->dev->dev,
553 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
554 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
555 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
556 (unsigned)readl(&udc->op_regs->epprime),
557 (unsigned)readl(&udc->op_regs->epstatus),
558 (unsigned)bit_pos);
559 goto en_done;
560 }
561 /* Set the max packet length, interrupt on Setup and Mult fields */
562 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
563 case USB_ENDPOINT_XFER_BULK:
564 zlt = 1;
565 mult = 0;
566 break;
567 case USB_ENDPOINT_XFER_CONTROL:
568 ios = 1;
569 case USB_ENDPOINT_XFER_INT:
570 mult = 0;
571 break;
572 case USB_ENDPOINT_XFER_ISOC:
573 /* Calculate transactions needed for high bandwidth iso */
574 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
575 max = max & 0x7ff; /* bit 0~10 */
576 /* 3 transactions at most */
577 if (mult > 3)
578 goto en_done;
579 break;
580 default:
581 goto en_done;
582 }
583
584 spin_lock_irqsave(&udc->lock, flags);
585 /* Get the endpoint queue head address */
586 dqh = ep->dqh;
587 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
588 | (mult << EP_QUEUE_HEAD_MULT_POS)
589 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
590 | (ios ? EP_QUEUE_HEAD_IOS : 0);
591 dqh->next_dtd_ptr = 1;
592 dqh->size_ioc_int_sts = 0;
593
594 ep->ep.maxpacket = max;
595 ep->desc = desc;
596 ep->stopped = 0;
597
598 /* Enable the endpoint for Rx or Tx and set the endpoint type */
599 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
600 if (direction == EP_DIR_IN) {
601 epctrlx &= ~EPCTRL_TX_ALL_MASK;
602 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
603 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
604 << EPCTRL_TX_EP_TYPE_SHIFT);
605 } else {
606 epctrlx &= ~EPCTRL_RX_ALL_MASK;
607 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
608 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
609 << EPCTRL_RX_EP_TYPE_SHIFT);
610 }
611 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
612
613 /*
614 * Implement Guideline (GL# USB-7) The unused endpoint type must
615 * be programmed to bulk.
616 */
617 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
618 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
619 epctrlx |= (USB_ENDPOINT_XFER_BULK
620 << EPCTRL_RX_EP_TYPE_SHIFT);
621 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
622 }
623
624 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
625 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
626 epctrlx |= (USB_ENDPOINT_XFER_BULK
627 << EPCTRL_TX_EP_TYPE_SHIFT);
628 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
629 }
630
631 spin_unlock_irqrestore(&udc->lock, flags);
632
633 return 0;
634 en_done:
635 return -EINVAL;
636 }
637
638 static int mv_ep_disable(struct usb_ep *_ep)
639 {
640 struct mv_udc *udc;
641 struct mv_ep *ep;
642 struct mv_dqh *dqh;
643 u32 bit_pos, epctrlx, direction;
644 unsigned long flags;
645
646 ep = container_of(_ep, struct mv_ep, ep);
647 if ((_ep == NULL) || !ep->desc)
648 return -EINVAL;
649
650 udc = ep->udc;
651
652 /* Get the endpoint queue head address */
653 dqh = ep->dqh;
654
655 spin_lock_irqsave(&udc->lock, flags);
656
657 direction = ep_dir(ep);
658 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
659
660 /* Reset the max packet length and the interrupt on Setup */
661 dqh->max_packet_length = 0;
662
663 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
664 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
665 epctrlx &= ~((direction == EP_DIR_IN)
666 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
667 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
668 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
669
670 /* nuke all pending requests (does flush) */
671 nuke(ep, -ESHUTDOWN);
672
673 ep->desc = NULL;
674 ep->stopped = 1;
675
676 spin_unlock_irqrestore(&udc->lock, flags);
677
678 return 0;
679 }
680
681 static struct usb_request *
682 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
683 {
684 struct mv_req *req = NULL;
685
686 req = kzalloc(sizeof *req, gfp_flags);
687 if (!req)
688 return NULL;
689
690 req->req.dma = DMA_ADDR_INVALID;
691 INIT_LIST_HEAD(&req->queue);
692
693 return &req->req;
694 }
695
696 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
697 {
698 struct mv_req *req = NULL;
699
700 req = container_of(_req, struct mv_req, req);
701
702 if (_req)
703 kfree(req);
704 }
705
706 static void mv_ep_fifo_flush(struct usb_ep *_ep)
707 {
708 struct mv_udc *udc;
709 u32 bit_pos, direction;
710 struct mv_ep *ep;
711 unsigned int loops;
712
713 if (!_ep)
714 return;
715
716 ep = container_of(_ep, struct mv_ep, ep);
717 if (!ep->desc)
718 return;
719
720 udc = ep->udc;
721 direction = ep_dir(ep);
722
723 if (ep->ep_num == 0)
724 bit_pos = (1 << 16) | 1;
725 else if (direction == EP_DIR_OUT)
726 bit_pos = 1 << ep->ep_num;
727 else
728 bit_pos = 1 << (16 + ep->ep_num);
729
730 loops = LOOPS(EPSTATUS_TIMEOUT);
731 do {
732 unsigned int inter_loops;
733
734 if (loops == 0) {
735 dev_err(&udc->dev->dev,
736 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
737 (unsigned)readl(&udc->op_regs->epstatus),
738 (unsigned)bit_pos);
739 return;
740 }
741 /* Write 1 to the Flush register */
742 writel(bit_pos, &udc->op_regs->epflush);
743
744 /* Wait until flushing completed */
745 inter_loops = LOOPS(FLUSH_TIMEOUT);
746 while (readl(&udc->op_regs->epflush)) {
747 /*
748 * ENDPTFLUSH bit should be cleared to indicate this
749 * operation is complete
750 */
751 if (inter_loops == 0) {
752 dev_err(&udc->dev->dev,
753 "TIMEOUT for ENDPTFLUSH=0x%x,"
754 "bit_pos=0x%x\n",
755 (unsigned)readl(&udc->op_regs->epflush),
756 (unsigned)bit_pos);
757 return;
758 }
759 inter_loops--;
760 udelay(LOOPS_USEC);
761 }
762 loops--;
763 } while (readl(&udc->op_regs->epstatus) & bit_pos);
764 }
765
766 /* queues (submits) an I/O request to an endpoint */
767 static int
768 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
769 {
770 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
771 struct mv_req *req = container_of(_req, struct mv_req, req);
772 struct mv_udc *udc = ep->udc;
773 unsigned long flags;
774
775 /* catch various bogus parameters */
776 if (!_req || !req->req.complete || !req->req.buf
777 || !list_empty(&req->queue)) {
778 dev_err(&udc->dev->dev, "%s, bad params", __func__);
779 return -EINVAL;
780 }
781 if (unlikely(!_ep || !ep->desc)) {
782 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
783 return -EINVAL;
784 }
785 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
786 if (req->req.length > ep->ep.maxpacket)
787 return -EMSGSIZE;
788 }
789
790 udc = ep->udc;
791 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
792 return -ESHUTDOWN;
793
794 req->ep = ep;
795
796 /* map virtual address to hardware */
797 if (req->req.dma == DMA_ADDR_INVALID) {
798 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
799 req->req.buf,
800 req->req.length, ep_dir(ep)
801 ? DMA_TO_DEVICE
802 : DMA_FROM_DEVICE);
803 req->mapped = 1;
804 } else {
805 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
806 req->req.dma, req->req.length,
807 ep_dir(ep)
808 ? DMA_TO_DEVICE
809 : DMA_FROM_DEVICE);
810 req->mapped = 0;
811 }
812
813 req->req.status = -EINPROGRESS;
814 req->req.actual = 0;
815 req->dtd_count = 0;
816
817 spin_lock_irqsave(&udc->lock, flags);
818
819 /* build dtds and push them to device queue */
820 if (!req_to_dtd(req)) {
821 int retval;
822 retval = queue_dtd(ep, req);
823 if (retval) {
824 spin_unlock_irqrestore(&udc->lock, flags);
825 return retval;
826 }
827 } else {
828 spin_unlock_irqrestore(&udc->lock, flags);
829 return -ENOMEM;
830 }
831
832 /* Update ep0 state */
833 if (ep->ep_num == 0)
834 udc->ep0_state = DATA_STATE_XMIT;
835
836 /* irq handler advances the queue */
837 if (req != NULL)
838 list_add_tail(&req->queue, &ep->queue);
839 spin_unlock_irqrestore(&udc->lock, flags);
840
841 return 0;
842 }
843
844 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
845 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
846 {
847 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
848 struct mv_req *req;
849 struct mv_udc *udc = ep->udc;
850 unsigned long flags;
851 int stopped, ret = 0;
852 u32 epctrlx;
853
854 if (!_ep || !_req)
855 return -EINVAL;
856
857 spin_lock_irqsave(&ep->udc->lock, flags);
858 stopped = ep->stopped;
859
860 /* Stop the ep before we deal with the queue */
861 ep->stopped = 1;
862 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
863 if (ep_dir(ep) == EP_DIR_IN)
864 epctrlx &= ~EPCTRL_TX_ENABLE;
865 else
866 epctrlx &= ~EPCTRL_RX_ENABLE;
867 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
868
869 /* make sure it's actually queued on this endpoint */
870 list_for_each_entry(req, &ep->queue, queue) {
871 if (&req->req == _req)
872 break;
873 }
874 if (&req->req != _req) {
875 ret = -EINVAL;
876 goto out;
877 }
878
879 /* The request is in progress, or completed but not dequeued */
880 if (ep->queue.next == &req->queue) {
881 _req->status = -ECONNRESET;
882 mv_ep_fifo_flush(_ep); /* flush current transfer */
883
884 /* The request isn't the last request in this ep queue */
885 if (req->queue.next != &ep->queue) {
886 struct mv_dqh *qh;
887 struct mv_req *next_req;
888
889 qh = ep->dqh;
890 next_req = list_entry(req->queue.next, struct mv_req,
891 queue);
892
893 /* Point the QH to the first TD of next request */
894 writel((u32) next_req->head, &qh->curr_dtd_ptr);
895 } else {
896 struct mv_dqh *qh;
897
898 qh = ep->dqh;
899 qh->next_dtd_ptr = 1;
900 qh->size_ioc_int_sts = 0;
901 }
902
903 /* The request hasn't been processed, patch up the TD chain */
904 } else {
905 struct mv_req *prev_req;
906
907 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
908 writel(readl(&req->tail->dtd_next),
909 &prev_req->tail->dtd_next);
910
911 }
912
913 done(ep, req, -ECONNRESET);
914
915 /* Enable EP */
916 out:
917 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
918 if (ep_dir(ep) == EP_DIR_IN)
919 epctrlx |= EPCTRL_TX_ENABLE;
920 else
921 epctrlx |= EPCTRL_RX_ENABLE;
922 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
923 ep->stopped = stopped;
924
925 spin_unlock_irqrestore(&ep->udc->lock, flags);
926 return ret;
927 }
928
929 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
930 {
931 u32 epctrlx;
932
933 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
934
935 if (stall) {
936 if (direction == EP_DIR_IN)
937 epctrlx |= EPCTRL_TX_EP_STALL;
938 else
939 epctrlx |= EPCTRL_RX_EP_STALL;
940 } else {
941 if (direction == EP_DIR_IN) {
942 epctrlx &= ~EPCTRL_TX_EP_STALL;
943 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
944 } else {
945 epctrlx &= ~EPCTRL_RX_EP_STALL;
946 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
947 }
948 }
949 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
950 }
951
952 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
953 {
954 u32 epctrlx;
955
956 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
957
958 if (direction == EP_DIR_OUT)
959 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
960 else
961 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
962 }
963
964 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
965 {
966 struct mv_ep *ep;
967 unsigned long flags = 0;
968 int status = 0;
969 struct mv_udc *udc;
970
971 ep = container_of(_ep, struct mv_ep, ep);
972 udc = ep->udc;
973 if (!_ep || !ep->desc) {
974 status = -EINVAL;
975 goto out;
976 }
977
978 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
979 status = -EOPNOTSUPP;
980 goto out;
981 }
982
983 /*
984 * Attempt to halt IN ep will fail if any transfer requests
985 * are still queue
986 */
987 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
988 status = -EAGAIN;
989 goto out;
990 }
991
992 spin_lock_irqsave(&ep->udc->lock, flags);
993 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
994 if (halt && wedge)
995 ep->wedge = 1;
996 else if (!halt)
997 ep->wedge = 0;
998 spin_unlock_irqrestore(&ep->udc->lock, flags);
999
1000 if (ep->ep_num == 0) {
1001 udc->ep0_state = WAIT_FOR_SETUP;
1002 udc->ep0_dir = EP_DIR_OUT;
1003 }
1004 out:
1005 return status;
1006 }
1007
1008 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
1009 {
1010 return mv_ep_set_halt_wedge(_ep, halt, 0);
1011 }
1012
1013 static int mv_ep_set_wedge(struct usb_ep *_ep)
1014 {
1015 return mv_ep_set_halt_wedge(_ep, 1, 1);
1016 }
1017
1018 static struct usb_ep_ops mv_ep_ops = {
1019 .enable = mv_ep_enable,
1020 .disable = mv_ep_disable,
1021
1022 .alloc_request = mv_alloc_request,
1023 .free_request = mv_free_request,
1024
1025 .queue = mv_ep_queue,
1026 .dequeue = mv_ep_dequeue,
1027
1028 .set_wedge = mv_ep_set_wedge,
1029 .set_halt = mv_ep_set_halt,
1030 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
1031 };
1032
1033 static void udc_clock_enable(struct mv_udc *udc)
1034 {
1035 unsigned int i;
1036
1037 for (i = 0; i < udc->clknum; i++)
1038 clk_enable(udc->clk[i]);
1039 }
1040
1041 static void udc_clock_disable(struct mv_udc *udc)
1042 {
1043 unsigned int i;
1044
1045 for (i = 0; i < udc->clknum; i++)
1046 clk_disable(udc->clk[i]);
1047 }
1048
1049 static void udc_stop(struct mv_udc *udc)
1050 {
1051 u32 tmp;
1052
1053 /* Disable interrupts */
1054 tmp = readl(&udc->op_regs->usbintr);
1055 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
1056 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
1057 writel(tmp, &udc->op_regs->usbintr);
1058
1059 udc->stopped = 1;
1060
1061 /* Reset the Run the bit in the command register to stop VUSB */
1062 tmp = readl(&udc->op_regs->usbcmd);
1063 tmp &= ~USBCMD_RUN_STOP;
1064 writel(tmp, &udc->op_regs->usbcmd);
1065 }
1066
1067 static void udc_start(struct mv_udc *udc)
1068 {
1069 u32 usbintr;
1070
1071 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1072 | USBINTR_PORT_CHANGE_DETECT_EN
1073 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1074 /* Enable interrupts */
1075 writel(usbintr, &udc->op_regs->usbintr);
1076
1077 udc->stopped = 0;
1078
1079 /* Set the Run bit in the command register */
1080 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1081 }
1082
1083 static int udc_reset(struct mv_udc *udc)
1084 {
1085 unsigned int loops;
1086 u32 tmp, portsc;
1087
1088 /* Stop the controller */
1089 tmp = readl(&udc->op_regs->usbcmd);
1090 tmp &= ~USBCMD_RUN_STOP;
1091 writel(tmp, &udc->op_regs->usbcmd);
1092
1093 /* Reset the controller to get default values */
1094 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1095
1096 /* wait for reset to complete */
1097 loops = LOOPS(RESET_TIMEOUT);
1098 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1099 if (loops == 0) {
1100 dev_err(&udc->dev->dev,
1101 "Wait for RESET completed TIMEOUT\n");
1102 return -ETIMEDOUT;
1103 }
1104 loops--;
1105 udelay(LOOPS_USEC);
1106 }
1107
1108 /* set controller to device mode */
1109 tmp = readl(&udc->op_regs->usbmode);
1110 tmp |= USBMODE_CTRL_MODE_DEVICE;
1111
1112 /* turn setup lockout off, require setup tripwire in usbcmd */
1113 tmp |= USBMODE_SETUP_LOCK_OFF | USBMODE_STREAM_DISABLE;
1114
1115 writel(tmp, &udc->op_regs->usbmode);
1116
1117 writel(0x0, &udc->op_regs->epsetupstat);
1118
1119 /* Configure the Endpoint List Address */
1120 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1121 &udc->op_regs->eplistaddr);
1122
1123 portsc = readl(&udc->op_regs->portsc[0]);
1124 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1125 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1126
1127 if (udc->force_fs)
1128 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1129 else
1130 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1131
1132 writel(portsc, &udc->op_regs->portsc[0]);
1133
1134 tmp = readl(&udc->op_regs->epctrlx[0]);
1135 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1136 writel(tmp, &udc->op_regs->epctrlx[0]);
1137
1138 return 0;
1139 }
1140
1141 static int mv_udc_enable_internal(struct mv_udc *udc)
1142 {
1143 int retval;
1144
1145 if (udc->active)
1146 return 0;
1147
1148 dev_dbg(&udc->dev->dev, "enable udc\n");
1149 udc_clock_enable(udc);
1150 if (udc->pdata->phy_init) {
1151 retval = udc->pdata->phy_init(udc->phy_regs);
1152 if (retval) {
1153 dev_err(&udc->dev->dev,
1154 "init phy error %d\n", retval);
1155 udc_clock_disable(udc);
1156 return retval;
1157 }
1158 }
1159 udc->active = 1;
1160
1161 return 0;
1162 }
1163
1164 static int mv_udc_enable(struct mv_udc *udc)
1165 {
1166 if (udc->clock_gating)
1167 return mv_udc_enable_internal(udc);
1168
1169 return 0;
1170 }
1171
1172 static void mv_udc_disable_internal(struct mv_udc *udc)
1173 {
1174 if (udc->active) {
1175 dev_dbg(&udc->dev->dev, "disable udc\n");
1176 if (udc->pdata->phy_deinit)
1177 udc->pdata->phy_deinit(udc->phy_regs);
1178 udc_clock_disable(udc);
1179 udc->active = 0;
1180 }
1181 }
1182
1183 static void mv_udc_disable(struct mv_udc *udc)
1184 {
1185 if (udc->clock_gating)
1186 mv_udc_disable_internal(udc);
1187 }
1188
1189 static int mv_udc_get_frame(struct usb_gadget *gadget)
1190 {
1191 struct mv_udc *udc;
1192 u16 retval;
1193
1194 if (!gadget)
1195 return -ENODEV;
1196
1197 udc = container_of(gadget, struct mv_udc, gadget);
1198
1199 retval = readl(udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1200
1201 return retval;
1202 }
1203
1204 /* Tries to wake up the host connected to this gadget */
1205 static int mv_udc_wakeup(struct usb_gadget *gadget)
1206 {
1207 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1208 u32 portsc;
1209
1210 /* Remote wakeup feature not enabled by host */
1211 if (!udc->remote_wakeup)
1212 return -ENOTSUPP;
1213
1214 portsc = readl(&udc->op_regs->portsc);
1215 /* not suspended? */
1216 if (!(portsc & PORTSCX_PORT_SUSPEND))
1217 return 0;
1218 /* trigger force resume */
1219 portsc |= PORTSCX_PORT_FORCE_RESUME;
1220 writel(portsc, &udc->op_regs->portsc[0]);
1221 return 0;
1222 }
1223
1224 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1225 {
1226 struct mv_udc *udc;
1227 unsigned long flags;
1228 int retval = 0;
1229
1230 udc = container_of(gadget, struct mv_udc, gadget);
1231 spin_lock_irqsave(&udc->lock, flags);
1232
1233 udc->vbus_active = (is_active != 0);
1234
1235 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1236 __func__, udc->softconnect, udc->vbus_active);
1237
1238 if (udc->driver && udc->softconnect && udc->vbus_active) {
1239 retval = mv_udc_enable(udc);
1240 if (retval == 0) {
1241 /* Clock is disabled, need re-init registers */
1242 udc_reset(udc);
1243 ep0_reset(udc);
1244 udc_start(udc);
1245 }
1246 } else if (udc->driver && udc->softconnect) {
1247 /* stop all the transfer in queue*/
1248 stop_activity(udc, udc->driver);
1249 udc_stop(udc);
1250 mv_udc_disable(udc);
1251 }
1252
1253 spin_unlock_irqrestore(&udc->lock, flags);
1254 return retval;
1255 }
1256
1257 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1258 {
1259 struct mv_udc *udc;
1260 unsigned long flags;
1261 int retval = 0;
1262
1263 udc = container_of(gadget, struct mv_udc, gadget);
1264 spin_lock_irqsave(&udc->lock, flags);
1265
1266 udc->softconnect = (is_on != 0);
1267
1268 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1269 __func__, udc->softconnect, udc->vbus_active);
1270
1271 if (udc->driver && udc->softconnect && udc->vbus_active) {
1272 retval = mv_udc_enable(udc);
1273 if (retval == 0) {
1274 /* Clock is disabled, need re-init registers */
1275 udc_reset(udc);
1276 ep0_reset(udc);
1277 udc_start(udc);
1278 }
1279 } else if (udc->driver && udc->vbus_active) {
1280 /* stop all the transfer in queue*/
1281 stop_activity(udc, udc->driver);
1282 udc_stop(udc);
1283 mv_udc_disable(udc);
1284 }
1285
1286 spin_unlock_irqrestore(&udc->lock, flags);
1287 return retval;
1288 }
1289
1290 static int mv_udc_start(struct usb_gadget_driver *driver,
1291 int (*bind)(struct usb_gadget *));
1292 static int mv_udc_stop(struct usb_gadget_driver *driver);
1293 /* device controller usb_gadget_ops structure */
1294 static const struct usb_gadget_ops mv_ops = {
1295
1296 /* returns the current frame number */
1297 .get_frame = mv_udc_get_frame,
1298
1299 /* tries to wake up the host connected to this gadget */
1300 .wakeup = mv_udc_wakeup,
1301
1302 /* notify controller that VBUS is powered or not */
1303 .vbus_session = mv_udc_vbus_session,
1304
1305 /* D+ pullup, software-controlled connect/disconnect to USB host */
1306 .pullup = mv_udc_pullup,
1307 .start = mv_udc_start,
1308 .stop = mv_udc_stop,
1309 };
1310
1311 static int eps_init(struct mv_udc *udc)
1312 {
1313 struct mv_ep *ep;
1314 char name[14];
1315 int i;
1316
1317 /* initialize ep0 */
1318 ep = &udc->eps[0];
1319 ep->udc = udc;
1320 strncpy(ep->name, "ep0", sizeof(ep->name));
1321 ep->ep.name = ep->name;
1322 ep->ep.ops = &mv_ep_ops;
1323 ep->wedge = 0;
1324 ep->stopped = 0;
1325 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1326 ep->ep_num = 0;
1327 ep->desc = &mv_ep0_desc;
1328 INIT_LIST_HEAD(&ep->queue);
1329
1330 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1331
1332 /* initialize other endpoints */
1333 for (i = 2; i < udc->max_eps * 2; i++) {
1334 ep = &udc->eps[i];
1335 if (i % 2) {
1336 snprintf(name, sizeof(name), "ep%din", i / 2);
1337 ep->direction = EP_DIR_IN;
1338 } else {
1339 snprintf(name, sizeof(name), "ep%dout", i / 2);
1340 ep->direction = EP_DIR_OUT;
1341 }
1342 ep->udc = udc;
1343 strncpy(ep->name, name, sizeof(ep->name));
1344 ep->ep.name = ep->name;
1345
1346 ep->ep.ops = &mv_ep_ops;
1347 ep->stopped = 0;
1348 ep->ep.maxpacket = (unsigned short) ~0;
1349 ep->ep_num = i / 2;
1350
1351 INIT_LIST_HEAD(&ep->queue);
1352 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1353
1354 ep->dqh = &udc->ep_dqh[i];
1355 }
1356
1357 return 0;
1358 }
1359
1360 /* delete all endpoint requests, called with spinlock held */
1361 static void nuke(struct mv_ep *ep, int status)
1362 {
1363 /* called with spinlock held */
1364 ep->stopped = 1;
1365
1366 /* endpoint fifo flush */
1367 mv_ep_fifo_flush(&ep->ep);
1368
1369 while (!list_empty(&ep->queue)) {
1370 struct mv_req *req = NULL;
1371 req = list_entry(ep->queue.next, struct mv_req, queue);
1372 done(ep, req, status);
1373 }
1374 }
1375
1376 /* stop all USB activities */
1377 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1378 {
1379 struct mv_ep *ep;
1380
1381 nuke(&udc->eps[0], -ESHUTDOWN);
1382
1383 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1384 nuke(ep, -ESHUTDOWN);
1385 }
1386
1387 /* report disconnect; the driver is already quiesced */
1388 if (driver) {
1389 spin_unlock(&udc->lock);
1390 driver->disconnect(&udc->gadget);
1391 spin_lock(&udc->lock);
1392 }
1393 }
1394
1395 static int mv_udc_start(struct usb_gadget_driver *driver,
1396 int (*bind)(struct usb_gadget *))
1397 {
1398 struct mv_udc *udc = the_controller;
1399 int retval = 0;
1400 unsigned long flags;
1401
1402 if (!udc)
1403 return -ENODEV;
1404
1405 if (udc->driver)
1406 return -EBUSY;
1407
1408 spin_lock_irqsave(&udc->lock, flags);
1409
1410 /* hook up the driver ... */
1411 driver->driver.bus = NULL;
1412 udc->driver = driver;
1413 udc->gadget.dev.driver = &driver->driver;
1414
1415 udc->usb_state = USB_STATE_ATTACHED;
1416 udc->ep0_state = WAIT_FOR_SETUP;
1417 udc->ep0_dir = EP_DIR_OUT;
1418
1419 spin_unlock_irqrestore(&udc->lock, flags);
1420
1421 retval = bind(&udc->gadget);
1422 if (retval) {
1423 dev_err(&udc->dev->dev, "bind to driver %s --> %d\n",
1424 driver->driver.name, retval);
1425 udc->driver = NULL;
1426 udc->gadget.dev.driver = NULL;
1427 return retval;
1428 }
1429
1430 if (udc->transceiver) {
1431 retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
1432 if (retval) {
1433 dev_err(&udc->dev->dev,
1434 "unable to register peripheral to otg\n");
1435 if (driver->unbind) {
1436 driver->unbind(&udc->gadget);
1437 udc->gadget.dev.driver = NULL;
1438 udc->driver = NULL;
1439 }
1440 return retval;
1441 }
1442 }
1443
1444 /* pullup is always on */
1445 mv_udc_pullup(&udc->gadget, 1);
1446
1447 /* When boot with cable attached, there will be no vbus irq occurred */
1448 if (udc->qwork)
1449 queue_work(udc->qwork, &udc->vbus_work);
1450
1451 return 0;
1452 }
1453
1454 static int mv_udc_stop(struct usb_gadget_driver *driver)
1455 {
1456 struct mv_udc *udc = the_controller;
1457 unsigned long flags;
1458
1459 if (!udc)
1460 return -ENODEV;
1461
1462 spin_lock_irqsave(&udc->lock, flags);
1463
1464 mv_udc_enable(udc);
1465 udc_stop(udc);
1466
1467 /* stop all usb activities */
1468 udc->gadget.speed = USB_SPEED_UNKNOWN;
1469 stop_activity(udc, driver);
1470 mv_udc_disable(udc);
1471
1472 spin_unlock_irqrestore(&udc->lock, flags);
1473
1474 /* unbind gadget driver */
1475 driver->unbind(&udc->gadget);
1476 udc->gadget.dev.driver = NULL;
1477 udc->driver = NULL;
1478
1479 return 0;
1480 }
1481
1482 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1483 {
1484 u32 portsc;
1485
1486 portsc = readl(&udc->op_regs->portsc[0]);
1487 portsc |= mode << 16;
1488 writel(portsc, &udc->op_regs->portsc[0]);
1489 }
1490
1491 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1492 {
1493 struct mv_udc *udc = the_controller;
1494 struct mv_req *req = container_of(_req, struct mv_req, req);
1495 unsigned long flags;
1496
1497 dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1498
1499 spin_lock_irqsave(&udc->lock, flags);
1500 if (req->test_mode) {
1501 mv_set_ptc(udc, req->test_mode);
1502 req->test_mode = 0;
1503 }
1504 spin_unlock_irqrestore(&udc->lock, flags);
1505 }
1506
1507 static int
1508 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1509 {
1510 int retval = 0;
1511 struct mv_req *req;
1512 struct mv_ep *ep;
1513
1514 ep = &udc->eps[0];
1515 udc->ep0_dir = direction;
1516 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1517
1518 req = udc->status_req;
1519
1520 /* fill in the reqest structure */
1521 if (empty == false) {
1522 *((u16 *) req->req.buf) = cpu_to_le16(status);
1523 req->req.length = 2;
1524 } else
1525 req->req.length = 0;
1526
1527 req->ep = ep;
1528 req->req.status = -EINPROGRESS;
1529 req->req.actual = 0;
1530 if (udc->test_mode) {
1531 req->req.complete = prime_status_complete;
1532 req->test_mode = udc->test_mode;
1533 udc->test_mode = 0;
1534 } else
1535 req->req.complete = NULL;
1536 req->dtd_count = 0;
1537
1538 if (req->req.dma == DMA_ADDR_INVALID) {
1539 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1540 req->req.buf, req->req.length,
1541 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1542 req->mapped = 1;
1543 }
1544
1545 /* prime the data phase */
1546 if (!req_to_dtd(req))
1547 retval = queue_dtd(ep, req);
1548 else{ /* no mem */
1549 retval = -ENOMEM;
1550 goto out;
1551 }
1552
1553 if (retval) {
1554 dev_err(&udc->dev->dev, "response error on GET_STATUS request\n");
1555 goto out;
1556 }
1557
1558 list_add_tail(&req->queue, &ep->queue);
1559
1560 return 0;
1561 out:
1562 return retval;
1563 }
1564
1565 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1566 {
1567 if (index <= TEST_FORCE_EN) {
1568 udc->test_mode = index;
1569 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1570 ep0_stall(udc);
1571 } else
1572 dev_err(&udc->dev->dev,
1573 "This test mode(%d) is not supported\n", index);
1574 }
1575
1576 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1577 {
1578 udc->dev_addr = (u8)setup->wValue;
1579
1580 /* update usb state */
1581 udc->usb_state = USB_STATE_ADDRESS;
1582
1583 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1584 ep0_stall(udc);
1585 }
1586
1587 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1588 struct usb_ctrlrequest *setup)
1589 {
1590 u16 status = 0;
1591 int retval;
1592
1593 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1594 != (USB_DIR_IN | USB_TYPE_STANDARD))
1595 return;
1596
1597 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1598 status = 1 << USB_DEVICE_SELF_POWERED;
1599 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1600 } else if ((setup->bRequestType & USB_RECIP_MASK)
1601 == USB_RECIP_INTERFACE) {
1602 /* get interface status */
1603 status = 0;
1604 } else if ((setup->bRequestType & USB_RECIP_MASK)
1605 == USB_RECIP_ENDPOINT) {
1606 u8 ep_num, direction;
1607
1608 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1609 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1610 ? EP_DIR_IN : EP_DIR_OUT;
1611 status = ep_is_stall(udc, ep_num, direction)
1612 << USB_ENDPOINT_HALT;
1613 }
1614
1615 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1616 if (retval)
1617 ep0_stall(udc);
1618 else
1619 udc->ep0_state = DATA_STATE_XMIT;
1620 }
1621
1622 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1623 {
1624 u8 ep_num;
1625 u8 direction;
1626 struct mv_ep *ep;
1627
1628 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1629 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1630 switch (setup->wValue) {
1631 case USB_DEVICE_REMOTE_WAKEUP:
1632 udc->remote_wakeup = 0;
1633 break;
1634 default:
1635 goto out;
1636 }
1637 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1638 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1639 switch (setup->wValue) {
1640 case USB_ENDPOINT_HALT:
1641 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1642 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1643 ? EP_DIR_IN : EP_DIR_OUT;
1644 if (setup->wValue != 0 || setup->wLength != 0
1645 || ep_num > udc->max_eps)
1646 goto out;
1647 ep = &udc->eps[ep_num * 2 + direction];
1648 if (ep->wedge == 1)
1649 break;
1650 spin_unlock(&udc->lock);
1651 ep_set_stall(udc, ep_num, direction, 0);
1652 spin_lock(&udc->lock);
1653 break;
1654 default:
1655 goto out;
1656 }
1657 } else
1658 goto out;
1659
1660 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1661 ep0_stall(udc);
1662 out:
1663 return;
1664 }
1665
1666 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1667 {
1668 u8 ep_num;
1669 u8 direction;
1670
1671 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1672 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1673 switch (setup->wValue) {
1674 case USB_DEVICE_REMOTE_WAKEUP:
1675 udc->remote_wakeup = 1;
1676 break;
1677 case USB_DEVICE_TEST_MODE:
1678 if (setup->wIndex & 0xFF
1679 || udc->gadget.speed != USB_SPEED_HIGH)
1680 ep0_stall(udc);
1681
1682 if (udc->usb_state != USB_STATE_CONFIGURED
1683 && udc->usb_state != USB_STATE_ADDRESS
1684 && udc->usb_state != USB_STATE_DEFAULT)
1685 ep0_stall(udc);
1686
1687 mv_udc_testmode(udc, (setup->wIndex >> 8));
1688 goto out;
1689 default:
1690 goto out;
1691 }
1692 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1693 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1694 switch (setup->wValue) {
1695 case USB_ENDPOINT_HALT:
1696 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1697 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1698 ? EP_DIR_IN : EP_DIR_OUT;
1699 if (setup->wValue != 0 || setup->wLength != 0
1700 || ep_num > udc->max_eps)
1701 goto out;
1702 spin_unlock(&udc->lock);
1703 ep_set_stall(udc, ep_num, direction, 1);
1704 spin_lock(&udc->lock);
1705 break;
1706 default:
1707 goto out;
1708 }
1709 } else
1710 goto out;
1711
1712 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1713 ep0_stall(udc);
1714 out:
1715 return;
1716 }
1717
1718 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1719 struct usb_ctrlrequest *setup)
1720 {
1721 bool delegate = false;
1722
1723 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1724
1725 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1726 setup->bRequestType, setup->bRequest,
1727 setup->wValue, setup->wIndex, setup->wLength);
1728 /* We process some stardard setup requests here */
1729 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1730 switch (setup->bRequest) {
1731 case USB_REQ_GET_STATUS:
1732 ch9getstatus(udc, ep_num, setup);
1733 break;
1734
1735 case USB_REQ_SET_ADDRESS:
1736 ch9setaddress(udc, setup);
1737 break;
1738
1739 case USB_REQ_CLEAR_FEATURE:
1740 ch9clearfeature(udc, setup);
1741 break;
1742
1743 case USB_REQ_SET_FEATURE:
1744 ch9setfeature(udc, setup);
1745 break;
1746
1747 default:
1748 delegate = true;
1749 }
1750 } else
1751 delegate = true;
1752
1753 /* delegate USB standard requests to the gadget driver */
1754 if (delegate == true) {
1755 /* USB requests handled by gadget */
1756 if (setup->wLength) {
1757 /* DATA phase from gadget, STATUS phase from udc */
1758 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1759 ? EP_DIR_IN : EP_DIR_OUT;
1760 spin_unlock(&udc->lock);
1761 if (udc->driver->setup(&udc->gadget,
1762 &udc->local_setup_buff) < 0)
1763 ep0_stall(udc);
1764 spin_lock(&udc->lock);
1765 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1766 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1767 } else {
1768 /* no DATA phase, IN STATUS phase from gadget */
1769 udc->ep0_dir = EP_DIR_IN;
1770 spin_unlock(&udc->lock);
1771 if (udc->driver->setup(&udc->gadget,
1772 &udc->local_setup_buff) < 0)
1773 ep0_stall(udc);
1774 spin_lock(&udc->lock);
1775 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1776 }
1777 }
1778 }
1779
1780 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1781 static void ep0_req_complete(struct mv_udc *udc,
1782 struct mv_ep *ep0, struct mv_req *req)
1783 {
1784 u32 new_addr;
1785
1786 if (udc->usb_state == USB_STATE_ADDRESS) {
1787 /* set the new address */
1788 new_addr = (u32)udc->dev_addr;
1789 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1790 &udc->op_regs->deviceaddr);
1791 }
1792
1793 done(ep0, req, 0);
1794
1795 switch (udc->ep0_state) {
1796 case DATA_STATE_XMIT:
1797 /* receive status phase */
1798 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1799 ep0_stall(udc);
1800 break;
1801 case DATA_STATE_RECV:
1802 /* send status phase */
1803 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1804 ep0_stall(udc);
1805 break;
1806 case WAIT_FOR_OUT_STATUS:
1807 udc->ep0_state = WAIT_FOR_SETUP;
1808 break;
1809 case WAIT_FOR_SETUP:
1810 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1811 break;
1812 default:
1813 ep0_stall(udc);
1814 break;
1815 }
1816 }
1817
1818 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1819 {
1820 u32 temp;
1821 struct mv_dqh *dqh;
1822
1823 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1824
1825 /* Clear bit in ENDPTSETUPSTAT */
1826 writel((1 << ep_num), &udc->op_regs->epsetupstat);
1827
1828 /* while a hazard exists when setup package arrives */
1829 do {
1830 /* Set Setup Tripwire */
1831 temp = readl(&udc->op_regs->usbcmd);
1832 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1833
1834 /* Copy the setup packet to local buffer */
1835 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1836 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1837
1838 /* Clear Setup Tripwire */
1839 temp = readl(&udc->op_regs->usbcmd);
1840 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1841 }
1842
1843 static void irq_process_tr_complete(struct mv_udc *udc)
1844 {
1845 u32 tmp, bit_pos;
1846 int i, ep_num = 0, direction = 0;
1847 struct mv_ep *curr_ep;
1848 struct mv_req *curr_req, *temp_req;
1849 int status;
1850
1851 /*
1852 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1853 * because the setup packets are to be read ASAP
1854 */
1855
1856 /* Process all Setup packet received interrupts */
1857 tmp = readl(&udc->op_regs->epsetupstat);
1858
1859 if (tmp) {
1860 for (i = 0; i < udc->max_eps; i++) {
1861 if (tmp & (1 << i)) {
1862 get_setup_data(udc, i,
1863 (u8 *)(&udc->local_setup_buff));
1864 handle_setup_packet(udc, i,
1865 &udc->local_setup_buff);
1866 }
1867 }
1868 }
1869
1870 /* Don't clear the endpoint setup status register here.
1871 * It is cleared as a setup packet is read out of the buffer
1872 */
1873
1874 /* Process non-setup transaction complete interrupts */
1875 tmp = readl(&udc->op_regs->epcomplete);
1876
1877 if (!tmp)
1878 return;
1879
1880 writel(tmp, &udc->op_regs->epcomplete);
1881
1882 for (i = 0; i < udc->max_eps * 2; i++) {
1883 ep_num = i >> 1;
1884 direction = i % 2;
1885
1886 bit_pos = 1 << (ep_num + 16 * direction);
1887
1888 if (!(bit_pos & tmp))
1889 continue;
1890
1891 if (i == 1)
1892 curr_ep = &udc->eps[0];
1893 else
1894 curr_ep = &udc->eps[i];
1895 /* process the req queue until an uncomplete request */
1896 list_for_each_entry_safe(curr_req, temp_req,
1897 &curr_ep->queue, queue) {
1898 status = process_ep_req(udc, i, curr_req);
1899 if (status)
1900 break;
1901
1902 /* write back status to req */
1903 curr_req->req.status = status;
1904
1905 /* ep0 request completion */
1906 if (ep_num == 0) {
1907 ep0_req_complete(udc, curr_ep, curr_req);
1908 break;
1909 } else {
1910 done(curr_ep, curr_req, status);
1911 }
1912 }
1913 }
1914 }
1915
1916 void irq_process_reset(struct mv_udc *udc)
1917 {
1918 u32 tmp;
1919 unsigned int loops;
1920
1921 udc->ep0_dir = EP_DIR_OUT;
1922 udc->ep0_state = WAIT_FOR_SETUP;
1923 udc->remote_wakeup = 0; /* default to 0 on reset */
1924
1925 /* The address bits are past bit 25-31. Set the address */
1926 tmp = readl(&udc->op_regs->deviceaddr);
1927 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1928 writel(tmp, &udc->op_regs->deviceaddr);
1929
1930 /* Clear all the setup token semaphores */
1931 tmp = readl(&udc->op_regs->epsetupstat);
1932 writel(tmp, &udc->op_regs->epsetupstat);
1933
1934 /* Clear all the endpoint complete status bits */
1935 tmp = readl(&udc->op_regs->epcomplete);
1936 writel(tmp, &udc->op_regs->epcomplete);
1937
1938 /* wait until all endptprime bits cleared */
1939 loops = LOOPS(PRIME_TIMEOUT);
1940 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1941 if (loops == 0) {
1942 dev_err(&udc->dev->dev,
1943 "Timeout for ENDPTPRIME = 0x%x\n",
1944 readl(&udc->op_regs->epprime));
1945 break;
1946 }
1947 loops--;
1948 udelay(LOOPS_USEC);
1949 }
1950
1951 /* Write 1s to the Flush register */
1952 writel((u32)~0, &udc->op_regs->epflush);
1953
1954 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1955 dev_info(&udc->dev->dev, "usb bus reset\n");
1956 udc->usb_state = USB_STATE_DEFAULT;
1957 /* reset all the queues, stop all USB activities */
1958 stop_activity(udc, udc->driver);
1959 } else {
1960 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1961 readl(&udc->op_regs->portsc));
1962
1963 /*
1964 * re-initialize
1965 * controller reset
1966 */
1967 udc_reset(udc);
1968
1969 /* reset all the queues, stop all USB activities */
1970 stop_activity(udc, udc->driver);
1971
1972 /* reset ep0 dQH and endptctrl */
1973 ep0_reset(udc);
1974
1975 /* enable interrupt and set controller to run state */
1976 udc_start(udc);
1977
1978 udc->usb_state = USB_STATE_ATTACHED;
1979 }
1980 }
1981
1982 static void handle_bus_resume(struct mv_udc *udc)
1983 {
1984 udc->usb_state = udc->resume_state;
1985 udc->resume_state = 0;
1986
1987 /* report resume to the driver */
1988 if (udc->driver) {
1989 if (udc->driver->resume) {
1990 spin_unlock(&udc->lock);
1991 udc->driver->resume(&udc->gadget);
1992 spin_lock(&udc->lock);
1993 }
1994 }
1995 }
1996
1997 static void irq_process_suspend(struct mv_udc *udc)
1998 {
1999 udc->resume_state = udc->usb_state;
2000 udc->usb_state = USB_STATE_SUSPENDED;
2001
2002 if (udc->driver->suspend) {
2003 spin_unlock(&udc->lock);
2004 udc->driver->suspend(&udc->gadget);
2005 spin_lock(&udc->lock);
2006 }
2007 }
2008
2009 static void irq_process_port_change(struct mv_udc *udc)
2010 {
2011 u32 portsc;
2012
2013 portsc = readl(&udc->op_regs->portsc[0]);
2014 if (!(portsc & PORTSCX_PORT_RESET)) {
2015 /* Get the speed */
2016 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
2017 switch (speed) {
2018 case PORTSCX_PORT_SPEED_HIGH:
2019 udc->gadget.speed = USB_SPEED_HIGH;
2020 break;
2021 case PORTSCX_PORT_SPEED_FULL:
2022 udc->gadget.speed = USB_SPEED_FULL;
2023 break;
2024 case PORTSCX_PORT_SPEED_LOW:
2025 udc->gadget.speed = USB_SPEED_LOW;
2026 break;
2027 default:
2028 udc->gadget.speed = USB_SPEED_UNKNOWN;
2029 break;
2030 }
2031 }
2032
2033 if (portsc & PORTSCX_PORT_SUSPEND) {
2034 udc->resume_state = udc->usb_state;
2035 udc->usb_state = USB_STATE_SUSPENDED;
2036 if (udc->driver->suspend) {
2037 spin_unlock(&udc->lock);
2038 udc->driver->suspend(&udc->gadget);
2039 spin_lock(&udc->lock);
2040 }
2041 }
2042
2043 if (!(portsc & PORTSCX_PORT_SUSPEND)
2044 && udc->usb_state == USB_STATE_SUSPENDED) {
2045 handle_bus_resume(udc);
2046 }
2047
2048 if (!udc->resume_state)
2049 udc->usb_state = USB_STATE_DEFAULT;
2050 }
2051
2052 static void irq_process_error(struct mv_udc *udc)
2053 {
2054 /* Increment the error count */
2055 udc->errors++;
2056 }
2057
2058 static irqreturn_t mv_udc_irq(int irq, void *dev)
2059 {
2060 struct mv_udc *udc = (struct mv_udc *)dev;
2061 u32 status, intr;
2062
2063 /* Disable ISR when stopped bit is set */
2064 if (udc->stopped)
2065 return IRQ_NONE;
2066
2067 spin_lock(&udc->lock);
2068
2069 status = readl(&udc->op_regs->usbsts);
2070 intr = readl(&udc->op_regs->usbintr);
2071 status &= intr;
2072
2073 if (status == 0) {
2074 spin_unlock(&udc->lock);
2075 return IRQ_NONE;
2076 }
2077
2078 /* Clear all the interrupts occurred */
2079 writel(status, &udc->op_regs->usbsts);
2080
2081 if (status & USBSTS_ERR)
2082 irq_process_error(udc);
2083
2084 if (status & USBSTS_RESET)
2085 irq_process_reset(udc);
2086
2087 if (status & USBSTS_PORT_CHANGE)
2088 irq_process_port_change(udc);
2089
2090 if (status & USBSTS_INT)
2091 irq_process_tr_complete(udc);
2092
2093 if (status & USBSTS_SUSPEND)
2094 irq_process_suspend(udc);
2095
2096 spin_unlock(&udc->lock);
2097
2098 return IRQ_HANDLED;
2099 }
2100
2101 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2102 {
2103 struct mv_udc *udc = (struct mv_udc *)dev;
2104
2105 /* polling VBUS and init phy may cause too much time*/
2106 if (udc->qwork)
2107 queue_work(udc->qwork, &udc->vbus_work);
2108
2109 return IRQ_HANDLED;
2110 }
2111
2112 static void mv_udc_vbus_work(struct work_struct *work)
2113 {
2114 struct mv_udc *udc;
2115 unsigned int vbus;
2116
2117 udc = container_of(work, struct mv_udc, vbus_work);
2118 if (!udc->pdata->vbus)
2119 return;
2120
2121 vbus = udc->pdata->vbus->poll();
2122 dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2123
2124 if (vbus == VBUS_HIGH)
2125 mv_udc_vbus_session(&udc->gadget, 1);
2126 else if (vbus == VBUS_LOW)
2127 mv_udc_vbus_session(&udc->gadget, 0);
2128 }
2129
2130 /* release device structure */
2131 static void gadget_release(struct device *_dev)
2132 {
2133 struct mv_udc *udc = the_controller;
2134
2135 complete(udc->done);
2136 }
2137
2138 static int __devexit mv_udc_remove(struct platform_device *dev)
2139 {
2140 struct mv_udc *udc = the_controller;
2141 int clk_i;
2142
2143 usb_del_gadget_udc(&udc->gadget);
2144
2145 if (udc->qwork) {
2146 flush_workqueue(udc->qwork);
2147 destroy_workqueue(udc->qwork);
2148 }
2149
2150 /*
2151 * If we have transceiver inited,
2152 * then vbus irq will not be requested in udc driver.
2153 */
2154 if (udc->pdata && udc->pdata->vbus
2155 && udc->clock_gating && udc->transceiver == NULL)
2156 free_irq(udc->pdata->vbus->irq, &dev->dev);
2157
2158 /* free memory allocated in probe */
2159 if (udc->dtd_pool)
2160 dma_pool_destroy(udc->dtd_pool);
2161
2162 if (udc->ep_dqh)
2163 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2164 udc->ep_dqh, udc->ep_dqh_dma);
2165
2166 kfree(udc->eps);
2167
2168 if (udc->irq)
2169 free_irq(udc->irq, &dev->dev);
2170
2171 mv_udc_disable(udc);
2172
2173 if (udc->cap_regs)
2174 iounmap(udc->cap_regs);
2175 udc->cap_regs = NULL;
2176
2177 if (udc->phy_regs)
2178 iounmap((void *)udc->phy_regs);
2179 udc->phy_regs = 0;
2180
2181 if (udc->status_req) {
2182 kfree(udc->status_req->req.buf);
2183 kfree(udc->status_req);
2184 }
2185
2186 for (clk_i = 0; clk_i <= udc->clknum; clk_i++)
2187 clk_put(udc->clk[clk_i]);
2188
2189 device_unregister(&udc->gadget.dev);
2190
2191 /* free dev, wait for the release() finished */
2192 wait_for_completion(udc->done);
2193 kfree(udc);
2194
2195 the_controller = NULL;
2196
2197 return 0;
2198 }
2199
2200 static int __devinit mv_udc_probe(struct platform_device *dev)
2201 {
2202 struct mv_usb_platform_data *pdata = dev->dev.platform_data;
2203 struct mv_udc *udc;
2204 int retval = 0;
2205 int clk_i = 0;
2206 struct resource *r;
2207 size_t size;
2208
2209 if (pdata == NULL) {
2210 dev_err(&dev->dev, "missing platform_data\n");
2211 return -ENODEV;
2212 }
2213
2214 size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
2215 udc = kzalloc(size, GFP_KERNEL);
2216 if (udc == NULL) {
2217 dev_err(&dev->dev, "failed to allocate memory for udc\n");
2218 return -ENOMEM;
2219 }
2220
2221 the_controller = udc;
2222 udc->done = &release_done;
2223 udc->pdata = dev->dev.platform_data;
2224 spin_lock_init(&udc->lock);
2225
2226 udc->dev = dev;
2227
2228 #ifdef CONFIG_USB_OTG_UTILS
2229 if (pdata->mode == MV_USB_MODE_OTG)
2230 udc->transceiver = otg_get_transceiver();
2231 #endif
2232
2233 udc->clknum = pdata->clknum;
2234 for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
2235 udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]);
2236 if (IS_ERR(udc->clk[clk_i])) {
2237 retval = PTR_ERR(udc->clk[clk_i]);
2238 goto err_put_clk;
2239 }
2240 }
2241
2242 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2243 if (r == NULL) {
2244 dev_err(&dev->dev, "no I/O memory resource defined\n");
2245 retval = -ENODEV;
2246 goto err_put_clk;
2247 }
2248
2249 udc->cap_regs = (struct mv_cap_regs __iomem *)
2250 ioremap(r->start, resource_size(r));
2251 if (udc->cap_regs == NULL) {
2252 dev_err(&dev->dev, "failed to map I/O memory\n");
2253 retval = -EBUSY;
2254 goto err_put_clk;
2255 }
2256
2257 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2258 if (r == NULL) {
2259 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
2260 retval = -ENODEV;
2261 goto err_iounmap_capreg;
2262 }
2263
2264 udc->phy_regs = (unsigned int)ioremap(r->start, resource_size(r));
2265 if (udc->phy_regs == 0) {
2266 dev_err(&dev->dev, "failed to map phy I/O memory\n");
2267 retval = -EBUSY;
2268 goto err_iounmap_capreg;
2269 }
2270
2271 /* we will acces controller register, so enable the clk */
2272 retval = mv_udc_enable_internal(udc);
2273 if (retval)
2274 goto err_iounmap_phyreg;
2275
2276 udc->op_regs = (struct mv_op_regs __iomem *)((u32)udc->cap_regs
2277 + (readl(&udc->cap_regs->caplength_hciversion)
2278 & CAPLENGTH_MASK));
2279 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2280
2281 /*
2282 * some platform will use usb to download image, it may not disconnect
2283 * usb gadget before loading kernel. So first stop udc here.
2284 */
2285 udc_stop(udc);
2286 writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2287
2288 size = udc->max_eps * sizeof(struct mv_dqh) *2;
2289 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2290 udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
2291 &udc->ep_dqh_dma, GFP_KERNEL);
2292
2293 if (udc->ep_dqh == NULL) {
2294 dev_err(&dev->dev, "allocate dQH memory failed\n");
2295 retval = -ENOMEM;
2296 goto err_disable_clock;
2297 }
2298 udc->ep_dqh_size = size;
2299
2300 /* create dTD dma_pool resource */
2301 udc->dtd_pool = dma_pool_create("mv_dtd",
2302 &dev->dev,
2303 sizeof(struct mv_dtd),
2304 DTD_ALIGNMENT,
2305 DMA_BOUNDARY);
2306
2307 if (!udc->dtd_pool) {
2308 retval = -ENOMEM;
2309 goto err_free_dma;
2310 }
2311
2312 size = udc->max_eps * sizeof(struct mv_ep) *2;
2313 udc->eps = kzalloc(size, GFP_KERNEL);
2314 if (udc->eps == NULL) {
2315 dev_err(&dev->dev, "allocate ep memory failed\n");
2316 retval = -ENOMEM;
2317 goto err_destroy_dma;
2318 }
2319
2320 /* initialize ep0 status request structure */
2321 udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2322 if (!udc->status_req) {
2323 dev_err(&dev->dev, "allocate status_req memory failed\n");
2324 retval = -ENOMEM;
2325 goto err_free_eps;
2326 }
2327 INIT_LIST_HEAD(&udc->status_req->queue);
2328
2329 /* allocate a small amount of memory to get valid address */
2330 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2331 udc->status_req->req.dma = DMA_ADDR_INVALID;
2332
2333 udc->resume_state = USB_STATE_NOTATTACHED;
2334 udc->usb_state = USB_STATE_POWERED;
2335 udc->ep0_dir = EP_DIR_OUT;
2336 udc->remote_wakeup = 0;
2337
2338 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2339 if (r == NULL) {
2340 dev_err(&dev->dev, "no IRQ resource defined\n");
2341 retval = -ENODEV;
2342 goto err_free_status_req;
2343 }
2344 udc->irq = r->start;
2345 if (request_irq(udc->irq, mv_udc_irq,
2346 IRQF_SHARED, driver_name, udc)) {
2347 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2348 udc->irq);
2349 retval = -ENODEV;
2350 goto err_free_status_req;
2351 }
2352
2353 /* initialize gadget structure */
2354 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2355 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2356 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2357 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
2358 udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2359
2360 /* the "gadget" abstracts/virtualizes the controller */
2361 dev_set_name(&udc->gadget.dev, "gadget");
2362 udc->gadget.dev.parent = &dev->dev;
2363 udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2364 udc->gadget.dev.release = gadget_release;
2365 udc->gadget.name = driver_name; /* gadget name */
2366
2367 retval = device_register(&udc->gadget.dev);
2368 if (retval)
2369 goto err_free_irq;
2370
2371 eps_init(udc);
2372
2373 /* VBUS detect: we can disable/enable clock on demand.*/
2374 if (udc->transceiver)
2375 udc->clock_gating = 1;
2376 else if (pdata->vbus) {
2377 udc->clock_gating = 1;
2378 retval = request_threaded_irq(pdata->vbus->irq, NULL,
2379 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2380 if (retval) {
2381 dev_info(&dev->dev,
2382 "Can not request irq for VBUS, "
2383 "disable clock gating\n");
2384 udc->clock_gating = 0;
2385 }
2386
2387 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2388 if (!udc->qwork) {
2389 dev_err(&dev->dev, "cannot create workqueue\n");
2390 retval = -ENOMEM;
2391 goto err_unregister;
2392 }
2393
2394 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2395 }
2396
2397 /*
2398 * When clock gating is supported, we can disable clk and phy.
2399 * If not, it means that VBUS detection is not supported, we
2400 * have to enable vbus active all the time to let controller work.
2401 */
2402 if (udc->clock_gating)
2403 mv_udc_disable_internal(udc);
2404 else
2405 udc->vbus_active = 1;
2406
2407 retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
2408 if (retval)
2409 goto err_unregister;
2410
2411 dev_info(&dev->dev, "successful probe UDC device %s clock gating.\n",
2412 udc->clock_gating ? "with" : "without");
2413
2414 return 0;
2415
2416 err_unregister:
2417 if (udc->pdata && udc->pdata->vbus
2418 && udc->clock_gating && udc->transceiver == NULL)
2419 free_irq(pdata->vbus->irq, &dev->dev);
2420 device_unregister(&udc->gadget.dev);
2421 err_free_irq:
2422 free_irq(udc->irq, &dev->dev);
2423 err_free_status_req:
2424 kfree(udc->status_req->req.buf);
2425 kfree(udc->status_req);
2426 err_free_eps:
2427 kfree(udc->eps);
2428 err_destroy_dma:
2429 dma_pool_destroy(udc->dtd_pool);
2430 err_free_dma:
2431 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2432 udc->ep_dqh, udc->ep_dqh_dma);
2433 err_disable_clock:
2434 mv_udc_disable_internal(udc);
2435 err_iounmap_phyreg:
2436 iounmap((void *)udc->phy_regs);
2437 err_iounmap_capreg:
2438 iounmap(udc->cap_regs);
2439 err_put_clk:
2440 for (clk_i--; clk_i >= 0; clk_i--)
2441 clk_put(udc->clk[clk_i]);
2442 the_controller = NULL;
2443 kfree(udc);
2444 return retval;
2445 }
2446
2447 #ifdef CONFIG_PM
2448 static int mv_udc_suspend(struct device *_dev)
2449 {
2450 struct mv_udc *udc = the_controller;
2451
2452 /* if OTG is enabled, the following will be done in OTG driver*/
2453 if (udc->transceiver)
2454 return 0;
2455
2456 if (udc->pdata->vbus && udc->pdata->vbus->poll)
2457 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2458 dev_info(&udc->dev->dev, "USB cable is connected!\n");
2459 return -EAGAIN;
2460 }
2461
2462 /*
2463 * only cable is unplugged, udc can suspend.
2464 * So do not care about clock_gating == 1.
2465 */
2466 if (!udc->clock_gating) {
2467 udc_stop(udc);
2468
2469 spin_lock_irq(&udc->lock);
2470 /* stop all usb activities */
2471 stop_activity(udc, udc->driver);
2472 spin_unlock_irq(&udc->lock);
2473
2474 mv_udc_disable_internal(udc);
2475 }
2476
2477 return 0;
2478 }
2479
2480 static int mv_udc_resume(struct device *_dev)
2481 {
2482 struct mv_udc *udc = the_controller;
2483 int retval;
2484
2485 /* if OTG is enabled, the following will be done in OTG driver*/
2486 if (udc->transceiver)
2487 return 0;
2488
2489 if (!udc->clock_gating) {
2490 retval = mv_udc_enable_internal(udc);
2491 if (retval)
2492 return retval;
2493
2494 if (udc->driver && udc->softconnect) {
2495 udc_reset(udc);
2496 ep0_reset(udc);
2497 udc_start(udc);
2498 }
2499 }
2500
2501 return 0;
2502 }
2503
2504 static const struct dev_pm_ops mv_udc_pm_ops = {
2505 .suspend = mv_udc_suspend,
2506 .resume = mv_udc_resume,
2507 };
2508 #endif
2509
2510 static void mv_udc_shutdown(struct platform_device *dev)
2511 {
2512 struct mv_udc *udc = the_controller;
2513 u32 mode;
2514
2515 /* reset controller mode to IDLE */
2516 mode = readl(&udc->op_regs->usbmode);
2517 mode &= ~3;
2518 writel(mode, &udc->op_regs->usbmode);
2519 }
2520
2521 static struct platform_driver udc_driver = {
2522 .probe = mv_udc_probe,
2523 .remove = __exit_p(mv_udc_remove),
2524 .shutdown = mv_udc_shutdown,
2525 .driver = {
2526 .owner = THIS_MODULE,
2527 .name = "pxa-u2o",
2528 #ifdef CONFIG_PM
2529 .pm = &mv_udc_pm_ops,
2530 #endif
2531 },
2532 };
2533 MODULE_ALIAS("platform:pxa-u2o");
2534
2535 MODULE_DESCRIPTION(DRIVER_DESC);
2536 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2537 MODULE_VERSION(DRIVER_VERSION);
2538 MODULE_LICENSE("GPL");
2539
2540
2541 static int __init init(void)
2542 {
2543 return platform_driver_register(&udc_driver);
2544 }
2545 module_init(init);
2546
2547
2548 static void __exit cleanup(void)
2549 {
2550 platform_driver_unregister(&udc_driver);
2551 }
2552 module_exit(cleanup);
2553
Linux kernel - Deliverables
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