drivers/usb/gadget/pxa27x_udc.h

   1 /*
   2  * linux/drivers/usb/gadget/pxa27x_udc.h
   3  * Intel PXA27x on-chip full speed USB device controller
   4  *
   5  * Inspired by original driver by Frank Becker, David Brownell, and others.
   6  * Copyright (C) 2008 Robert Jarzmik
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #ifndef __LINUX_USB_GADGET_PXA27X_H
  24 #define __LINUX_USB_GADGET_PXA27X_H
  25
  26 #include <linux/types.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/io.h>
  29
  30 /*
  31  * Register definitions
  32  */
  33 /* Offsets */
  34 #define UDCCR           0x0000          /* UDC Control Register */
  35 #define UDCICR0         0x0004          /* UDC Interrupt Control Register0 */
  36 #define UDCICR1         0x0008          /* UDC Interrupt Control Register1 */
  37 #define UDCISR0         0x000C          /* UDC Interrupt Status Register 0 */
  38 #define UDCISR1         0x0010          /* UDC Interrupt Status Register 1 */
  39 #define UDCFNR          0x0014          /* UDC Frame Number Register */
  40 #define UDCOTGICR       0x0018          /* UDC On-The-Go interrupt control */
  41 #define UP2OCR          0x0020          /* USB Port 2 Output Control register */
  42 #define UP3OCR          0x0024          /* USB Port 3 Output Control register */
  43 #define UDCCSRn(x)      (0x0100 + ((x)<<2)) /* UDC Control/Status register */
  44 #define UDCBCRn(x)      (0x0200 + ((x)<<2)) /* UDC Byte Count Register */
  45 #define UDCDRn(x)       (0x0300 + ((x)<<2)) /* UDC Data Register  */
  46 #define UDCCRn(x)       (0x0400 + ((x)<<2)) /* UDC Control Register */
  47
  48 #define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
  49 #define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
  50                                            Protocol Port Support */
  51 #define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
  52                                            Support */
  53 #define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
  54                                            Enable */
  55 #define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
  56 #define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
  57 #define UDCCR_ACN_S     11
  58 #define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
  59 #define UDCCR_AIN_S     8
  60 #define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
  61                                            Setting Number */
  62 #define UDCCR_AAISN_S   5
  63 #define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
  64                                            Configuration */
  65 #define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
  66                                            Error */
  67 #define UDCCR_UDR       (1 << 2)        /* UDC Resume */
  68 #define UDCCR_UDA       (1 << 1)        /* UDC Active */
  69 #define UDCCR_UDE       (1 << 0)        /* UDC Enable */
  70
  71 #define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
  72 #define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
  73 #define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
  74 #define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
  75 #define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
  76 #define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
  77 #define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
  78 #define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
  79 #define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
  80
  81 #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
  82 #define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
  83 #define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
  84 #define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
  85 #define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
  86 #define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
  87 #define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
  88
  89 #define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
  90 #define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
  91                                            Rising Edge Interrupt Enable */
  92 #define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
  93                                            Falling Edge Interrupt Enable */
  94 #define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
  95                                            Interrupt Enable */
  96 #define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
  97                                            Interrupt Enable */
  98 #define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
  99                                            Interrupt Enable */
 100 #define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
 101                                            Interrupt Enable */
 102 #define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
 103                                            Interrupt Enable */
 104 #define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
 105                                            Interrupt Enable */
 106 #define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
 107                                            Edge Interrupt Enable */
 108 #define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
 109                                            Edge Interrupt Enable */
 110 #define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
 111                                            Interrupt Enable */
 112 #define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
 113                                            Interrupt Enable */
 114
 115 /* Host Port 2 field bits */
 116 #define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
 117 #define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
 118                                         /* Transceiver enablers */
 119 #define UP2OCR_DPPDE    (1 << 2)        /*   D+ Pull Down Enable */
 120 #define UP2OCR_DMPDE    (1 << 3)        /*   D- Pull Down Enable */
 121 #define UP2OCR_DPPUE    (1 << 4)        /*   D+ Pull Up Enable */
 122 #define UP2OCR_DMPUE    (1 << 5)        /*   D- Pull Up Enable */
 123 #define UP2OCR_DPPUBE   (1 << 6)        /*   D+ Pull Up Bypass Enable */
 124 #define UP2OCR_DMPUBE   (1 << 7)        /*   D- Pull Up Bypass Enable */
 125 #define UP2OCR_EXSP     (1 << 8)        /* External Transceiver Speed Control */
 126 #define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
 127 #define UP2OCR_IDON     (1 << 10)       /* OTG ID Read Enable */
 128 #define UP2OCR_HXS      (1 << 16)       /* Transceiver Output Select */
 129 #define UP2OCR_HXOE     (1 << 17)       /* Transceiver Output Enable */
 130 #define UP2OCR_SEOS     (1 << 24)       /* Single-Ended Output Select */
 131
 132 #define UDCCSR0_SA      (1 << 7)        /* Setup Active */
 133 #define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
 134 #define UDCCSR0_FST     (1 << 5)        /* Force Stall */
 135 #define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
 136 #define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
 137 #define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
 138 #define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
 139 #define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
 140
 141 #define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
 142 #define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
 143 #define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
 144 #define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
 145 #define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
 146 #define UDCCSR_FST      (1 << 5)        /* Force STALL */
 147 #define UDCCSR_SST      (1 << 4)        /* Sent STALL */
 148 #define UDCCSR_DME      (1 << 3)        /* DMA Enable */
 149 #define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
 150 #define UDCCSR_PC       (1 << 1)        /* Packet Complete */
 151 #define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
 152
 153 #define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
 154 #define UDCCONR_CN_S    25
 155 #define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
 156 #define UDCCONR_IN_S    22
 157 #define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
 158 #define UDCCONR_AISN_S  19
 159 #define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
 160 #define UDCCONR_EN_S    15
 161 #define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
 162 #define UDCCONR_ET_S    13
 163 #define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
 164 #define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
 165 #define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
 166 #define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
 167 #define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
 168 #define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
 169 #define UDCCONR_MPS_S   2
 170 #define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
 171 #define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
 172
 173 #define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE)
 174 #define UDCCSR_WR_MASK  (UDCCSR_DME | UDCCSR_FST)
 175 #define UDC_FNR_MASK    (0x7ff)
 176 #define UDC_BCR_MASK    (0x3ff)
 177
 178 /*
 179  * UDCCR = UDC Endpoint Configuration Registers
 180  * UDCCSR = UDC Control/Status Register for this EP
 181  * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo)
 182  * UDCDR = UDC Endpoint Data Register (the fifo)
 183  */
 184 #define ofs_UDCCR(ep)   (UDCCRn(ep->idx))
 185 #define ofs_UDCCSR(ep)  (UDCCSRn(ep->idx))
 186 #define ofs_UDCBCR(ep)  (UDCBCRn(ep->idx))
 187 #define ofs_UDCDR(ep)   (UDCDRn(ep->idx))
 188
 189 /* Register access macros */
 190 #define udc_ep_readl(ep, reg)   \
 191         __raw_readl((ep)->dev->regs + ofs_##reg(ep))
 192 #define udc_ep_writel(ep, reg, value)   \
 193         __raw_writel((value), ep->dev->regs + ofs_##reg(ep))
 194 #define udc_ep_readb(ep, reg)   \
 195         __raw_readb((ep)->dev->regs + ofs_##reg(ep))
 196 #define udc_ep_writeb(ep, reg, value)   \
 197         __raw_writeb((value), ep->dev->regs + ofs_##reg(ep))
 198 #define udc_readl(dev, reg)     \
 199         __raw_readl((dev)->regs + (reg))
 200 #define udc_writel(udc, reg, value)     \
 201         __raw_writel((value), (udc)->regs + (reg))
 202
 203 #define UDCCSR_MASK             (UDCCSR_FST | UDCCSR_DME)
 204 #define UDCCISR0_EP_MASK        ~0
 205 #define UDCCISR1_EP_MASK        0xffff
 206 #define UDCCSR0_CTRL_REQ_MASK   (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)
 207
 208 #define EPIDX(ep)       (ep->idx)
 209 #define EPADDR(ep)      (ep->addr)
 210 #define EPXFERTYPE(ep)  (ep->type)
 211 #define EPNAME(ep)      (ep->name)
 212 #define is_ep0(ep)      (!ep->idx)
 213 #define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC)
 214
 215 /*
 216  * Endpoint definitions
 217  *
 218  * Once enabled, pxa endpoint configuration is freezed, and cannot change
 219  * unless a reset happens or the udc is disabled.
 220  * Therefore, we must define all pxa potential endpoint definitions needed for
 221  * all gadget and set them up before the udc is enabled.
 222  *
 223  * As the architecture chosen is fully static, meaning the pxa endpoint
 224  * configurations are set up once and for all, we must provide a way to match
 225  * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget
 226  * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt)
 227  * criteria, while the pxa architecture requires that.
 228  *
 229  * The solution is to define several pxa endpoints matching one usb_ep. Ex:
 230  *   - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when
 231  *     the udc talks on (config=3, interface=0, alt=0)
 232  *   - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when
 233  *     the udc talks on (config=3, interface=0, alt=1)
 234  *   - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when
 235  *     the udc talks on (config=2, interface=0, alt=0)
 236  *
 237  * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...)
 238  */
 239
 240 /*
 241  * Endpoint definition helpers
 242  */
 243 #define USB_EP_DEF(addr, bname, dir, type, maxpkt) \
 244 { .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \
 245   .desc = {     .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \
 246                 .bmAttributes = type, \
 247                 .wMaxPacketSize = maxpkt, }, \
 248   .dev = &memory \
 249 }
 250 #define USB_EP_BULK(addr, bname, dir) \
 251   USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE)
 252 #define USB_EP_ISO(addr, bname, dir) \
 253   USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE)
 254 #define USB_EP_INT(addr, bname, dir) \
 255   USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE)
 256 #define USB_EP_IN_BULK(n)       USB_EP_BULK(n, "ep" #n "in-bulk", 1)
 257 #define USB_EP_OUT_BULK(n)      USB_EP_BULK(n, "ep" #n "out-bulk", 0)
 258 #define USB_EP_IN_ISO(n)        USB_EP_ISO(n,  "ep" #n "in-iso", 1)
 259 #define USB_EP_OUT_ISO(n)       USB_EP_ISO(n,  "ep" #n "out-iso", 0)
 260 #define USB_EP_IN_INT(n)        USB_EP_INT(n,  "ep" #n "in-int", 1)
 261 #define USB_EP_CTRL             USB_EP_DEF(0,  "ep0", 0, 0, EP0_FIFO_SIZE)
 262
 263 #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \
 264 { \
 265         .dev = &memory, \
 266         .name = "ep" #_idx, \
 267         .idx = _idx, .enabled = 0, \
 268         .dir_in = dir, .addr = _addr, \
 269         .config = _config, .interface = iface, .alternate = altset, \
 270         .type = _type, .fifo_size = maxpkt, \
 271 }
 272 #define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \
 273   PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \
 274                 config, iface, alt)
 275 #define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \
 276   PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \
 277                 config, iface, alt)
 278 #define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \
 279   PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \
 280                 config, iface, alt)
 281 #define PXA_EP_IN_BULK(i, adr, c, f, a)         PXA_EP_BULK(i, adr, 1, c, f, a)
 282 #define PXA_EP_OUT_BULK(i, adr, c, f, a)        PXA_EP_BULK(i, adr, 0, c, f, a)
 283 #define PXA_EP_IN_ISO(i, adr, c, f, a)          PXA_EP_ISO(i, adr, 1, c, f, a)
 284 #define PXA_EP_OUT_ISO(i, adr, c, f, a)         PXA_EP_ISO(i, adr, 0, c, f, a)
 285 #define PXA_EP_IN_INT(i, adr, c, f, a)          PXA_EP_INT(i, adr, 1, c, f, a)
 286 #define PXA_EP_CTRL     PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0)
 287
 288 struct pxa27x_udc;
 289
 290 struct stats {
 291         unsigned long in_ops;
 292         unsigned long out_ops;
 293         unsigned long in_bytes;
 294         unsigned long out_bytes;
 295         unsigned long irqs;
 296 };
 297
 298 /**
 299  * struct udc_usb_ep - container of each usb_ep structure
 300  * @usb_ep: usb endpoint
 301  * @desc: usb descriptor, especially type and address
 302  * @dev: udc managing this endpoint
 303  * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call)
 304  */
 305 struct udc_usb_ep {
 306         struct usb_ep usb_ep;
 307         struct usb_endpoint_descriptor desc;
 308         struct pxa_udc *dev;
 309         struct pxa_ep *pxa_ep;
 310 };
 311
 312 /**
 313  * struct pxa_ep - pxa endpoint
 314  * @dev: udc device
 315  * @queue: requests queue
 316  * @lock: lock to pxa_ep data (queues and stats)
 317  * @enabled: true when endpoint enabled (not stopped by gadget layer)
 318  * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX)
 319  * @name: endpoint name (for trace/debug purpose)
 320  * @dir_in: 1 if IN endpoint, 0 if OUT endpoint
 321  * @addr: usb endpoint number
 322  * @config: configuration in which this endpoint is active
 323  * @interface: interface in which this endpoint is active
 324  * @alternate: altsetting in which this endpoitn is active
 325  * @fifo_size: max packet size in the endpoint fifo
 326  * @type: endpoint type (bulk, iso, int, ...)
 327  * @udccsr_value: save register of UDCCSR0 for suspend/resume
 328  * @udccr_value: save register of UDCCR for suspend/resume
 329  * @stats: endpoint statistics
 330  *
 331  * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned
 332  * (cares about config/interface/altsetting, thus placing needless limits on
 333  * device capability) and full of implementation bugs forcing it to be set up
 334  * for use more or less like a pxa255.
 335  *
 336  * As we define the pxa_ep statically, we must guess all needed pxa_ep for all
 337  * gadget which may work with this udc driver.
 338  */
 339 struct pxa_ep {
 340         struct pxa_udc          *dev;
 341
 342         struct list_head        queue;
 343         spinlock_t              lock;           /* Protects this structure */
 344                                                 /* (queues, stats) */
 345         unsigned                enabled:1;
 346
 347         unsigned                idx:5;
 348         char                    *name;
 349
 350         /*
 351          * Specific pxa endpoint data, needed for hardware initialization
 352          */
 353         unsigned                dir_in:1;
 354         unsigned                addr:3;
 355         unsigned                config:2;
 356         unsigned                interface:3;
 357         unsigned                alternate:3;
 358         unsigned                fifo_size;
 359         unsigned                type;
 360
 361 #ifdef CONFIG_PM
 362         u32                     udccsr_value;
 363         u32                     udccr_value;
 364 #endif
 365         struct stats            stats;
 366 };
 367
 368 /**
 369  * struct pxa27x_request - container of each usb_request structure
 370  * @req: usb request
 371  * @udc_usb_ep: usb endpoint the request was submitted on
 372  * @in_use: sanity check if request already queued on an pxa_ep
 373  * @queue: linked list of requests, linked on pxa_ep->queue
 374  */
 375 struct pxa27x_request {
 376         struct usb_request                      req;
 377         struct udc_usb_ep                       *udc_usb_ep;
 378         unsigned                                in_use:1;
 379         struct list_head                        queue;
 380 };
 381
 382 enum ep0_state {
 383         WAIT_FOR_SETUP,
 384         SETUP_STAGE,
 385         IN_DATA_STAGE,
 386         OUT_DATA_STAGE,
 387         IN_STATUS_STAGE,
 388         OUT_STATUS_STAGE,
 389         STALL,
 390         WAIT_ACK_SET_CONF_INTERF
 391 };
 392
 393 static char *ep0_state_name[] = {
 394         "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE",
 395         "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL",
 396         "WAIT_ACK_SET_CONF_INTERF"
 397 };
 398 #define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
 399
 400 #define EP0_FIFO_SIZE   16U
 401 #define BULK_FIFO_SIZE  64U
 402 #define ISO_FIFO_SIZE   256U
 403 #define INT_FIFO_SIZE   16U
 404
 405 struct udc_stats {
 406         unsigned long   irqs_reset;
 407         unsigned long   irqs_suspend;
 408         unsigned long   irqs_resume;
 409         unsigned long   irqs_reconfig;
 410 };
 411
 412 #define NR_USB_ENDPOINTS (1 + 5)        /* ep0 + ep1in-bulk + .. + ep3in-iso */
 413 #define NR_PXA_ENDPOINTS (1 + 14)       /* ep0 + epA + epB + .. + epX */
 414
 415 /**
 416  * struct pxa_udc - udc structure
 417  * @regs: mapped IO space
 418  * @irq: udc irq
 419  * @clk: udc clock
 420  * @usb_gadget: udc gadget structure
 421  * @driver: bound gadget (zero, g_ether, g_file_storage, ...)
 422  * @dev: device
 423  * @mach: machine info, used to activate specific GPIO
 424  * @ep0state: control endpoint state machine state
 425  * @stats: statistics on udc usage
 426  * @udc_usb_ep: array of usb endpoints offered by the gadget
 427  * @pxa_ep: array of pxa available endpoints
 428  * @config: UDC active configuration
 429  * @last_interface: UDC interface of the last SET_INTERFACE host request
 430  * @last_alternate: UDC altsetting of the last SET_INTERFACE host request
 431  * @udccsr0: save of udccsr0 in case of suspend
 432  * @debugfs_root: root entry of debug filesystem
 433  * @debugfs_state: debugfs entry for "udcstate"
 434  * @debugfs_queues: debugfs entry for "queues"
 435  * @debugfs_eps: debugfs entry for "epstate"
 436  */
 437 struct pxa_udc {
 438         void __iomem                            *regs;
 439         int                                     irq;
 440         struct clk                              *clk;
 441
 442         struct usb_gadget                       gadget;
 443         struct usb_gadget_driver                *driver;
 444         struct device                           *dev;
 445         struct pxa2xx_udc_mach_info             *mach;
 446
 447         enum ep0_state                          ep0state;
 448         struct udc_stats                        stats;
 449
 450         struct udc_usb_ep                       udc_usb_ep[NR_USB_ENDPOINTS];
 451         struct pxa_ep                           pxa_ep[NR_PXA_ENDPOINTS];
 452
 453         unsigned                                config:2;
 454         unsigned                                last_interface:3;
 455         unsigned                                last_alternate:3;
 456
 457 #ifdef CONFIG_PM
 458         unsigned                                udccsr0;
 459 #endif
 460 #ifdef CONFIG_USB_GADGET_DEBUG_FS
 461         struct dentry                           *debugfs_root;
 462         struct dentry                           *debugfs_state;
 463         struct dentry                           *debugfs_queues;
 464         struct dentry                           *debugfs_eps;
 465 #endif
 466 };
 467
 468 static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
 469 {
 470         return container_of(gadget, struct pxa_udc, gadget);
 471 }
 472
 473 /*
 474  * Debugging/message support
 475  */
 476 #define ep_dbg(ep, fmt, arg...) \
 477         dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
 478 #define ep_vdbg(ep, fmt, arg...) \
 479         dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
 480 #define ep_err(ep, fmt, arg...) \
 481         dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
 482 #define ep_info(ep, fmt, arg...) \
 483         dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
 484 #define ep_warn(ep, fmt, arg...) \
 485         dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
 486
 487 #endif /* __LINUX_USB_GADGET_PXA27X_H */