2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/of_platform.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
41 #include "s3c-hsotg.h"
43 static const char * const s3c_hsotg_supply_names
[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
51 * Unfortunately there seems to be a limit of the amount of data that can
52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
53 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * This means if we are wanting to move >127 bytes of data, we need to
57 * split the transactions up, but just doing one packet at a time does
58 * not work (this may be an implicit DATA0 PID on first packet of the
59 * transaction) and doing 2 packets is outside the controller's limits.
61 * If we try to lower the MPS size for EP0, then no transfers work properly
62 * for EP0, and the system will fail basic enumeration. As no cause for this
63 * has currently been found, we cannot support any large IN transfers for
66 #define EP0_MPS_LIMIT 64
72 * struct s3c_hsotg_ep - driver endpoint definition.
73 * @ep: The gadget layer representation of the endpoint.
74 * @name: The driver generated name for the endpoint.
75 * @queue: Queue of requests for this endpoint.
76 * @parent: Reference back to the parent device structure.
77 * @req: The current request that the endpoint is processing. This is
78 * used to indicate an request has been loaded onto the endpoint
79 * and has yet to be completed (maybe due to data move, or simply
80 * awaiting an ack from the core all the data has been completed).
81 * @debugfs: File entry for debugfs file for this endpoint.
82 * @lock: State lock to protect contents of endpoint.
83 * @dir_in: Set to true if this endpoint is of the IN direction, which
84 * means that it is sending data to the Host.
85 * @index: The index for the endpoint registers.
86 * @mc: Multi Count - number of transactions per microframe
87 * @interval - Interval for periodic endpoints
88 * @name: The name array passed to the USB core.
89 * @halted: Set if the endpoint has been halted.
90 * @periodic: Set if this is a periodic ep, such as Interrupt
91 * @isochronous: Set if this is a isochronous ep
92 * @sent_zlp: Set if we've sent a zero-length packet.
93 * @total_data: The total number of data bytes done.
94 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
95 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
96 * @last_load: The offset of data for the last start of request.
97 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
99 * This is the driver's state for each registered enpoint, allowing it
100 * to keep track of transactions that need doing. Each endpoint has a
101 * lock to protect the state, to try and avoid using an overall lock
102 * for the host controller as much as possible.
104 * For periodic IN endpoints, we have fifo_size and fifo_load to try
105 * and keep track of the amount of data in the periodic FIFO for each
106 * of these as we don't have a status register that tells us how much
107 * is in each of them. (note, this may actually be useless information
108 * as in shared-fifo mode periodic in acts like a single-frame packet
109 * buffer than a fifo)
111 struct s3c_hsotg_ep
{
113 struct list_head queue
;
114 struct s3c_hsotg
*parent
;
115 struct s3c_hsotg_req
*req
;
116 struct dentry
*debugfs
;
119 unsigned long total_data
;
120 unsigned int size_loaded
;
121 unsigned int last_load
;
122 unsigned int fifo_load
;
123 unsigned short fifo_size
;
125 unsigned char dir_in
;
128 unsigned char interval
;
130 unsigned int halted
:1;
131 unsigned int periodic
:1;
132 unsigned int isochronous
:1;
133 unsigned int sent_zlp
:1;
139 * struct s3c_hsotg - driver state.
140 * @dev: The parent device supplied to the probe function
141 * @driver: USB gadget driver
142 * @phy: The otg phy transceiver structure for phy control.
143 * @plat: The platform specific configuration data. This can be removed once
144 * all SoCs support usb transceiver.
145 * @regs: The memory area mapped for accessing registers.
146 * @irq: The IRQ number we are using
147 * @supplies: Definition of USB power supplies
148 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
149 * @num_of_eps: Number of available EPs (excluding EP0)
150 * @debug_root: root directrory for debugfs.
151 * @debug_file: main status file for debugfs.
152 * @debug_fifo: FIFO status file for debugfs.
153 * @ep0_reply: Request used for ep0 reply.
154 * @ep0_buff: Buffer for EP0 reply data, if needed.
155 * @ctrl_buff: Buffer for EP0 control requests.
156 * @ctrl_req: Request for EP0 control packets.
157 * @setup: NAK management for EP0 SETUP
158 * @last_rst: Time of last reset
159 * @eps: The endpoints being supplied to the gadget framework
163 struct usb_gadget_driver
*driver
;
165 struct s3c_hsotg_plat
*plat
;
173 struct regulator_bulk_data supplies
[ARRAY_SIZE(s3c_hsotg_supply_names
)];
175 unsigned int dedicated_fifos
:1;
176 unsigned char num_of_eps
;
178 struct dentry
*debug_root
;
179 struct dentry
*debug_file
;
180 struct dentry
*debug_fifo
;
182 struct usb_request
*ep0_reply
;
183 struct usb_request
*ctrl_req
;
187 struct usb_gadget gadget
;
189 unsigned long last_rst
;
190 struct s3c_hsotg_ep
*eps
;
194 * struct s3c_hsotg_req - data transfer request
195 * @req: The USB gadget request
196 * @queue: The list of requests for the endpoint this is queued for.
197 * @in_progress: Has already had size/packets written to core
198 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
200 struct s3c_hsotg_req
{
201 struct usb_request req
;
202 struct list_head queue
;
203 unsigned char in_progress
;
204 unsigned char mapped
;
207 /* conversion functions */
208 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
210 return container_of(req
, struct s3c_hsotg_req
, req
);
213 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
215 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
218 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
220 return container_of(gadget
, struct s3c_hsotg
, gadget
);
223 static inline void __orr32(void __iomem
*ptr
, u32 val
)
225 writel(readl(ptr
) | val
, ptr
);
228 static inline void __bic32(void __iomem
*ptr
, u32 val
)
230 writel(readl(ptr
) & ~val
, ptr
);
233 /* forward decleration of functions */
234 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
237 * using_dma - return the DMA status of the driver.
238 * @hsotg: The driver state.
240 * Return true if we're using DMA.
242 * Currently, we have the DMA support code worked into everywhere
243 * that needs it, but the AMBA DMA implementation in the hardware can
244 * only DMA from 32bit aligned addresses. This means that gadgets such
245 * as the CDC Ethernet cannot work as they often pass packets which are
248 * Unfortunately the choice to use DMA or not is global to the controller
249 * and seems to be only settable when the controller is being put through
250 * a core reset. This means we either need to fix the gadgets to take
251 * account of DMA alignment, or add bounce buffers (yuerk).
253 * Until this issue is sorted out, we always return 'false'.
255 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
257 return false; /* support is not complete */
261 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
262 * @hsotg: The device state
263 * @ints: A bitmask of the interrupts to enable
265 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
267 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
270 new_gsintmsk
= gsintmsk
| ints
;
272 if (new_gsintmsk
!= gsintmsk
) {
273 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
274 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
279 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
280 * @hsotg: The device state
281 * @ints: A bitmask of the interrupts to enable
283 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
285 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
288 new_gsintmsk
= gsintmsk
& ~ints
;
290 if (new_gsintmsk
!= gsintmsk
)
291 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
295 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
296 * @hsotg: The device state
297 * @ep: The endpoint index
298 * @dir_in: True if direction is in.
299 * @en: The enable value, true to enable
301 * Set or clear the mask for an individual endpoint's interrupt
304 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
305 unsigned int ep
, unsigned int dir_in
,
315 local_irq_save(flags
);
316 daint
= readl(hsotg
->regs
+ DAINTMSK
);
321 writel(daint
, hsotg
->regs
+ DAINTMSK
);
322 local_irq_restore(flags
);
326 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
327 * @hsotg: The device instance.
329 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
337 /* set FIFO sizes to 2048/1024 */
339 writel(2048, hsotg
->regs
+ GRXFSIZ
);
340 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
341 GNPTXFSIZ_NPTxFDep(1024),
342 hsotg
->regs
+ GNPTXFSIZ
);
345 * arange all the rest of the TX FIFOs, as some versions of this
346 * block have overlapping default addresses. This also ensures
347 * that if the settings have been changed, then they are set to
351 /* start at the end of the GNPTXFSIZ, rounded up */
356 * currently we allocate TX FIFOs for all possible endpoints,
357 * and assume that they are all the same size.
360 for (ep
= 1; ep
<= 15; ep
++) {
362 val
|= size
<< DPTXFSIZn_DPTxFSize_SHIFT
;
365 writel(val
, hsotg
->regs
+ DPTXFSIZn(ep
));
369 * according to p428 of the design guide, we need to ensure that
370 * all fifos are flushed before continuing
373 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh
|
374 GRSTCTL_RxFFlsh
, hsotg
->regs
+ GRSTCTL
);
376 /* wait until the fifos are both flushed */
379 val
= readl(hsotg
->regs
+ GRSTCTL
);
381 if ((val
& (GRSTCTL_TxFFlsh
| GRSTCTL_RxFFlsh
)) == 0)
384 if (--timeout
== 0) {
386 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
393 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
397 * @ep: USB endpoint to allocate request for.
398 * @flags: Allocation flags
400 * Allocate a new USB request structure appropriate for the specified endpoint
402 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
405 struct s3c_hsotg_req
*req
;
407 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
411 INIT_LIST_HEAD(&req
->queue
);
417 * is_ep_periodic - return true if the endpoint is in periodic mode.
418 * @hs_ep: The endpoint to query.
420 * Returns true if the endpoint is in periodic mode, meaning it is being
421 * used for an Interrupt or ISO transfer.
423 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
425 return hs_ep
->periodic
;
429 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
430 * @hsotg: The device state.
431 * @hs_ep: The endpoint for the request
432 * @hs_req: The request being processed.
434 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
435 * of a request to ensure the buffer is ready for access by the caller.
437 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
438 struct s3c_hsotg_ep
*hs_ep
,
439 struct s3c_hsotg_req
*hs_req
)
441 struct usb_request
*req
= &hs_req
->req
;
443 /* ignore this if we're not moving any data */
444 if (hs_req
->req
.length
== 0)
447 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
451 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
452 * @hsotg: The controller state.
453 * @hs_ep: The endpoint we're going to write for.
454 * @hs_req: The request to write data for.
456 * This is called when the TxFIFO has some space in it to hold a new
457 * transmission and we have something to give it. The actual setup of
458 * the data size is done elsewhere, so all we have to do is to actually
461 * The return value is zero if there is more space (or nothing was done)
462 * otherwise -ENOSPC is returned if the FIFO space was used up.
464 * This routine is only needed for PIO
466 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
467 struct s3c_hsotg_ep
*hs_ep
,
468 struct s3c_hsotg_req
*hs_req
)
470 bool periodic
= is_ep_periodic(hs_ep
);
471 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
472 int buf_pos
= hs_req
->req
.actual
;
473 int to_write
= hs_ep
->size_loaded
;
479 to_write
-= (buf_pos
- hs_ep
->last_load
);
481 /* if there's nothing to write, get out early */
485 if (periodic
&& !hsotg
->dedicated_fifos
) {
486 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
491 * work out how much data was loaded so we can calculate
492 * how much data is left in the fifo.
495 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
498 * if shared fifo, we cannot write anything until the
499 * previous data has been completely sent.
501 if (hs_ep
->fifo_load
!= 0) {
502 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
506 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
508 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
510 /* how much of the data has moved */
511 size_done
= hs_ep
->size_loaded
- size_left
;
513 /* how much data is left in the fifo */
514 can_write
= hs_ep
->fifo_load
- size_done
;
515 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
516 __func__
, can_write
);
518 can_write
= hs_ep
->fifo_size
- can_write
;
519 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
520 __func__
, can_write
);
522 if (can_write
<= 0) {
523 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
526 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
527 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
532 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
534 "%s: no queue slots available (0x%08x)\n",
537 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTxFEmp
);
541 can_write
= GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
542 can_write
*= 4; /* fifo size is in 32bit quantities. */
545 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
547 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
548 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
551 * limit to 512 bytes of data, it seems at least on the non-periodic
552 * FIFO, requests of >512 cause the endpoint to get stuck with a
553 * fragment of the end of the transfer in it.
559 * limit the write to one max-packet size worth of data, but allow
560 * the transfer to return that it did not run out of fifo space
563 if (to_write
> max_transfer
) {
564 to_write
= max_transfer
;
566 /* it's needed only when we do not use dedicated fifos */
567 if (!hsotg
->dedicated_fifos
)
568 s3c_hsotg_en_gsint(hsotg
,
569 periodic
? GINTSTS_PTxFEmp
:
573 /* see if we can write data */
575 if (to_write
> can_write
) {
576 to_write
= can_write
;
577 pkt_round
= to_write
% max_transfer
;
580 * Round the write down to an
581 * exact number of packets.
583 * Note, we do not currently check to see if we can ever
584 * write a full packet or not to the FIFO.
588 to_write
-= pkt_round
;
591 * enable correct FIFO interrupt to alert us when there
595 /* it's needed only when we do not use dedicated fifos */
596 if (!hsotg
->dedicated_fifos
)
597 s3c_hsotg_en_gsint(hsotg
,
598 periodic
? GINTSTS_PTxFEmp
:
602 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
603 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
608 hs_req
->req
.actual
= buf_pos
+ to_write
;
609 hs_ep
->total_data
+= to_write
;
612 hs_ep
->fifo_load
+= to_write
;
614 to_write
= DIV_ROUND_UP(to_write
, 4);
615 data
= hs_req
->req
.buf
+ buf_pos
;
617 writesl(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
619 return (to_write
>= can_write
) ? -ENOSPC
: 0;
623 * get_ep_limit - get the maximum data legnth for this endpoint
624 * @hs_ep: The endpoint
626 * Return the maximum data that can be queued in one go on a given endpoint
627 * so that transfers that are too long can be split.
629 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
631 int index
= hs_ep
->index
;
636 maxsize
= DxEPTSIZ_XferSize_LIMIT
+ 1;
637 maxpkt
= DxEPTSIZ_PktCnt_LIMIT
+ 1;
641 maxpkt
= DIEPTSIZ0_PktCnt_LIMIT
+ 1;
646 /* we made the constant loading easier above by using +1 */
651 * constrain by packet count if maxpkts*pktsize is greater
652 * than the length register size.
655 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
656 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
662 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
663 * @hsotg: The controller state.
664 * @hs_ep: The endpoint to process a request for
665 * @hs_req: The request to start.
666 * @continuing: True if we are doing more for the current request.
668 * Start the given request running by setting the endpoint registers
669 * appropriately, and writing any data to the FIFOs.
671 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
672 struct s3c_hsotg_ep
*hs_ep
,
673 struct s3c_hsotg_req
*hs_req
,
676 struct usb_request
*ureq
= &hs_req
->req
;
677 int index
= hs_ep
->index
;
678 int dir_in
= hs_ep
->dir_in
;
688 if (hs_ep
->req
&& !continuing
) {
689 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
692 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
694 "%s: continue different req\n", __func__
);
700 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
701 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
703 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
704 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
705 hs_ep
->dir_in
? "in" : "out");
707 /* If endpoint is stalled, we will restart request later */
708 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
710 if (ctrl
& DxEPCTL_Stall
) {
711 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
715 length
= ureq
->length
- ureq
->actual
;
716 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
717 ureq
->length
, ureq
->actual
);
720 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
721 ureq
->buf
, length
, ureq
->dma
,
722 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
724 maxreq
= get_ep_limit(hs_ep
);
725 if (length
> maxreq
) {
726 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
728 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
729 __func__
, length
, maxreq
, round
);
731 /* round down to multiple of packets */
739 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
741 packets
= 1; /* send one packet if length is zero. */
743 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
744 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
748 if (dir_in
&& index
!= 0)
749 if (hs_ep
->isochronous
)
750 epsize
= DxEPTSIZ_MC(packets
);
752 epsize
= DxEPTSIZ_MC(1);
756 if (index
!= 0 && ureq
->zero
) {
758 * test for the packets being exactly right for the
762 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
766 epsize
|= DxEPTSIZ_PktCnt(packets
);
767 epsize
|= DxEPTSIZ_XferSize(length
);
769 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
770 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
772 /* store the request as the current one we're doing */
775 /* write size / packets */
776 writel(epsize
, hsotg
->regs
+ epsize_reg
);
778 if (using_dma(hsotg
) && !continuing
) {
779 unsigned int dma_reg
;
782 * write DMA address to control register, buffer already
783 * synced by s3c_hsotg_ep_queue().
786 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
787 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
789 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
790 __func__
, ureq
->dma
, dma_reg
);
793 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
794 ctrl
|= DxEPCTL_USBActEp
;
796 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
798 /* For Setup request do not clear NAK */
799 if (hsotg
->setup
&& index
== 0)
802 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
805 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
806 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
809 * set these, it seems that DMA support increments past the end
810 * of the packet buffer so we need to calculate the length from
813 hs_ep
->size_loaded
= length
;
814 hs_ep
->last_load
= ureq
->actual
;
816 if (dir_in
&& !using_dma(hsotg
)) {
817 /* set these anyway, we may need them for non-periodic in */
818 hs_ep
->fifo_load
= 0;
820 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
824 * clear the INTknTXFEmpMsk when we start request, more as a aide
825 * to debugging to see what is going on.
828 writel(DIEPMSK_INTknTXFEmpMsk
,
829 hsotg
->regs
+ DIEPINT(index
));
832 * Note, trying to clear the NAK here causes problems with transmit
833 * on the S3C6400 ending up with the TXFIFO becoming full.
836 /* check ep is enabled */
837 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DxEPCTL_EPEna
))
839 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
840 index
, readl(hsotg
->regs
+ epctrl_reg
));
842 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
843 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
845 /* enable ep interrupts */
846 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 1);
850 * s3c_hsotg_map_dma - map the DMA memory being used for the request
851 * @hsotg: The device state.
852 * @hs_ep: The endpoint the request is on.
853 * @req: The request being processed.
855 * We've been asked to queue a request, so ensure that the memory buffer
856 * is correctly setup for DMA. If we've been passed an extant DMA address
857 * then ensure the buffer has been synced to memory. If our buffer has no
858 * DMA memory, then we map the memory and mark our request to allow us to
859 * cleanup on completion.
861 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
862 struct s3c_hsotg_ep
*hs_ep
,
863 struct usb_request
*req
)
865 struct s3c_hsotg_req
*hs_req
= our_req(req
);
868 /* if the length is zero, ignore the DMA data */
869 if (hs_req
->req
.length
== 0)
872 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
879 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
880 __func__
, req
->buf
, req
->length
);
885 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
888 struct s3c_hsotg_req
*hs_req
= our_req(req
);
889 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
890 struct s3c_hsotg
*hs
= hs_ep
->parent
;
893 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
894 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
895 req
->zero
, req
->short_not_ok
);
897 /* initialise status of the request */
898 INIT_LIST_HEAD(&hs_req
->queue
);
900 req
->status
= -EINPROGRESS
;
902 /* if we're using DMA, sync the buffers as necessary */
904 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
909 first
= list_empty(&hs_ep
->queue
);
910 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
913 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
918 static int s3c_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
921 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
922 struct s3c_hsotg
*hs
= hs_ep
->parent
;
923 unsigned long flags
= 0;
926 spin_lock_irqsave(&hs
->lock
, flags
);
927 ret
= s3c_hsotg_ep_queue(ep
, req
, gfp_flags
);
928 spin_unlock_irqrestore(&hs
->lock
, flags
);
933 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
934 struct usb_request
*req
)
936 struct s3c_hsotg_req
*hs_req
= our_req(req
);
942 * s3c_hsotg_complete_oursetup - setup completion callback
943 * @ep: The endpoint the request was on.
944 * @req: The request completed.
946 * Called on completion of any requests the driver itself
947 * submitted that need cleaning up.
949 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
950 struct usb_request
*req
)
952 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
953 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
955 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
957 s3c_hsotg_ep_free_request(ep
, req
);
961 * ep_from_windex - convert control wIndex value to endpoint
962 * @hsotg: The driver state.
963 * @windex: The control request wIndex field (in host order).
965 * Convert the given wIndex into a pointer to an driver endpoint
966 * structure, or return NULL if it is not a valid endpoint.
968 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
971 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
972 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
973 int idx
= windex
& 0x7F;
978 if (idx
> hsotg
->num_of_eps
)
981 if (idx
&& ep
->dir_in
!= dir
)
988 * s3c_hsotg_send_reply - send reply to control request
989 * @hsotg: The device state
991 * @buff: Buffer for request
992 * @length: Length of reply.
994 * Create a request and queue it on the given endpoint. This is useful as
995 * an internal method of sending replies to certain control requests, etc.
997 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
998 struct s3c_hsotg_ep
*ep
,
1002 struct usb_request
*req
;
1005 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1007 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1008 hsotg
->ep0_reply
= req
;
1010 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1014 req
->buf
= hsotg
->ep0_buff
;
1015 req
->length
= length
;
1016 req
->zero
= 1; /* always do zero-length final transfer */
1017 req
->complete
= s3c_hsotg_complete_oursetup
;
1020 memcpy(req
->buf
, buff
, length
);
1024 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1026 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1034 * s3c_hsotg_process_req_status - process request GET_STATUS
1035 * @hsotg: The device state
1036 * @ctrl: USB control request
1038 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
1039 struct usb_ctrlrequest
*ctrl
)
1041 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1042 struct s3c_hsotg_ep
*ep
;
1046 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1049 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1053 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1054 case USB_RECIP_DEVICE
:
1055 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1056 * bit 1 => remote wakeup */
1059 case USB_RECIP_INTERFACE
:
1060 /* currently, the data result should be zero */
1061 reply
= cpu_to_le16(0);
1064 case USB_RECIP_ENDPOINT
:
1065 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1069 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1076 if (le16_to_cpu(ctrl
->wLength
) != 2)
1079 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1081 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1088 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1091 * get_ep_head - return the first request on the endpoint
1092 * @hs_ep: The controller endpoint to get
1094 * Get the first request on the endpoint.
1096 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1098 if (list_empty(&hs_ep
->queue
))
1101 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1105 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1106 * @hsotg: The device state
1107 * @ctrl: USB control request
1109 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1110 struct usb_ctrlrequest
*ctrl
)
1112 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1113 struct s3c_hsotg_req
*hs_req
;
1115 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1116 struct s3c_hsotg_ep
*ep
;
1119 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1120 __func__
, set
? "SET" : "CLEAR");
1122 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1123 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1125 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1126 __func__
, le16_to_cpu(ctrl
->wIndex
));
1130 switch (le16_to_cpu(ctrl
->wValue
)) {
1131 case USB_ENDPOINT_HALT
:
1132 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1134 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1137 "%s: failed to send reply\n", __func__
);
1143 * If we have request in progress,
1149 list_del_init(&hs_req
->queue
);
1150 hs_req
->req
.complete(&ep
->ep
,
1154 /* If we have pending request, then start it */
1155 restart
= !list_empty(&ep
->queue
);
1157 hs_req
= get_ep_head(ep
);
1158 s3c_hsotg_start_req(hsotg
, ep
,
1169 return -ENOENT
; /* currently only deal with endpoint */
1174 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1177 * s3c_hsotg_process_control - process a control request
1178 * @hsotg: The device state
1179 * @ctrl: The control request received
1181 * The controller has received the SETUP phase of a control request, and
1182 * needs to work out what to do next (and whether to pass it on to the
1185 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1186 struct usb_ctrlrequest
*ctrl
)
1188 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1194 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1195 ctrl
->bRequest
, ctrl
->bRequestType
,
1196 ctrl
->wValue
, ctrl
->wLength
);
1199 * record the direction of the request, for later use when enquing
1203 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1204 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1207 * if we've no data with this request, then the last part of the
1208 * transaction is going to implicitly be IN.
1210 if (ctrl
->wLength
== 0)
1213 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1214 switch (ctrl
->bRequest
) {
1215 case USB_REQ_SET_ADDRESS
:
1216 dcfg
= readl(hsotg
->regs
+ DCFG
);
1217 dcfg
&= ~DCFG_DevAddr_MASK
;
1218 dcfg
|= ctrl
->wValue
<< DCFG_DevAddr_SHIFT
;
1219 writel(dcfg
, hsotg
->regs
+ DCFG
);
1221 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1223 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1226 case USB_REQ_GET_STATUS
:
1227 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1230 case USB_REQ_CLEAR_FEATURE
:
1231 case USB_REQ_SET_FEATURE
:
1232 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1237 /* as a fallback, try delivering it to the driver to deal with */
1239 if (ret
== 0 && hsotg
->driver
) {
1240 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1242 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1246 * the request is either unhandlable, or is not formatted correctly
1247 * so respond with a STALL for the status stage to indicate failure.
1254 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1255 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1258 * DxEPCTL_Stall will be cleared by EP once it has
1259 * taken effect, so no need to clear later.
1262 ctrl
= readl(hsotg
->regs
+ reg
);
1263 ctrl
|= DxEPCTL_Stall
;
1264 ctrl
|= DxEPCTL_CNAK
;
1265 writel(ctrl
, hsotg
->regs
+ reg
);
1268 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1269 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1272 * don't believe we need to anything more to get the EP
1273 * to reply with a STALL packet
1277 * complete won't be called, so we enqueue
1278 * setup request here
1280 s3c_hsotg_enqueue_setup(hsotg
);
1285 * s3c_hsotg_complete_setup - completion of a setup transfer
1286 * @ep: The endpoint the request was on.
1287 * @req: The request completed.
1289 * Called on completion of any requests the driver itself submitted for
1292 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1293 struct usb_request
*req
)
1295 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1296 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1298 if (req
->status
< 0) {
1299 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1303 if (req
->actual
== 0)
1304 s3c_hsotg_enqueue_setup(hsotg
);
1306 s3c_hsotg_process_control(hsotg
, req
->buf
);
1310 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1311 * @hsotg: The device state.
1313 * Enqueue a request on EP0 if necessary to received any SETUP packets
1314 * received from the host.
1316 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1318 struct usb_request
*req
= hsotg
->ctrl_req
;
1319 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1322 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1326 req
->buf
= hsotg
->ctrl_buff
;
1327 req
->complete
= s3c_hsotg_complete_setup
;
1329 if (!list_empty(&hs_req
->queue
)) {
1330 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1334 hsotg
->eps
[0].dir_in
= 0;
1336 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1338 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1340 * Don't think there's much we can do other than watch the
1347 * s3c_hsotg_complete_request - complete a request given to us
1348 * @hsotg: The device state.
1349 * @hs_ep: The endpoint the request was on.
1350 * @hs_req: The request to complete.
1351 * @result: The result code (0 => Ok, otherwise errno)
1353 * The given request has finished, so call the necessary completion
1354 * if it has one and then look to see if we can start a new request
1357 * Note, expects the ep to already be locked as appropriate.
1359 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1360 struct s3c_hsotg_ep
*hs_ep
,
1361 struct s3c_hsotg_req
*hs_req
,
1367 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1371 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1372 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1375 * only replace the status if we've not already set an error
1376 * from a previous transaction
1379 if (hs_req
->req
.status
== -EINPROGRESS
)
1380 hs_req
->req
.status
= result
;
1383 list_del_init(&hs_req
->queue
);
1385 if (using_dma(hsotg
))
1386 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1389 * call the complete request with the locks off, just in case the
1390 * request tries to queue more work for this endpoint.
1393 if (hs_req
->req
.complete
) {
1394 spin_unlock(&hsotg
->lock
);
1395 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1396 spin_lock(&hsotg
->lock
);
1400 * Look to see if there is anything else to do. Note, the completion
1401 * of the previous request may have caused a new request to be started
1402 * so be careful when doing this.
1405 if (!hs_ep
->req
&& result
>= 0) {
1406 restart
= !list_empty(&hs_ep
->queue
);
1408 hs_req
= get_ep_head(hs_ep
);
1409 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1415 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1416 * @hsotg: The device state.
1417 * @ep_idx: The endpoint index for the data
1418 * @size: The size of data in the fifo, in bytes
1420 * The FIFO status shows there is data to read from the FIFO for a given
1421 * endpoint, so sort out whether we need to read the data into a request
1422 * that has been made for that endpoint.
1424 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1426 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1427 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1428 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1435 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1438 dev_warn(hsotg
->dev
,
1439 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1440 __func__
, size
, ep_idx
, epctl
);
1442 /* dump the data from the FIFO, we've nothing we can do */
1443 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1450 read_ptr
= hs_req
->req
.actual
;
1451 max_req
= hs_req
->req
.length
- read_ptr
;
1453 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1454 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1456 if (to_read
> max_req
) {
1458 * more data appeared than we where willing
1459 * to deal with in this request.
1462 /* currently we don't deal this */
1466 hs_ep
->total_data
+= to_read
;
1467 hs_req
->req
.actual
+= to_read
;
1468 to_read
= DIV_ROUND_UP(to_read
, 4);
1471 * note, we might over-write the buffer end by 3 bytes depending on
1472 * alignment of the data.
1474 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1478 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1479 * @hsotg: The device instance
1480 * @req: The request currently on this endpoint
1482 * Generate a zero-length IN packet request for terminating a SETUP
1485 * Note, since we don't write any data to the TxFIFO, then it is
1486 * currently believed that we do not need to wait for any space in
1489 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1490 struct s3c_hsotg_req
*req
)
1495 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1499 if (req
->req
.length
== 0) {
1500 hsotg
->eps
[0].sent_zlp
= 1;
1501 s3c_hsotg_enqueue_setup(hsotg
);
1505 hsotg
->eps
[0].dir_in
= 1;
1506 hsotg
->eps
[0].sent_zlp
= 1;
1508 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1510 /* issue a zero-sized packet to terminate this */
1511 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1512 DxEPTSIZ_XferSize(0), hsotg
->regs
+ DIEPTSIZ(0));
1514 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1515 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
1516 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
1517 ctrl
|= DxEPCTL_USBActEp
;
1518 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1522 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1523 * @hsotg: The device instance
1524 * @epnum: The endpoint received from
1525 * @was_setup: Set if processing a SetupDone event.
1527 * The RXFIFO has delivered an OutDone event, which means that the data
1528 * transfer for an OUT endpoint has been completed, either by a short
1529 * packet or by the finish of a transfer.
1531 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1532 int epnum
, bool was_setup
)
1534 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1535 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1536 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1537 struct usb_request
*req
= &hs_req
->req
;
1538 unsigned size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1542 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1546 if (using_dma(hsotg
)) {
1550 * Calculate the size of the transfer by checking how much
1551 * is left in the endpoint size register and then working it
1552 * out from the amount we loaded for the transfer.
1554 * We need to do this as DMA pointers are always 32bit aligned
1555 * so may overshoot/undershoot the transfer.
1558 size_done
= hs_ep
->size_loaded
- size_left
;
1559 size_done
+= hs_ep
->last_load
;
1561 req
->actual
= size_done
;
1564 /* if there is more request to do, schedule new transfer */
1565 if (req
->actual
< req
->length
&& size_left
== 0) {
1566 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1568 } else if (epnum
== 0) {
1570 * After was_setup = 1 =>
1571 * set CNAK for non Setup requests
1573 hsotg
->setup
= was_setup
? 0 : 1;
1576 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1577 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1578 __func__
, req
->actual
, req
->length
);
1581 * todo - what should we return here? there's no one else
1582 * even bothering to check the status.
1588 * Condition req->complete != s3c_hsotg_complete_setup says:
1589 * send ZLP when we have an asynchronous request from gadget
1591 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1592 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1595 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1599 * s3c_hsotg_read_frameno - read current frame number
1600 * @hsotg: The device instance
1602 * Return the current frame number
1604 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1608 dsts
= readl(hsotg
->regs
+ DSTS
);
1609 dsts
&= DSTS_SOFFN_MASK
;
1610 dsts
>>= DSTS_SOFFN_SHIFT
;
1616 * s3c_hsotg_handle_rx - RX FIFO has data
1617 * @hsotg: The device instance
1619 * The IRQ handler has detected that the RX FIFO has some data in it
1620 * that requires processing, so find out what is in there and do the
1623 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1624 * chunks, so if you have x packets received on an endpoint you'll get x
1625 * FIFO events delivered, each with a packet's worth of data in it.
1627 * When using DMA, we should not be processing events from the RXFIFO
1628 * as the actual data should be sent to the memory directly and we turn
1629 * on the completion interrupts to get notifications of transfer completion.
1631 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1633 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1634 u32 epnum
, status
, size
;
1636 WARN_ON(using_dma(hsotg
));
1638 epnum
= grxstsr
& GRXSTS_EPNum_MASK
;
1639 status
= grxstsr
& GRXSTS_PktSts_MASK
;
1641 size
= grxstsr
& GRXSTS_ByteCnt_MASK
;
1642 size
>>= GRXSTS_ByteCnt_SHIFT
;
1645 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1646 __func__
, grxstsr
, size
, epnum
);
1648 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1650 switch (status
>> GRXSTS_PktSts_SHIFT
) {
1651 case __status(GRXSTS_PktSts_GlobalOutNAK
):
1652 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1655 case __status(GRXSTS_PktSts_OutDone
):
1656 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1657 s3c_hsotg_read_frameno(hsotg
));
1659 if (!using_dma(hsotg
))
1660 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1663 case __status(GRXSTS_PktSts_SetupDone
):
1665 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1666 s3c_hsotg_read_frameno(hsotg
),
1667 readl(hsotg
->regs
+ DOEPCTL(0)));
1669 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1672 case __status(GRXSTS_PktSts_OutRX
):
1673 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1676 case __status(GRXSTS_PktSts_SetupRX
):
1678 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1679 s3c_hsotg_read_frameno(hsotg
),
1680 readl(hsotg
->regs
+ DOEPCTL(0)));
1682 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1686 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1689 s3c_hsotg_dump(hsotg
);
1695 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1696 * @mps: The maximum packet size in bytes.
1698 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1702 return D0EPCTL_MPS_64
;
1704 return D0EPCTL_MPS_32
;
1706 return D0EPCTL_MPS_16
;
1708 return D0EPCTL_MPS_8
;
1711 /* bad max packet size, warn and return invalid result */
1717 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1718 * @hsotg: The driver state.
1719 * @ep: The index number of the endpoint
1720 * @mps: The maximum packet size in bytes
1722 * Configure the maximum packet size for the given endpoint, updating
1723 * the hardware control registers to reflect this.
1725 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1726 unsigned int ep
, unsigned int mps
)
1728 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1729 void __iomem
*regs
= hsotg
->regs
;
1735 /* EP0 is a special case */
1736 mpsval
= s3c_hsotg_ep0_mps(mps
);
1739 hs_ep
->ep
.maxpacket
= mps
;
1742 mpsval
= mps
& DxEPCTL_MPS_MASK
;
1745 mcval
= ((mps
>> 11) & 0x3) + 1;
1749 hs_ep
->ep
.maxpacket
= mpsval
;
1753 * update both the in and out endpoint controldir_ registers, even
1754 * if one of the directions may not be in use.
1757 reg
= readl(regs
+ DIEPCTL(ep
));
1758 reg
&= ~DxEPCTL_MPS_MASK
;
1760 writel(reg
, regs
+ DIEPCTL(ep
));
1763 reg
= readl(regs
+ DOEPCTL(ep
));
1764 reg
&= ~DxEPCTL_MPS_MASK
;
1766 writel(reg
, regs
+ DOEPCTL(ep
));
1772 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1776 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1777 * @hsotg: The driver state
1778 * @idx: The index for the endpoint (0..15)
1780 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg
*hsotg
, unsigned int idx
)
1785 writel(GRSTCTL_TxFNum(idx
) | GRSTCTL_TxFFlsh
,
1786 hsotg
->regs
+ GRSTCTL
);
1788 /* wait until the fifo is flushed */
1792 val
= readl(hsotg
->regs
+ GRSTCTL
);
1794 if ((val
& (GRSTCTL_TxFFlsh
)) == 0)
1797 if (--timeout
== 0) {
1799 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1808 * s3c_hsotg_trytx - check to see if anything needs transmitting
1809 * @hsotg: The driver state
1810 * @hs_ep: The driver endpoint to check.
1812 * Check to see if there is a request that has data to send, and if so
1813 * make an attempt to write data into the FIFO.
1815 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1816 struct s3c_hsotg_ep
*hs_ep
)
1818 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1820 if (!hs_ep
->dir_in
|| !hs_req
) {
1822 * if request is not enqueued, we disable interrupts
1823 * for endpoints, excepting ep0
1825 if (hs_ep
->index
!= 0)
1826 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
,
1831 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1832 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1834 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1841 * s3c_hsotg_complete_in - complete IN transfer
1842 * @hsotg: The device state.
1843 * @hs_ep: The endpoint that has just completed.
1845 * An IN transfer has been completed, update the transfer's state and then
1846 * call the relevant completion routines.
1848 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1849 struct s3c_hsotg_ep
*hs_ep
)
1851 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1852 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1853 int size_left
, size_done
;
1856 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1860 /* Finish ZLP handling for IN EP0 transactions */
1861 if (hsotg
->eps
[0].sent_zlp
) {
1862 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1863 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1868 * Calculate the size of the transfer by checking how much is left
1869 * in the endpoint size register and then working it out from
1870 * the amount we loaded for the transfer.
1872 * We do this even for DMA, as the transfer may have incremented
1873 * past the end of the buffer (DMA transfers are always 32bit
1877 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1879 size_done
= hs_ep
->size_loaded
- size_left
;
1880 size_done
+= hs_ep
->last_load
;
1882 if (hs_req
->req
.actual
!= size_done
)
1883 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1884 __func__
, hs_req
->req
.actual
, size_done
);
1886 hs_req
->req
.actual
= size_done
;
1887 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1888 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1891 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1892 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1893 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1894 * inform the host that no more data is available.
1895 * The state of req.zero member is checked to be sure that the value to
1896 * send is smaller than wValue expected from host.
1897 * Check req.length to NOT send another ZLP when the current one is
1898 * under completion (the one for which this completion has been called).
1900 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1901 hs_req
->req
.length
== hs_req
->req
.actual
&&
1902 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1904 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1905 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1910 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1911 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1912 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1914 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1918 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1919 * @hsotg: The driver state
1920 * @idx: The index for the endpoint (0..15)
1921 * @dir_in: Set if this is an IN endpoint
1923 * Process and clear any interrupt pending for an individual endpoint
1925 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1928 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1929 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1930 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1931 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1935 ints
= readl(hsotg
->regs
+ epint_reg
);
1936 ctrl
= readl(hsotg
->regs
+ epctl_reg
);
1938 /* Clear endpoint interrupts */
1939 writel(ints
, hsotg
->regs
+ epint_reg
);
1941 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1942 __func__
, idx
, dir_in
? "in" : "out", ints
);
1944 if (ints
& DxEPINT_XferCompl
) {
1945 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1) {
1946 if (ctrl
& DxEPCTL_EOFrNum
)
1947 ctrl
|= DxEPCTL_SetEvenFr
;
1949 ctrl
|= DxEPCTL_SetOddFr
;
1950 writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1954 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1955 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1956 readl(hsotg
->regs
+ epsiz_reg
));
1959 * we get OutDone from the FIFO, so we only need to look
1960 * at completing IN requests here
1963 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1965 if (idx
== 0 && !hs_ep
->req
)
1966 s3c_hsotg_enqueue_setup(hsotg
);
1967 } else if (using_dma(hsotg
)) {
1969 * We're using DMA, we need to fire an OutDone here
1970 * as we ignore the RXFIFO.
1973 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1977 if (ints
& DxEPINT_EPDisbld
) {
1978 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1981 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1983 s3c_hsotg_txfifo_flush(hsotg
, idx
);
1985 if ((epctl
& DxEPCTL_Stall
) &&
1986 (epctl
& DxEPCTL_EPType_Bulk
)) {
1987 int dctl
= readl(hsotg
->regs
+ DCTL
);
1989 dctl
|= DCTL_CGNPInNAK
;
1990 writel(dctl
, hsotg
->regs
+ DCTL
);
1995 if (ints
& DxEPINT_AHBErr
)
1996 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1998 if (ints
& DxEPINT_Setup
) { /* Setup or Timeout */
1999 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
2001 if (using_dma(hsotg
) && idx
== 0) {
2003 * this is the notification we've received a
2004 * setup packet. In non-DMA mode we'd get this
2005 * from the RXFIFO, instead we need to process
2012 s3c_hsotg_handle_outdone(hsotg
, 0, true);
2016 if (ints
& DxEPINT_Back2BackSetup
)
2017 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2019 if (dir_in
&& !hs_ep
->isochronous
) {
2020 /* not sure if this is important, but we'll clear it anyway */
2021 if (ints
& DIEPMSK_INTknTXFEmpMsk
) {
2022 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2026 /* this probably means something bad is happening */
2027 if (ints
& DIEPMSK_INTknEPMisMsk
) {
2028 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2032 /* FIFO has space or is empty (see GAHBCFG) */
2033 if (hsotg
->dedicated_fifos
&&
2034 ints
& DIEPMSK_TxFIFOEmpty
) {
2035 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2037 if (!using_dma(hsotg
))
2038 s3c_hsotg_trytx(hsotg
, hs_ep
);
2044 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2045 * @hsotg: The device state.
2047 * Handle updating the device settings after the enumeration phase has
2050 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
2052 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
2053 int ep0_mps
= 0, ep_mps
;
2056 * This should signal the finish of the enumeration phase
2057 * of the USB handshaking, so we should now know what rate
2061 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2064 * note, since we're limited by the size of transfer on EP0, and
2065 * it seems IN transfers must be a even number of packets we do
2066 * not advertise a 64byte MPS on EP0.
2069 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2070 switch (dsts
& DSTS_EnumSpd_MASK
) {
2071 case DSTS_EnumSpd_FS
:
2072 case DSTS_EnumSpd_FS48
:
2073 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2074 ep0_mps
= EP0_MPS_LIMIT
;
2078 case DSTS_EnumSpd_HS
:
2079 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2080 ep0_mps
= EP0_MPS_LIMIT
;
2084 case DSTS_EnumSpd_LS
:
2085 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2087 * note, we don't actually support LS in this driver at the
2088 * moment, and the documentation seems to imply that it isn't
2089 * supported by the PHYs on some of the devices.
2093 dev_info(hsotg
->dev
, "new device is %s\n",
2094 usb_speed_string(hsotg
->gadget
.speed
));
2097 * we should now know the maximum packet size for an
2098 * endpoint, so set the endpoints to a default value.
2103 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
2104 for (i
= 1; i
< hsotg
->num_of_eps
; i
++)
2105 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
2108 /* ensure after enumeration our EP0 is active */
2110 s3c_hsotg_enqueue_setup(hsotg
);
2112 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2113 readl(hsotg
->regs
+ DIEPCTL0
),
2114 readl(hsotg
->regs
+ DOEPCTL0
));
2118 * kill_all_requests - remove all requests from the endpoint's queue
2119 * @hsotg: The device state.
2120 * @ep: The endpoint the requests may be on.
2121 * @result: The result code to use.
2122 * @force: Force removal of any current requests
2124 * Go through the requests on the given endpoint and mark them
2125 * completed with the given result code.
2127 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
2128 struct s3c_hsotg_ep
*ep
,
2129 int result
, bool force
)
2131 struct s3c_hsotg_req
*req
, *treq
;
2133 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2135 * currently, we can't do much about an already
2136 * running request on an in endpoint
2139 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
2142 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2147 #define call_gadget(_hs, _entry) \
2149 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2150 (_hs)->driver && (_hs)->driver->_entry) { \
2151 spin_unlock(&_hs->lock); \
2152 (_hs)->driver->_entry(&(_hs)->gadget); \
2153 spin_lock(&_hs->lock); \
2158 * s3c_hsotg_disconnect - disconnect service
2159 * @hsotg: The device state.
2161 * The device has been disconnected. Remove all current
2162 * transactions and signal the gadget driver that this
2165 static void s3c_hsotg_disconnect(struct s3c_hsotg
*hsotg
)
2169 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2170 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
2172 call_gadget(hsotg
, disconnect
);
2176 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2177 * @hsotg: The device state:
2178 * @periodic: True if this is a periodic FIFO interrupt
2180 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2182 struct s3c_hsotg_ep
*ep
;
2185 /* look through for any more data to transmit */
2187 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2188 ep
= &hsotg
->eps
[epno
];
2193 if ((periodic
&& !ep
->periodic
) ||
2194 (!periodic
&& ep
->periodic
))
2197 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2203 /* IRQ flags which will trigger a retry around the IRQ loop */
2204 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2209 * s3c_hsotg_corereset - issue softreset to the core
2210 * @hsotg: The device state
2212 * Issue a soft reset to the core, and await the core finishing it.
2214 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2219 dev_dbg(hsotg
->dev
, "resetting core\n");
2221 /* issue soft reset */
2222 writel(GRSTCTL_CSftRst
, hsotg
->regs
+ GRSTCTL
);
2226 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2227 } while ((grstctl
& GRSTCTL_CSftRst
) && timeout
-- > 0);
2229 if (grstctl
& GRSTCTL_CSftRst
) {
2230 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2237 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2239 if (timeout
-- < 0) {
2240 dev_info(hsotg
->dev
,
2241 "%s: reset failed, GRSTCTL=%08x\n",
2246 if (!(grstctl
& GRSTCTL_AHBIdle
))
2249 break; /* reset done */
2252 dev_dbg(hsotg
->dev
, "reset successful\n");
2257 * s3c_hsotg_core_init - issue softreset to the core
2258 * @hsotg: The device state
2260 * Issue a soft reset to the core, and await the core finishing it.
2262 static void s3c_hsotg_core_init(struct s3c_hsotg
*hsotg
)
2264 s3c_hsotg_corereset(hsotg
);
2267 * we must now enable ep0 ready for host detection and then
2268 * set configuration.
2271 /* set the PLL on, remove the HNP/SRP and set the PHY */
2272 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) |
2273 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2275 s3c_hsotg_init_fifo(hsotg
);
2277 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2279 writel(1 << 18 | DCFG_DevSpd_HS
, hsotg
->regs
+ DCFG
);
2281 /* Clear any pending OTG interrupts */
2282 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2284 /* Clear any pending interrupts */
2285 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2287 writel(GINTSTS_ErlySusp
| GINTSTS_SessReqInt
|
2288 GINTSTS_GOUTNakEff
| GINTSTS_GINNakEff
|
2289 GINTSTS_ConIDStsChng
| GINTSTS_USBRst
|
2290 GINTSTS_EnumDone
| GINTSTS_OTGInt
|
2291 GINTSTS_USBSusp
| GINTSTS_WkUpInt
,
2292 hsotg
->regs
+ GINTMSK
);
2294 if (using_dma(hsotg
))
2295 writel(GAHBCFG_GlblIntrEn
| GAHBCFG_DMAEn
|
2296 GAHBCFG_HBstLen_Incr4
,
2297 hsotg
->regs
+ GAHBCFG
);
2299 writel(GAHBCFG_GlblIntrEn
, hsotg
->regs
+ GAHBCFG
);
2302 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2303 * up being flooded with interrupts if the host is polling the
2304 * endpoint to try and read data.
2307 writel(((hsotg
->dedicated_fifos
) ? DIEPMSK_TxFIFOEmpty
: 0) |
2308 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
|
2309 DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2310 DIEPMSK_INTknEPMisMsk
,
2311 hsotg
->regs
+ DIEPMSK
);
2314 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2315 * DMA mode we may need this.
2317 writel((using_dma(hsotg
) ? (DIEPMSK_XferComplMsk
|
2318 DIEPMSK_TimeOUTMsk
) : 0) |
2319 DOEPMSK_EPDisbldMsk
| DOEPMSK_AHBErrMsk
|
2321 hsotg
->regs
+ DOEPMSK
);
2323 writel(0, hsotg
->regs
+ DAINTMSK
);
2325 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2326 readl(hsotg
->regs
+ DIEPCTL0
),
2327 readl(hsotg
->regs
+ DOEPCTL0
));
2329 /* enable in and out endpoint interrupts */
2330 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPInt
| GINTSTS_IEPInt
);
2333 * Enable the RXFIFO when in slave mode, as this is how we collect
2334 * the data. In DMA mode, we get events from the FIFO but also
2335 * things we cannot process, so do not use it.
2337 if (!using_dma(hsotg
))
2338 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RxFLvl
);
2340 /* Enable interrupts for EP0 in and out */
2341 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2342 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2344 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2345 udelay(10); /* see openiboot */
2346 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2348 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2351 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2352 * writing to the EPCTL register..
2355 /* set to read 1 8byte packet */
2356 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2357 DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2359 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2360 DxEPCTL_CNAK
| DxEPCTL_EPEna
|
2362 hsotg
->regs
+ DOEPCTL0
);
2364 /* enable, but don't activate EP0in */
2365 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2366 DxEPCTL_USBActEp
, hsotg
->regs
+ DIEPCTL0
);
2368 s3c_hsotg_enqueue_setup(hsotg
);
2370 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2371 readl(hsotg
->regs
+ DIEPCTL0
),
2372 readl(hsotg
->regs
+ DOEPCTL0
));
2374 /* clear global NAKs */
2375 writel(DCTL_CGOUTNak
| DCTL_CGNPInNAK
,
2376 hsotg
->regs
+ DCTL
);
2378 /* must be at-least 3ms to allow bus to see disconnect */
2381 /* remove the soft-disconnect and let's go */
2382 __bic32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2386 * s3c_hsotg_irq - handle device interrupt
2387 * @irq: The IRQ number triggered
2388 * @pw: The pw value when registered the handler.
2390 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2392 struct s3c_hsotg
*hsotg
= pw
;
2393 int retry_count
= 8;
2397 spin_lock(&hsotg
->lock
);
2399 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2400 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2402 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2403 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2407 if (gintsts
& GINTSTS_OTGInt
) {
2408 u32 otgint
= readl(hsotg
->regs
+ GOTGINT
);
2410 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2412 writel(otgint
, hsotg
->regs
+ GOTGINT
);
2415 if (gintsts
& GINTSTS_SessReqInt
) {
2416 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2417 writel(GINTSTS_SessReqInt
, hsotg
->regs
+ GINTSTS
);
2420 if (gintsts
& GINTSTS_EnumDone
) {
2421 writel(GINTSTS_EnumDone
, hsotg
->regs
+ GINTSTS
);
2423 s3c_hsotg_irq_enumdone(hsotg
);
2426 if (gintsts
& GINTSTS_ConIDStsChng
) {
2427 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2428 readl(hsotg
->regs
+ DSTS
),
2429 readl(hsotg
->regs
+ GOTGCTL
));
2431 writel(GINTSTS_ConIDStsChng
, hsotg
->regs
+ GINTSTS
);
2434 if (gintsts
& (GINTSTS_OEPInt
| GINTSTS_IEPInt
)) {
2435 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2436 u32 daintmsk
= readl(hsotg
->regs
+ DAINTMSK
);
2437 u32 daint_out
, daint_in
;
2441 daint_out
= daint
>> DAINT_OutEP_SHIFT
;
2442 daint_in
= daint
& ~(daint_out
<< DAINT_OutEP_SHIFT
);
2444 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2446 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2448 s3c_hsotg_epint(hsotg
, ep
, 0);
2451 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2453 s3c_hsotg_epint(hsotg
, ep
, 1);
2457 if (gintsts
& GINTSTS_USBRst
) {
2459 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2461 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2462 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2463 readl(hsotg
->regs
+ GNPTXSTS
));
2465 writel(GINTSTS_USBRst
, hsotg
->regs
+ GINTSTS
);
2467 if (usb_status
& GOTGCTL_BSESVLD
) {
2468 if (time_after(jiffies
, hsotg
->last_rst
+
2469 msecs_to_jiffies(200))) {
2471 kill_all_requests(hsotg
, &hsotg
->eps
[0],
2474 s3c_hsotg_core_init(hsotg
);
2475 hsotg
->last_rst
= jiffies
;
2480 /* check both FIFOs */
2482 if (gintsts
& GINTSTS_NPTxFEmp
) {
2483 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2486 * Disable the interrupt to stop it happening again
2487 * unless one of these endpoint routines decides that
2488 * it needs re-enabling
2491 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTxFEmp
);
2492 s3c_hsotg_irq_fifoempty(hsotg
, false);
2495 if (gintsts
& GINTSTS_PTxFEmp
) {
2496 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2498 /* See note in GINTSTS_NPTxFEmp */
2500 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTxFEmp
);
2501 s3c_hsotg_irq_fifoempty(hsotg
, true);
2504 if (gintsts
& GINTSTS_RxFLvl
) {
2506 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2507 * we need to retry s3c_hsotg_handle_rx if this is still
2511 s3c_hsotg_handle_rx(hsotg
);
2514 if (gintsts
& GINTSTS_ModeMis
) {
2515 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2516 writel(GINTSTS_ModeMis
, hsotg
->regs
+ GINTSTS
);
2519 if (gintsts
& GINTSTS_USBSusp
) {
2520 dev_info(hsotg
->dev
, "GINTSTS_USBSusp\n");
2521 writel(GINTSTS_USBSusp
, hsotg
->regs
+ GINTSTS
);
2523 call_gadget(hsotg
, suspend
);
2524 s3c_hsotg_disconnect(hsotg
);
2527 if (gintsts
& GINTSTS_WkUpInt
) {
2528 dev_info(hsotg
->dev
, "GINTSTS_WkUpIn\n");
2529 writel(GINTSTS_WkUpInt
, hsotg
->regs
+ GINTSTS
);
2531 call_gadget(hsotg
, resume
);
2534 if (gintsts
& GINTSTS_ErlySusp
) {
2535 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2536 writel(GINTSTS_ErlySusp
, hsotg
->regs
+ GINTSTS
);
2540 * these next two seem to crop-up occasionally causing the core
2541 * to shutdown the USB transfer, so try clearing them and logging
2545 if (gintsts
& GINTSTS_GOUTNakEff
) {
2546 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2548 writel(DCTL_CGOUTNak
, hsotg
->regs
+ DCTL
);
2550 s3c_hsotg_dump(hsotg
);
2553 if (gintsts
& GINTSTS_GINNakEff
) {
2554 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2556 writel(DCTL_CGNPInNAK
, hsotg
->regs
+ DCTL
);
2558 s3c_hsotg_dump(hsotg
);
2562 * if we've had fifo events, we should try and go around the
2563 * loop again to see if there's any point in returning yet.
2566 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2569 spin_unlock(&hsotg
->lock
);
2575 * s3c_hsotg_ep_enable - enable the given endpoint
2576 * @ep: The USB endpint to configure
2577 * @desc: The USB endpoint descriptor to configure with.
2579 * This is called from the USB gadget code's usb_ep_enable().
2581 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2582 const struct usb_endpoint_descriptor
*desc
)
2584 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2585 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2586 unsigned long flags
;
2587 int index
= hs_ep
->index
;
2595 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2596 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2597 desc
->wMaxPacketSize
, desc
->bInterval
);
2599 /* not to be called for EP0 */
2600 WARN_ON(index
== 0);
2602 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2603 if (dir_in
!= hs_ep
->dir_in
) {
2604 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2608 mps
= usb_endpoint_maxp(desc
);
2610 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2612 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2613 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2615 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2616 __func__
, epctrl
, epctrl_reg
);
2618 spin_lock_irqsave(&hsotg
->lock
, flags
);
2620 epctrl
&= ~(DxEPCTL_EPType_MASK
| DxEPCTL_MPS_MASK
);
2621 epctrl
|= DxEPCTL_MPS(mps
);
2624 * mark the endpoint as active, otherwise the core may ignore
2625 * transactions entirely for this endpoint
2627 epctrl
|= DxEPCTL_USBActEp
;
2630 * set the NAK status on the endpoint, otherwise we might try and
2631 * do something with data that we've yet got a request to process
2632 * since the RXFIFO will take data for an endpoint even if the
2633 * size register hasn't been set.
2636 epctrl
|= DxEPCTL_SNAK
;
2638 /* update the endpoint state */
2639 s3c_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
);
2641 /* default, set to non-periodic */
2642 hs_ep
->isochronous
= 0;
2643 hs_ep
->periodic
= 0;
2645 hs_ep
->interval
= desc
->bInterval
;
2647 if (hs_ep
->interval
> 1 && hs_ep
->mc
> 1)
2648 dev_err(hsotg
->dev
, "MC > 1 when interval is not 1\n");
2650 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2651 case USB_ENDPOINT_XFER_ISOC
:
2652 epctrl
|= DxEPCTL_EPType_Iso
;
2653 epctrl
|= DxEPCTL_SetEvenFr
;
2654 hs_ep
->isochronous
= 1;
2656 hs_ep
->periodic
= 1;
2659 case USB_ENDPOINT_XFER_BULK
:
2660 epctrl
|= DxEPCTL_EPType_Bulk
;
2663 case USB_ENDPOINT_XFER_INT
:
2666 * Allocate our TxFNum by simply using the index
2667 * of the endpoint for the moment. We could do
2668 * something better if the host indicates how
2669 * many FIFOs we are expecting to use.
2672 hs_ep
->periodic
= 1;
2673 epctrl
|= DxEPCTL_TxFNum(index
);
2676 epctrl
|= DxEPCTL_EPType_Intterupt
;
2679 case USB_ENDPOINT_XFER_CONTROL
:
2680 epctrl
|= DxEPCTL_EPType_Control
;
2685 * if the hardware has dedicated fifos, we must give each IN EP
2686 * a unique tx-fifo even if it is non-periodic.
2688 if (dir_in
&& hsotg
->dedicated_fifos
)
2689 epctrl
|= DxEPCTL_TxFNum(index
);
2691 /* for non control endpoints, set PID to D0 */
2693 epctrl
|= DxEPCTL_SetD0PID
;
2695 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2698 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2699 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2700 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2702 /* enable the endpoint interrupt */
2703 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2705 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2710 * s3c_hsotg_ep_disable - disable given endpoint
2711 * @ep: The endpoint to disable.
2713 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2715 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2716 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2717 int dir_in
= hs_ep
->dir_in
;
2718 int index
= hs_ep
->index
;
2719 unsigned long flags
;
2723 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2725 if (ep
== &hsotg
->eps
[0].ep
) {
2726 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2730 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2732 spin_lock_irqsave(&hsotg
->lock
, flags
);
2733 /* terminate all requests with shutdown */
2734 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2737 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2738 ctrl
&= ~DxEPCTL_EPEna
;
2739 ctrl
&= ~DxEPCTL_USBActEp
;
2740 ctrl
|= DxEPCTL_SNAK
;
2742 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2743 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2745 /* disable endpoint interrupts */
2746 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2748 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2753 * on_list - check request is on the given endpoint
2754 * @ep: The endpoint to check.
2755 * @test: The request to test if it is on the endpoint.
2757 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2759 struct s3c_hsotg_req
*req
, *treq
;
2761 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2770 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2771 * @ep: The endpoint to dequeue.
2772 * @req: The request to be removed from a queue.
2774 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2776 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2777 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2778 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2779 unsigned long flags
;
2781 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2783 spin_lock_irqsave(&hs
->lock
, flags
);
2785 if (!on_list(hs_ep
, hs_req
)) {
2786 spin_unlock_irqrestore(&hs
->lock
, flags
);
2790 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2791 spin_unlock_irqrestore(&hs
->lock
, flags
);
2797 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2798 * @ep: The endpoint to set halt.
2799 * @value: Set or unset the halt.
2801 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2803 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2804 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2805 int index
= hs_ep
->index
;
2810 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2812 /* write both IN and OUT control registers */
2814 epreg
= DIEPCTL(index
);
2815 epctl
= readl(hs
->regs
+ epreg
);
2818 epctl
|= DxEPCTL_Stall
+ DxEPCTL_SNAK
;
2819 if (epctl
& DxEPCTL_EPEna
)
2820 epctl
|= DxEPCTL_EPDis
;
2822 epctl
&= ~DxEPCTL_Stall
;
2823 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2824 if (xfertype
== DxEPCTL_EPType_Bulk
||
2825 xfertype
== DxEPCTL_EPType_Intterupt
)
2826 epctl
|= DxEPCTL_SetD0PID
;
2829 writel(epctl
, hs
->regs
+ epreg
);
2831 epreg
= DOEPCTL(index
);
2832 epctl
= readl(hs
->regs
+ epreg
);
2835 epctl
|= DxEPCTL_Stall
;
2837 epctl
&= ~DxEPCTL_Stall
;
2838 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2839 if (xfertype
== DxEPCTL_EPType_Bulk
||
2840 xfertype
== DxEPCTL_EPType_Intterupt
)
2841 epctl
|= DxEPCTL_SetD0PID
;
2844 writel(epctl
, hs
->regs
+ epreg
);
2846 hs_ep
->halted
= value
;
2852 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2853 * @ep: The endpoint to set halt.
2854 * @value: Set or unset the halt.
2856 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
2858 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2859 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2860 unsigned long flags
= 0;
2863 spin_lock_irqsave(&hs
->lock
, flags
);
2864 ret
= s3c_hsotg_ep_sethalt(ep
, value
);
2865 spin_unlock_irqrestore(&hs
->lock
, flags
);
2870 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2871 .enable
= s3c_hsotg_ep_enable
,
2872 .disable
= s3c_hsotg_ep_disable
,
2873 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2874 .free_request
= s3c_hsotg_ep_free_request
,
2875 .queue
= s3c_hsotg_ep_queue_lock
,
2876 .dequeue
= s3c_hsotg_ep_dequeue
,
2877 .set_halt
= s3c_hsotg_ep_sethalt_lock
,
2878 /* note, don't believe we have any call for the fifo routines */
2882 * s3c_hsotg_phy_enable - enable platform phy dev
2883 * @hsotg: The driver state
2885 * A wrapper for platform code responsible for controlling
2886 * low-level USB code
2888 static void s3c_hsotg_phy_enable(struct s3c_hsotg
*hsotg
)
2890 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2892 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2895 usb_phy_init(hsotg
->phy
);
2896 else if (hsotg
->plat
->phy_init
)
2897 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2901 * s3c_hsotg_phy_disable - disable platform phy dev
2902 * @hsotg: The driver state
2904 * A wrapper for platform code responsible for controlling
2905 * low-level USB code
2907 static void s3c_hsotg_phy_disable(struct s3c_hsotg
*hsotg
)
2909 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2912 usb_phy_shutdown(hsotg
->phy
);
2913 else if (hsotg
->plat
->phy_exit
)
2914 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2918 * s3c_hsotg_init - initalize the usb core
2919 * @hsotg: The driver state
2921 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2923 /* unmask subset of endpoint interrupts */
2925 writel(DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2926 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
,
2927 hsotg
->regs
+ DIEPMSK
);
2929 writel(DOEPMSK_SetupMsk
| DOEPMSK_AHBErrMsk
|
2930 DOEPMSK_EPDisbldMsk
| DOEPMSK_XferComplMsk
,
2931 hsotg
->regs
+ DOEPMSK
);
2933 writel(0, hsotg
->regs
+ DAINTMSK
);
2935 /* Be in disconnected state until gadget is registered */
2936 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2939 /* post global nak until we're ready */
2940 writel(DCTL_SGNPInNAK
| DCTL_SGOUTNak
,
2941 hsotg
->regs
+ DCTL
);
2946 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2947 readl(hsotg
->regs
+ GRXFSIZ
),
2948 readl(hsotg
->regs
+ GNPTXFSIZ
));
2950 s3c_hsotg_init_fifo(hsotg
);
2952 /* set the PLL on, remove the HNP/SRP and set the PHY */
2953 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) | (0x5 << 10),
2954 hsotg
->regs
+ GUSBCFG
);
2956 writel(using_dma(hsotg
) ? GAHBCFG_DMAEn
: 0x0,
2957 hsotg
->regs
+ GAHBCFG
);
2961 * s3c_hsotg_udc_start - prepare the udc for work
2962 * @gadget: The usb gadget state
2963 * @driver: The usb gadget driver
2965 * Perform initialization to prepare udc device and driver
2968 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2969 struct usb_gadget_driver
*driver
)
2971 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2975 pr_err("%s: called with no device\n", __func__
);
2980 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2984 if (driver
->max_speed
< USB_SPEED_FULL
)
2985 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2987 if (!driver
->setup
) {
2988 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2992 WARN_ON(hsotg
->driver
);
2994 driver
->driver
.bus
= NULL
;
2995 hsotg
->driver
= driver
;
2996 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
2997 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2999 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3002 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3006 hsotg
->last_rst
= jiffies
;
3007 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
3011 hsotg
->driver
= NULL
;
3016 * s3c_hsotg_udc_stop - stop the udc
3017 * @gadget: The usb gadget state
3018 * @driver: The usb gadget driver
3020 * Stop udc hw block and stay tunned for future transmissions
3022 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
,
3023 struct usb_gadget_driver
*driver
)
3025 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
3026 unsigned long flags
= 0;
3032 /* all endpoints should be shutdown */
3033 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
3034 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
3036 spin_lock_irqsave(&hsotg
->lock
, flags
);
3038 s3c_hsotg_phy_disable(hsotg
);
3041 hsotg
->driver
= NULL
;
3043 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3045 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3047 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3053 * s3c_hsotg_gadget_getframe - read the frame number
3054 * @gadget: The usb gadget state
3056 * Read the {micro} frame number
3058 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
3060 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
3064 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3065 * @gadget: The usb gadget state
3066 * @is_on: Current state of the USB PHY
3068 * Connect/Disconnect the USB PHY pullup
3070 static int s3c_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
3072 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
3073 unsigned long flags
= 0;
3075 dev_dbg(hsotg
->dev
, "%s: is_in: %d\n", __func__
, is_on
);
3077 spin_lock_irqsave(&hsotg
->lock
, flags
);
3079 s3c_hsotg_phy_enable(hsotg
);
3080 s3c_hsotg_core_init(hsotg
);
3082 s3c_hsotg_disconnect(hsotg
);
3083 s3c_hsotg_phy_disable(hsotg
);
3086 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3087 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3092 static const struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
3093 .get_frame
= s3c_hsotg_gadget_getframe
,
3094 .udc_start
= s3c_hsotg_udc_start
,
3095 .udc_stop
= s3c_hsotg_udc_stop
,
3096 .pullup
= s3c_hsotg_pullup
,
3100 * s3c_hsotg_initep - initialise a single endpoint
3101 * @hsotg: The device state.
3102 * @hs_ep: The endpoint to be initialised.
3103 * @epnum: The endpoint number
3105 * Initialise the given endpoint (as part of the probe and device state
3106 * creation) to give to the gadget driver. Setup the endpoint name, any
3107 * direction information and other state that may be required.
3109 static void s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
3110 struct s3c_hsotg_ep
*hs_ep
,
3118 else if ((epnum
% 2) == 0) {
3125 hs_ep
->index
= epnum
;
3127 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3129 INIT_LIST_HEAD(&hs_ep
->queue
);
3130 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3132 /* add to the list of endpoints known by the gadget driver */
3134 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3136 hs_ep
->parent
= hsotg
;
3137 hs_ep
->ep
.name
= hs_ep
->name
;
3138 hs_ep
->ep
.maxpacket
= epnum
? 1024 : EP0_MPS_LIMIT
;
3139 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3142 * Read the FIFO size for the Periodic TX FIFO, even if we're
3143 * an OUT endpoint, we may as well do this if in future the
3144 * code is changed to make each endpoint's direction changeable.
3147 ptxfifo
= readl(hsotg
->regs
+ DPTXFSIZn(epnum
));
3148 hs_ep
->fifo_size
= DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
3151 * if we're using dma, we need to set the next-endpoint pointer
3152 * to be something valid.
3155 if (using_dma(hsotg
)) {
3156 u32 next
= DxEPCTL_NextEp((epnum
+ 1) % 15);
3157 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3158 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3163 * s3c_hsotg_hw_cfg - read HW configuration registers
3164 * @param: The device state
3166 * Read the USB core HW configuration registers
3168 static void s3c_hsotg_hw_cfg(struct s3c_hsotg
*hsotg
)
3171 /* check hardware configuration */
3173 cfg2
= readl(hsotg
->regs
+ 0x48);
3174 hsotg
->num_of_eps
= (cfg2
>> 10) & 0xF;
3176 dev_info(hsotg
->dev
, "EPs:%d\n", hsotg
->num_of_eps
);
3178 cfg4
= readl(hsotg
->regs
+ 0x50);
3179 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
3181 dev_info(hsotg
->dev
, "%s fifos\n",
3182 hsotg
->dedicated_fifos
? "dedicated" : "shared");
3186 * s3c_hsotg_dump - dump state of the udc
3187 * @param: The device state
3189 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
3192 struct device
*dev
= hsotg
->dev
;
3193 void __iomem
*regs
= hsotg
->regs
;
3197 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3198 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3199 readl(regs
+ DIEPMSK
));
3201 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3202 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3204 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3205 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3207 /* show periodic fifo settings */
3209 for (idx
= 1; idx
<= 15; idx
++) {
3210 val
= readl(regs
+ DPTXFSIZn(idx
));
3211 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3212 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3213 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3216 for (idx
= 0; idx
< 15; idx
++) {
3218 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3219 readl(regs
+ DIEPCTL(idx
)),
3220 readl(regs
+ DIEPTSIZ(idx
)),
3221 readl(regs
+ DIEPDMA(idx
)));
3223 val
= readl(regs
+ DOEPCTL(idx
));
3225 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3226 idx
, readl(regs
+ DOEPCTL(idx
)),
3227 readl(regs
+ DOEPTSIZ(idx
)),
3228 readl(regs
+ DOEPDMA(idx
)));
3232 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3233 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3238 * state_show - debugfs: show overall driver and device state.
3239 * @seq: The seq file to write to.
3240 * @v: Unused parameter.
3242 * This debugfs entry shows the overall state of the hardware and
3243 * some general information about each of the endpoints available
3246 static int state_show(struct seq_file
*seq
, void *v
)
3248 struct s3c_hsotg
*hsotg
= seq
->private;
3249 void __iomem
*regs
= hsotg
->regs
;
3252 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3255 readl(regs
+ DSTS
));
3257 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3258 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3260 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3261 readl(regs
+ GINTMSK
),
3262 readl(regs
+ GINTSTS
));
3264 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3265 readl(regs
+ DAINTMSK
),
3266 readl(regs
+ DAINT
));
3268 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3269 readl(regs
+ GNPTXSTS
),
3270 readl(regs
+ GRXSTSR
));
3272 seq_puts(seq
, "\nEndpoint status:\n");
3274 for (idx
= 0; idx
< 15; idx
++) {
3277 in
= readl(regs
+ DIEPCTL(idx
));
3278 out
= readl(regs
+ DOEPCTL(idx
));
3280 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3283 in
= readl(regs
+ DIEPTSIZ(idx
));
3284 out
= readl(regs
+ DOEPTSIZ(idx
));
3286 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3289 seq_puts(seq
, "\n");
3295 static int state_open(struct inode
*inode
, struct file
*file
)
3297 return single_open(file
, state_show
, inode
->i_private
);
3300 static const struct file_operations state_fops
= {
3301 .owner
= THIS_MODULE
,
3304 .llseek
= seq_lseek
,
3305 .release
= single_release
,
3309 * fifo_show - debugfs: show the fifo information
3310 * @seq: The seq_file to write data to.
3311 * @v: Unused parameter.
3313 * Show the FIFO information for the overall fifo and all the
3314 * periodic transmission FIFOs.
3316 static int fifo_show(struct seq_file
*seq
, void *v
)
3318 struct s3c_hsotg
*hsotg
= seq
->private;
3319 void __iomem
*regs
= hsotg
->regs
;
3323 seq_puts(seq
, "Non-periodic FIFOs:\n");
3324 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3326 val
= readl(regs
+ GNPTXFSIZ
);
3327 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3328 val
>> GNPTXFSIZ_NPTxFDep_SHIFT
,
3329 val
& GNPTXFSIZ_NPTxFStAddr_MASK
);
3331 seq_puts(seq
, "\nPeriodic TXFIFOs:\n");
3333 for (idx
= 1; idx
<= 15; idx
++) {
3334 val
= readl(regs
+ DPTXFSIZn(idx
));
3336 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3337 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3338 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3344 static int fifo_open(struct inode
*inode
, struct file
*file
)
3346 return single_open(file
, fifo_show
, inode
->i_private
);
3349 static const struct file_operations fifo_fops
= {
3350 .owner
= THIS_MODULE
,
3353 .llseek
= seq_lseek
,
3354 .release
= single_release
,
3358 static const char *decode_direction(int is_in
)
3360 return is_in
? "in" : "out";
3364 * ep_show - debugfs: show the state of an endpoint.
3365 * @seq: The seq_file to write data to.
3366 * @v: Unused parameter.
3368 * This debugfs entry shows the state of the given endpoint (one is
3369 * registered for each available).
3371 static int ep_show(struct seq_file
*seq
, void *v
)
3373 struct s3c_hsotg_ep
*ep
= seq
->private;
3374 struct s3c_hsotg
*hsotg
= ep
->parent
;
3375 struct s3c_hsotg_req
*req
;
3376 void __iomem
*regs
= hsotg
->regs
;
3377 int index
= ep
->index
;
3378 int show_limit
= 15;
3379 unsigned long flags
;
3381 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3382 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3384 /* first show the register state */
3386 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3387 readl(regs
+ DIEPCTL(index
)),
3388 readl(regs
+ DOEPCTL(index
)));
3390 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3391 readl(regs
+ DIEPDMA(index
)),
3392 readl(regs
+ DOEPDMA(index
)));
3394 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3395 readl(regs
+ DIEPINT(index
)),
3396 readl(regs
+ DOEPINT(index
)));
3398 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3399 readl(regs
+ DIEPTSIZ(index
)),
3400 readl(regs
+ DOEPTSIZ(index
)));
3402 seq_puts(seq
, "\n");
3403 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3404 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3406 seq_printf(seq
, "request list (%p,%p):\n",
3407 ep
->queue
.next
, ep
->queue
.prev
);
3409 spin_lock_irqsave(&hsotg
->lock
, flags
);
3411 list_for_each_entry(req
, &ep
->queue
, queue
) {
3412 if (--show_limit
< 0) {
3413 seq_puts(seq
, "not showing more requests...\n");
3417 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3418 req
== ep
->req
? '*' : ' ',
3419 req
, req
->req
.length
, req
->req
.buf
);
3420 seq_printf(seq
, "%d done, res %d\n",
3421 req
->req
.actual
, req
->req
.status
);
3424 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3429 static int ep_open(struct inode
*inode
, struct file
*file
)
3431 return single_open(file
, ep_show
, inode
->i_private
);
3434 static const struct file_operations ep_fops
= {
3435 .owner
= THIS_MODULE
,
3438 .llseek
= seq_lseek
,
3439 .release
= single_release
,
3443 * s3c_hsotg_create_debug - create debugfs directory and files
3444 * @hsotg: The driver state
3446 * Create the debugfs files to allow the user to get information
3447 * about the state of the system. The directory name is created
3448 * with the same name as the device itself, in case we end up
3449 * with multiple blocks in future systems.
3451 static void s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3453 struct dentry
*root
;
3456 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3457 hsotg
->debug_root
= root
;
3459 dev_err(hsotg
->dev
, "cannot create debug root\n");
3463 /* create general state file */
3465 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3466 hsotg
, &state_fops
);
3468 if (IS_ERR(hsotg
->debug_file
))
3469 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3471 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3474 if (IS_ERR(hsotg
->debug_fifo
))
3475 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3477 /* create one file for each endpoint */
3479 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3480 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3482 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3483 root
, ep
, &ep_fops
);
3485 if (IS_ERR(ep
->debugfs
))
3486 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3492 * s3c_hsotg_delete_debug - cleanup debugfs entries
3493 * @hsotg: The driver state
3495 * Cleanup (remove) the debugfs files for use on module exit.
3497 static void s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3501 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3502 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3503 debugfs_remove(ep
->debugfs
);
3506 debugfs_remove(hsotg
->debug_file
);
3507 debugfs_remove(hsotg
->debug_fifo
);
3508 debugfs_remove(hsotg
->debug_root
);
3512 * s3c_hsotg_probe - probe function for hsotg driver
3513 * @pdev: The platform information for the driver
3516 static int s3c_hsotg_probe(struct platform_device
*pdev
)
3518 struct s3c_hsotg_plat
*plat
= dev_get_platdata(&pdev
->dev
);
3519 struct usb_phy
*phy
;
3520 struct device
*dev
= &pdev
->dev
;
3521 struct s3c_hsotg_ep
*eps
;
3522 struct s3c_hsotg
*hsotg
;
3523 struct resource
*res
;
3528 hsotg
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c_hsotg
), GFP_KERNEL
);
3530 dev_err(dev
, "cannot get memory\n");
3534 phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB2
);
3536 /* Fallback for pdata */
3537 plat
= dev_get_platdata(&pdev
->dev
);
3539 dev_err(&pdev
->dev
, "no platform data or transceiver defined\n");
3540 return -EPROBE_DEFER
;
3550 hsotg
->clk
= devm_clk_get(&pdev
->dev
, "otg");
3551 if (IS_ERR(hsotg
->clk
)) {
3552 dev_err(dev
, "cannot get otg clock\n");
3553 return PTR_ERR(hsotg
->clk
);
3556 platform_set_drvdata(pdev
, hsotg
);
3558 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3560 hsotg
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
3561 if (IS_ERR(hsotg
->regs
)) {
3562 ret
= PTR_ERR(hsotg
->regs
);
3566 ret
= platform_get_irq(pdev
, 0);
3568 dev_err(dev
, "cannot find IRQ\n");
3572 spin_lock_init(&hsotg
->lock
);
3576 ret
= devm_request_irq(&pdev
->dev
, hsotg
->irq
, s3c_hsotg_irq
, 0,
3577 dev_name(dev
), hsotg
);
3579 dev_err(dev
, "cannot claim IRQ\n");
3583 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3585 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3586 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3587 hsotg
->gadget
.name
= dev_name(dev
);
3589 /* reset the system */
3591 clk_prepare_enable(hsotg
->clk
);
3595 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3596 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3598 ret
= devm_regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3601 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3605 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3609 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3613 /* usb phy enable */
3614 s3c_hsotg_phy_enable(hsotg
);
3616 s3c_hsotg_corereset(hsotg
);
3617 s3c_hsotg_init(hsotg
);
3618 s3c_hsotg_hw_cfg(hsotg
);
3620 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3622 if (hsotg
->num_of_eps
== 0) {
3623 dev_err(dev
, "wrong number of EPs (zero)\n");
3628 eps
= kcalloc(hsotg
->num_of_eps
+ 1, sizeof(struct s3c_hsotg_ep
),
3631 dev_err(dev
, "cannot get memory\n");
3638 /* setup endpoint information */
3640 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3641 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3643 /* allocate EP0 request */
3645 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3647 if (!hsotg
->ctrl_req
) {
3648 dev_err(dev
, "failed to allocate ctrl req\n");
3653 /* initialise the endpoints now the core has been initialised */
3654 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++)
3655 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3657 /* disable power and clock */
3659 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3662 dev_err(hsotg
->dev
, "failed to disable supplies: %d\n", ret
);
3666 s3c_hsotg_phy_disable(hsotg
);
3668 ret
= usb_add_gadget_udc(&pdev
->dev
, &hsotg
->gadget
);
3672 s3c_hsotg_create_debug(hsotg
);
3674 s3c_hsotg_dump(hsotg
);
3681 s3c_hsotg_phy_disable(hsotg
);
3683 clk_disable_unprepare(hsotg
->clk
);
3689 * s3c_hsotg_remove - remove function for hsotg driver
3690 * @pdev: The platform information for the driver
3692 static int s3c_hsotg_remove(struct platform_device
*pdev
)
3694 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3696 usb_del_gadget_udc(&hsotg
->gadget
);
3698 s3c_hsotg_delete_debug(hsotg
);
3700 if (hsotg
->driver
) {
3701 /* should have been done already by driver model core */
3702 usb_gadget_unregister_driver(hsotg
->driver
);
3705 s3c_hsotg_phy_disable(hsotg
);
3706 clk_disable_unprepare(hsotg
->clk
);
3712 #define s3c_hsotg_suspend NULL
3713 #define s3c_hsotg_resume NULL
3717 static const struct of_device_id s3c_hsotg_of_ids
[] = {
3718 { .compatible
= "samsung,s3c6400-hsotg", },
3721 MODULE_DEVICE_TABLE(of
, s3c_hsotg_of_ids
);
3724 static struct platform_driver s3c_hsotg_driver
= {
3726 .name
= "s3c-hsotg",
3727 .owner
= THIS_MODULE
,
3728 .of_match_table
= of_match_ptr(s3c_hsotg_of_ids
),
3730 .probe
= s3c_hsotg_probe
,
3731 .remove
= s3c_hsotg_remove
,
3732 .suspend
= s3c_hsotg_suspend
,
3733 .resume
= s3c_hsotg_resume
,
3736 module_platform_driver(s3c_hsotg_driver
);
3738 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3739 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3740 MODULE_LICENSE("GPL");
3741 MODULE_ALIAS("platform:s3c-hsotg");