2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/phy.h>
36 #include <linux/platform_data/s3c-hsotg.h>
40 #include "s3c-hsotg.h"
42 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
44 static const char * const s3c_hsotg_supply_names
[] = {
45 "vusb_d", /* digital USB supply, 1.2V */
46 "vusb_a", /* analog USB supply, 1.1V */
52 * Unfortunately there seems to be a limit of the amount of data that can
53 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
54 * packets (which practically means 1 packet and 63 bytes of data) when the
57 * This means if we are wanting to move >127 bytes of data, we need to
58 * split the transactions up, but just doing one packet at a time does
59 * not work (this may be an implicit DATA0 PID on first packet of the
60 * transaction) and doing 2 packets is outside the controller's limits.
62 * If we try to lower the MPS size for EP0, then no transfers work properly
63 * for EP0, and the system will fail basic enumeration. As no cause for this
64 * has currently been found, we cannot support any large IN transfers for
67 #define EP0_MPS_LIMIT 64
73 * struct s3c_hsotg_ep - driver endpoint definition.
74 * @ep: The gadget layer representation of the endpoint.
75 * @name: The driver generated name for the endpoint.
76 * @queue: Queue of requests for this endpoint.
77 * @parent: Reference back to the parent device structure.
78 * @req: The current request that the endpoint is processing. This is
79 * used to indicate an request has been loaded onto the endpoint
80 * and has yet to be completed (maybe due to data move, or simply
81 * awaiting an ack from the core all the data has been completed).
82 * @debugfs: File entry for debugfs file for this endpoint.
83 * @lock: State lock to protect contents of endpoint.
84 * @dir_in: Set to true if this endpoint is of the IN direction, which
85 * means that it is sending data to the Host.
86 * @index: The index for the endpoint registers.
87 * @name: The name array passed to the USB core.
88 * @halted: Set if the endpoint has been halted.
89 * @periodic: Set if this is a periodic ep, such as Interrupt
90 * @sent_zlp: Set if we've sent a zero-length packet.
91 * @total_data: The total number of data bytes done.
92 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
93 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
94 * @last_load: The offset of data for the last start of request.
95 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
97 * This is the driver's state for each registered enpoint, allowing it
98 * to keep track of transactions that need doing. Each endpoint has a
99 * lock to protect the state, to try and avoid using an overall lock
100 * for the host controller as much as possible.
102 * For periodic IN endpoints, we have fifo_size and fifo_load to try
103 * and keep track of the amount of data in the periodic FIFO for each
104 * of these as we don't have a status register that tells us how much
105 * is in each of them. (note, this may actually be useless information
106 * as in shared-fifo mode periodic in acts like a single-frame packet
107 * buffer than a fifo)
109 struct s3c_hsotg_ep
{
111 struct list_head queue
;
112 struct s3c_hsotg
*parent
;
113 struct s3c_hsotg_req
*req
;
114 struct dentry
*debugfs
;
117 unsigned long total_data
;
118 unsigned int size_loaded
;
119 unsigned int last_load
;
120 unsigned int fifo_load
;
121 unsigned short fifo_size
;
123 unsigned char dir_in
;
126 unsigned int halted
:1;
127 unsigned int periodic
:1;
128 unsigned int sent_zlp
:1;
134 * struct s3c_hsotg - driver state.
135 * @dev: The parent device supplied to the probe function
136 * @driver: USB gadget driver
137 * @phy: The otg phy transceiver structure for phy control.
138 * @plat: The platform specific configuration data. This can be removed once
139 * all SoCs support usb transceiver.
140 * @regs: The memory area mapped for accessing registers.
141 * @irq: The IRQ number we are using
142 * @supplies: Definition of USB power supplies
143 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
144 * @num_of_eps: Number of available EPs (excluding EP0)
145 * @debug_root: root directrory for debugfs.
146 * @debug_file: main status file for debugfs.
147 * @debug_fifo: FIFO status file for debugfs.
148 * @ep0_reply: Request used for ep0 reply.
149 * @ep0_buff: Buffer for EP0 reply data, if needed.
150 * @ctrl_buff: Buffer for EP0 control requests.
151 * @ctrl_req: Request for EP0 control packets.
152 * @setup: NAK management for EP0 SETUP
153 * @last_rst: Time of last reset
154 * @eps: The endpoints being supplied to the gadget framework
158 struct usb_gadget_driver
*driver
;
160 struct s3c_hsotg_plat
*plat
;
168 struct regulator_bulk_data supplies
[ARRAY_SIZE(s3c_hsotg_supply_names
)];
170 unsigned int dedicated_fifos
:1;
171 unsigned char num_of_eps
;
173 struct dentry
*debug_root
;
174 struct dentry
*debug_file
;
175 struct dentry
*debug_fifo
;
177 struct usb_request
*ep0_reply
;
178 struct usb_request
*ctrl_req
;
182 struct usb_gadget gadget
;
184 unsigned long last_rst
;
185 struct s3c_hsotg_ep
*eps
;
189 * struct s3c_hsotg_req - data transfer request
190 * @req: The USB gadget request
191 * @queue: The list of requests for the endpoint this is queued for.
192 * @in_progress: Has already had size/packets written to core
193 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
195 struct s3c_hsotg_req
{
196 struct usb_request req
;
197 struct list_head queue
;
198 unsigned char in_progress
;
199 unsigned char mapped
;
202 /* conversion functions */
203 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
205 return container_of(req
, struct s3c_hsotg_req
, req
);
208 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
210 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
213 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
215 return container_of(gadget
, struct s3c_hsotg
, gadget
);
218 static inline void __orr32(void __iomem
*ptr
, u32 val
)
220 writel(readl(ptr
) | val
, ptr
);
223 static inline void __bic32(void __iomem
*ptr
, u32 val
)
225 writel(readl(ptr
) & ~val
, ptr
);
228 /* forward decleration of functions */
229 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
232 * using_dma - return the DMA status of the driver.
233 * @hsotg: The driver state.
235 * Return true if we're using DMA.
237 * Currently, we have the DMA support code worked into everywhere
238 * that needs it, but the AMBA DMA implementation in the hardware can
239 * only DMA from 32bit aligned addresses. This means that gadgets such
240 * as the CDC Ethernet cannot work as they often pass packets which are
243 * Unfortunately the choice to use DMA or not is global to the controller
244 * and seems to be only settable when the controller is being put through
245 * a core reset. This means we either need to fix the gadgets to take
246 * account of DMA alignment, or add bounce buffers (yuerk).
248 * Until this issue is sorted out, we always return 'false'.
250 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
252 return false; /* support is not complete */
256 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
257 * @hsotg: The device state
258 * @ints: A bitmask of the interrupts to enable
260 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
262 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
265 new_gsintmsk
= gsintmsk
| ints
;
267 if (new_gsintmsk
!= gsintmsk
) {
268 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
269 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
274 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
275 * @hsotg: The device state
276 * @ints: A bitmask of the interrupts to enable
278 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
280 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
283 new_gsintmsk
= gsintmsk
& ~ints
;
285 if (new_gsintmsk
!= gsintmsk
)
286 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
290 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
291 * @hsotg: The device state
292 * @ep: The endpoint index
293 * @dir_in: True if direction is in.
294 * @en: The enable value, true to enable
296 * Set or clear the mask for an individual endpoint's interrupt
299 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
300 unsigned int ep
, unsigned int dir_in
,
310 local_irq_save(flags
);
311 daint
= readl(hsotg
->regs
+ DAINTMSK
);
316 writel(daint
, hsotg
->regs
+ DAINTMSK
);
317 local_irq_restore(flags
);
321 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
322 * @hsotg: The device instance.
324 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
332 /* set FIFO sizes to 2048/1024 */
334 writel(2048, hsotg
->regs
+ GRXFSIZ
);
335 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
336 GNPTXFSIZ_NPTxFDep(1024),
337 hsotg
->regs
+ GNPTXFSIZ
);
340 * arange all the rest of the TX FIFOs, as some versions of this
341 * block have overlapping default addresses. This also ensures
342 * that if the settings have been changed, then they are set to
346 /* start at the end of the GNPTXFSIZ, rounded up */
351 * currently we allocate TX FIFOs for all possible endpoints,
352 * and assume that they are all the same size.
355 for (ep
= 1; ep
<= 15; ep
++) {
357 val
|= size
<< DPTXFSIZn_DPTxFSize_SHIFT
;
360 writel(val
, hsotg
->regs
+ DPTXFSIZn(ep
));
364 * according to p428 of the design guide, we need to ensure that
365 * all fifos are flushed before continuing
368 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh
|
369 GRSTCTL_RxFFlsh
, hsotg
->regs
+ GRSTCTL
);
371 /* wait until the fifos are both flushed */
374 val
= readl(hsotg
->regs
+ GRSTCTL
);
376 if ((val
& (GRSTCTL_TxFFlsh
| GRSTCTL_RxFFlsh
)) == 0)
379 if (--timeout
== 0) {
381 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
388 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
392 * @ep: USB endpoint to allocate request for.
393 * @flags: Allocation flags
395 * Allocate a new USB request structure appropriate for the specified endpoint
397 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
400 struct s3c_hsotg_req
*req
;
402 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
406 INIT_LIST_HEAD(&req
->queue
);
408 req
->req
.dma
= DMA_ADDR_INVALID
;
413 * is_ep_periodic - return true if the endpoint is in periodic mode.
414 * @hs_ep: The endpoint to query.
416 * Returns true if the endpoint is in periodic mode, meaning it is being
417 * used for an Interrupt or ISO transfer.
419 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
421 return hs_ep
->periodic
;
425 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
426 * @hsotg: The device state.
427 * @hs_ep: The endpoint for the request
428 * @hs_req: The request being processed.
430 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
431 * of a request to ensure the buffer is ready for access by the caller.
433 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
434 struct s3c_hsotg_ep
*hs_ep
,
435 struct s3c_hsotg_req
*hs_req
)
437 struct usb_request
*req
= &hs_req
->req
;
438 enum dma_data_direction dir
;
440 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
442 /* ignore this if we're not moving any data */
443 if (hs_req
->req
.length
== 0)
446 if (hs_req
->mapped
) {
447 /* we mapped this, so unmap and remove the dma */
449 dma_unmap_single(hsotg
->dev
, req
->dma
, req
->length
, dir
);
451 req
->dma
= DMA_ADDR_INVALID
;
454 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
459 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
460 * @hsotg: The controller state.
461 * @hs_ep: The endpoint we're going to write for.
462 * @hs_req: The request to write data for.
464 * This is called when the TxFIFO has some space in it to hold a new
465 * transmission and we have something to give it. The actual setup of
466 * the data size is done elsewhere, so all we have to do is to actually
469 * The return value is zero if there is more space (or nothing was done)
470 * otherwise -ENOSPC is returned if the FIFO space was used up.
472 * This routine is only needed for PIO
474 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
475 struct s3c_hsotg_ep
*hs_ep
,
476 struct s3c_hsotg_req
*hs_req
)
478 bool periodic
= is_ep_periodic(hs_ep
);
479 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
480 int buf_pos
= hs_req
->req
.actual
;
481 int to_write
= hs_ep
->size_loaded
;
486 to_write
-= (buf_pos
- hs_ep
->last_load
);
488 /* if there's nothing to write, get out early */
492 if (periodic
&& !hsotg
->dedicated_fifos
) {
493 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
498 * work out how much data was loaded so we can calculate
499 * how much data is left in the fifo.
502 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
505 * if shared fifo, we cannot write anything until the
506 * previous data has been completely sent.
508 if (hs_ep
->fifo_load
!= 0) {
509 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
513 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
515 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
517 /* how much of the data has moved */
518 size_done
= hs_ep
->size_loaded
- size_left
;
520 /* how much data is left in the fifo */
521 can_write
= hs_ep
->fifo_load
- size_done
;
522 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
523 __func__
, can_write
);
525 can_write
= hs_ep
->fifo_size
- can_write
;
526 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
527 __func__
, can_write
);
529 if (can_write
<= 0) {
530 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
533 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
534 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
539 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
541 "%s: no queue slots available (0x%08x)\n",
544 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTxFEmp
);
548 can_write
= GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
549 can_write
*= 4; /* fifo size is in 32bit quantities. */
552 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
553 __func__
, gnptxsts
, can_write
, to_write
, hs_ep
->ep
.maxpacket
);
556 * limit to 512 bytes of data, it seems at least on the non-periodic
557 * FIFO, requests of >512 cause the endpoint to get stuck with a
558 * fragment of the end of the transfer in it.
564 * limit the write to one max-packet size worth of data, but allow
565 * the transfer to return that it did not run out of fifo space
568 if (to_write
> hs_ep
->ep
.maxpacket
) {
569 to_write
= hs_ep
->ep
.maxpacket
;
571 s3c_hsotg_en_gsint(hsotg
,
572 periodic
? GINTSTS_PTxFEmp
:
576 /* see if we can write data */
578 if (to_write
> can_write
) {
579 to_write
= can_write
;
580 pkt_round
= to_write
% hs_ep
->ep
.maxpacket
;
583 * Round the write down to an
584 * exact number of packets.
586 * Note, we do not currently check to see if we can ever
587 * write a full packet or not to the FIFO.
591 to_write
-= pkt_round
;
594 * enable correct FIFO interrupt to alert us when there
598 s3c_hsotg_en_gsint(hsotg
,
599 periodic
? GINTSTS_PTxFEmp
:
603 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
604 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
609 hs_req
->req
.actual
= buf_pos
+ to_write
;
610 hs_ep
->total_data
+= to_write
;
613 hs_ep
->fifo_load
+= to_write
;
615 to_write
= DIV_ROUND_UP(to_write
, 4);
616 data
= hs_req
->req
.buf
+ buf_pos
;
618 writesl(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
620 return (to_write
>= can_write
) ? -ENOSPC
: 0;
624 * get_ep_limit - get the maximum data legnth for this endpoint
625 * @hs_ep: The endpoint
627 * Return the maximum data that can be queued in one go on a given endpoint
628 * so that transfers that are too long can be split.
630 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
632 int index
= hs_ep
->index
;
637 maxsize
= DxEPTSIZ_XferSize_LIMIT
+ 1;
638 maxpkt
= DxEPTSIZ_PktCnt_LIMIT
+ 1;
642 maxpkt
= DIEPTSIZ0_PktCnt_LIMIT
+ 1;
647 /* we made the constant loading easier above by using +1 */
652 * constrain by packet count if maxpkts*pktsize is greater
653 * than the length register size.
656 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
657 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
663 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
664 * @hsotg: The controller state.
665 * @hs_ep: The endpoint to process a request for
666 * @hs_req: The request to start.
667 * @continuing: True if we are doing more for the current request.
669 * Start the given request running by setting the endpoint registers
670 * appropriately, and writing any data to the FIFOs.
672 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
673 struct s3c_hsotg_ep
*hs_ep
,
674 struct s3c_hsotg_req
*hs_req
,
677 struct usb_request
*ureq
= &hs_req
->req
;
678 int index
= hs_ep
->index
;
679 int dir_in
= hs_ep
->dir_in
;
689 if (hs_ep
->req
&& !continuing
) {
690 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
693 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
695 "%s: continue different req\n", __func__
);
701 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
702 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
704 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
705 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
706 hs_ep
->dir_in
? "in" : "out");
708 /* If endpoint is stalled, we will restart request later */
709 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
711 if (ctrl
& DxEPCTL_Stall
) {
712 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
716 length
= ureq
->length
- ureq
->actual
;
717 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
718 ureq
->length
, ureq
->actual
);
721 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
722 ureq
->buf
, length
, ureq
->dma
,
723 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
725 maxreq
= get_ep_limit(hs_ep
);
726 if (length
> maxreq
) {
727 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
729 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
730 __func__
, length
, maxreq
, round
);
732 /* round down to multiple of packets */
740 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
742 packets
= 1; /* send one packet if length is zero. */
744 if (dir_in
&& index
!= 0)
745 epsize
= DxEPTSIZ_MC(1);
749 if (index
!= 0 && ureq
->zero
) {
751 * test for the packets being exactly right for the
755 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
759 epsize
|= DxEPTSIZ_PktCnt(packets
);
760 epsize
|= DxEPTSIZ_XferSize(length
);
762 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
763 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
765 /* store the request as the current one we're doing */
768 /* write size / packets */
769 writel(epsize
, hsotg
->regs
+ epsize_reg
);
771 if (using_dma(hsotg
) && !continuing
) {
772 unsigned int dma_reg
;
775 * write DMA address to control register, buffer already
776 * synced by s3c_hsotg_ep_queue().
779 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
780 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
782 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
783 __func__
, ureq
->dma
, dma_reg
);
786 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
787 ctrl
|= DxEPCTL_USBActEp
;
789 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
791 /* For Setup request do not clear NAK */
792 if (hsotg
->setup
&& index
== 0)
795 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
798 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
799 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
802 * set these, it seems that DMA support increments past the end
803 * of the packet buffer so we need to calculate the length from
806 hs_ep
->size_loaded
= length
;
807 hs_ep
->last_load
= ureq
->actual
;
809 if (dir_in
&& !using_dma(hsotg
)) {
810 /* set these anyway, we may need them for non-periodic in */
811 hs_ep
->fifo_load
= 0;
813 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
817 * clear the INTknTXFEmpMsk when we start request, more as a aide
818 * to debugging to see what is going on.
821 writel(DIEPMSK_INTknTXFEmpMsk
,
822 hsotg
->regs
+ DIEPINT(index
));
825 * Note, trying to clear the NAK here causes problems with transmit
826 * on the S3C6400 ending up with the TXFIFO becoming full.
829 /* check ep is enabled */
830 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DxEPCTL_EPEna
))
832 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
833 index
, readl(hsotg
->regs
+ epctrl_reg
));
835 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
836 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
840 * s3c_hsotg_map_dma - map the DMA memory being used for the request
841 * @hsotg: The device state.
842 * @hs_ep: The endpoint the request is on.
843 * @req: The request being processed.
845 * We've been asked to queue a request, so ensure that the memory buffer
846 * is correctly setup for DMA. If we've been passed an extant DMA address
847 * then ensure the buffer has been synced to memory. If our buffer has no
848 * DMA memory, then we map the memory and mark our request to allow us to
849 * cleanup on completion.
851 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
852 struct s3c_hsotg_ep
*hs_ep
,
853 struct usb_request
*req
)
855 enum dma_data_direction dir
;
856 struct s3c_hsotg_req
*hs_req
= our_req(req
);
858 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
860 /* if the length is zero, ignore the DMA data */
861 if (hs_req
->req
.length
== 0)
864 if (req
->dma
== DMA_ADDR_INVALID
) {
867 dma
= dma_map_single(hsotg
->dev
, req
->buf
, req
->length
, dir
);
869 if (unlikely(dma_mapping_error(hsotg
->dev
, dma
)))
873 dev_err(hsotg
->dev
, "%s: unaligned dma buffer\n",
876 dma_unmap_single(hsotg
->dev
, dma
, req
->length
, dir
);
883 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
890 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
891 __func__
, req
->buf
, req
->length
);
896 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
899 struct s3c_hsotg_req
*hs_req
= our_req(req
);
900 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
901 struct s3c_hsotg
*hs
= hs_ep
->parent
;
904 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
905 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
906 req
->zero
, req
->short_not_ok
);
908 /* initialise status of the request */
909 INIT_LIST_HEAD(&hs_req
->queue
);
911 req
->status
= -EINPROGRESS
;
913 /* if we're using DMA, sync the buffers as necessary */
915 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
920 first
= list_empty(&hs_ep
->queue
);
921 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
924 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
929 static int s3c_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
932 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
933 struct s3c_hsotg
*hs
= hs_ep
->parent
;
934 unsigned long flags
= 0;
937 spin_lock_irqsave(&hs
->lock
, flags
);
938 ret
= s3c_hsotg_ep_queue(ep
, req
, gfp_flags
);
939 spin_unlock_irqrestore(&hs
->lock
, flags
);
944 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
945 struct usb_request
*req
)
947 struct s3c_hsotg_req
*hs_req
= our_req(req
);
953 * s3c_hsotg_complete_oursetup - setup completion callback
954 * @ep: The endpoint the request was on.
955 * @req: The request completed.
957 * Called on completion of any requests the driver itself
958 * submitted that need cleaning up.
960 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
961 struct usb_request
*req
)
963 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
964 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
966 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
968 s3c_hsotg_ep_free_request(ep
, req
);
972 * ep_from_windex - convert control wIndex value to endpoint
973 * @hsotg: The driver state.
974 * @windex: The control request wIndex field (in host order).
976 * Convert the given wIndex into a pointer to an driver endpoint
977 * structure, or return NULL if it is not a valid endpoint.
979 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
982 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
983 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
984 int idx
= windex
& 0x7F;
989 if (idx
> hsotg
->num_of_eps
)
992 if (idx
&& ep
->dir_in
!= dir
)
999 * s3c_hsotg_send_reply - send reply to control request
1000 * @hsotg: The device state
1002 * @buff: Buffer for request
1003 * @length: Length of reply.
1005 * Create a request and queue it on the given endpoint. This is useful as
1006 * an internal method of sending replies to certain control requests, etc.
1008 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
1009 struct s3c_hsotg_ep
*ep
,
1013 struct usb_request
*req
;
1016 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1018 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1019 hsotg
->ep0_reply
= req
;
1021 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1025 req
->buf
= hsotg
->ep0_buff
;
1026 req
->length
= length
;
1027 req
->zero
= 1; /* always do zero-length final transfer */
1028 req
->complete
= s3c_hsotg_complete_oursetup
;
1031 memcpy(req
->buf
, buff
, length
);
1035 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1037 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1045 * s3c_hsotg_process_req_status - process request GET_STATUS
1046 * @hsotg: The device state
1047 * @ctrl: USB control request
1049 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
1050 struct usb_ctrlrequest
*ctrl
)
1052 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1053 struct s3c_hsotg_ep
*ep
;
1057 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1060 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1064 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1065 case USB_RECIP_DEVICE
:
1066 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1067 * bit 1 => remote wakeup */
1070 case USB_RECIP_INTERFACE
:
1071 /* currently, the data result should be zero */
1072 reply
= cpu_to_le16(0);
1075 case USB_RECIP_ENDPOINT
:
1076 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1080 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1087 if (le16_to_cpu(ctrl
->wLength
) != 2)
1090 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1092 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1099 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1102 * get_ep_head - return the first request on the endpoint
1103 * @hs_ep: The controller endpoint to get
1105 * Get the first request on the endpoint.
1107 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1109 if (list_empty(&hs_ep
->queue
))
1112 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1116 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1117 * @hsotg: The device state
1118 * @ctrl: USB control request
1120 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1121 struct usb_ctrlrequest
*ctrl
)
1123 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1124 struct s3c_hsotg_req
*hs_req
;
1126 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1127 struct s3c_hsotg_ep
*ep
;
1130 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1131 __func__
, set
? "SET" : "CLEAR");
1133 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1134 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1136 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1137 __func__
, le16_to_cpu(ctrl
->wIndex
));
1141 switch (le16_to_cpu(ctrl
->wValue
)) {
1142 case USB_ENDPOINT_HALT
:
1143 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1145 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1148 "%s: failed to send reply\n", __func__
);
1154 * If we have request in progress,
1160 list_del_init(&hs_req
->queue
);
1161 hs_req
->req
.complete(&ep
->ep
,
1165 /* If we have pending request, then start it */
1166 restart
= !list_empty(&ep
->queue
);
1168 hs_req
= get_ep_head(ep
);
1169 s3c_hsotg_start_req(hsotg
, ep
,
1180 return -ENOENT
; /* currently only deal with endpoint */
1186 * s3c_hsotg_process_control - process a control request
1187 * @hsotg: The device state
1188 * @ctrl: The control request received
1190 * The controller has received the SETUP phase of a control request, and
1191 * needs to work out what to do next (and whether to pass it on to the
1194 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1195 struct usb_ctrlrequest
*ctrl
)
1197 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1203 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1204 ctrl
->bRequest
, ctrl
->bRequestType
,
1205 ctrl
->wValue
, ctrl
->wLength
);
1208 * record the direction of the request, for later use when enquing
1212 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1213 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1216 * if we've no data with this request, then the last part of the
1217 * transaction is going to implicitly be IN.
1219 if (ctrl
->wLength
== 0)
1222 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1223 switch (ctrl
->bRequest
) {
1224 case USB_REQ_SET_ADDRESS
:
1225 dcfg
= readl(hsotg
->regs
+ DCFG
);
1226 dcfg
&= ~DCFG_DevAddr_MASK
;
1227 dcfg
|= ctrl
->wValue
<< DCFG_DevAddr_SHIFT
;
1228 writel(dcfg
, hsotg
->regs
+ DCFG
);
1230 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1232 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1235 case USB_REQ_GET_STATUS
:
1236 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1239 case USB_REQ_CLEAR_FEATURE
:
1240 case USB_REQ_SET_FEATURE
:
1241 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1246 /* as a fallback, try delivering it to the driver to deal with */
1248 if (ret
== 0 && hsotg
->driver
) {
1249 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1251 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1255 * the request is either unhandlable, or is not formatted correctly
1256 * so respond with a STALL for the status stage to indicate failure.
1263 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1264 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1267 * DxEPCTL_Stall will be cleared by EP once it has
1268 * taken effect, so no need to clear later.
1271 ctrl
= readl(hsotg
->regs
+ reg
);
1272 ctrl
|= DxEPCTL_Stall
;
1273 ctrl
|= DxEPCTL_CNAK
;
1274 writel(ctrl
, hsotg
->regs
+ reg
);
1277 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1278 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1281 * don't believe we need to anything more to get the EP
1282 * to reply with a STALL packet
1287 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1290 * s3c_hsotg_complete_setup - completion of a setup transfer
1291 * @ep: The endpoint the request was on.
1292 * @req: The request completed.
1294 * Called on completion of any requests the driver itself submitted for
1297 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1298 struct usb_request
*req
)
1300 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1301 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1303 if (req
->status
< 0) {
1304 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1308 if (req
->actual
== 0)
1309 s3c_hsotg_enqueue_setup(hsotg
);
1311 s3c_hsotg_process_control(hsotg
, req
->buf
);
1315 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1316 * @hsotg: The device state.
1318 * Enqueue a request on EP0 if necessary to received any SETUP packets
1319 * received from the host.
1321 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1323 struct usb_request
*req
= hsotg
->ctrl_req
;
1324 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1327 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1331 req
->buf
= hsotg
->ctrl_buff
;
1332 req
->complete
= s3c_hsotg_complete_setup
;
1334 if (!list_empty(&hs_req
->queue
)) {
1335 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1339 hsotg
->eps
[0].dir_in
= 0;
1341 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1343 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1345 * Don't think there's much we can do other than watch the
1352 * s3c_hsotg_complete_request - complete a request given to us
1353 * @hsotg: The device state.
1354 * @hs_ep: The endpoint the request was on.
1355 * @hs_req: The request to complete.
1356 * @result: The result code (0 => Ok, otherwise errno)
1358 * The given request has finished, so call the necessary completion
1359 * if it has one and then look to see if we can start a new request
1362 * Note, expects the ep to already be locked as appropriate.
1364 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1365 struct s3c_hsotg_ep
*hs_ep
,
1366 struct s3c_hsotg_req
*hs_req
,
1372 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1376 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1377 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1380 * only replace the status if we've not already set an error
1381 * from a previous transaction
1384 if (hs_req
->req
.status
== -EINPROGRESS
)
1385 hs_req
->req
.status
= result
;
1388 list_del_init(&hs_req
->queue
);
1390 if (using_dma(hsotg
))
1391 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1394 * call the complete request with the locks off, just in case the
1395 * request tries to queue more work for this endpoint.
1398 if (hs_req
->req
.complete
) {
1399 spin_unlock(&hsotg
->lock
);
1400 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1401 spin_lock(&hsotg
->lock
);
1405 * Look to see if there is anything else to do. Note, the completion
1406 * of the previous request may have caused a new request to be started
1407 * so be careful when doing this.
1410 if (!hs_ep
->req
&& result
>= 0) {
1411 restart
= !list_empty(&hs_ep
->queue
);
1413 hs_req
= get_ep_head(hs_ep
);
1414 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1420 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1421 * @hsotg: The device state.
1422 * @ep_idx: The endpoint index for the data
1423 * @size: The size of data in the fifo, in bytes
1425 * The FIFO status shows there is data to read from the FIFO for a given
1426 * endpoint, so sort out whether we need to read the data into a request
1427 * that has been made for that endpoint.
1429 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1431 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1432 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1433 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1440 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1443 dev_warn(hsotg
->dev
,
1444 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1445 __func__
, size
, ep_idx
, epctl
);
1447 /* dump the data from the FIFO, we've nothing we can do */
1448 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1455 read_ptr
= hs_req
->req
.actual
;
1456 max_req
= hs_req
->req
.length
- read_ptr
;
1458 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1459 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1461 if (to_read
> max_req
) {
1463 * more data appeared than we where willing
1464 * to deal with in this request.
1467 /* currently we don't deal this */
1471 hs_ep
->total_data
+= to_read
;
1472 hs_req
->req
.actual
+= to_read
;
1473 to_read
= DIV_ROUND_UP(to_read
, 4);
1476 * note, we might over-write the buffer end by 3 bytes depending on
1477 * alignment of the data.
1479 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1483 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1484 * @hsotg: The device instance
1485 * @req: The request currently on this endpoint
1487 * Generate a zero-length IN packet request for terminating a SETUP
1490 * Note, since we don't write any data to the TxFIFO, then it is
1491 * currently believed that we do not need to wait for any space in
1494 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1495 struct s3c_hsotg_req
*req
)
1500 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1504 if (req
->req
.length
== 0) {
1505 hsotg
->eps
[0].sent_zlp
= 1;
1506 s3c_hsotg_enqueue_setup(hsotg
);
1510 hsotg
->eps
[0].dir_in
= 1;
1511 hsotg
->eps
[0].sent_zlp
= 1;
1513 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1515 /* issue a zero-sized packet to terminate this */
1516 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1517 DxEPTSIZ_XferSize(0), hsotg
->regs
+ DIEPTSIZ(0));
1519 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1520 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
1521 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
1522 ctrl
|= DxEPCTL_USBActEp
;
1523 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1527 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1528 * @hsotg: The device instance
1529 * @epnum: The endpoint received from
1530 * @was_setup: Set if processing a SetupDone event.
1532 * The RXFIFO has delivered an OutDone event, which means that the data
1533 * transfer for an OUT endpoint has been completed, either by a short
1534 * packet or by the finish of a transfer.
1536 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1537 int epnum
, bool was_setup
)
1539 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1540 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1541 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1542 struct usb_request
*req
= &hs_req
->req
;
1543 unsigned size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1547 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1551 if (using_dma(hsotg
)) {
1555 * Calculate the size of the transfer by checking how much
1556 * is left in the endpoint size register and then working it
1557 * out from the amount we loaded for the transfer.
1559 * We need to do this as DMA pointers are always 32bit aligned
1560 * so may overshoot/undershoot the transfer.
1563 size_done
= hs_ep
->size_loaded
- size_left
;
1564 size_done
+= hs_ep
->last_load
;
1566 req
->actual
= size_done
;
1569 /* if there is more request to do, schedule new transfer */
1570 if (req
->actual
< req
->length
&& size_left
== 0) {
1571 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1573 } else if (epnum
== 0) {
1575 * After was_setup = 1 =>
1576 * set CNAK for non Setup requests
1578 hsotg
->setup
= was_setup
? 0 : 1;
1581 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1582 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1583 __func__
, req
->actual
, req
->length
);
1586 * todo - what should we return here? there's no one else
1587 * even bothering to check the status.
1593 * Condition req->complete != s3c_hsotg_complete_setup says:
1594 * send ZLP when we have an asynchronous request from gadget
1596 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1597 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1600 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1604 * s3c_hsotg_read_frameno - read current frame number
1605 * @hsotg: The device instance
1607 * Return the current frame number
1609 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1613 dsts
= readl(hsotg
->regs
+ DSTS
);
1614 dsts
&= DSTS_SOFFN_MASK
;
1615 dsts
>>= DSTS_SOFFN_SHIFT
;
1621 * s3c_hsotg_handle_rx - RX FIFO has data
1622 * @hsotg: The device instance
1624 * The IRQ handler has detected that the RX FIFO has some data in it
1625 * that requires processing, so find out what is in there and do the
1628 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1629 * chunks, so if you have x packets received on an endpoint you'll get x
1630 * FIFO events delivered, each with a packet's worth of data in it.
1632 * When using DMA, we should not be processing events from the RXFIFO
1633 * as the actual data should be sent to the memory directly and we turn
1634 * on the completion interrupts to get notifications of transfer completion.
1636 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1638 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1639 u32 epnum
, status
, size
;
1641 WARN_ON(using_dma(hsotg
));
1643 epnum
= grxstsr
& GRXSTS_EPNum_MASK
;
1644 status
= grxstsr
& GRXSTS_PktSts_MASK
;
1646 size
= grxstsr
& GRXSTS_ByteCnt_MASK
;
1647 size
>>= GRXSTS_ByteCnt_SHIFT
;
1650 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1651 __func__
, grxstsr
, size
, epnum
);
1653 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1655 switch (status
>> GRXSTS_PktSts_SHIFT
) {
1656 case __status(GRXSTS_PktSts_GlobalOutNAK
):
1657 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1660 case __status(GRXSTS_PktSts_OutDone
):
1661 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1662 s3c_hsotg_read_frameno(hsotg
));
1664 if (!using_dma(hsotg
))
1665 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1668 case __status(GRXSTS_PktSts_SetupDone
):
1670 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1671 s3c_hsotg_read_frameno(hsotg
),
1672 readl(hsotg
->regs
+ DOEPCTL(0)));
1674 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1677 case __status(GRXSTS_PktSts_OutRX
):
1678 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1681 case __status(GRXSTS_PktSts_SetupRX
):
1683 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1684 s3c_hsotg_read_frameno(hsotg
),
1685 readl(hsotg
->regs
+ DOEPCTL(0)));
1687 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1691 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1694 s3c_hsotg_dump(hsotg
);
1700 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1701 * @mps: The maximum packet size in bytes.
1703 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1707 return D0EPCTL_MPS_64
;
1709 return D0EPCTL_MPS_32
;
1711 return D0EPCTL_MPS_16
;
1713 return D0EPCTL_MPS_8
;
1716 /* bad max packet size, warn and return invalid result */
1722 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1723 * @hsotg: The driver state.
1724 * @ep: The index number of the endpoint
1725 * @mps: The maximum packet size in bytes
1727 * Configure the maximum packet size for the given endpoint, updating
1728 * the hardware control registers to reflect this.
1730 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1731 unsigned int ep
, unsigned int mps
)
1733 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1734 void __iomem
*regs
= hsotg
->regs
;
1739 /* EP0 is a special case */
1740 mpsval
= s3c_hsotg_ep0_mps(mps
);
1744 if (mps
>= DxEPCTL_MPS_LIMIT
+1)
1750 hs_ep
->ep
.maxpacket
= mps
;
1753 * update both the in and out endpoint controldir_ registers, even
1754 * if one of the directions may not be in use.
1757 reg
= readl(regs
+ DIEPCTL(ep
));
1758 reg
&= ~DxEPCTL_MPS_MASK
;
1760 writel(reg
, regs
+ DIEPCTL(ep
));
1763 reg
= readl(regs
+ DOEPCTL(ep
));
1764 reg
&= ~DxEPCTL_MPS_MASK
;
1766 writel(reg
, regs
+ DOEPCTL(ep
));
1772 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1776 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1777 * @hsotg: The driver state
1778 * @idx: The index for the endpoint (0..15)
1780 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg
*hsotg
, unsigned int idx
)
1785 writel(GRSTCTL_TxFNum(idx
) | GRSTCTL_TxFFlsh
,
1786 hsotg
->regs
+ GRSTCTL
);
1788 /* wait until the fifo is flushed */
1792 val
= readl(hsotg
->regs
+ GRSTCTL
);
1794 if ((val
& (GRSTCTL_TxFFlsh
)) == 0)
1797 if (--timeout
== 0) {
1799 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1808 * s3c_hsotg_trytx - check to see if anything needs transmitting
1809 * @hsotg: The driver state
1810 * @hs_ep: The driver endpoint to check.
1812 * Check to see if there is a request that has data to send, and if so
1813 * make an attempt to write data into the FIFO.
1815 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1816 struct s3c_hsotg_ep
*hs_ep
)
1818 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1820 if (!hs_ep
->dir_in
|| !hs_req
)
1823 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1824 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1826 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1833 * s3c_hsotg_complete_in - complete IN transfer
1834 * @hsotg: The device state.
1835 * @hs_ep: The endpoint that has just completed.
1837 * An IN transfer has been completed, update the transfer's state and then
1838 * call the relevant completion routines.
1840 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1841 struct s3c_hsotg_ep
*hs_ep
)
1843 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1844 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1845 int size_left
, size_done
;
1848 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1852 /* Finish ZLP handling for IN EP0 transactions */
1853 if (hsotg
->eps
[0].sent_zlp
) {
1854 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1855 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1860 * Calculate the size of the transfer by checking how much is left
1861 * in the endpoint size register and then working it out from
1862 * the amount we loaded for the transfer.
1864 * We do this even for DMA, as the transfer may have incremented
1865 * past the end of the buffer (DMA transfers are always 32bit
1869 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1871 size_done
= hs_ep
->size_loaded
- size_left
;
1872 size_done
+= hs_ep
->last_load
;
1874 if (hs_req
->req
.actual
!= size_done
)
1875 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1876 __func__
, hs_req
->req
.actual
, size_done
);
1878 hs_req
->req
.actual
= size_done
;
1879 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1880 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1883 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1884 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1885 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1886 * inform the host that no more data is available.
1887 * The state of req.zero member is checked to be sure that the value to
1888 * send is smaller than wValue expected from host.
1889 * Check req.length to NOT send another ZLP when the current one is
1890 * under completion (the one for which this completion has been called).
1892 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1893 hs_req
->req
.length
== hs_req
->req
.actual
&&
1894 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1896 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1897 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1902 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1903 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1904 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1906 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1910 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1911 * @hsotg: The driver state
1912 * @idx: The index for the endpoint (0..15)
1913 * @dir_in: Set if this is an IN endpoint
1915 * Process and clear any interrupt pending for an individual endpoint
1917 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1920 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1921 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1922 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1923 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1926 ints
= readl(hsotg
->regs
+ epint_reg
);
1928 /* Clear endpoint interrupts */
1929 writel(ints
, hsotg
->regs
+ epint_reg
);
1931 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1932 __func__
, idx
, dir_in
? "in" : "out", ints
);
1934 if (ints
& DxEPINT_XferCompl
) {
1936 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1937 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1938 readl(hsotg
->regs
+ epsiz_reg
));
1941 * we get OutDone from the FIFO, so we only need to look
1942 * at completing IN requests here
1945 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1947 if (idx
== 0 && !hs_ep
->req
)
1948 s3c_hsotg_enqueue_setup(hsotg
);
1949 } else if (using_dma(hsotg
)) {
1951 * We're using DMA, we need to fire an OutDone here
1952 * as we ignore the RXFIFO.
1955 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1959 if (ints
& DxEPINT_EPDisbld
) {
1960 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1963 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1965 s3c_hsotg_txfifo_flush(hsotg
, idx
);
1967 if ((epctl
& DxEPCTL_Stall
) &&
1968 (epctl
& DxEPCTL_EPType_Bulk
)) {
1969 int dctl
= readl(hsotg
->regs
+ DCTL
);
1971 dctl
|= DCTL_CGNPInNAK
;
1972 writel(dctl
, hsotg
->regs
+ DCTL
);
1977 if (ints
& DxEPINT_AHBErr
)
1978 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1980 if (ints
& DxEPINT_Setup
) { /* Setup or Timeout */
1981 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1983 if (using_dma(hsotg
) && idx
== 0) {
1985 * this is the notification we've received a
1986 * setup packet. In non-DMA mode we'd get this
1987 * from the RXFIFO, instead we need to process
1994 s3c_hsotg_handle_outdone(hsotg
, 0, true);
1998 if (ints
& DxEPINT_Back2BackSetup
)
1999 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2002 /* not sure if this is important, but we'll clear it anyway */
2003 if (ints
& DIEPMSK_INTknTXFEmpMsk
) {
2004 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2008 /* this probably means something bad is happening */
2009 if (ints
& DIEPMSK_INTknEPMisMsk
) {
2010 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2014 /* FIFO has space or is empty (see GAHBCFG) */
2015 if (hsotg
->dedicated_fifos
&&
2016 ints
& DIEPMSK_TxFIFOEmpty
) {
2017 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2019 if (!using_dma(hsotg
))
2020 s3c_hsotg_trytx(hsotg
, hs_ep
);
2026 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2027 * @hsotg: The device state.
2029 * Handle updating the device settings after the enumeration phase has
2032 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
2034 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
2035 int ep0_mps
= 0, ep_mps
;
2038 * This should signal the finish of the enumeration phase
2039 * of the USB handshaking, so we should now know what rate
2043 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2046 * note, since we're limited by the size of transfer on EP0, and
2047 * it seems IN transfers must be a even number of packets we do
2048 * not advertise a 64byte MPS on EP0.
2051 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2052 switch (dsts
& DSTS_EnumSpd_MASK
) {
2053 case DSTS_EnumSpd_FS
:
2054 case DSTS_EnumSpd_FS48
:
2055 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2056 ep0_mps
= EP0_MPS_LIMIT
;
2060 case DSTS_EnumSpd_HS
:
2061 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2062 ep0_mps
= EP0_MPS_LIMIT
;
2066 case DSTS_EnumSpd_LS
:
2067 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2069 * note, we don't actually support LS in this driver at the
2070 * moment, and the documentation seems to imply that it isn't
2071 * supported by the PHYs on some of the devices.
2075 dev_info(hsotg
->dev
, "new device is %s\n",
2076 usb_speed_string(hsotg
->gadget
.speed
));
2079 * we should now know the maximum packet size for an
2080 * endpoint, so set the endpoints to a default value.
2085 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
2086 for (i
= 1; i
< hsotg
->num_of_eps
; i
++)
2087 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
2090 /* ensure after enumeration our EP0 is active */
2092 s3c_hsotg_enqueue_setup(hsotg
);
2094 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2095 readl(hsotg
->regs
+ DIEPCTL0
),
2096 readl(hsotg
->regs
+ DOEPCTL0
));
2100 * kill_all_requests - remove all requests from the endpoint's queue
2101 * @hsotg: The device state.
2102 * @ep: The endpoint the requests may be on.
2103 * @result: The result code to use.
2104 * @force: Force removal of any current requests
2106 * Go through the requests on the given endpoint and mark them
2107 * completed with the given result code.
2109 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
2110 struct s3c_hsotg_ep
*ep
,
2111 int result
, bool force
)
2113 struct s3c_hsotg_req
*req
, *treq
;
2115 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2117 * currently, we can't do much about an already
2118 * running request on an in endpoint
2121 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
2124 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2129 #define call_gadget(_hs, _entry) \
2130 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2131 (_hs)->driver && (_hs)->driver->_entry) { \
2132 spin_unlock(&_hs->lock); \
2133 (_hs)->driver->_entry(&(_hs)->gadget); \
2134 spin_lock(&_hs->lock); \
2138 * s3c_hsotg_disconnect - disconnect service
2139 * @hsotg: The device state.
2141 * The device has been disconnected. Remove all current
2142 * transactions and signal the gadget driver that this
2145 static void s3c_hsotg_disconnect(struct s3c_hsotg
*hsotg
)
2149 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2150 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
2152 call_gadget(hsotg
, disconnect
);
2156 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2157 * @hsotg: The device state:
2158 * @periodic: True if this is a periodic FIFO interrupt
2160 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2162 struct s3c_hsotg_ep
*ep
;
2165 /* look through for any more data to transmit */
2167 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2168 ep
= &hsotg
->eps
[epno
];
2173 if ((periodic
&& !ep
->periodic
) ||
2174 (!periodic
&& ep
->periodic
))
2177 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2183 /* IRQ flags which will trigger a retry around the IRQ loop */
2184 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2189 * s3c_hsotg_corereset - issue softreset to the core
2190 * @hsotg: The device state
2192 * Issue a soft reset to the core, and await the core finishing it.
2194 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2199 dev_dbg(hsotg
->dev
, "resetting core\n");
2201 /* issue soft reset */
2202 writel(GRSTCTL_CSftRst
, hsotg
->regs
+ GRSTCTL
);
2206 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2207 } while ((grstctl
& GRSTCTL_CSftRst
) && timeout
-- > 0);
2209 if (grstctl
& GRSTCTL_CSftRst
) {
2210 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2217 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2219 if (timeout
-- < 0) {
2220 dev_info(hsotg
->dev
,
2221 "%s: reset failed, GRSTCTL=%08x\n",
2226 if (!(grstctl
& GRSTCTL_AHBIdle
))
2229 break; /* reset done */
2232 dev_dbg(hsotg
->dev
, "reset successful\n");
2237 * s3c_hsotg_core_init - issue softreset to the core
2238 * @hsotg: The device state
2240 * Issue a soft reset to the core, and await the core finishing it.
2242 static void s3c_hsotg_core_init(struct s3c_hsotg
*hsotg
)
2244 s3c_hsotg_corereset(hsotg
);
2247 * we must now enable ep0 ready for host detection and then
2248 * set configuration.
2251 /* set the PLL on, remove the HNP/SRP and set the PHY */
2252 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) |
2253 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2255 s3c_hsotg_init_fifo(hsotg
);
2257 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2259 writel(1 << 18 | DCFG_DevSpd_HS
, hsotg
->regs
+ DCFG
);
2261 /* Clear any pending OTG interrupts */
2262 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2264 /* Clear any pending interrupts */
2265 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2267 writel(GINTSTS_ErlySusp
| GINTSTS_SessReqInt
|
2268 GINTSTS_GOUTNakEff
| GINTSTS_GINNakEff
|
2269 GINTSTS_ConIDStsChng
| GINTSTS_USBRst
|
2270 GINTSTS_EnumDone
| GINTSTS_OTGInt
|
2271 GINTSTS_USBSusp
| GINTSTS_WkUpInt
,
2272 hsotg
->regs
+ GINTMSK
);
2274 if (using_dma(hsotg
))
2275 writel(GAHBCFG_GlblIntrEn
| GAHBCFG_DMAEn
|
2276 GAHBCFG_HBstLen_Incr4
,
2277 hsotg
->regs
+ GAHBCFG
);
2279 writel(GAHBCFG_GlblIntrEn
, hsotg
->regs
+ GAHBCFG
);
2282 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2283 * up being flooded with interrupts if the host is polling the
2284 * endpoint to try and read data.
2287 writel(((hsotg
->dedicated_fifos
) ? DIEPMSK_TxFIFOEmpty
: 0) |
2288 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
|
2289 DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2290 DIEPMSK_INTknEPMisMsk
,
2291 hsotg
->regs
+ DIEPMSK
);
2294 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2295 * DMA mode we may need this.
2297 writel((using_dma(hsotg
) ? (DIEPMSK_XferComplMsk
|
2298 DIEPMSK_TimeOUTMsk
) : 0) |
2299 DOEPMSK_EPDisbldMsk
| DOEPMSK_AHBErrMsk
|
2301 hsotg
->regs
+ DOEPMSK
);
2303 writel(0, hsotg
->regs
+ DAINTMSK
);
2305 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2306 readl(hsotg
->regs
+ DIEPCTL0
),
2307 readl(hsotg
->regs
+ DOEPCTL0
));
2309 /* enable in and out endpoint interrupts */
2310 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPInt
| GINTSTS_IEPInt
);
2313 * Enable the RXFIFO when in slave mode, as this is how we collect
2314 * the data. In DMA mode, we get events from the FIFO but also
2315 * things we cannot process, so do not use it.
2317 if (!using_dma(hsotg
))
2318 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RxFLvl
);
2320 /* Enable interrupts for EP0 in and out */
2321 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2322 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2324 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2325 udelay(10); /* see openiboot */
2326 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2328 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2331 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2332 * writing to the EPCTL register..
2335 /* set to read 1 8byte packet */
2336 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2337 DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2339 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2340 DxEPCTL_CNAK
| DxEPCTL_EPEna
|
2342 hsotg
->regs
+ DOEPCTL0
);
2344 /* enable, but don't activate EP0in */
2345 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2346 DxEPCTL_USBActEp
, hsotg
->regs
+ DIEPCTL0
);
2348 s3c_hsotg_enqueue_setup(hsotg
);
2350 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2351 readl(hsotg
->regs
+ DIEPCTL0
),
2352 readl(hsotg
->regs
+ DOEPCTL0
));
2354 /* clear global NAKs */
2355 writel(DCTL_CGOUTNak
| DCTL_CGNPInNAK
,
2356 hsotg
->regs
+ DCTL
);
2358 /* must be at-least 3ms to allow bus to see disconnect */
2361 /* remove the soft-disconnect and let's go */
2362 __bic32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2366 * s3c_hsotg_irq - handle device interrupt
2367 * @irq: The IRQ number triggered
2368 * @pw: The pw value when registered the handler.
2370 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2372 struct s3c_hsotg
*hsotg
= pw
;
2373 int retry_count
= 8;
2377 spin_lock(&hsotg
->lock
);
2379 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2380 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2382 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2383 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2387 if (gintsts
& GINTSTS_OTGInt
) {
2388 u32 otgint
= readl(hsotg
->regs
+ GOTGINT
);
2390 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2392 writel(otgint
, hsotg
->regs
+ GOTGINT
);
2395 if (gintsts
& GINTSTS_SessReqInt
) {
2396 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2397 writel(GINTSTS_SessReqInt
, hsotg
->regs
+ GINTSTS
);
2400 if (gintsts
& GINTSTS_EnumDone
) {
2401 writel(GINTSTS_EnumDone
, hsotg
->regs
+ GINTSTS
);
2403 s3c_hsotg_irq_enumdone(hsotg
);
2406 if (gintsts
& GINTSTS_ConIDStsChng
) {
2407 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2408 readl(hsotg
->regs
+ DSTS
),
2409 readl(hsotg
->regs
+ GOTGCTL
));
2411 writel(GINTSTS_ConIDStsChng
, hsotg
->regs
+ GINTSTS
);
2414 if (gintsts
& (GINTSTS_OEPInt
| GINTSTS_IEPInt
)) {
2415 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2416 u32 daint_out
= daint
>> DAINT_OutEP_SHIFT
;
2417 u32 daint_in
= daint
& ~(daint_out
<< DAINT_OutEP_SHIFT
);
2420 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2422 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2424 s3c_hsotg_epint(hsotg
, ep
, 0);
2427 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2429 s3c_hsotg_epint(hsotg
, ep
, 1);
2433 if (gintsts
& GINTSTS_USBRst
) {
2435 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2437 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2438 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2439 readl(hsotg
->regs
+ GNPTXSTS
));
2441 writel(GINTSTS_USBRst
, hsotg
->regs
+ GINTSTS
);
2443 if (usb_status
& GOTGCTL_BSESVLD
) {
2444 if (time_after(jiffies
, hsotg
->last_rst
+
2445 msecs_to_jiffies(200))) {
2447 kill_all_requests(hsotg
, &hsotg
->eps
[0],
2450 s3c_hsotg_core_init(hsotg
);
2451 hsotg
->last_rst
= jiffies
;
2456 /* check both FIFOs */
2458 if (gintsts
& GINTSTS_NPTxFEmp
) {
2459 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2462 * Disable the interrupt to stop it happening again
2463 * unless one of these endpoint routines decides that
2464 * it needs re-enabling
2467 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTxFEmp
);
2468 s3c_hsotg_irq_fifoempty(hsotg
, false);
2471 if (gintsts
& GINTSTS_PTxFEmp
) {
2472 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2474 /* See note in GINTSTS_NPTxFEmp */
2476 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTxFEmp
);
2477 s3c_hsotg_irq_fifoempty(hsotg
, true);
2480 if (gintsts
& GINTSTS_RxFLvl
) {
2482 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2483 * we need to retry s3c_hsotg_handle_rx if this is still
2487 s3c_hsotg_handle_rx(hsotg
);
2490 if (gintsts
& GINTSTS_ModeMis
) {
2491 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2492 writel(GINTSTS_ModeMis
, hsotg
->regs
+ GINTSTS
);
2495 if (gintsts
& GINTSTS_USBSusp
) {
2496 dev_info(hsotg
->dev
, "GINTSTS_USBSusp\n");
2497 writel(GINTSTS_USBSusp
, hsotg
->regs
+ GINTSTS
);
2499 call_gadget(hsotg
, suspend
);
2500 s3c_hsotg_disconnect(hsotg
);
2503 if (gintsts
& GINTSTS_WkUpInt
) {
2504 dev_info(hsotg
->dev
, "GINTSTS_WkUpIn\n");
2505 writel(GINTSTS_WkUpInt
, hsotg
->regs
+ GINTSTS
);
2507 call_gadget(hsotg
, resume
);
2510 if (gintsts
& GINTSTS_ErlySusp
) {
2511 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2512 writel(GINTSTS_ErlySusp
, hsotg
->regs
+ GINTSTS
);
2514 s3c_hsotg_disconnect(hsotg
);
2518 * these next two seem to crop-up occasionally causing the core
2519 * to shutdown the USB transfer, so try clearing them and logging
2523 if (gintsts
& GINTSTS_GOUTNakEff
) {
2524 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2526 writel(DCTL_CGOUTNak
, hsotg
->regs
+ DCTL
);
2528 s3c_hsotg_dump(hsotg
);
2531 if (gintsts
& GINTSTS_GINNakEff
) {
2532 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2534 writel(DCTL_CGNPInNAK
, hsotg
->regs
+ DCTL
);
2536 s3c_hsotg_dump(hsotg
);
2540 * if we've had fifo events, we should try and go around the
2541 * loop again to see if there's any point in returning yet.
2544 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2547 spin_unlock(&hsotg
->lock
);
2553 * s3c_hsotg_ep_enable - enable the given endpoint
2554 * @ep: The USB endpint to configure
2555 * @desc: The USB endpoint descriptor to configure with.
2557 * This is called from the USB gadget code's usb_ep_enable().
2559 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2560 const struct usb_endpoint_descriptor
*desc
)
2562 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2563 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2564 unsigned long flags
;
2565 int index
= hs_ep
->index
;
2573 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2574 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2575 desc
->wMaxPacketSize
, desc
->bInterval
);
2577 /* not to be called for EP0 */
2578 WARN_ON(index
== 0);
2580 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2581 if (dir_in
!= hs_ep
->dir_in
) {
2582 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2586 mps
= usb_endpoint_maxp(desc
);
2588 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2590 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2591 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2593 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2594 __func__
, epctrl
, epctrl_reg
);
2596 spin_lock_irqsave(&hsotg
->lock
, flags
);
2598 epctrl
&= ~(DxEPCTL_EPType_MASK
| DxEPCTL_MPS_MASK
);
2599 epctrl
|= DxEPCTL_MPS(mps
);
2602 * mark the endpoint as active, otherwise the core may ignore
2603 * transactions entirely for this endpoint
2605 epctrl
|= DxEPCTL_USBActEp
;
2608 * set the NAK status on the endpoint, otherwise we might try and
2609 * do something with data that we've yet got a request to process
2610 * since the RXFIFO will take data for an endpoint even if the
2611 * size register hasn't been set.
2614 epctrl
|= DxEPCTL_SNAK
;
2616 /* update the endpoint state */
2617 hs_ep
->ep
.maxpacket
= mps
;
2619 /* default, set to non-periodic */
2620 hs_ep
->periodic
= 0;
2622 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2623 case USB_ENDPOINT_XFER_ISOC
:
2624 dev_err(hsotg
->dev
, "no current ISOC support\n");
2628 case USB_ENDPOINT_XFER_BULK
:
2629 epctrl
|= DxEPCTL_EPType_Bulk
;
2632 case USB_ENDPOINT_XFER_INT
:
2635 * Allocate our TxFNum by simply using the index
2636 * of the endpoint for the moment. We could do
2637 * something better if the host indicates how
2638 * many FIFOs we are expecting to use.
2641 hs_ep
->periodic
= 1;
2642 epctrl
|= DxEPCTL_TxFNum(index
);
2645 epctrl
|= DxEPCTL_EPType_Intterupt
;
2648 case USB_ENDPOINT_XFER_CONTROL
:
2649 epctrl
|= DxEPCTL_EPType_Control
;
2654 * if the hardware has dedicated fifos, we must give each IN EP
2655 * a unique tx-fifo even if it is non-periodic.
2657 if (dir_in
&& hsotg
->dedicated_fifos
)
2658 epctrl
|= DxEPCTL_TxFNum(index
);
2660 /* for non control endpoints, set PID to D0 */
2662 epctrl
|= DxEPCTL_SetD0PID
;
2664 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2667 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2668 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2669 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2671 /* enable the endpoint interrupt */
2672 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2675 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2680 * s3c_hsotg_ep_disable - disable given endpoint
2681 * @ep: The endpoint to disable.
2683 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2685 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2686 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2687 int dir_in
= hs_ep
->dir_in
;
2688 int index
= hs_ep
->index
;
2689 unsigned long flags
;
2693 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2695 if (ep
== &hsotg
->eps
[0].ep
) {
2696 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2700 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2702 spin_lock_irqsave(&hsotg
->lock
, flags
);
2703 /* terminate all requests with shutdown */
2704 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2707 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2708 ctrl
&= ~DxEPCTL_EPEna
;
2709 ctrl
&= ~DxEPCTL_USBActEp
;
2710 ctrl
|= DxEPCTL_SNAK
;
2712 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2713 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2715 /* disable endpoint interrupts */
2716 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2718 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2723 * on_list - check request is on the given endpoint
2724 * @ep: The endpoint to check.
2725 * @test: The request to test if it is on the endpoint.
2727 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2729 struct s3c_hsotg_req
*req
, *treq
;
2731 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2740 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2741 * @ep: The endpoint to dequeue.
2742 * @req: The request to be removed from a queue.
2744 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2746 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2747 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2748 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2749 unsigned long flags
;
2751 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2753 spin_lock_irqsave(&hs
->lock
, flags
);
2755 if (!on_list(hs_ep
, hs_req
)) {
2756 spin_unlock_irqrestore(&hs
->lock
, flags
);
2760 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2761 spin_unlock_irqrestore(&hs
->lock
, flags
);
2767 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2768 * @ep: The endpoint to set halt.
2769 * @value: Set or unset the halt.
2771 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2773 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2774 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2775 int index
= hs_ep
->index
;
2780 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2782 /* write both IN and OUT control registers */
2784 epreg
= DIEPCTL(index
);
2785 epctl
= readl(hs
->regs
+ epreg
);
2788 epctl
|= DxEPCTL_Stall
+ DxEPCTL_SNAK
;
2789 if (epctl
& DxEPCTL_EPEna
)
2790 epctl
|= DxEPCTL_EPDis
;
2792 epctl
&= ~DxEPCTL_Stall
;
2793 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2794 if (xfertype
== DxEPCTL_EPType_Bulk
||
2795 xfertype
== DxEPCTL_EPType_Intterupt
)
2796 epctl
|= DxEPCTL_SetD0PID
;
2799 writel(epctl
, hs
->regs
+ epreg
);
2801 epreg
= DOEPCTL(index
);
2802 epctl
= readl(hs
->regs
+ epreg
);
2805 epctl
|= DxEPCTL_Stall
;
2807 epctl
&= ~DxEPCTL_Stall
;
2808 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2809 if (xfertype
== DxEPCTL_EPType_Bulk
||
2810 xfertype
== DxEPCTL_EPType_Intterupt
)
2811 epctl
|= DxEPCTL_SetD0PID
;
2814 writel(epctl
, hs
->regs
+ epreg
);
2820 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2821 * @ep: The endpoint to set halt.
2822 * @value: Set or unset the halt.
2824 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
2826 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2827 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2828 unsigned long flags
= 0;
2831 spin_lock_irqsave(&hs
->lock
, flags
);
2832 ret
= s3c_hsotg_ep_sethalt(ep
, value
);
2833 spin_unlock_irqrestore(&hs
->lock
, flags
);
2838 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2839 .enable
= s3c_hsotg_ep_enable
,
2840 .disable
= s3c_hsotg_ep_disable
,
2841 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2842 .free_request
= s3c_hsotg_ep_free_request
,
2843 .queue
= s3c_hsotg_ep_queue_lock
,
2844 .dequeue
= s3c_hsotg_ep_dequeue
,
2845 .set_halt
= s3c_hsotg_ep_sethalt_lock
,
2846 /* note, don't believe we have any call for the fifo routines */
2850 * s3c_hsotg_phy_enable - enable platform phy dev
2851 * @hsotg: The driver state
2853 * A wrapper for platform code responsible for controlling
2854 * low-level USB code
2856 static void s3c_hsotg_phy_enable(struct s3c_hsotg
*hsotg
)
2858 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2860 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2863 usb_phy_init(hsotg
->phy
);
2864 else if (hsotg
->plat
->phy_init
)
2865 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2869 * s3c_hsotg_phy_disable - disable platform phy dev
2870 * @hsotg: The driver state
2872 * A wrapper for platform code responsible for controlling
2873 * low-level USB code
2875 static void s3c_hsotg_phy_disable(struct s3c_hsotg
*hsotg
)
2877 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2880 usb_phy_shutdown(hsotg
->phy
);
2881 else if (hsotg
->plat
->phy_exit
)
2882 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2886 * s3c_hsotg_init - initalize the usb core
2887 * @hsotg: The driver state
2889 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2891 /* unmask subset of endpoint interrupts */
2893 writel(DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2894 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
,
2895 hsotg
->regs
+ DIEPMSK
);
2897 writel(DOEPMSK_SetupMsk
| DOEPMSK_AHBErrMsk
|
2898 DOEPMSK_EPDisbldMsk
| DOEPMSK_XferComplMsk
,
2899 hsotg
->regs
+ DOEPMSK
);
2901 writel(0, hsotg
->regs
+ DAINTMSK
);
2903 /* Be in disconnected state until gadget is registered */
2904 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2907 /* post global nak until we're ready */
2908 writel(DCTL_SGNPInNAK
| DCTL_SGOUTNak
,
2909 hsotg
->regs
+ DCTL
);
2914 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2915 readl(hsotg
->regs
+ GRXFSIZ
),
2916 readl(hsotg
->regs
+ GNPTXFSIZ
));
2918 s3c_hsotg_init_fifo(hsotg
);
2920 /* set the PLL on, remove the HNP/SRP and set the PHY */
2921 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) | (0x5 << 10),
2922 hsotg
->regs
+ GUSBCFG
);
2924 writel(using_dma(hsotg
) ? GAHBCFG_DMAEn
: 0x0,
2925 hsotg
->regs
+ GAHBCFG
);
2929 * s3c_hsotg_udc_start - prepare the udc for work
2930 * @gadget: The usb gadget state
2931 * @driver: The usb gadget driver
2933 * Perform initialization to prepare udc device and driver
2936 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2937 struct usb_gadget_driver
*driver
)
2939 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2943 printk(KERN_ERR
"%s: called with no device\n", __func__
);
2948 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2952 if (driver
->max_speed
< USB_SPEED_FULL
)
2953 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2955 if (!driver
->setup
) {
2956 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2960 WARN_ON(hsotg
->driver
);
2962 driver
->driver
.bus
= NULL
;
2963 hsotg
->driver
= driver
;
2964 hsotg
->gadget
.dev
.driver
= &driver
->driver
;
2965 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
2966 hsotg
->gadget
.dev
.dma_mask
= hsotg
->dev
->dma_mask
;
2967 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2969 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
2972 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
2976 hsotg
->last_rst
= jiffies
;
2977 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2981 hsotg
->driver
= NULL
;
2982 hsotg
->gadget
.dev
.driver
= NULL
;
2987 * s3c_hsotg_udc_stop - stop the udc
2988 * @gadget: The usb gadget state
2989 * @driver: The usb gadget driver
2991 * Stop udc hw block and stay tunned for future transmissions
2993 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
,
2994 struct usb_gadget_driver
*driver
)
2996 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2997 unsigned long flags
= 0;
3003 if (!driver
|| driver
!= hsotg
->driver
|| !driver
->unbind
)
3006 /* all endpoints should be shutdown */
3007 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
3008 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
3010 spin_lock_irqsave(&hsotg
->lock
, flags
);
3012 s3c_hsotg_phy_disable(hsotg
);
3013 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3015 hsotg
->driver
= NULL
;
3016 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3017 hsotg
->gadget
.dev
.driver
= NULL
;
3019 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3021 dev_info(hsotg
->dev
, "unregistered gadget driver '%s'\n",
3022 driver
->driver
.name
);
3028 * s3c_hsotg_gadget_getframe - read the frame number
3029 * @gadget: The usb gadget state
3031 * Read the {micro} frame number
3033 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
3035 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
3039 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3040 * @gadget: The usb gadget state
3041 * @is_on: Current state of the USB PHY
3043 * Connect/Disconnect the USB PHY pullup
3045 static int s3c_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
3047 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
3048 unsigned long flags
= 0;
3050 dev_dbg(hsotg
->dev
, "%s: is_in: %d\n", __func__
, is_on
);
3052 spin_lock_irqsave(&hsotg
->lock
, flags
);
3054 s3c_hsotg_phy_enable(hsotg
);
3055 s3c_hsotg_core_init(hsotg
);
3057 s3c_hsotg_disconnect(hsotg
);
3058 s3c_hsotg_phy_disable(hsotg
);
3061 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3062 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3067 static const struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
3068 .get_frame
= s3c_hsotg_gadget_getframe
,
3069 .udc_start
= s3c_hsotg_udc_start
,
3070 .udc_stop
= s3c_hsotg_udc_stop
,
3071 .pullup
= s3c_hsotg_pullup
,
3075 * s3c_hsotg_initep - initialise a single endpoint
3076 * @hsotg: The device state.
3077 * @hs_ep: The endpoint to be initialised.
3078 * @epnum: The endpoint number
3080 * Initialise the given endpoint (as part of the probe and device state
3081 * creation) to give to the gadget driver. Setup the endpoint name, any
3082 * direction information and other state that may be required.
3084 static void s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
3085 struct s3c_hsotg_ep
*hs_ep
,
3093 else if ((epnum
% 2) == 0) {
3100 hs_ep
->index
= epnum
;
3102 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3104 INIT_LIST_HEAD(&hs_ep
->queue
);
3105 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3107 /* add to the list of endpoints known by the gadget driver */
3109 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3111 hs_ep
->parent
= hsotg
;
3112 hs_ep
->ep
.name
= hs_ep
->name
;
3113 hs_ep
->ep
.maxpacket
= epnum
? 512 : EP0_MPS_LIMIT
;
3114 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3117 * Read the FIFO size for the Periodic TX FIFO, even if we're
3118 * an OUT endpoint, we may as well do this if in future the
3119 * code is changed to make each endpoint's direction changeable.
3122 ptxfifo
= readl(hsotg
->regs
+ DPTXFSIZn(epnum
));
3123 hs_ep
->fifo_size
= DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
3126 * if we're using dma, we need to set the next-endpoint pointer
3127 * to be something valid.
3130 if (using_dma(hsotg
)) {
3131 u32 next
= DxEPCTL_NextEp((epnum
+ 1) % 15);
3132 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3133 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3138 * s3c_hsotg_hw_cfg - read HW configuration registers
3139 * @param: The device state
3141 * Read the USB core HW configuration registers
3143 static void s3c_hsotg_hw_cfg(struct s3c_hsotg
*hsotg
)
3146 /* check hardware configuration */
3148 cfg2
= readl(hsotg
->regs
+ 0x48);
3149 hsotg
->num_of_eps
= (cfg2
>> 10) & 0xF;
3151 dev_info(hsotg
->dev
, "EPs:%d\n", hsotg
->num_of_eps
);
3153 cfg4
= readl(hsotg
->regs
+ 0x50);
3154 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
3156 dev_info(hsotg
->dev
, "%s fifos\n",
3157 hsotg
->dedicated_fifos
? "dedicated" : "shared");
3161 * s3c_hsotg_dump - dump state of the udc
3162 * @param: The device state
3164 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
3167 struct device
*dev
= hsotg
->dev
;
3168 void __iomem
*regs
= hsotg
->regs
;
3172 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3173 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3174 readl(regs
+ DIEPMSK
));
3176 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3177 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3179 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3180 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3182 /* show periodic fifo settings */
3184 for (idx
= 1; idx
<= 15; idx
++) {
3185 val
= readl(regs
+ DPTXFSIZn(idx
));
3186 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3187 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3188 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3191 for (idx
= 0; idx
< 15; idx
++) {
3193 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3194 readl(regs
+ DIEPCTL(idx
)),
3195 readl(regs
+ DIEPTSIZ(idx
)),
3196 readl(regs
+ DIEPDMA(idx
)));
3198 val
= readl(regs
+ DOEPCTL(idx
));
3200 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3201 idx
, readl(regs
+ DOEPCTL(idx
)),
3202 readl(regs
+ DOEPTSIZ(idx
)),
3203 readl(regs
+ DOEPDMA(idx
)));
3207 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3208 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3213 * state_show - debugfs: show overall driver and device state.
3214 * @seq: The seq file to write to.
3215 * @v: Unused parameter.
3217 * This debugfs entry shows the overall state of the hardware and
3218 * some general information about each of the endpoints available
3221 static int state_show(struct seq_file
*seq
, void *v
)
3223 struct s3c_hsotg
*hsotg
= seq
->private;
3224 void __iomem
*regs
= hsotg
->regs
;
3227 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3230 readl(regs
+ DSTS
));
3232 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3233 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3235 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3236 readl(regs
+ GINTMSK
),
3237 readl(regs
+ GINTSTS
));
3239 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3240 readl(regs
+ DAINTMSK
),
3241 readl(regs
+ DAINT
));
3243 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3244 readl(regs
+ GNPTXSTS
),
3245 readl(regs
+ GRXSTSR
));
3247 seq_printf(seq
, "\nEndpoint status:\n");
3249 for (idx
= 0; idx
< 15; idx
++) {
3252 in
= readl(regs
+ DIEPCTL(idx
));
3253 out
= readl(regs
+ DOEPCTL(idx
));
3255 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3258 in
= readl(regs
+ DIEPTSIZ(idx
));
3259 out
= readl(regs
+ DOEPTSIZ(idx
));
3261 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3264 seq_printf(seq
, "\n");
3270 static int state_open(struct inode
*inode
, struct file
*file
)
3272 return single_open(file
, state_show
, inode
->i_private
);
3275 static const struct file_operations state_fops
= {
3276 .owner
= THIS_MODULE
,
3279 .llseek
= seq_lseek
,
3280 .release
= single_release
,
3284 * fifo_show - debugfs: show the fifo information
3285 * @seq: The seq_file to write data to.
3286 * @v: Unused parameter.
3288 * Show the FIFO information for the overall fifo and all the
3289 * periodic transmission FIFOs.
3291 static int fifo_show(struct seq_file
*seq
, void *v
)
3293 struct s3c_hsotg
*hsotg
= seq
->private;
3294 void __iomem
*regs
= hsotg
->regs
;
3298 seq_printf(seq
, "Non-periodic FIFOs:\n");
3299 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3301 val
= readl(regs
+ GNPTXFSIZ
);
3302 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3303 val
>> GNPTXFSIZ_NPTxFDep_SHIFT
,
3304 val
& GNPTXFSIZ_NPTxFStAddr_MASK
);
3306 seq_printf(seq
, "\nPeriodic TXFIFOs:\n");
3308 for (idx
= 1; idx
<= 15; idx
++) {
3309 val
= readl(regs
+ DPTXFSIZn(idx
));
3311 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3312 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3313 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3319 static int fifo_open(struct inode
*inode
, struct file
*file
)
3321 return single_open(file
, fifo_show
, inode
->i_private
);
3324 static const struct file_operations fifo_fops
= {
3325 .owner
= THIS_MODULE
,
3328 .llseek
= seq_lseek
,
3329 .release
= single_release
,
3333 static const char *decode_direction(int is_in
)
3335 return is_in
? "in" : "out";
3339 * ep_show - debugfs: show the state of an endpoint.
3340 * @seq: The seq_file to write data to.
3341 * @v: Unused parameter.
3343 * This debugfs entry shows the state of the given endpoint (one is
3344 * registered for each available).
3346 static int ep_show(struct seq_file
*seq
, void *v
)
3348 struct s3c_hsotg_ep
*ep
= seq
->private;
3349 struct s3c_hsotg
*hsotg
= ep
->parent
;
3350 struct s3c_hsotg_req
*req
;
3351 void __iomem
*regs
= hsotg
->regs
;
3352 int index
= ep
->index
;
3353 int show_limit
= 15;
3354 unsigned long flags
;
3356 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3357 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3359 /* first show the register state */
3361 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3362 readl(regs
+ DIEPCTL(index
)),
3363 readl(regs
+ DOEPCTL(index
)));
3365 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3366 readl(regs
+ DIEPDMA(index
)),
3367 readl(regs
+ DOEPDMA(index
)));
3369 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3370 readl(regs
+ DIEPINT(index
)),
3371 readl(regs
+ DOEPINT(index
)));
3373 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3374 readl(regs
+ DIEPTSIZ(index
)),
3375 readl(regs
+ DOEPTSIZ(index
)));
3377 seq_printf(seq
, "\n");
3378 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3379 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3381 seq_printf(seq
, "request list (%p,%p):\n",
3382 ep
->queue
.next
, ep
->queue
.prev
);
3384 spin_lock_irqsave(&hsotg
->lock
, flags
);
3386 list_for_each_entry(req
, &ep
->queue
, queue
) {
3387 if (--show_limit
< 0) {
3388 seq_printf(seq
, "not showing more requests...\n");
3392 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3393 req
== ep
->req
? '*' : ' ',
3394 req
, req
->req
.length
, req
->req
.buf
);
3395 seq_printf(seq
, "%d done, res %d\n",
3396 req
->req
.actual
, req
->req
.status
);
3399 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3404 static int ep_open(struct inode
*inode
, struct file
*file
)
3406 return single_open(file
, ep_show
, inode
->i_private
);
3409 static const struct file_operations ep_fops
= {
3410 .owner
= THIS_MODULE
,
3413 .llseek
= seq_lseek
,
3414 .release
= single_release
,
3418 * s3c_hsotg_create_debug - create debugfs directory and files
3419 * @hsotg: The driver state
3421 * Create the debugfs files to allow the user to get information
3422 * about the state of the system. The directory name is created
3423 * with the same name as the device itself, in case we end up
3424 * with multiple blocks in future systems.
3426 static void s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3428 struct dentry
*root
;
3431 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3432 hsotg
->debug_root
= root
;
3434 dev_err(hsotg
->dev
, "cannot create debug root\n");
3438 /* create general state file */
3440 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3441 hsotg
, &state_fops
);
3443 if (IS_ERR(hsotg
->debug_file
))
3444 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3446 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3449 if (IS_ERR(hsotg
->debug_fifo
))
3450 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3452 /* create one file for each endpoint */
3454 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3455 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3457 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3458 root
, ep
, &ep_fops
);
3460 if (IS_ERR(ep
->debugfs
))
3461 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3467 * s3c_hsotg_delete_debug - cleanup debugfs entries
3468 * @hsotg: The driver state
3470 * Cleanup (remove) the debugfs files for use on module exit.
3472 static void s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3476 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3477 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3478 debugfs_remove(ep
->debugfs
);
3481 debugfs_remove(hsotg
->debug_file
);
3482 debugfs_remove(hsotg
->debug_fifo
);
3483 debugfs_remove(hsotg
->debug_root
);
3487 * s3c_hsotg_release - release callback for hsotg device
3488 * @dev: Device to for which release is called
3490 * Nothing to do as the resource is allocated using devm_ API.
3492 static void s3c_hsotg_release(struct device
*dev
)
3497 * s3c_hsotg_probe - probe function for hsotg driver
3498 * @pdev: The platform information for the driver
3501 static int s3c_hsotg_probe(struct platform_device
*pdev
)
3503 struct s3c_hsotg_plat
*plat
= pdev
->dev
.platform_data
;
3504 struct usb_phy
*phy
;
3505 struct device
*dev
= &pdev
->dev
;
3506 struct s3c_hsotg_ep
*eps
;
3507 struct s3c_hsotg
*hsotg
;
3508 struct resource
*res
;
3513 hsotg
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c_hsotg
), GFP_KERNEL
);
3515 dev_err(dev
, "cannot get memory\n");
3519 phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB2
);
3520 if (IS_ERR_OR_NULL(phy
)) {
3521 /* Fallback for pdata */
3522 plat
= pdev
->dev
.platform_data
;
3524 dev_err(&pdev
->dev
, "no platform data or transceiver defined\n");
3525 return -EPROBE_DEFER
;
3535 hsotg
->clk
= devm_clk_get(&pdev
->dev
, "otg");
3536 if (IS_ERR(hsotg
->clk
)) {
3537 dev_err(dev
, "cannot get otg clock\n");
3538 return PTR_ERR(hsotg
->clk
);
3541 platform_set_drvdata(pdev
, hsotg
);
3543 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3545 hsotg
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
3546 if (IS_ERR(hsotg
->regs
)) {
3547 ret
= PTR_ERR(hsotg
->regs
);
3551 ret
= platform_get_irq(pdev
, 0);
3553 dev_err(dev
, "cannot find IRQ\n");
3557 spin_lock_init(&hsotg
->lock
);
3561 ret
= devm_request_irq(&pdev
->dev
, hsotg
->irq
, s3c_hsotg_irq
, 0,
3562 dev_name(dev
), hsotg
);
3564 dev_err(dev
, "cannot claim IRQ\n");
3568 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3570 device_initialize(&hsotg
->gadget
.dev
);
3572 dev_set_name(&hsotg
->gadget
.dev
, "gadget");
3574 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3575 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3576 hsotg
->gadget
.name
= dev_name(dev
);
3578 hsotg
->gadget
.dev
.parent
= dev
;
3579 hsotg
->gadget
.dev
.dma_mask
= dev
->dma_mask
;
3580 hsotg
->gadget
.dev
.release
= s3c_hsotg_release
;
3582 /* reset the system */
3584 clk_prepare_enable(hsotg
->clk
);
3588 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3589 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3591 ret
= devm_regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3594 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3598 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3602 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3606 /* usb phy enable */
3607 s3c_hsotg_phy_enable(hsotg
);
3609 s3c_hsotg_corereset(hsotg
);
3610 s3c_hsotg_init(hsotg
);
3611 s3c_hsotg_hw_cfg(hsotg
);
3613 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3615 if (hsotg
->num_of_eps
== 0) {
3616 dev_err(dev
, "wrong number of EPs (zero)\n");
3621 eps
= kcalloc(hsotg
->num_of_eps
+ 1, sizeof(struct s3c_hsotg_ep
),
3624 dev_err(dev
, "cannot get memory\n");
3631 /* setup endpoint information */
3633 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3634 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3636 /* allocate EP0 request */
3638 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3640 if (!hsotg
->ctrl_req
) {
3641 dev_err(dev
, "failed to allocate ctrl req\n");
3646 /* initialise the endpoints now the core has been initialised */
3647 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++)
3648 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3650 /* disable power and clock */
3652 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3655 dev_err(hsotg
->dev
, "failed to disable supplies: %d\n", ret
);
3659 s3c_hsotg_phy_disable(hsotg
);
3661 ret
= device_add(&hsotg
->gadget
.dev
);
3663 put_device(&hsotg
->gadget
.dev
);
3667 ret
= usb_add_gadget_udc(&pdev
->dev
, &hsotg
->gadget
);
3671 s3c_hsotg_create_debug(hsotg
);
3673 s3c_hsotg_dump(hsotg
);
3680 s3c_hsotg_phy_disable(hsotg
);
3682 clk_disable_unprepare(hsotg
->clk
);
3688 * s3c_hsotg_remove - remove function for hsotg driver
3689 * @pdev: The platform information for the driver
3691 static int s3c_hsotg_remove(struct platform_device
*pdev
)
3693 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3695 usb_del_gadget_udc(&hsotg
->gadget
);
3697 s3c_hsotg_delete_debug(hsotg
);
3699 if (hsotg
->driver
) {
3700 /* should have been done already by driver model core */
3701 usb_gadget_unregister_driver(hsotg
->driver
);
3704 s3c_hsotg_phy_disable(hsotg
);
3706 clk_disable_unprepare(hsotg
->clk
);
3708 device_unregister(&hsotg
->gadget
.dev
);
3713 #define s3c_hsotg_suspend NULL
3714 #define s3c_hsotg_resume NULL
3717 static struct platform_driver s3c_hsotg_driver
= {
3719 .name
= "s3c-hsotg",
3720 .owner
= THIS_MODULE
,
3722 .probe
= s3c_hsotg_probe
,
3723 .remove
= s3c_hsotg_remove
,
3724 .suspend
= s3c_hsotg_suspend
,
3725 .resume
= s3c_hsotg_resume
,
3728 module_platform_driver(s3c_hsotg_driver
);
3730 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3731 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3732 MODULE_LICENSE("GPL");
3733 MODULE_ALIAS("platform:s3c-hsotg");