2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/platform_data/s3c-hsotg.h>
39 #include "s3c-hsotg.h"
41 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 static const char * const s3c_hsotg_supply_names
[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
51 * Unfortunately there seems to be a limit of the amount of data that can
52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
53 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * This means if we are wanting to move >127 bytes of data, we need to
57 * split the transactions up, but just doing one packet at a time does
58 * not work (this may be an implicit DATA0 PID on first packet of the
59 * transaction) and doing 2 packets is outside the controller's limits.
61 * If we try to lower the MPS size for EP0, then no transfers work properly
62 * for EP0, and the system will fail basic enumeration. As no cause for this
63 * has currently been found, we cannot support any large IN transfers for
66 #define EP0_MPS_LIMIT 64
72 * struct s3c_hsotg_ep - driver endpoint definition.
73 * @ep: The gadget layer representation of the endpoint.
74 * @name: The driver generated name for the endpoint.
75 * @queue: Queue of requests for this endpoint.
76 * @parent: Reference back to the parent device structure.
77 * @req: The current request that the endpoint is processing. This is
78 * used to indicate an request has been loaded onto the endpoint
79 * and has yet to be completed (maybe due to data move, or simply
80 * awaiting an ack from the core all the data has been completed).
81 * @debugfs: File entry for debugfs file for this endpoint.
82 * @lock: State lock to protect contents of endpoint.
83 * @dir_in: Set to true if this endpoint is of the IN direction, which
84 * means that it is sending data to the Host.
85 * @index: The index for the endpoint registers.
86 * @name: The name array passed to the USB core.
87 * @halted: Set if the endpoint has been halted.
88 * @periodic: Set if this is a periodic ep, such as Interrupt
89 * @sent_zlp: Set if we've sent a zero-length packet.
90 * @total_data: The total number of data bytes done.
91 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
92 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
93 * @last_load: The offset of data for the last start of request.
94 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
96 * This is the driver's state for each registered enpoint, allowing it
97 * to keep track of transactions that need doing. Each endpoint has a
98 * lock to protect the state, to try and avoid using an overall lock
99 * for the host controller as much as possible.
101 * For periodic IN endpoints, we have fifo_size and fifo_load to try
102 * and keep track of the amount of data in the periodic FIFO for each
103 * of these as we don't have a status register that tells us how much
104 * is in each of them. (note, this may actually be useless information
105 * as in shared-fifo mode periodic in acts like a single-frame packet
106 * buffer than a fifo)
108 struct s3c_hsotg_ep
{
110 struct list_head queue
;
111 struct s3c_hsotg
*parent
;
112 struct s3c_hsotg_req
*req
;
113 struct dentry
*debugfs
;
117 unsigned long total_data
;
118 unsigned int size_loaded
;
119 unsigned int last_load
;
120 unsigned int fifo_load
;
121 unsigned short fifo_size
;
123 unsigned char dir_in
;
126 unsigned int halted
:1;
127 unsigned int periodic
:1;
128 unsigned int sent_zlp
:1;
134 * struct s3c_hsotg - driver state.
135 * @dev: The parent device supplied to the probe function
136 * @driver: USB gadget driver
137 * @plat: The platform specific configuration data.
138 * @regs: The memory area mapped for accessing registers.
139 * @irq: The IRQ number we are using
140 * @supplies: Definition of USB power supplies
141 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
142 * @num_of_eps: Number of available EPs (excluding EP0)
143 * @debug_root: root directrory for debugfs.
144 * @debug_file: main status file for debugfs.
145 * @debug_fifo: FIFO status file for debugfs.
146 * @ep0_reply: Request used for ep0 reply.
147 * @ep0_buff: Buffer for EP0 reply data, if needed.
148 * @ctrl_buff: Buffer for EP0 control requests.
149 * @ctrl_req: Request for EP0 control packets.
150 * @setup: NAK management for EP0 SETUP
151 * @last_rst: Time of last reset
152 * @eps: The endpoints being supplied to the gadget framework
156 struct usb_gadget_driver
*driver
;
157 struct s3c_hsotg_plat
*plat
;
163 struct regulator_bulk_data supplies
[ARRAY_SIZE(s3c_hsotg_supply_names
)];
165 unsigned int dedicated_fifos
:1;
166 unsigned char num_of_eps
;
168 struct dentry
*debug_root
;
169 struct dentry
*debug_file
;
170 struct dentry
*debug_fifo
;
172 struct usb_request
*ep0_reply
;
173 struct usb_request
*ctrl_req
;
177 struct usb_gadget gadget
;
179 unsigned long last_rst
;
180 struct s3c_hsotg_ep
*eps
;
184 * struct s3c_hsotg_req - data transfer request
185 * @req: The USB gadget request
186 * @queue: The list of requests for the endpoint this is queued for.
187 * @in_progress: Has already had size/packets written to core
188 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
190 struct s3c_hsotg_req
{
191 struct usb_request req
;
192 struct list_head queue
;
193 unsigned char in_progress
;
194 unsigned char mapped
;
197 /* conversion functions */
198 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
200 return container_of(req
, struct s3c_hsotg_req
, req
);
203 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
205 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
208 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
210 return container_of(gadget
, struct s3c_hsotg
, gadget
);
213 static inline void __orr32(void __iomem
*ptr
, u32 val
)
215 writel(readl(ptr
) | val
, ptr
);
218 static inline void __bic32(void __iomem
*ptr
, u32 val
)
220 writel(readl(ptr
) & ~val
, ptr
);
223 /* forward decleration of functions */
224 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
227 * using_dma - return the DMA status of the driver.
228 * @hsotg: The driver state.
230 * Return true if we're using DMA.
232 * Currently, we have the DMA support code worked into everywhere
233 * that needs it, but the AMBA DMA implementation in the hardware can
234 * only DMA from 32bit aligned addresses. This means that gadgets such
235 * as the CDC Ethernet cannot work as they often pass packets which are
238 * Unfortunately the choice to use DMA or not is global to the controller
239 * and seems to be only settable when the controller is being put through
240 * a core reset. This means we either need to fix the gadgets to take
241 * account of DMA alignment, or add bounce buffers (yuerk).
243 * Until this issue is sorted out, we always return 'false'.
245 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
247 return false; /* support is not complete */
251 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
252 * @hsotg: The device state
253 * @ints: A bitmask of the interrupts to enable
255 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
257 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
260 new_gsintmsk
= gsintmsk
| ints
;
262 if (new_gsintmsk
!= gsintmsk
) {
263 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
264 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
269 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
270 * @hsotg: The device state
271 * @ints: A bitmask of the interrupts to enable
273 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
275 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
278 new_gsintmsk
= gsintmsk
& ~ints
;
280 if (new_gsintmsk
!= gsintmsk
)
281 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
285 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
286 * @hsotg: The device state
287 * @ep: The endpoint index
288 * @dir_in: True if direction is in.
289 * @en: The enable value, true to enable
291 * Set or clear the mask for an individual endpoint's interrupt
294 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
295 unsigned int ep
, unsigned int dir_in
,
305 local_irq_save(flags
);
306 daint
= readl(hsotg
->regs
+ DAINTMSK
);
311 writel(daint
, hsotg
->regs
+ DAINTMSK
);
312 local_irq_restore(flags
);
316 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
317 * @hsotg: The device instance.
319 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
327 /* set FIFO sizes to 2048/1024 */
329 writel(2048, hsotg
->regs
+ GRXFSIZ
);
330 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
331 GNPTXFSIZ_NPTxFDep(1024),
332 hsotg
->regs
+ GNPTXFSIZ
);
335 * arange all the rest of the TX FIFOs, as some versions of this
336 * block have overlapping default addresses. This also ensures
337 * that if the settings have been changed, then they are set to
341 /* start at the end of the GNPTXFSIZ, rounded up */
346 * currently we allocate TX FIFOs for all possible endpoints,
347 * and assume that they are all the same size.
350 for (ep
= 1; ep
<= 15; ep
++) {
352 val
|= size
<< DPTXFSIZn_DPTxFSize_SHIFT
;
355 writel(val
, hsotg
->regs
+ DPTXFSIZn(ep
));
359 * according to p428 of the design guide, we need to ensure that
360 * all fifos are flushed before continuing
363 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh
|
364 GRSTCTL_RxFFlsh
, hsotg
->regs
+ GRSTCTL
);
366 /* wait until the fifos are both flushed */
369 val
= readl(hsotg
->regs
+ GRSTCTL
);
371 if ((val
& (GRSTCTL_TxFFlsh
| GRSTCTL_RxFFlsh
)) == 0)
374 if (--timeout
== 0) {
376 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
383 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
387 * @ep: USB endpoint to allocate request for.
388 * @flags: Allocation flags
390 * Allocate a new USB request structure appropriate for the specified endpoint
392 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
395 struct s3c_hsotg_req
*req
;
397 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
401 INIT_LIST_HEAD(&req
->queue
);
403 req
->req
.dma
= DMA_ADDR_INVALID
;
408 * is_ep_periodic - return true if the endpoint is in periodic mode.
409 * @hs_ep: The endpoint to query.
411 * Returns true if the endpoint is in periodic mode, meaning it is being
412 * used for an Interrupt or ISO transfer.
414 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
416 return hs_ep
->periodic
;
420 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
421 * @hsotg: The device state.
422 * @hs_ep: The endpoint for the request
423 * @hs_req: The request being processed.
425 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
426 * of a request to ensure the buffer is ready for access by the caller.
428 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
429 struct s3c_hsotg_ep
*hs_ep
,
430 struct s3c_hsotg_req
*hs_req
)
432 struct usb_request
*req
= &hs_req
->req
;
433 enum dma_data_direction dir
;
435 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
437 /* ignore this if we're not moving any data */
438 if (hs_req
->req
.length
== 0)
441 if (hs_req
->mapped
) {
442 /* we mapped this, so unmap and remove the dma */
444 dma_unmap_single(hsotg
->dev
, req
->dma
, req
->length
, dir
);
446 req
->dma
= DMA_ADDR_INVALID
;
449 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
454 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
455 * @hsotg: The controller state.
456 * @hs_ep: The endpoint we're going to write for.
457 * @hs_req: The request to write data for.
459 * This is called when the TxFIFO has some space in it to hold a new
460 * transmission and we have something to give it. The actual setup of
461 * the data size is done elsewhere, so all we have to do is to actually
464 * The return value is zero if there is more space (or nothing was done)
465 * otherwise -ENOSPC is returned if the FIFO space was used up.
467 * This routine is only needed for PIO
469 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
470 struct s3c_hsotg_ep
*hs_ep
,
471 struct s3c_hsotg_req
*hs_req
)
473 bool periodic
= is_ep_periodic(hs_ep
);
474 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
475 int buf_pos
= hs_req
->req
.actual
;
476 int to_write
= hs_ep
->size_loaded
;
481 to_write
-= (buf_pos
- hs_ep
->last_load
);
483 /* if there's nothing to write, get out early */
487 if (periodic
&& !hsotg
->dedicated_fifos
) {
488 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
493 * work out how much data was loaded so we can calculate
494 * how much data is left in the fifo.
497 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
500 * if shared fifo, we cannot write anything until the
501 * previous data has been completely sent.
503 if (hs_ep
->fifo_load
!= 0) {
504 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
508 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
510 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
512 /* how much of the data has moved */
513 size_done
= hs_ep
->size_loaded
- size_left
;
515 /* how much data is left in the fifo */
516 can_write
= hs_ep
->fifo_load
- size_done
;
517 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
518 __func__
, can_write
);
520 can_write
= hs_ep
->fifo_size
- can_write
;
521 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
522 __func__
, can_write
);
524 if (can_write
<= 0) {
525 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
528 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
529 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
534 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
536 "%s: no queue slots available (0x%08x)\n",
539 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTxFEmp
);
543 can_write
= GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
544 can_write
*= 4; /* fifo size is in 32bit quantities. */
547 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
548 __func__
, gnptxsts
, can_write
, to_write
, hs_ep
->ep
.maxpacket
);
551 * limit to 512 bytes of data, it seems at least on the non-periodic
552 * FIFO, requests of >512 cause the endpoint to get stuck with a
553 * fragment of the end of the transfer in it.
559 * limit the write to one max-packet size worth of data, but allow
560 * the transfer to return that it did not run out of fifo space
563 if (to_write
> hs_ep
->ep
.maxpacket
) {
564 to_write
= hs_ep
->ep
.maxpacket
;
566 s3c_hsotg_en_gsint(hsotg
,
567 periodic
? GINTSTS_PTxFEmp
:
571 /* see if we can write data */
573 if (to_write
> can_write
) {
574 to_write
= can_write
;
575 pkt_round
= to_write
% hs_ep
->ep
.maxpacket
;
578 * Round the write down to an
579 * exact number of packets.
581 * Note, we do not currently check to see if we can ever
582 * write a full packet or not to the FIFO.
586 to_write
-= pkt_round
;
589 * enable correct FIFO interrupt to alert us when there
593 s3c_hsotg_en_gsint(hsotg
,
594 periodic
? GINTSTS_PTxFEmp
:
598 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
599 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
604 hs_req
->req
.actual
= buf_pos
+ to_write
;
605 hs_ep
->total_data
+= to_write
;
608 hs_ep
->fifo_load
+= to_write
;
610 to_write
= DIV_ROUND_UP(to_write
, 4);
611 data
= hs_req
->req
.buf
+ buf_pos
;
613 writesl(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
615 return (to_write
>= can_write
) ? -ENOSPC
: 0;
619 * get_ep_limit - get the maximum data legnth for this endpoint
620 * @hs_ep: The endpoint
622 * Return the maximum data that can be queued in one go on a given endpoint
623 * so that transfers that are too long can be split.
625 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
627 int index
= hs_ep
->index
;
632 maxsize
= DxEPTSIZ_XferSize_LIMIT
+ 1;
633 maxpkt
= DxEPTSIZ_PktCnt_LIMIT
+ 1;
637 maxpkt
= DIEPTSIZ0_PktCnt_LIMIT
+ 1;
642 /* we made the constant loading easier above by using +1 */
647 * constrain by packet count if maxpkts*pktsize is greater
648 * than the length register size.
651 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
652 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
658 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
659 * @hsotg: The controller state.
660 * @hs_ep: The endpoint to process a request for
661 * @hs_req: The request to start.
662 * @continuing: True if we are doing more for the current request.
664 * Start the given request running by setting the endpoint registers
665 * appropriately, and writing any data to the FIFOs.
667 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
668 struct s3c_hsotg_ep
*hs_ep
,
669 struct s3c_hsotg_req
*hs_req
,
672 struct usb_request
*ureq
= &hs_req
->req
;
673 int index
= hs_ep
->index
;
674 int dir_in
= hs_ep
->dir_in
;
684 if (hs_ep
->req
&& !continuing
) {
685 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
688 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
690 "%s: continue different req\n", __func__
);
696 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
697 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
699 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
700 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
701 hs_ep
->dir_in
? "in" : "out");
703 /* If endpoint is stalled, we will restart request later */
704 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
706 if (ctrl
& DxEPCTL_Stall
) {
707 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
711 length
= ureq
->length
- ureq
->actual
;
712 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
713 ureq
->length
, ureq
->actual
);
716 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
717 ureq
->buf
, length
, ureq
->dma
,
718 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
720 maxreq
= get_ep_limit(hs_ep
);
721 if (length
> maxreq
) {
722 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
724 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
725 __func__
, length
, maxreq
, round
);
727 /* round down to multiple of packets */
735 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
737 packets
= 1; /* send one packet if length is zero. */
739 if (dir_in
&& index
!= 0)
740 epsize
= DxEPTSIZ_MC(1);
744 if (index
!= 0 && ureq
->zero
) {
746 * test for the packets being exactly right for the
750 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
754 epsize
|= DxEPTSIZ_PktCnt(packets
);
755 epsize
|= DxEPTSIZ_XferSize(length
);
757 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
758 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
760 /* store the request as the current one we're doing */
763 /* write size / packets */
764 writel(epsize
, hsotg
->regs
+ epsize_reg
);
766 if (using_dma(hsotg
) && !continuing
) {
767 unsigned int dma_reg
;
770 * write DMA address to control register, buffer already
771 * synced by s3c_hsotg_ep_queue().
774 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
775 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
777 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
778 __func__
, ureq
->dma
, dma_reg
);
781 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
782 ctrl
|= DxEPCTL_USBActEp
;
784 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
786 /* For Setup request do not clear NAK */
787 if (hsotg
->setup
&& index
== 0)
790 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
793 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
794 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
797 * set these, it seems that DMA support increments past the end
798 * of the packet buffer so we need to calculate the length from
801 hs_ep
->size_loaded
= length
;
802 hs_ep
->last_load
= ureq
->actual
;
804 if (dir_in
&& !using_dma(hsotg
)) {
805 /* set these anyway, we may need them for non-periodic in */
806 hs_ep
->fifo_load
= 0;
808 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
812 * clear the INTknTXFEmpMsk when we start request, more as a aide
813 * to debugging to see what is going on.
816 writel(DIEPMSK_INTknTXFEmpMsk
,
817 hsotg
->regs
+ DIEPINT(index
));
820 * Note, trying to clear the NAK here causes problems with transmit
821 * on the S3C6400 ending up with the TXFIFO becoming full.
824 /* check ep is enabled */
825 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DxEPCTL_EPEna
))
827 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
828 index
, readl(hsotg
->regs
+ epctrl_reg
));
830 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
831 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
835 * s3c_hsotg_map_dma - map the DMA memory being used for the request
836 * @hsotg: The device state.
837 * @hs_ep: The endpoint the request is on.
838 * @req: The request being processed.
840 * We've been asked to queue a request, so ensure that the memory buffer
841 * is correctly setup for DMA. If we've been passed an extant DMA address
842 * then ensure the buffer has been synced to memory. If our buffer has no
843 * DMA memory, then we map the memory and mark our request to allow us to
844 * cleanup on completion.
846 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
847 struct s3c_hsotg_ep
*hs_ep
,
848 struct usb_request
*req
)
850 enum dma_data_direction dir
;
851 struct s3c_hsotg_req
*hs_req
= our_req(req
);
853 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
855 /* if the length is zero, ignore the DMA data */
856 if (hs_req
->req
.length
== 0)
859 if (req
->dma
== DMA_ADDR_INVALID
) {
862 dma
= dma_map_single(hsotg
->dev
, req
->buf
, req
->length
, dir
);
864 if (unlikely(dma_mapping_error(hsotg
->dev
, dma
)))
868 dev_err(hsotg
->dev
, "%s: unaligned dma buffer\n",
871 dma_unmap_single(hsotg
->dev
, dma
, req
->length
, dir
);
878 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
885 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
886 __func__
, req
->buf
, req
->length
);
891 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
894 struct s3c_hsotg_req
*hs_req
= our_req(req
);
895 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
896 struct s3c_hsotg
*hs
= hs_ep
->parent
;
897 unsigned long irqflags
;
900 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
901 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
902 req
->zero
, req
->short_not_ok
);
904 /* initialise status of the request */
905 INIT_LIST_HEAD(&hs_req
->queue
);
907 req
->status
= -EINPROGRESS
;
909 /* if we're using DMA, sync the buffers as necessary */
911 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
916 spin_lock_irqsave(&hs_ep
->lock
, irqflags
);
918 first
= list_empty(&hs_ep
->queue
);
919 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
922 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
924 spin_unlock_irqrestore(&hs_ep
->lock
, irqflags
);
929 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
930 struct usb_request
*req
)
932 struct s3c_hsotg_req
*hs_req
= our_req(req
);
938 * s3c_hsotg_complete_oursetup - setup completion callback
939 * @ep: The endpoint the request was on.
940 * @req: The request completed.
942 * Called on completion of any requests the driver itself
943 * submitted that need cleaning up.
945 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
946 struct usb_request
*req
)
948 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
949 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
951 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
953 s3c_hsotg_ep_free_request(ep
, req
);
957 * ep_from_windex - convert control wIndex value to endpoint
958 * @hsotg: The driver state.
959 * @windex: The control request wIndex field (in host order).
961 * Convert the given wIndex into a pointer to an driver endpoint
962 * structure, or return NULL if it is not a valid endpoint.
964 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
967 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
968 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
969 int idx
= windex
& 0x7F;
974 if (idx
> hsotg
->num_of_eps
)
977 if (idx
&& ep
->dir_in
!= dir
)
984 * s3c_hsotg_send_reply - send reply to control request
985 * @hsotg: The device state
987 * @buff: Buffer for request
988 * @length: Length of reply.
990 * Create a request and queue it on the given endpoint. This is useful as
991 * an internal method of sending replies to certain control requests, etc.
993 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
994 struct s3c_hsotg_ep
*ep
,
998 struct usb_request
*req
;
1001 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1003 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1004 hsotg
->ep0_reply
= req
;
1006 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1010 req
->buf
= hsotg
->ep0_buff
;
1011 req
->length
= length
;
1012 req
->zero
= 1; /* always do zero-length final transfer */
1013 req
->complete
= s3c_hsotg_complete_oursetup
;
1016 memcpy(req
->buf
, buff
, length
);
1020 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1022 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1030 * s3c_hsotg_process_req_status - process request GET_STATUS
1031 * @hsotg: The device state
1032 * @ctrl: USB control request
1034 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
1035 struct usb_ctrlrequest
*ctrl
)
1037 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1038 struct s3c_hsotg_ep
*ep
;
1042 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1045 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1049 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1050 case USB_RECIP_DEVICE
:
1051 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1052 * bit 1 => remote wakeup */
1055 case USB_RECIP_INTERFACE
:
1056 /* currently, the data result should be zero */
1057 reply
= cpu_to_le16(0);
1060 case USB_RECIP_ENDPOINT
:
1061 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1065 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1072 if (le16_to_cpu(ctrl
->wLength
) != 2)
1075 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1077 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1084 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1087 * get_ep_head - return the first request on the endpoint
1088 * @hs_ep: The controller endpoint to get
1090 * Get the first request on the endpoint.
1092 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1094 if (list_empty(&hs_ep
->queue
))
1097 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1101 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1102 * @hsotg: The device state
1103 * @ctrl: USB control request
1105 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1106 struct usb_ctrlrequest
*ctrl
)
1108 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1109 struct s3c_hsotg_req
*hs_req
;
1111 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1112 struct s3c_hsotg_ep
*ep
;
1115 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1116 __func__
, set
? "SET" : "CLEAR");
1118 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1119 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1121 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1122 __func__
, le16_to_cpu(ctrl
->wIndex
));
1126 switch (le16_to_cpu(ctrl
->wValue
)) {
1127 case USB_ENDPOINT_HALT
:
1128 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1130 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1133 "%s: failed to send reply\n", __func__
);
1139 * If we have request in progress,
1145 list_del_init(&hs_req
->queue
);
1146 hs_req
->req
.complete(&ep
->ep
,
1150 /* If we have pending request, then start it */
1151 restart
= !list_empty(&ep
->queue
);
1153 hs_req
= get_ep_head(ep
);
1154 s3c_hsotg_start_req(hsotg
, ep
,
1165 return -ENOENT
; /* currently only deal with endpoint */
1171 * s3c_hsotg_process_control - process a control request
1172 * @hsotg: The device state
1173 * @ctrl: The control request received
1175 * The controller has received the SETUP phase of a control request, and
1176 * needs to work out what to do next (and whether to pass it on to the
1179 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1180 struct usb_ctrlrequest
*ctrl
)
1182 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1188 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1189 ctrl
->bRequest
, ctrl
->bRequestType
,
1190 ctrl
->wValue
, ctrl
->wLength
);
1193 * record the direction of the request, for later use when enquing
1197 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1198 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1201 * if we've no data with this request, then the last part of the
1202 * transaction is going to implicitly be IN.
1204 if (ctrl
->wLength
== 0)
1207 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1208 switch (ctrl
->bRequest
) {
1209 case USB_REQ_SET_ADDRESS
:
1210 dcfg
= readl(hsotg
->regs
+ DCFG
);
1211 dcfg
&= ~DCFG_DevAddr_MASK
;
1212 dcfg
|= ctrl
->wValue
<< DCFG_DevAddr_SHIFT
;
1213 writel(dcfg
, hsotg
->regs
+ DCFG
);
1215 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1217 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1220 case USB_REQ_GET_STATUS
:
1221 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1224 case USB_REQ_CLEAR_FEATURE
:
1225 case USB_REQ_SET_FEATURE
:
1226 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1231 /* as a fallback, try delivering it to the driver to deal with */
1233 if (ret
== 0 && hsotg
->driver
) {
1234 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1236 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1240 * the request is either unhandlable, or is not formatted correctly
1241 * so respond with a STALL for the status stage to indicate failure.
1248 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1249 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1252 * DxEPCTL_Stall will be cleared by EP once it has
1253 * taken effect, so no need to clear later.
1256 ctrl
= readl(hsotg
->regs
+ reg
);
1257 ctrl
|= DxEPCTL_Stall
;
1258 ctrl
|= DxEPCTL_CNAK
;
1259 writel(ctrl
, hsotg
->regs
+ reg
);
1262 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1263 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1266 * don't believe we need to anything more to get the EP
1267 * to reply with a STALL packet
1272 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1275 * s3c_hsotg_complete_setup - completion of a setup transfer
1276 * @ep: The endpoint the request was on.
1277 * @req: The request completed.
1279 * Called on completion of any requests the driver itself submitted for
1282 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1283 struct usb_request
*req
)
1285 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1286 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1288 if (req
->status
< 0) {
1289 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1293 if (req
->actual
== 0)
1294 s3c_hsotg_enqueue_setup(hsotg
);
1296 s3c_hsotg_process_control(hsotg
, req
->buf
);
1300 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1301 * @hsotg: The device state.
1303 * Enqueue a request on EP0 if necessary to received any SETUP packets
1304 * received from the host.
1306 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1308 struct usb_request
*req
= hsotg
->ctrl_req
;
1309 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1312 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1316 req
->buf
= hsotg
->ctrl_buff
;
1317 req
->complete
= s3c_hsotg_complete_setup
;
1319 if (!list_empty(&hs_req
->queue
)) {
1320 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1324 hsotg
->eps
[0].dir_in
= 0;
1326 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1328 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1330 * Don't think there's much we can do other than watch the
1337 * s3c_hsotg_complete_request - complete a request given to us
1338 * @hsotg: The device state.
1339 * @hs_ep: The endpoint the request was on.
1340 * @hs_req: The request to complete.
1341 * @result: The result code (0 => Ok, otherwise errno)
1343 * The given request has finished, so call the necessary completion
1344 * if it has one and then look to see if we can start a new request
1347 * Note, expects the ep to already be locked as appropriate.
1349 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1350 struct s3c_hsotg_ep
*hs_ep
,
1351 struct s3c_hsotg_req
*hs_req
,
1357 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1361 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1362 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1365 * only replace the status if we've not already set an error
1366 * from a previous transaction
1369 if (hs_req
->req
.status
== -EINPROGRESS
)
1370 hs_req
->req
.status
= result
;
1373 list_del_init(&hs_req
->queue
);
1375 if (using_dma(hsotg
))
1376 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1379 * call the complete request with the locks off, just in case the
1380 * request tries to queue more work for this endpoint.
1383 if (hs_req
->req
.complete
) {
1384 spin_unlock(&hs_ep
->lock
);
1385 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1386 spin_lock(&hs_ep
->lock
);
1390 * Look to see if there is anything else to do. Note, the completion
1391 * of the previous request may have caused a new request to be started
1392 * so be careful when doing this.
1395 if (!hs_ep
->req
&& result
>= 0) {
1396 restart
= !list_empty(&hs_ep
->queue
);
1398 hs_req
= get_ep_head(hs_ep
);
1399 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1405 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1406 * @hsotg: The device state.
1407 * @hs_ep: The endpoint the request was on.
1408 * @hs_req: The request to complete.
1409 * @result: The result code (0 => Ok, otherwise errno)
1411 * See s3c_hsotg_complete_request(), but called with the endpoint's
1414 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg
*hsotg
,
1415 struct s3c_hsotg_ep
*hs_ep
,
1416 struct s3c_hsotg_req
*hs_req
,
1419 unsigned long flags
;
1421 spin_lock_irqsave(&hs_ep
->lock
, flags
);
1422 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1423 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
1427 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1428 * @hsotg: The device state.
1429 * @ep_idx: The endpoint index for the data
1430 * @size: The size of data in the fifo, in bytes
1432 * The FIFO status shows there is data to read from the FIFO for a given
1433 * endpoint, so sort out whether we need to read the data into a request
1434 * that has been made for that endpoint.
1436 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1438 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1439 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1440 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1446 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1449 dev_warn(hsotg
->dev
,
1450 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1451 __func__
, size
, ep_idx
, epctl
);
1453 /* dump the data from the FIFO, we've nothing we can do */
1454 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1460 spin_lock(&hs_ep
->lock
);
1463 read_ptr
= hs_req
->req
.actual
;
1464 max_req
= hs_req
->req
.length
- read_ptr
;
1466 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1467 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1469 if (to_read
> max_req
) {
1471 * more data appeared than we where willing
1472 * to deal with in this request.
1475 /* currently we don't deal this */
1479 hs_ep
->total_data
+= to_read
;
1480 hs_req
->req
.actual
+= to_read
;
1481 to_read
= DIV_ROUND_UP(to_read
, 4);
1484 * note, we might over-write the buffer end by 3 bytes depending on
1485 * alignment of the data.
1487 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1489 spin_unlock(&hs_ep
->lock
);
1493 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1494 * @hsotg: The device instance
1495 * @req: The request currently on this endpoint
1497 * Generate a zero-length IN packet request for terminating a SETUP
1500 * Note, since we don't write any data to the TxFIFO, then it is
1501 * currently believed that we do not need to wait for any space in
1504 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1505 struct s3c_hsotg_req
*req
)
1510 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1514 if (req
->req
.length
== 0) {
1515 hsotg
->eps
[0].sent_zlp
= 1;
1516 s3c_hsotg_enqueue_setup(hsotg
);
1520 hsotg
->eps
[0].dir_in
= 1;
1521 hsotg
->eps
[0].sent_zlp
= 1;
1523 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1525 /* issue a zero-sized packet to terminate this */
1526 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1527 DxEPTSIZ_XferSize(0), hsotg
->regs
+ DIEPTSIZ(0));
1529 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1530 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
1531 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
1532 ctrl
|= DxEPCTL_USBActEp
;
1533 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1537 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1538 * @hsotg: The device instance
1539 * @epnum: The endpoint received from
1540 * @was_setup: Set if processing a SetupDone event.
1542 * The RXFIFO has delivered an OutDone event, which means that the data
1543 * transfer for an OUT endpoint has been completed, either by a short
1544 * packet or by the finish of a transfer.
1546 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1547 int epnum
, bool was_setup
)
1549 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1550 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1551 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1552 struct usb_request
*req
= &hs_req
->req
;
1553 unsigned size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1557 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1561 if (using_dma(hsotg
)) {
1565 * Calculate the size of the transfer by checking how much
1566 * is left in the endpoint size register and then working it
1567 * out from the amount we loaded for the transfer.
1569 * We need to do this as DMA pointers are always 32bit aligned
1570 * so may overshoot/undershoot the transfer.
1573 size_done
= hs_ep
->size_loaded
- size_left
;
1574 size_done
+= hs_ep
->last_load
;
1576 req
->actual
= size_done
;
1579 /* if there is more request to do, schedule new transfer */
1580 if (req
->actual
< req
->length
&& size_left
== 0) {
1581 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1583 } else if (epnum
== 0) {
1585 * After was_setup = 1 =>
1586 * set CNAK for non Setup requests
1588 hsotg
->setup
= was_setup
? 0 : 1;
1591 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1592 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1593 __func__
, req
->actual
, req
->length
);
1596 * todo - what should we return here? there's no one else
1597 * even bothering to check the status.
1603 * Condition req->complete != s3c_hsotg_complete_setup says:
1604 * send ZLP when we have an asynchronous request from gadget
1606 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1607 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1610 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, result
);
1614 * s3c_hsotg_read_frameno - read current frame number
1615 * @hsotg: The device instance
1617 * Return the current frame number
1619 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1623 dsts
= readl(hsotg
->regs
+ DSTS
);
1624 dsts
&= DSTS_SOFFN_MASK
;
1625 dsts
>>= DSTS_SOFFN_SHIFT
;
1631 * s3c_hsotg_handle_rx - RX FIFO has data
1632 * @hsotg: The device instance
1634 * The IRQ handler has detected that the RX FIFO has some data in it
1635 * that requires processing, so find out what is in there and do the
1638 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1639 * chunks, so if you have x packets received on an endpoint you'll get x
1640 * FIFO events delivered, each with a packet's worth of data in it.
1642 * When using DMA, we should not be processing events from the RXFIFO
1643 * as the actual data should be sent to the memory directly and we turn
1644 * on the completion interrupts to get notifications of transfer completion.
1646 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1648 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1649 u32 epnum
, status
, size
;
1651 WARN_ON(using_dma(hsotg
));
1653 epnum
= grxstsr
& GRXSTS_EPNum_MASK
;
1654 status
= grxstsr
& GRXSTS_PktSts_MASK
;
1656 size
= grxstsr
& GRXSTS_ByteCnt_MASK
;
1657 size
>>= GRXSTS_ByteCnt_SHIFT
;
1660 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1661 __func__
, grxstsr
, size
, epnum
);
1663 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1665 switch (status
>> GRXSTS_PktSts_SHIFT
) {
1666 case __status(GRXSTS_PktSts_GlobalOutNAK
):
1667 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1670 case __status(GRXSTS_PktSts_OutDone
):
1671 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1672 s3c_hsotg_read_frameno(hsotg
));
1674 if (!using_dma(hsotg
))
1675 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1678 case __status(GRXSTS_PktSts_SetupDone
):
1680 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1681 s3c_hsotg_read_frameno(hsotg
),
1682 readl(hsotg
->regs
+ DOEPCTL(0)));
1684 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1687 case __status(GRXSTS_PktSts_OutRX
):
1688 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1691 case __status(GRXSTS_PktSts_SetupRX
):
1693 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1694 s3c_hsotg_read_frameno(hsotg
),
1695 readl(hsotg
->regs
+ DOEPCTL(0)));
1697 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1701 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1704 s3c_hsotg_dump(hsotg
);
1710 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1711 * @mps: The maximum packet size in bytes.
1713 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1717 return D0EPCTL_MPS_64
;
1719 return D0EPCTL_MPS_32
;
1721 return D0EPCTL_MPS_16
;
1723 return D0EPCTL_MPS_8
;
1726 /* bad max packet size, warn and return invalid result */
1732 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1733 * @hsotg: The driver state.
1734 * @ep: The index number of the endpoint
1735 * @mps: The maximum packet size in bytes
1737 * Configure the maximum packet size for the given endpoint, updating
1738 * the hardware control registers to reflect this.
1740 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1741 unsigned int ep
, unsigned int mps
)
1743 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1744 void __iomem
*regs
= hsotg
->regs
;
1749 /* EP0 is a special case */
1750 mpsval
= s3c_hsotg_ep0_mps(mps
);
1754 if (mps
>= DxEPCTL_MPS_LIMIT
+1)
1760 hs_ep
->ep
.maxpacket
= mps
;
1763 * update both the in and out endpoint controldir_ registers, even
1764 * if one of the directions may not be in use.
1767 reg
= readl(regs
+ DIEPCTL(ep
));
1768 reg
&= ~DxEPCTL_MPS_MASK
;
1770 writel(reg
, regs
+ DIEPCTL(ep
));
1773 reg
= readl(regs
+ DOEPCTL(ep
));
1774 reg
&= ~DxEPCTL_MPS_MASK
;
1776 writel(reg
, regs
+ DOEPCTL(ep
));
1782 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1786 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1787 * @hsotg: The driver state
1788 * @idx: The index for the endpoint (0..15)
1790 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg
*hsotg
, unsigned int idx
)
1795 writel(GRSTCTL_TxFNum(idx
) | GRSTCTL_TxFFlsh
,
1796 hsotg
->regs
+ GRSTCTL
);
1798 /* wait until the fifo is flushed */
1802 val
= readl(hsotg
->regs
+ GRSTCTL
);
1804 if ((val
& (GRSTCTL_TxFFlsh
)) == 0)
1807 if (--timeout
== 0) {
1809 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1818 * s3c_hsotg_trytx - check to see if anything needs transmitting
1819 * @hsotg: The driver state
1820 * @hs_ep: The driver endpoint to check.
1822 * Check to see if there is a request that has data to send, and if so
1823 * make an attempt to write data into the FIFO.
1825 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1826 struct s3c_hsotg_ep
*hs_ep
)
1828 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1830 if (!hs_ep
->dir_in
|| !hs_req
)
1833 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1834 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1836 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1843 * s3c_hsotg_complete_in - complete IN transfer
1844 * @hsotg: The device state.
1845 * @hs_ep: The endpoint that has just completed.
1847 * An IN transfer has been completed, update the transfer's state and then
1848 * call the relevant completion routines.
1850 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1851 struct s3c_hsotg_ep
*hs_ep
)
1853 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1854 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1855 int size_left
, size_done
;
1858 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1862 /* Finish ZLP handling for IN EP0 transactions */
1863 if (hsotg
->eps
[0].sent_zlp
) {
1864 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1865 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, 0);
1870 * Calculate the size of the transfer by checking how much is left
1871 * in the endpoint size register and then working it out from
1872 * the amount we loaded for the transfer.
1874 * We do this even for DMA, as the transfer may have incremented
1875 * past the end of the buffer (DMA transfers are always 32bit
1879 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1881 size_done
= hs_ep
->size_loaded
- size_left
;
1882 size_done
+= hs_ep
->last_load
;
1884 if (hs_req
->req
.actual
!= size_done
)
1885 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1886 __func__
, hs_req
->req
.actual
, size_done
);
1888 hs_req
->req
.actual
= size_done
;
1889 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1890 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1893 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1894 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1895 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1896 * inform the host that no more data is available.
1897 * The state of req.zero member is checked to be sure that the value to
1898 * send is smaller than wValue expected from host.
1899 * Check req.length to NOT send another ZLP when the current one is
1900 * under completion (the one for which this completion has been called).
1902 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1903 hs_req
->req
.length
== hs_req
->req
.actual
&&
1904 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1906 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1907 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1912 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1913 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1914 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1916 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, 0);
1920 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1921 * @hsotg: The driver state
1922 * @idx: The index for the endpoint (0..15)
1923 * @dir_in: Set if this is an IN endpoint
1925 * Process and clear any interrupt pending for an individual endpoint
1927 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1930 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1931 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1932 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1933 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1936 ints
= readl(hsotg
->regs
+ epint_reg
);
1938 /* Clear endpoint interrupts */
1939 writel(ints
, hsotg
->regs
+ epint_reg
);
1941 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1942 __func__
, idx
, dir_in
? "in" : "out", ints
);
1944 if (ints
& DxEPINT_XferCompl
) {
1946 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1947 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1948 readl(hsotg
->regs
+ epsiz_reg
));
1951 * we get OutDone from the FIFO, so we only need to look
1952 * at completing IN requests here
1955 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1957 if (idx
== 0 && !hs_ep
->req
)
1958 s3c_hsotg_enqueue_setup(hsotg
);
1959 } else if (using_dma(hsotg
)) {
1961 * We're using DMA, we need to fire an OutDone here
1962 * as we ignore the RXFIFO.
1965 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1969 if (ints
& DxEPINT_EPDisbld
) {
1970 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1973 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1975 s3c_hsotg_txfifo_flush(hsotg
, idx
);
1977 if ((epctl
& DxEPCTL_Stall
) &&
1978 (epctl
& DxEPCTL_EPType_Bulk
)) {
1979 int dctl
= readl(hsotg
->regs
+ DCTL
);
1981 dctl
|= DCTL_CGNPInNAK
;
1982 writel(dctl
, hsotg
->regs
+ DCTL
);
1987 if (ints
& DxEPINT_AHBErr
)
1988 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1990 if (ints
& DxEPINT_Setup
) { /* Setup or Timeout */
1991 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1993 if (using_dma(hsotg
) && idx
== 0) {
1995 * this is the notification we've received a
1996 * setup packet. In non-DMA mode we'd get this
1997 * from the RXFIFO, instead we need to process
2004 s3c_hsotg_handle_outdone(hsotg
, 0, true);
2008 if (ints
& DxEPINT_Back2BackSetup
)
2009 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2012 /* not sure if this is important, but we'll clear it anyway */
2013 if (ints
& DIEPMSK_INTknTXFEmpMsk
) {
2014 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2018 /* this probably means something bad is happening */
2019 if (ints
& DIEPMSK_INTknEPMisMsk
) {
2020 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2024 /* FIFO has space or is empty (see GAHBCFG) */
2025 if (hsotg
->dedicated_fifos
&&
2026 ints
& DIEPMSK_TxFIFOEmpty
) {
2027 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2029 if (!using_dma(hsotg
))
2030 s3c_hsotg_trytx(hsotg
, hs_ep
);
2036 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2037 * @hsotg: The device state.
2039 * Handle updating the device settings after the enumeration phase has
2042 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
2044 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
2045 int ep0_mps
= 0, ep_mps
;
2048 * This should signal the finish of the enumeration phase
2049 * of the USB handshaking, so we should now know what rate
2053 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2056 * note, since we're limited by the size of transfer on EP0, and
2057 * it seems IN transfers must be a even number of packets we do
2058 * not advertise a 64byte MPS on EP0.
2061 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2062 switch (dsts
& DSTS_EnumSpd_MASK
) {
2063 case DSTS_EnumSpd_FS
:
2064 case DSTS_EnumSpd_FS48
:
2065 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2066 ep0_mps
= EP0_MPS_LIMIT
;
2070 case DSTS_EnumSpd_HS
:
2071 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2072 ep0_mps
= EP0_MPS_LIMIT
;
2076 case DSTS_EnumSpd_LS
:
2077 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2079 * note, we don't actually support LS in this driver at the
2080 * moment, and the documentation seems to imply that it isn't
2081 * supported by the PHYs on some of the devices.
2085 dev_info(hsotg
->dev
, "new device is %s\n",
2086 usb_speed_string(hsotg
->gadget
.speed
));
2089 * we should now know the maximum packet size for an
2090 * endpoint, so set the endpoints to a default value.
2095 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
2096 for (i
= 1; i
< hsotg
->num_of_eps
; i
++)
2097 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
2100 /* ensure after enumeration our EP0 is active */
2102 s3c_hsotg_enqueue_setup(hsotg
);
2104 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2105 readl(hsotg
->regs
+ DIEPCTL0
),
2106 readl(hsotg
->regs
+ DOEPCTL0
));
2110 * kill_all_requests - remove all requests from the endpoint's queue
2111 * @hsotg: The device state.
2112 * @ep: The endpoint the requests may be on.
2113 * @result: The result code to use.
2114 * @force: Force removal of any current requests
2116 * Go through the requests on the given endpoint and mark them
2117 * completed with the given result code.
2119 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
2120 struct s3c_hsotg_ep
*ep
,
2121 int result
, bool force
)
2123 struct s3c_hsotg_req
*req
, *treq
;
2124 unsigned long flags
;
2126 spin_lock_irqsave(&ep
->lock
, flags
);
2128 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2130 * currently, we can't do much about an already
2131 * running request on an in endpoint
2134 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
2137 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2141 spin_unlock_irqrestore(&ep
->lock
, flags
);
2144 #define call_gadget(_hs, _entry) \
2145 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2146 (_hs)->driver && (_hs)->driver->_entry) \
2147 (_hs)->driver->_entry(&(_hs)->gadget);
2150 * s3c_hsotg_disconnect - disconnect service
2151 * @hsotg: The device state.
2153 * The device has been disconnected. Remove all current
2154 * transactions and signal the gadget driver that this
2157 static void s3c_hsotg_disconnect(struct s3c_hsotg
*hsotg
)
2161 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2162 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
2164 call_gadget(hsotg
, disconnect
);
2168 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2169 * @hsotg: The device state:
2170 * @periodic: True if this is a periodic FIFO interrupt
2172 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2174 struct s3c_hsotg_ep
*ep
;
2177 /* look through for any more data to transmit */
2179 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2180 ep
= &hsotg
->eps
[epno
];
2185 if ((periodic
&& !ep
->periodic
) ||
2186 (!periodic
&& ep
->periodic
))
2189 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2195 /* IRQ flags which will trigger a retry around the IRQ loop */
2196 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2201 * s3c_hsotg_corereset - issue softreset to the core
2202 * @hsotg: The device state
2204 * Issue a soft reset to the core, and await the core finishing it.
2206 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2211 dev_dbg(hsotg
->dev
, "resetting core\n");
2213 /* issue soft reset */
2214 writel(GRSTCTL_CSftRst
, hsotg
->regs
+ GRSTCTL
);
2218 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2219 } while ((grstctl
& GRSTCTL_CSftRst
) && timeout
-- > 0);
2221 if (grstctl
& GRSTCTL_CSftRst
) {
2222 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2229 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2231 if (timeout
-- < 0) {
2232 dev_info(hsotg
->dev
,
2233 "%s: reset failed, GRSTCTL=%08x\n",
2238 if (!(grstctl
& GRSTCTL_AHBIdle
))
2241 break; /* reset done */
2244 dev_dbg(hsotg
->dev
, "reset successful\n");
2249 * s3c_hsotg_core_init - issue softreset to the core
2250 * @hsotg: The device state
2252 * Issue a soft reset to the core, and await the core finishing it.
2254 static void s3c_hsotg_core_init(struct s3c_hsotg
*hsotg
)
2256 s3c_hsotg_corereset(hsotg
);
2259 * we must now enable ep0 ready for host detection and then
2260 * set configuration.
2263 /* set the PLL on, remove the HNP/SRP and set the PHY */
2264 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) |
2265 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2267 s3c_hsotg_init_fifo(hsotg
);
2269 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2271 writel(1 << 18 | DCFG_DevSpd_HS
, hsotg
->regs
+ DCFG
);
2273 /* Clear any pending OTG interrupts */
2274 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2276 /* Clear any pending interrupts */
2277 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2279 writel(GINTSTS_ErlySusp
| GINTSTS_SessReqInt
|
2280 GINTSTS_GOUTNakEff
| GINTSTS_GINNakEff
|
2281 GINTSTS_ConIDStsChng
| GINTSTS_USBRst
|
2282 GINTSTS_EnumDone
| GINTSTS_OTGInt
|
2283 GINTSTS_USBSusp
| GINTSTS_WkUpInt
,
2284 hsotg
->regs
+ GINTMSK
);
2286 if (using_dma(hsotg
))
2287 writel(GAHBCFG_GlblIntrEn
| GAHBCFG_DMAEn
|
2288 GAHBCFG_HBstLen_Incr4
,
2289 hsotg
->regs
+ GAHBCFG
);
2291 writel(GAHBCFG_GlblIntrEn
, hsotg
->regs
+ GAHBCFG
);
2294 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2295 * up being flooded with interrupts if the host is polling the
2296 * endpoint to try and read data.
2299 writel(((hsotg
->dedicated_fifos
) ? DIEPMSK_TxFIFOEmpty
: 0) |
2300 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
|
2301 DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2302 DIEPMSK_INTknEPMisMsk
,
2303 hsotg
->regs
+ DIEPMSK
);
2306 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2307 * DMA mode we may need this.
2309 writel((using_dma(hsotg
) ? (DIEPMSK_XferComplMsk
|
2310 DIEPMSK_TimeOUTMsk
) : 0) |
2311 DOEPMSK_EPDisbldMsk
| DOEPMSK_AHBErrMsk
|
2313 hsotg
->regs
+ DOEPMSK
);
2315 writel(0, hsotg
->regs
+ DAINTMSK
);
2317 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2318 readl(hsotg
->regs
+ DIEPCTL0
),
2319 readl(hsotg
->regs
+ DOEPCTL0
));
2321 /* enable in and out endpoint interrupts */
2322 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPInt
| GINTSTS_IEPInt
);
2325 * Enable the RXFIFO when in slave mode, as this is how we collect
2326 * the data. In DMA mode, we get events from the FIFO but also
2327 * things we cannot process, so do not use it.
2329 if (!using_dma(hsotg
))
2330 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RxFLvl
);
2332 /* Enable interrupts for EP0 in and out */
2333 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2334 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2336 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2337 udelay(10); /* see openiboot */
2338 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2340 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2343 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2344 * writing to the EPCTL register..
2347 /* set to read 1 8byte packet */
2348 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2349 DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2351 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2352 DxEPCTL_CNAK
| DxEPCTL_EPEna
|
2354 hsotg
->regs
+ DOEPCTL0
);
2356 /* enable, but don't activate EP0in */
2357 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2358 DxEPCTL_USBActEp
, hsotg
->regs
+ DIEPCTL0
);
2360 s3c_hsotg_enqueue_setup(hsotg
);
2362 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2363 readl(hsotg
->regs
+ DIEPCTL0
),
2364 readl(hsotg
->regs
+ DOEPCTL0
));
2366 /* clear global NAKs */
2367 writel(DCTL_CGOUTNak
| DCTL_CGNPInNAK
,
2368 hsotg
->regs
+ DCTL
);
2370 /* must be at-least 3ms to allow bus to see disconnect */
2373 /* remove the soft-disconnect and let's go */
2374 __bic32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2378 * s3c_hsotg_irq - handle device interrupt
2379 * @irq: The IRQ number triggered
2380 * @pw: The pw value when registered the handler.
2382 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2384 struct s3c_hsotg
*hsotg
= pw
;
2385 int retry_count
= 8;
2390 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2391 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2393 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2394 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2398 if (gintsts
& GINTSTS_OTGInt
) {
2399 u32 otgint
= readl(hsotg
->regs
+ GOTGINT
);
2401 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2403 writel(otgint
, hsotg
->regs
+ GOTGINT
);
2406 if (gintsts
& GINTSTS_SessReqInt
) {
2407 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2408 writel(GINTSTS_SessReqInt
, hsotg
->regs
+ GINTSTS
);
2411 if (gintsts
& GINTSTS_EnumDone
) {
2412 writel(GINTSTS_EnumDone
, hsotg
->regs
+ GINTSTS
);
2414 s3c_hsotg_irq_enumdone(hsotg
);
2417 if (gintsts
& GINTSTS_ConIDStsChng
) {
2418 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2419 readl(hsotg
->regs
+ DSTS
),
2420 readl(hsotg
->regs
+ GOTGCTL
));
2422 writel(GINTSTS_ConIDStsChng
, hsotg
->regs
+ GINTSTS
);
2425 if (gintsts
& (GINTSTS_OEPInt
| GINTSTS_IEPInt
)) {
2426 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2427 u32 daint_out
= daint
>> DAINT_OutEP_SHIFT
;
2428 u32 daint_in
= daint
& ~(daint_out
<< DAINT_OutEP_SHIFT
);
2431 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2433 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2435 s3c_hsotg_epint(hsotg
, ep
, 0);
2438 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2440 s3c_hsotg_epint(hsotg
, ep
, 1);
2444 if (gintsts
& GINTSTS_USBRst
) {
2446 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2448 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2449 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2450 readl(hsotg
->regs
+ GNPTXSTS
));
2452 writel(GINTSTS_USBRst
, hsotg
->regs
+ GINTSTS
);
2454 if (usb_status
& GOTGCTL_BSESVLD
) {
2455 if (time_after(jiffies
, hsotg
->last_rst
+
2456 msecs_to_jiffies(200))) {
2458 kill_all_requests(hsotg
, &hsotg
->eps
[0],
2461 s3c_hsotg_core_init(hsotg
);
2462 hsotg
->last_rst
= jiffies
;
2467 /* check both FIFOs */
2469 if (gintsts
& GINTSTS_NPTxFEmp
) {
2470 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2473 * Disable the interrupt to stop it happening again
2474 * unless one of these endpoint routines decides that
2475 * it needs re-enabling
2478 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTxFEmp
);
2479 s3c_hsotg_irq_fifoempty(hsotg
, false);
2482 if (gintsts
& GINTSTS_PTxFEmp
) {
2483 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2485 /* See note in GINTSTS_NPTxFEmp */
2487 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTxFEmp
);
2488 s3c_hsotg_irq_fifoempty(hsotg
, true);
2491 if (gintsts
& GINTSTS_RxFLvl
) {
2493 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2494 * we need to retry s3c_hsotg_handle_rx if this is still
2498 s3c_hsotg_handle_rx(hsotg
);
2501 if (gintsts
& GINTSTS_ModeMis
) {
2502 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2503 writel(GINTSTS_ModeMis
, hsotg
->regs
+ GINTSTS
);
2506 if (gintsts
& GINTSTS_USBSusp
) {
2507 dev_info(hsotg
->dev
, "GINTSTS_USBSusp\n");
2508 writel(GINTSTS_USBSusp
, hsotg
->regs
+ GINTSTS
);
2510 call_gadget(hsotg
, suspend
);
2511 s3c_hsotg_disconnect(hsotg
);
2514 if (gintsts
& GINTSTS_WkUpInt
) {
2515 dev_info(hsotg
->dev
, "GINTSTS_WkUpIn\n");
2516 writel(GINTSTS_WkUpInt
, hsotg
->regs
+ GINTSTS
);
2518 call_gadget(hsotg
, resume
);
2521 if (gintsts
& GINTSTS_ErlySusp
) {
2522 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2523 writel(GINTSTS_ErlySusp
, hsotg
->regs
+ GINTSTS
);
2525 s3c_hsotg_disconnect(hsotg
);
2529 * these next two seem to crop-up occasionally causing the core
2530 * to shutdown the USB transfer, so try clearing them and logging
2534 if (gintsts
& GINTSTS_GOUTNakEff
) {
2535 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2537 writel(DCTL_CGOUTNak
, hsotg
->regs
+ DCTL
);
2539 s3c_hsotg_dump(hsotg
);
2542 if (gintsts
& GINTSTS_GINNakEff
) {
2543 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2545 writel(DCTL_CGNPInNAK
, hsotg
->regs
+ DCTL
);
2547 s3c_hsotg_dump(hsotg
);
2551 * if we've had fifo events, we should try and go around the
2552 * loop again to see if there's any point in returning yet.
2555 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2562 * s3c_hsotg_ep_enable - enable the given endpoint
2563 * @ep: The USB endpint to configure
2564 * @desc: The USB endpoint descriptor to configure with.
2566 * This is called from the USB gadget code's usb_ep_enable().
2568 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2569 const struct usb_endpoint_descriptor
*desc
)
2571 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2572 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2573 unsigned long flags
;
2574 int index
= hs_ep
->index
;
2582 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2583 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2584 desc
->wMaxPacketSize
, desc
->bInterval
);
2586 /* not to be called for EP0 */
2587 WARN_ON(index
== 0);
2589 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2590 if (dir_in
!= hs_ep
->dir_in
) {
2591 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2595 mps
= usb_endpoint_maxp(desc
);
2597 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2599 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2600 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2602 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2603 __func__
, epctrl
, epctrl_reg
);
2605 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2607 epctrl
&= ~(DxEPCTL_EPType_MASK
| DxEPCTL_MPS_MASK
);
2608 epctrl
|= DxEPCTL_MPS(mps
);
2611 * mark the endpoint as active, otherwise the core may ignore
2612 * transactions entirely for this endpoint
2614 epctrl
|= DxEPCTL_USBActEp
;
2617 * set the NAK status on the endpoint, otherwise we might try and
2618 * do something with data that we've yet got a request to process
2619 * since the RXFIFO will take data for an endpoint even if the
2620 * size register hasn't been set.
2623 epctrl
|= DxEPCTL_SNAK
;
2625 /* update the endpoint state */
2626 hs_ep
->ep
.maxpacket
= mps
;
2628 /* default, set to non-periodic */
2629 hs_ep
->periodic
= 0;
2631 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2632 case USB_ENDPOINT_XFER_ISOC
:
2633 dev_err(hsotg
->dev
, "no current ISOC support\n");
2637 case USB_ENDPOINT_XFER_BULK
:
2638 epctrl
|= DxEPCTL_EPType_Bulk
;
2641 case USB_ENDPOINT_XFER_INT
:
2644 * Allocate our TxFNum by simply using the index
2645 * of the endpoint for the moment. We could do
2646 * something better if the host indicates how
2647 * many FIFOs we are expecting to use.
2650 hs_ep
->periodic
= 1;
2651 epctrl
|= DxEPCTL_TxFNum(index
);
2654 epctrl
|= DxEPCTL_EPType_Intterupt
;
2657 case USB_ENDPOINT_XFER_CONTROL
:
2658 epctrl
|= DxEPCTL_EPType_Control
;
2663 * if the hardware has dedicated fifos, we must give each IN EP
2664 * a unique tx-fifo even if it is non-periodic.
2666 if (dir_in
&& hsotg
->dedicated_fifos
)
2667 epctrl
|= DxEPCTL_TxFNum(index
);
2669 /* for non control endpoints, set PID to D0 */
2671 epctrl
|= DxEPCTL_SetD0PID
;
2673 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2676 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2677 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2678 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2680 /* enable the endpoint interrupt */
2681 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2684 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2689 * s3c_hsotg_ep_disable - disable given endpoint
2690 * @ep: The endpoint to disable.
2692 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2694 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2695 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2696 int dir_in
= hs_ep
->dir_in
;
2697 int index
= hs_ep
->index
;
2698 unsigned long flags
;
2702 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2704 if (ep
== &hsotg
->eps
[0].ep
) {
2705 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2709 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2711 /* terminate all requests with shutdown */
2712 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2714 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2716 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2717 ctrl
&= ~DxEPCTL_EPEna
;
2718 ctrl
&= ~DxEPCTL_USBActEp
;
2719 ctrl
|= DxEPCTL_SNAK
;
2721 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2722 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2724 /* disable endpoint interrupts */
2725 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2727 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2732 * on_list - check request is on the given endpoint
2733 * @ep: The endpoint to check.
2734 * @test: The request to test if it is on the endpoint.
2736 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2738 struct s3c_hsotg_req
*req
, *treq
;
2740 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2749 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2750 * @ep: The endpoint to dequeue.
2751 * @req: The request to be removed from a queue.
2753 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2755 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2756 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2757 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2758 unsigned long flags
;
2760 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2762 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2764 if (!on_list(hs_ep
, hs_req
)) {
2765 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2769 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2770 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2776 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2777 * @ep: The endpoint to set halt.
2778 * @value: Set or unset the halt.
2780 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2782 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2783 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2784 int index
= hs_ep
->index
;
2785 unsigned long irqflags
;
2790 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2792 spin_lock_irqsave(&hs_ep
->lock
, irqflags
);
2794 /* write both IN and OUT control registers */
2796 epreg
= DIEPCTL(index
);
2797 epctl
= readl(hs
->regs
+ epreg
);
2800 epctl
|= DxEPCTL_Stall
+ DxEPCTL_SNAK
;
2801 if (epctl
& DxEPCTL_EPEna
)
2802 epctl
|= DxEPCTL_EPDis
;
2804 epctl
&= ~DxEPCTL_Stall
;
2805 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2806 if (xfertype
== DxEPCTL_EPType_Bulk
||
2807 xfertype
== DxEPCTL_EPType_Intterupt
)
2808 epctl
|= DxEPCTL_SetD0PID
;
2811 writel(epctl
, hs
->regs
+ epreg
);
2813 epreg
= DOEPCTL(index
);
2814 epctl
= readl(hs
->regs
+ epreg
);
2817 epctl
|= DxEPCTL_Stall
;
2819 epctl
&= ~DxEPCTL_Stall
;
2820 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2821 if (xfertype
== DxEPCTL_EPType_Bulk
||
2822 xfertype
== DxEPCTL_EPType_Intterupt
)
2823 epctl
|= DxEPCTL_SetD0PID
;
2826 writel(epctl
, hs
->regs
+ epreg
);
2828 spin_unlock_irqrestore(&hs_ep
->lock
, irqflags
);
2833 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2834 .enable
= s3c_hsotg_ep_enable
,
2835 .disable
= s3c_hsotg_ep_disable
,
2836 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2837 .free_request
= s3c_hsotg_ep_free_request
,
2838 .queue
= s3c_hsotg_ep_queue
,
2839 .dequeue
= s3c_hsotg_ep_dequeue
,
2840 .set_halt
= s3c_hsotg_ep_sethalt
,
2841 /* note, don't believe we have any call for the fifo routines */
2845 * s3c_hsotg_phy_enable - enable platform phy dev
2846 * @hsotg: The driver state
2848 * A wrapper for platform code responsible for controlling
2849 * low-level USB code
2851 static void s3c_hsotg_phy_enable(struct s3c_hsotg
*hsotg
)
2853 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2855 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2856 if (hsotg
->plat
->phy_init
)
2857 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2861 * s3c_hsotg_phy_disable - disable platform phy dev
2862 * @hsotg: The driver state
2864 * A wrapper for platform code responsible for controlling
2865 * low-level USB code
2867 static void s3c_hsotg_phy_disable(struct s3c_hsotg
*hsotg
)
2869 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2871 if (hsotg
->plat
->phy_exit
)
2872 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2876 * s3c_hsotg_init - initalize the usb core
2877 * @hsotg: The driver state
2879 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2881 /* unmask subset of endpoint interrupts */
2883 writel(DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2884 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
,
2885 hsotg
->regs
+ DIEPMSK
);
2887 writel(DOEPMSK_SetupMsk
| DOEPMSK_AHBErrMsk
|
2888 DOEPMSK_EPDisbldMsk
| DOEPMSK_XferComplMsk
,
2889 hsotg
->regs
+ DOEPMSK
);
2891 writel(0, hsotg
->regs
+ DAINTMSK
);
2893 /* Be in disconnected state until gadget is registered */
2894 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2897 /* post global nak until we're ready */
2898 writel(DCTL_SGNPInNAK
| DCTL_SGOUTNak
,
2899 hsotg
->regs
+ DCTL
);
2904 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2905 readl(hsotg
->regs
+ GRXFSIZ
),
2906 readl(hsotg
->regs
+ GNPTXFSIZ
));
2908 s3c_hsotg_init_fifo(hsotg
);
2910 /* set the PLL on, remove the HNP/SRP and set the PHY */
2911 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) | (0x5 << 10),
2912 hsotg
->regs
+ GUSBCFG
);
2914 writel(using_dma(hsotg
) ? GAHBCFG_DMAEn
: 0x0,
2915 hsotg
->regs
+ GAHBCFG
);
2919 * s3c_hsotg_udc_start - prepare the udc for work
2920 * @gadget: The usb gadget state
2921 * @driver: The usb gadget driver
2923 * Perform initialization to prepare udc device and driver
2926 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2927 struct usb_gadget_driver
*driver
)
2929 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2933 printk(KERN_ERR
"%s: called with no device\n", __func__
);
2938 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2942 if (driver
->max_speed
< USB_SPEED_FULL
)
2943 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2945 if (!driver
->setup
) {
2946 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2950 WARN_ON(hsotg
->driver
);
2952 driver
->driver
.bus
= NULL
;
2953 hsotg
->driver
= driver
;
2954 hsotg
->gadget
.dev
.driver
= &driver
->driver
;
2955 hsotg
->gadget
.dev
.dma_mask
= hsotg
->dev
->dma_mask
;
2956 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2958 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
2961 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
2965 s3c_hsotg_phy_enable(hsotg
);
2967 s3c_hsotg_core_init(hsotg
);
2968 hsotg
->last_rst
= jiffies
;
2969 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2973 hsotg
->driver
= NULL
;
2974 hsotg
->gadget
.dev
.driver
= NULL
;
2979 * s3c_hsotg_udc_stop - stop the udc
2980 * @gadget: The usb gadget state
2981 * @driver: The usb gadget driver
2983 * Stop udc hw block and stay tunned for future transmissions
2985 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
,
2986 struct usb_gadget_driver
*driver
)
2988 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2994 if (!driver
|| driver
!= hsotg
->driver
|| !driver
->unbind
)
2997 /* all endpoints should be shutdown */
2998 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2999 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
3001 s3c_hsotg_phy_disable(hsotg
);
3002 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3004 hsotg
->driver
= NULL
;
3005 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3006 hsotg
->gadget
.dev
.driver
= NULL
;
3008 dev_info(hsotg
->dev
, "unregistered gadget driver '%s'\n",
3009 driver
->driver
.name
);
3015 * s3c_hsotg_gadget_getframe - read the frame number
3016 * @gadget: The usb gadget state
3018 * Read the {micro} frame number
3020 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
3022 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
3025 static struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
3026 .get_frame
= s3c_hsotg_gadget_getframe
,
3027 .udc_start
= s3c_hsotg_udc_start
,
3028 .udc_stop
= s3c_hsotg_udc_stop
,
3032 * s3c_hsotg_initep - initialise a single endpoint
3033 * @hsotg: The device state.
3034 * @hs_ep: The endpoint to be initialised.
3035 * @epnum: The endpoint number
3037 * Initialise the given endpoint (as part of the probe and device state
3038 * creation) to give to the gadget driver. Setup the endpoint name, any
3039 * direction information and other state that may be required.
3041 static void __devinit
s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
3042 struct s3c_hsotg_ep
*hs_ep
,
3050 else if ((epnum
% 2) == 0) {
3057 hs_ep
->index
= epnum
;
3059 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3061 INIT_LIST_HEAD(&hs_ep
->queue
);
3062 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3064 spin_lock_init(&hs_ep
->lock
);
3066 /* add to the list of endpoints known by the gadget driver */
3068 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3070 hs_ep
->parent
= hsotg
;
3071 hs_ep
->ep
.name
= hs_ep
->name
;
3072 hs_ep
->ep
.maxpacket
= epnum
? 512 : EP0_MPS_LIMIT
;
3073 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3076 * Read the FIFO size for the Periodic TX FIFO, even if we're
3077 * an OUT endpoint, we may as well do this if in future the
3078 * code is changed to make each endpoint's direction changeable.
3081 ptxfifo
= readl(hsotg
->regs
+ DPTXFSIZn(epnum
));
3082 hs_ep
->fifo_size
= DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
3085 * if we're using dma, we need to set the next-endpoint pointer
3086 * to be something valid.
3089 if (using_dma(hsotg
)) {
3090 u32 next
= DxEPCTL_NextEp((epnum
+ 1) % 15);
3091 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3092 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3097 * s3c_hsotg_hw_cfg - read HW configuration registers
3098 * @param: The device state
3100 * Read the USB core HW configuration registers
3102 static void s3c_hsotg_hw_cfg(struct s3c_hsotg
*hsotg
)
3105 /* check hardware configuration */
3107 cfg2
= readl(hsotg
->regs
+ 0x48);
3108 hsotg
->num_of_eps
= (cfg2
>> 10) & 0xF;
3110 dev_info(hsotg
->dev
, "EPs:%d\n", hsotg
->num_of_eps
);
3112 cfg4
= readl(hsotg
->regs
+ 0x50);
3113 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
3115 dev_info(hsotg
->dev
, "%s fifos\n",
3116 hsotg
->dedicated_fifos
? "dedicated" : "shared");
3120 * s3c_hsotg_dump - dump state of the udc
3121 * @param: The device state
3123 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
3126 struct device
*dev
= hsotg
->dev
;
3127 void __iomem
*regs
= hsotg
->regs
;
3131 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3132 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3133 readl(regs
+ DIEPMSK
));
3135 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3136 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3138 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3139 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3141 /* show periodic fifo settings */
3143 for (idx
= 1; idx
<= 15; idx
++) {
3144 val
= readl(regs
+ DPTXFSIZn(idx
));
3145 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3146 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3147 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3150 for (idx
= 0; idx
< 15; idx
++) {
3152 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3153 readl(regs
+ DIEPCTL(idx
)),
3154 readl(regs
+ DIEPTSIZ(idx
)),
3155 readl(regs
+ DIEPDMA(idx
)));
3157 val
= readl(regs
+ DOEPCTL(idx
));
3159 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3160 idx
, readl(regs
+ DOEPCTL(idx
)),
3161 readl(regs
+ DOEPTSIZ(idx
)),
3162 readl(regs
+ DOEPDMA(idx
)));
3166 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3167 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3172 * state_show - debugfs: show overall driver and device state.
3173 * @seq: The seq file to write to.
3174 * @v: Unused parameter.
3176 * This debugfs entry shows the overall state of the hardware and
3177 * some general information about each of the endpoints available
3180 static int state_show(struct seq_file
*seq
, void *v
)
3182 struct s3c_hsotg
*hsotg
= seq
->private;
3183 void __iomem
*regs
= hsotg
->regs
;
3186 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3189 readl(regs
+ DSTS
));
3191 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3192 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3194 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3195 readl(regs
+ GINTMSK
),
3196 readl(regs
+ GINTSTS
));
3198 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3199 readl(regs
+ DAINTMSK
),
3200 readl(regs
+ DAINT
));
3202 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3203 readl(regs
+ GNPTXSTS
),
3204 readl(regs
+ GRXSTSR
));
3206 seq_printf(seq
, "\nEndpoint status:\n");
3208 for (idx
= 0; idx
< 15; idx
++) {
3211 in
= readl(regs
+ DIEPCTL(idx
));
3212 out
= readl(regs
+ DOEPCTL(idx
));
3214 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3217 in
= readl(regs
+ DIEPTSIZ(idx
));
3218 out
= readl(regs
+ DOEPTSIZ(idx
));
3220 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3223 seq_printf(seq
, "\n");
3229 static int state_open(struct inode
*inode
, struct file
*file
)
3231 return single_open(file
, state_show
, inode
->i_private
);
3234 static const struct file_operations state_fops
= {
3235 .owner
= THIS_MODULE
,
3238 .llseek
= seq_lseek
,
3239 .release
= single_release
,
3243 * fifo_show - debugfs: show the fifo information
3244 * @seq: The seq_file to write data to.
3245 * @v: Unused parameter.
3247 * Show the FIFO information for the overall fifo and all the
3248 * periodic transmission FIFOs.
3250 static int fifo_show(struct seq_file
*seq
, void *v
)
3252 struct s3c_hsotg
*hsotg
= seq
->private;
3253 void __iomem
*regs
= hsotg
->regs
;
3257 seq_printf(seq
, "Non-periodic FIFOs:\n");
3258 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3260 val
= readl(regs
+ GNPTXFSIZ
);
3261 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3262 val
>> GNPTXFSIZ_NPTxFDep_SHIFT
,
3263 val
& GNPTXFSIZ_NPTxFStAddr_MASK
);
3265 seq_printf(seq
, "\nPeriodic TXFIFOs:\n");
3267 for (idx
= 1; idx
<= 15; idx
++) {
3268 val
= readl(regs
+ DPTXFSIZn(idx
));
3270 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3271 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3272 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3278 static int fifo_open(struct inode
*inode
, struct file
*file
)
3280 return single_open(file
, fifo_show
, inode
->i_private
);
3283 static const struct file_operations fifo_fops
= {
3284 .owner
= THIS_MODULE
,
3287 .llseek
= seq_lseek
,
3288 .release
= single_release
,
3292 static const char *decode_direction(int is_in
)
3294 return is_in
? "in" : "out";
3298 * ep_show - debugfs: show the state of an endpoint.
3299 * @seq: The seq_file to write data to.
3300 * @v: Unused parameter.
3302 * This debugfs entry shows the state of the given endpoint (one is
3303 * registered for each available).
3305 static int ep_show(struct seq_file
*seq
, void *v
)
3307 struct s3c_hsotg_ep
*ep
= seq
->private;
3308 struct s3c_hsotg
*hsotg
= ep
->parent
;
3309 struct s3c_hsotg_req
*req
;
3310 void __iomem
*regs
= hsotg
->regs
;
3311 int index
= ep
->index
;
3312 int show_limit
= 15;
3313 unsigned long flags
;
3315 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3316 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3318 /* first show the register state */
3320 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3321 readl(regs
+ DIEPCTL(index
)),
3322 readl(regs
+ DOEPCTL(index
)));
3324 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3325 readl(regs
+ DIEPDMA(index
)),
3326 readl(regs
+ DOEPDMA(index
)));
3328 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3329 readl(regs
+ DIEPINT(index
)),
3330 readl(regs
+ DOEPINT(index
)));
3332 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3333 readl(regs
+ DIEPTSIZ(index
)),
3334 readl(regs
+ DOEPTSIZ(index
)));
3336 seq_printf(seq
, "\n");
3337 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3338 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3340 seq_printf(seq
, "request list (%p,%p):\n",
3341 ep
->queue
.next
, ep
->queue
.prev
);
3343 spin_lock_irqsave(&ep
->lock
, flags
);
3345 list_for_each_entry(req
, &ep
->queue
, queue
) {
3346 if (--show_limit
< 0) {
3347 seq_printf(seq
, "not showing more requests...\n");
3351 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3352 req
== ep
->req
? '*' : ' ',
3353 req
, req
->req
.length
, req
->req
.buf
);
3354 seq_printf(seq
, "%d done, res %d\n",
3355 req
->req
.actual
, req
->req
.status
);
3358 spin_unlock_irqrestore(&ep
->lock
, flags
);
3363 static int ep_open(struct inode
*inode
, struct file
*file
)
3365 return single_open(file
, ep_show
, inode
->i_private
);
3368 static const struct file_operations ep_fops
= {
3369 .owner
= THIS_MODULE
,
3372 .llseek
= seq_lseek
,
3373 .release
= single_release
,
3377 * s3c_hsotg_create_debug - create debugfs directory and files
3378 * @hsotg: The driver state
3380 * Create the debugfs files to allow the user to get information
3381 * about the state of the system. The directory name is created
3382 * with the same name as the device itself, in case we end up
3383 * with multiple blocks in future systems.
3385 static void __devinit
s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3387 struct dentry
*root
;
3390 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3391 hsotg
->debug_root
= root
;
3393 dev_err(hsotg
->dev
, "cannot create debug root\n");
3397 /* create general state file */
3399 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3400 hsotg
, &state_fops
);
3402 if (IS_ERR(hsotg
->debug_file
))
3403 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3405 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3408 if (IS_ERR(hsotg
->debug_fifo
))
3409 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3411 /* create one file for each endpoint */
3413 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3414 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3416 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3417 root
, ep
, &ep_fops
);
3419 if (IS_ERR(ep
->debugfs
))
3420 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3426 * s3c_hsotg_delete_debug - cleanup debugfs entries
3427 * @hsotg: The driver state
3429 * Cleanup (remove) the debugfs files for use on module exit.
3431 static void __devexit
s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3435 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3436 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3437 debugfs_remove(ep
->debugfs
);
3440 debugfs_remove(hsotg
->debug_file
);
3441 debugfs_remove(hsotg
->debug_fifo
);
3442 debugfs_remove(hsotg
->debug_root
);
3446 * s3c_hsotg_release - release callback for hsotg device
3447 * @dev: Device to for which release is called
3449 static void s3c_hsotg_release(struct device
*dev
)
3451 struct s3c_hsotg
*hsotg
= dev_get_drvdata(dev
);
3457 * s3c_hsotg_probe - probe function for hsotg driver
3458 * @pdev: The platform information for the driver
3461 static int __devinit
s3c_hsotg_probe(struct platform_device
*pdev
)
3463 struct s3c_hsotg_plat
*plat
= pdev
->dev
.platform_data
;
3464 struct device
*dev
= &pdev
->dev
;
3465 struct s3c_hsotg_ep
*eps
;
3466 struct s3c_hsotg
*hsotg
;
3467 struct resource
*res
;
3472 plat
= pdev
->dev
.platform_data
;
3474 dev_err(&pdev
->dev
, "no platform data defined\n");
3478 hsotg
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c_hsotg
), GFP_KERNEL
);
3480 dev_err(dev
, "cannot get memory\n");
3487 hsotg
->clk
= clk_get(&pdev
->dev
, "otg");
3488 if (IS_ERR(hsotg
->clk
)) {
3489 dev_err(dev
, "cannot get otg clock\n");
3490 return PTR_ERR(hsotg
->clk
);
3493 platform_set_drvdata(pdev
, hsotg
);
3495 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3497 hsotg
->regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
3499 dev_err(dev
, "cannot map registers\n");
3504 ret
= platform_get_irq(pdev
, 0);
3506 dev_err(dev
, "cannot find IRQ\n");
3512 ret
= devm_request_irq(&pdev
->dev
, hsotg
->irq
, s3c_hsotg_irq
, 0,
3513 dev_name(dev
), hsotg
);
3515 dev_err(dev
, "cannot claim IRQ\n");
3519 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3521 device_initialize(&hsotg
->gadget
.dev
);
3523 dev_set_name(&hsotg
->gadget
.dev
, "gadget");
3525 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3526 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3527 hsotg
->gadget
.name
= dev_name(dev
);
3529 hsotg
->gadget
.dev
.parent
= dev
;
3530 hsotg
->gadget
.dev
.dma_mask
= dev
->dma_mask
;
3531 hsotg
->gadget
.dev
.release
= s3c_hsotg_release
;
3533 /* reset the system */
3535 clk_prepare_enable(hsotg
->clk
);
3539 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3540 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3542 ret
= regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3545 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3549 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3553 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3557 /* usb phy enable */
3558 s3c_hsotg_phy_enable(hsotg
);
3560 s3c_hsotg_corereset(hsotg
);
3561 s3c_hsotg_init(hsotg
);
3562 s3c_hsotg_hw_cfg(hsotg
);
3564 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3566 if (hsotg
->num_of_eps
== 0) {
3567 dev_err(dev
, "wrong number of EPs (zero)\n");
3571 eps
= kcalloc(hsotg
->num_of_eps
+ 1, sizeof(struct s3c_hsotg_ep
),
3574 dev_err(dev
, "cannot get memory\n");
3580 /* setup endpoint information */
3582 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3583 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3585 /* allocate EP0 request */
3587 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3589 if (!hsotg
->ctrl_req
) {
3590 dev_err(dev
, "failed to allocate ctrl req\n");
3594 /* initialise the endpoints now the core has been initialised */
3595 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++)
3596 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3598 /* disable power and clock */
3600 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3603 dev_err(hsotg
->dev
, "failed to disable supplies: %d\n", ret
);
3607 s3c_hsotg_phy_disable(hsotg
);
3609 ret
= device_add(&hsotg
->gadget
.dev
);
3611 put_device(&hsotg
->gadget
.dev
);
3615 ret
= usb_add_gadget_udc(&pdev
->dev
, &hsotg
->gadget
);
3619 s3c_hsotg_create_debug(hsotg
);
3621 s3c_hsotg_dump(hsotg
);
3628 s3c_hsotg_phy_disable(hsotg
);
3629 regulator_bulk_free(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3632 clk_disable_unprepare(hsotg
->clk
);
3633 clk_put(hsotg
->clk
);
3639 * s3c_hsotg_remove - remove function for hsotg driver
3640 * @pdev: The platform information for the driver
3642 static int __devexit
s3c_hsotg_remove(struct platform_device
*pdev
)
3644 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3646 usb_del_gadget_udc(&hsotg
->gadget
);
3648 s3c_hsotg_delete_debug(hsotg
);
3650 if (hsotg
->driver
) {
3651 /* should have been done already by driver model core */
3652 usb_gadget_unregister_driver(hsotg
->driver
);
3655 s3c_hsotg_phy_disable(hsotg
);
3656 regulator_bulk_free(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3658 clk_disable_unprepare(hsotg
->clk
);
3659 clk_put(hsotg
->clk
);
3661 device_unregister(&hsotg
->gadget
.dev
);
3666 #define s3c_hsotg_suspend NULL
3667 #define s3c_hsotg_resume NULL
3670 static struct platform_driver s3c_hsotg_driver
= {
3672 .name
= "s3c-hsotg",
3673 .owner
= THIS_MODULE
,
3675 .probe
= s3c_hsotg_probe
,
3676 .remove
= __devexit_p(s3c_hsotg_remove
),
3677 .suspend
= s3c_hsotg_suspend
,
3678 .resume
= s3c_hsotg_resume
,
3681 module_platform_driver(s3c_hsotg_driver
);
3683 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3684 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3685 MODULE_LICENSE("GPL");
3686 MODULE_ALIAS("platform:s3c-hsotg");