drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* called after powerup, by probe or system-pm "wakeup" */
  28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  29 {
  30         int                     retval;
  31
  32         /* we expect static quirk code to handle the "extended capabilities"
  33          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  34          */
  35
  36         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  37         retval = pci_set_mwi(pdev);
  38         if (!retval)
  39                 ehci_dbg(ehci, "MWI active\n");
  40
  41         return 0;
  42 }
  43
  44 /* called during probe() after chip reset completes */
  45 static int ehci_pci_setup(struct usb_hcd *hcd)
  46 {
  47         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  48         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  49         struct pci_dev          *p_smbus;
  50         u8                      rev;
  51         u32                     temp;
  52         int                     retval;
  53
  54         switch (pdev->vendor) {
  55         case PCI_VENDOR_ID_TOSHIBA_2:
  56                 /* celleb's companion chip */
  57                 if (pdev->device == 0x01b5) {
  58 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  59                         ehci->big_endian_mmio = 1;
  60 #else
  61                         ehci_warn(ehci,
  62                                   "unsupported big endian Toshiba quirk\n");
  63 #endif
  64                 }
  65                 break;
  66         }
  67
  68         ehci->caps = hcd->regs;
  69         ehci->regs = hcd->regs +
  70                 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
  71
  72         dbg_hcs_params(ehci, "reset");
  73         dbg_hcc_params(ehci, "reset");
  74
  75         /* ehci_init() causes memory for DMA transfers to be
  76          * allocated.  Thus, any vendor-specific workarounds based on
  77          * limiting the type of memory used for DMA transfers must
  78          * happen before ehci_init() is called. */
  79         switch (pdev->vendor) {
  80         case PCI_VENDOR_ID_NVIDIA:
  81                 /* NVidia reports that certain chips don't handle
  82                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
  83                  * data buffer, and periodic schedule are normal.)
  84                  */
  85                 switch (pdev->device) {
  86                 case 0x003c:    /* MCP04 */
  87                 case 0x005b:    /* CK804 */
  88                 case 0x00d8:    /* CK8 */
  89                 case 0x00e8:    /* CK8S */
  90                         if (pci_set_consistent_dma_mask(pdev,
  91                                                 DMA_BIT_MASK(31)) < 0)
  92                                 ehci_warn(ehci, "can't enable NVidia "
  93                                         "workaround for >2GB RAM\n");
  94                         break;
  95                 }
  96                 break;
  97         }
  98
  99         /* cache this readonly data; minimize chip reads */
 100         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 101
 102         retval = ehci_halt(ehci);
 103         if (retval)
 104                 return retval;
 105
 106         /* data structure init */
 107         retval = ehci_init(hcd);
 108         if (retval)
 109                 return retval;
 110
 111         switch (pdev->vendor) {
 112         case PCI_VENDOR_ID_NEC:
 113                 ehci->need_io_watchdog = 0;
 114                 break;
 115         case PCI_VENDOR_ID_INTEL:
 116                 ehci->need_io_watchdog = 0;
 117                 ehci->fs_i_thresh = 1;
 118                 if (pdev->device == 0x27cc) {
 119                         ehci->broken_periodic = 1;
 120                         ehci_info(ehci, "using broken periodic workaround\n");
 121                 }
 122                 break;
 123         case PCI_VENDOR_ID_TDI:
 124                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 125                         hcd->has_tt = 1;
 126                         tdi_reset(ehci);
 127                 }
 128                 break;
 129         case PCI_VENDOR_ID_AMD:
 130                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 131                 if (pdev->device == 0x7463) {
 132                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 133                         retval = -EIO;
 134                         goto done;
 135                 }
 136                 break;
 137         case PCI_VENDOR_ID_NVIDIA:
 138                 switch (pdev->device) {
 139                 /* Some NForce2 chips have problems with selective suspend;
 140                  * fixed in newer silicon.
 141                  */
 142                 case 0x0068:
 143                         if (pdev->revision < 0xa4)
 144                                 ehci->no_selective_suspend = 1;
 145                         break;
 146                 }
 147                 break;
 148         case PCI_VENDOR_ID_VIA:
 149                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 150                         u8 tmp;
 151
 152                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 153                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 154                          * that sleep time use the conventional 10 usec.
 155                          */
 156                         pci_read_config_byte(pdev, 0x4b, &tmp);
 157                         if (tmp & 0x20)
 158                                 break;
 159                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 160                 }
 161                 break;
 162         case PCI_VENDOR_ID_ATI:
 163                 /* SB600 and old version of SB700 have a bug in EHCI controller,
 164                  * which causes usb devices lose response in some cases.
 165                  */
 166                 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
 167                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
 168                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 169                                                  NULL);
 170                         if (!p_smbus)
 171                                 break;
 172                         rev = p_smbus->revision;
 173                         if ((pdev->device == 0x4386) || (rev == 0x3a)
 174                             || (rev == 0x3b)) {
 175                                 u8 tmp;
 176                                 ehci_info(ehci, "applying AMD SB600/SB700 USB "
 177                                         "freeze workaround\n");
 178                                 pci_read_config_byte(pdev, 0x53, &tmp);
 179                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 180                         }
 181                         pci_dev_put(p_smbus);
 182                 }
 183                 break;
 184         }
 185
 186         /* optional debug port, normally in the first BAR */
 187         temp = pci_find_capability(pdev, 0x0a);
 188         if (temp) {
 189                 pci_read_config_dword(pdev, temp, &temp);
 190                 temp >>= 16;
 191                 if ((temp & (3 << 13)) == (1 << 13)) {
 192                         temp &= 0x1fff;
 193                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
 194                         temp = ehci_readl(ehci, &ehci->debug->control);
 195                         ehci_info(ehci, "debug port %d%s\n",
 196                                 HCS_DEBUG_PORT(ehci->hcs_params),
 197                                 (temp & DBGP_ENABLED)
 198                                         ? " IN USE"
 199                                         : "");
 200                         if (!(temp & DBGP_ENABLED))
 201                                 ehci->debug = NULL;
 202                 }
 203         }
 204
 205         ehci_reset(ehci);
 206
 207         /* at least the Genesys GL880S needs fixup here */
 208         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 209         temp &= 0x0f;
 210         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 211                 ehci_dbg(ehci, "bogus port configuration: "
 212                         "cc=%d x pcc=%d < ports=%d\n",
 213                         HCS_N_CC(ehci->hcs_params),
 214                         HCS_N_PCC(ehci->hcs_params),
 215                         HCS_N_PORTS(ehci->hcs_params));
 216
 217                 switch (pdev->vendor) {
 218                 case 0x17a0:            /* GENESYS */
 219                         /* GL880S: should be PORTS=2 */
 220                         temp |= (ehci->hcs_params & ~0xf);
 221                         ehci->hcs_params = temp;
 222                         break;
 223                 case PCI_VENDOR_ID_NVIDIA:
 224                         /* NF4: should be PCC=10 */
 225                         break;
 226                 }
 227         }
 228
 229         /* Serial Bus Release Number is at PCI 0x60 offset */
 230         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 231
 232         /* Keep this around for a while just in case some EHCI
 233          * implementation uses legacy PCI PM support.  This test
 234          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 235          * been triggered by then.
 236          */
 237         if (!device_can_wakeup(&pdev->dev)) {
 238                 u16     port_wake;
 239
 240                 pci_read_config_word(pdev, 0x62, &port_wake);
 241                 if (port_wake & 0x0001) {
 242                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 243                         device_set_wakeup_capable(&pdev->dev, 1);
 244                 }
 245         }
 246
 247 #ifdef  CONFIG_USB_SUSPEND
 248         /* REVISIT: the controller works fine for wakeup iff the root hub
 249          * itself is "globally" suspended, but usbcore currently doesn't
 250          * understand such things.
 251          *
 252          * System suspend currently expects to be able to suspend the entire
 253          * device tree, device-at-a-time.  If we failed selective suspend
 254          * reports, system suspend would fail; so the root hub code must claim
 255          * success.  That's lying to usbcore, and it matters for runtime
 256          * PM scenarios with selective suspend and remote wakeup...
 257          */
 258         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 259                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 260 #endif
 261
 262         ehci_port_power(ehci, 1);
 263         retval = ehci_pci_reinit(ehci, pdev);
 264 done:
 265         return retval;
 266 }
 267
 268 /*-------------------------------------------------------------------------*/
 269
 270 #ifdef  CONFIG_PM
 271
 272 /* suspend/resume, section 4.3 */
 273
 274 /* These routines rely on the PCI bus glue
 275  * to handle powerdown and wakeup, and currently also on
 276  * transceivers that don't need any software attention to set up
 277  * the right sort of wakeup.
 278  * Also they depend on separate root hub suspend/resume.
 279  */
 280
 281 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 282 {
 283         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 284         unsigned long           flags;
 285         int                     rc = 0;
 286
 287         if (time_before(jiffies, ehci->next_statechange))
 288                 msleep(10);
 289
 290         /* Root hub was already suspended. Disable irq emission and
 291          * mark HW unaccessible.  The PM and USB cores make sure that
 292          * the root hub is either suspended or stopped.
 293          */
 294         spin_lock_irqsave (&ehci->lock, flags);
 295         ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
 296         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 297         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 298
 299         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 300         spin_unlock_irqrestore (&ehci->lock, flags);
 301
 302         // could save FLADJ in case of Vaux power loss
 303         // ... we'd only use it to handle clock skew
 304
 305         return rc;
 306 }
 307
 308 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 309 {
 310         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 311         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 312
 313         // maybe restore FLADJ
 314
 315         if (time_before(jiffies, ehci->next_statechange))
 316                 msleep(100);
 317
 318         /* Mark hardware accessible again as we are out of D3 state by now */
 319         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 320
 321         /* If CF is still set and we aren't resuming from hibernation
 322          * then we maintained PCI Vaux power.
 323          * Just undo the effect of ehci_pci_suspend().
 324          */
 325         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
 326                                 !hibernated) {
 327                 int     mask = INTR_MASK;
 328
 329                 ehci_prepare_ports_for_controller_resume(ehci);
 330                 if (!hcd->self.root_hub->do_remote_wakeup)
 331                         mask &= ~STS_PCD;
 332                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 333                 ehci_readl(ehci, &ehci->regs->intr_enable);
 334                 return 0;
 335         }
 336
 337         usb_root_hub_lost_power(hcd->self.root_hub);
 338
 339         /* Else reset, to cope with power loss or flush-to-storage
 340          * style "resume" having let BIOS kick in during reboot.
 341          */
 342         (void) ehci_halt(ehci);
 343         (void) ehci_reset(ehci);
 344         (void) ehci_pci_reinit(ehci, pdev);
 345
 346         /* emptying the schedule aborts any urbs */
 347         spin_lock_irq(&ehci->lock);
 348         if (ehci->reclaim)
 349                 end_unlink_async(ehci);
 350         ehci_work(ehci);
 351         spin_unlock_irq(&ehci->lock);
 352
 353         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 354         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 355         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 356
 357         /* here we "know" root ports should always stay powered */
 358         ehci_port_power(ehci, 1);
 359
 360         hcd->state = HC_STATE_SUSPENDED;
 361         return 0;
 362 }
 363 #endif
 364
 365 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
 366 {
 367         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 368         int rc = 0;
 369
 370         if (!udev->parent) /* udev is root hub itself, impossible */
 371                 rc = -1;
 372         /* we only support lpm device connected to root hub yet */
 373         if (ehci->has_lpm && !udev->parent->parent) {
 374                 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
 375                 if (!rc)
 376                         rc = ehci_lpm_check(ehci, udev->portnum);
 377         }
 378         return rc;
 379 }
 380
 381 static const struct hc_driver ehci_pci_hc_driver = {
 382         .description =          hcd_name,
 383         .product_desc =         "EHCI Host Controller",
 384         .hcd_priv_size =        sizeof(struct ehci_hcd),
 385
 386         /*
 387          * generic hardware linkage
 388          */
 389         .irq =                  ehci_irq,
 390         .flags =                HCD_MEMORY | HCD_USB2,
 391
 392         /*
 393          * basic lifecycle operations
 394          */
 395         .reset =                ehci_pci_setup,
 396         .start =                ehci_run,
 397 #ifdef  CONFIG_PM
 398         .pci_suspend =          ehci_pci_suspend,
 399         .pci_resume =           ehci_pci_resume,
 400 #endif
 401         .stop =                 ehci_stop,
 402         .shutdown =             ehci_shutdown,
 403
 404         /*
 405          * managing i/o requests and associated device resources
 406          */
 407         .urb_enqueue =          ehci_urb_enqueue,
 408         .urb_dequeue =          ehci_urb_dequeue,
 409         .endpoint_disable =     ehci_endpoint_disable,
 410         .endpoint_reset =       ehci_endpoint_reset,
 411
 412         /*
 413          * scheduling support
 414          */
 415         .get_frame_number =     ehci_get_frame,
 416
 417         /*
 418          * root hub support
 419          */
 420         .hub_status_data =      ehci_hub_status_data,
 421         .hub_control =          ehci_hub_control,
 422         .bus_suspend =          ehci_bus_suspend,
 423         .bus_resume =           ehci_bus_resume,
 424         .relinquish_port =      ehci_relinquish_port,
 425         .port_handed_over =     ehci_port_handed_over,
 426
 427         /*
 428          * call back when device connected and addressed
 429          */
 430         .update_device =        ehci_update_device,
 431
 432         .clear_tt_buffer_complete       = ehci_clear_tt_buffer_complete,
 433 };
 434
 435 /*-------------------------------------------------------------------------*/
 436
 437 /* PCI driver selection metadata; PCI hotplugging uses this */
 438 static const struct pci_device_id pci_ids [] = { {
 439         /* handle any USB 2.0 EHCI controller */
 440         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 441         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 442         },
 443         { /* end: all zeroes */ }
 444 };
 445 MODULE_DEVICE_TABLE(pci, pci_ids);
 446
 447 /* pci driver glue; this is a "new style" PCI driver module */
 448 static struct pci_driver ehci_pci_driver = {
 449         .name =         (char *) hcd_name,
 450         .id_table =     pci_ids,
 451
 452         .probe =        usb_hcd_pci_probe,
 453         .remove =       usb_hcd_pci_remove,
 454         .shutdown =     usb_hcd_pci_shutdown,
 455
 456 #ifdef CONFIG_PM_SLEEP
 457         .driver =       {
 458                 .pm =   &usb_hcd_pci_pm_ops
 459         },
 460 #endif
 461 };