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Merge 3.4-rc6 into usb-next
[deliverable/linux.git] / drivers / usb / host / ehci-tegra.c
1 /*
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/platform_data/tegra_usb.h>
22 #include <linux/irq.h>
23 #include <linux/usb/otg.h>
24 #include <linux/gpio.h>
25 #include <linux/of.h>
26 #include <linux/of_gpio.h>
27 #include <linux/pm_runtime.h>
28
29 #include <mach/usb_phy.h>
30 #include <mach/iomap.h>
31
32 #define TEGRA_USB_DMA_ALIGN 32
33
34 struct tegra_ehci_hcd {
35 struct ehci_hcd *ehci;
36 struct tegra_usb_phy *phy;
37 struct clk *clk;
38 struct clk *emc_clk;
39 struct usb_phy *transceiver;
40 int host_resumed;
41 int port_resuming;
42 enum tegra_usb_phy_port_speed port_speed;
43 };
44
45 static void tegra_ehci_power_up(struct usb_hcd *hcd)
46 {
47 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
48
49 clk_enable(tegra->emc_clk);
50 clk_enable(tegra->clk);
51 tegra_usb_phy_power_on(tegra->phy);
52 tegra->host_resumed = 1;
53 }
54
55 static void tegra_ehci_power_down(struct usb_hcd *hcd)
56 {
57 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
58
59 tegra->host_resumed = 0;
60 tegra_usb_phy_power_off(tegra->phy);
61 clk_disable(tegra->clk);
62 clk_disable(tegra->emc_clk);
63 }
64
65 static int tegra_ehci_internal_port_reset(
66 struct ehci_hcd *ehci,
67 u32 __iomem *portsc_reg
68 )
69 {
70 u32 temp;
71 unsigned long flags;
72 int retval = 0;
73 int i, tries;
74 u32 saved_usbintr;
75
76 spin_lock_irqsave(&ehci->lock, flags);
77 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
78 /* disable USB interrupt */
79 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
80 spin_unlock_irqrestore(&ehci->lock, flags);
81
82 /*
83 * Here we have to do Port Reset at most twice for
84 * Port Enable bit to be set.
85 */
86 for (i = 0; i < 2; i++) {
87 temp = ehci_readl(ehci, portsc_reg);
88 temp |= PORT_RESET;
89 ehci_writel(ehci, temp, portsc_reg);
90 mdelay(10);
91 temp &= ~PORT_RESET;
92 ehci_writel(ehci, temp, portsc_reg);
93 mdelay(1);
94 tries = 100;
95 do {
96 mdelay(1);
97 /*
98 * Up to this point, Port Enable bit is
99 * expected to be set after 2 ms waiting.
100 * USB1 usually takes extra 45 ms, for safety,
101 * we take 100 ms as timeout.
102 */
103 temp = ehci_readl(ehci, portsc_reg);
104 } while (!(temp & PORT_PE) && tries--);
105 if (temp & PORT_PE)
106 break;
107 }
108 if (i == 2)
109 retval = -ETIMEDOUT;
110
111 /*
112 * Clear Connect Status Change bit if it's set.
113 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
114 */
115 if (temp & PORT_CSC)
116 ehci_writel(ehci, PORT_CSC, portsc_reg);
117
118 /*
119 * Write to clear any interrupt status bits that might be set
120 * during port reset.
121 */
122 temp = ehci_readl(ehci, &ehci->regs->status);
123 ehci_writel(ehci, temp, &ehci->regs->status);
124
125 /* restore original interrupt enable bits */
126 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
127 return retval;
128 }
129
130 static int tegra_ehci_hub_control(
131 struct usb_hcd *hcd,
132 u16 typeReq,
133 u16 wValue,
134 u16 wIndex,
135 char *buf,
136 u16 wLength
137 )
138 {
139 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
140 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
141 u32 __iomem *status_reg;
142 u32 temp;
143 unsigned long flags;
144 int retval = 0;
145
146 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
147
148 spin_lock_irqsave(&ehci->lock, flags);
149
150 if (typeReq == GetPortStatus) {
151 temp = ehci_readl(ehci, status_reg);
152 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
153 /* Resume completed, re-enable disconnect detection */
154 tegra->port_resuming = 0;
155 tegra_usb_phy_postresume(tegra->phy);
156 }
157 }
158
159 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
160 temp = ehci_readl(ehci, status_reg);
161 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
162 retval = -EPIPE;
163 goto done;
164 }
165
166 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
167 temp |= PORT_WKDISC_E | PORT_WKOC_E;
168 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
169
170 /*
171 * If a transaction is in progress, there may be a delay in
172 * suspending the port. Poll until the port is suspended.
173 */
174 if (handshake(ehci, status_reg, PORT_SUSPEND,
175 PORT_SUSPEND, 5000))
176 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
177
178 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
179 goto done;
180 }
181
182 /* For USB1 port we need to issue Port Reset twice internally */
183 if (tegra->phy->instance == 0 &&
184 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
185 spin_unlock_irqrestore(&ehci->lock, flags);
186 return tegra_ehci_internal_port_reset(ehci, status_reg);
187 }
188
189 /*
190 * Tegra host controller will time the resume operation to clear the bit
191 * when the port control state switches to HS or FS Idle. This behavior
192 * is different from EHCI where the host controller driver is required
193 * to set this bit to a zero after the resume duration is timed in the
194 * driver.
195 */
196 else if (typeReq == ClearPortFeature &&
197 wValue == USB_PORT_FEAT_SUSPEND) {
198 temp = ehci_readl(ehci, status_reg);
199 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
200 retval = -EPIPE;
201 goto done;
202 }
203
204 if (!(temp & PORT_SUSPEND))
205 goto done;
206
207 /* Disable disconnect detection during port resume */
208 tegra_usb_phy_preresume(tegra->phy);
209
210 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
211
212 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
213 /* start resume signalling */
214 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
215 set_bit(wIndex-1, &ehci->resuming_ports);
216
217 spin_unlock_irqrestore(&ehci->lock, flags);
218 msleep(20);
219 spin_lock_irqsave(&ehci->lock, flags);
220
221 /* Poll until the controller clears RESUME and SUSPEND */
222 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
223 pr_err("%s: timeout waiting for RESUME\n", __func__);
224 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
225 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
226
227 ehci->reset_done[wIndex-1] = 0;
228 clear_bit(wIndex-1, &ehci->resuming_ports);
229
230 tegra->port_resuming = 1;
231 goto done;
232 }
233
234 spin_unlock_irqrestore(&ehci->lock, flags);
235
236 /* Handle the hub control events here */
237 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
238 done:
239 spin_unlock_irqrestore(&ehci->lock, flags);
240 return retval;
241 }
242
243 static void tegra_ehci_restart(struct usb_hcd *hcd)
244 {
245 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
246
247 ehci_reset(ehci);
248
249 /* setup the frame list and Async q heads */
250 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
251 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
252 /* setup the command register and set the controller in RUN mode */
253 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
254 ehci->command |= CMD_RUN;
255 ehci_writel(ehci, ehci->command, &ehci->regs->command);
256
257 down_write(&ehci_cf_port_reset_rwsem);
258 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
259 /* flush posted writes */
260 ehci_readl(ehci, &ehci->regs->command);
261 up_write(&ehci_cf_port_reset_rwsem);
262 }
263
264 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
265 {
266 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
267
268 /* ehci_shutdown touches the USB controller registers, make sure
269 * controller has clocks to it */
270 if (!tegra->host_resumed)
271 tegra_ehci_power_up(hcd);
272
273 ehci_shutdown(hcd);
274 }
275
276 static int tegra_ehci_setup(struct usb_hcd *hcd)
277 {
278 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
279 int retval;
280
281 /* EHCI registers start at offset 0x100 */
282 ehci->caps = hcd->regs + 0x100;
283 ehci->regs = hcd->regs + 0x100 +
284 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
285
286 dbg_hcs_params(ehci, "reset");
287 dbg_hcc_params(ehci, "reset");
288
289 /* cache this readonly data; minimize chip reads */
290 ehci->hcs_params = readl(&ehci->caps->hcs_params);
291
292 /* switch to host mode */
293 hcd->has_tt = 1;
294 ehci_reset(ehci);
295
296 retval = ehci_halt(ehci);
297 if (retval)
298 return retval;
299
300 /* data structure init */
301 retval = ehci_init(hcd);
302 if (retval)
303 return retval;
304
305 ehci->sbrn = 0x20;
306
307 ehci_port_power(ehci, 1);
308 return retval;
309 }
310
311 struct dma_aligned_buffer {
312 void *kmalloc_ptr;
313 void *old_xfer_buffer;
314 u8 data[0];
315 };
316
317 static void free_dma_aligned_buffer(struct urb *urb)
318 {
319 struct dma_aligned_buffer *temp;
320
321 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
322 return;
323
324 temp = container_of(urb->transfer_buffer,
325 struct dma_aligned_buffer, data);
326
327 if (usb_urb_dir_in(urb))
328 memcpy(temp->old_xfer_buffer, temp->data,
329 urb->transfer_buffer_length);
330 urb->transfer_buffer = temp->old_xfer_buffer;
331 kfree(temp->kmalloc_ptr);
332
333 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
334 }
335
336 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
337 {
338 struct dma_aligned_buffer *temp, *kmalloc_ptr;
339 size_t kmalloc_size;
340
341 if (urb->num_sgs || urb->sg ||
342 urb->transfer_buffer_length == 0 ||
343 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
344 return 0;
345
346 /* Allocate a buffer with enough padding for alignment */
347 kmalloc_size = urb->transfer_buffer_length +
348 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
349
350 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
351 if (!kmalloc_ptr)
352 return -ENOMEM;
353
354 /* Position our struct dma_aligned_buffer such that data is aligned */
355 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
356 temp->kmalloc_ptr = kmalloc_ptr;
357 temp->old_xfer_buffer = urb->transfer_buffer;
358 if (usb_urb_dir_out(urb))
359 memcpy(temp->data, urb->transfer_buffer,
360 urb->transfer_buffer_length);
361 urb->transfer_buffer = temp->data;
362
363 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
364
365 return 0;
366 }
367
368 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
369 gfp_t mem_flags)
370 {
371 int ret;
372
373 ret = alloc_dma_aligned_buffer(urb, mem_flags);
374 if (ret)
375 return ret;
376
377 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
378 if (ret)
379 free_dma_aligned_buffer(urb);
380
381 return ret;
382 }
383
384 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
385 {
386 usb_hcd_unmap_urb_for_dma(hcd, urb);
387 free_dma_aligned_buffer(urb);
388 }
389
390 static const struct hc_driver tegra_ehci_hc_driver = {
391 .description = hcd_name,
392 .product_desc = "Tegra EHCI Host Controller",
393 .hcd_priv_size = sizeof(struct ehci_hcd),
394 .flags = HCD_USB2 | HCD_MEMORY,
395
396 /* standard ehci functions */
397 .irq = ehci_irq,
398 .start = ehci_run,
399 .stop = ehci_stop,
400 .urb_enqueue = ehci_urb_enqueue,
401 .urb_dequeue = ehci_urb_dequeue,
402 .endpoint_disable = ehci_endpoint_disable,
403 .endpoint_reset = ehci_endpoint_reset,
404 .get_frame_number = ehci_get_frame,
405 .hub_status_data = ehci_hub_status_data,
406 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
407 .relinquish_port = ehci_relinquish_port,
408 .port_handed_over = ehci_port_handed_over,
409
410 /* modified ehci functions for tegra */
411 .reset = tegra_ehci_setup,
412 .shutdown = tegra_ehci_shutdown,
413 .map_urb_for_dma = tegra_ehci_map_urb_for_dma,
414 .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma,
415 .hub_control = tegra_ehci_hub_control,
416 #ifdef CONFIG_PM
417 .bus_suspend = ehci_bus_suspend,
418 .bus_resume = ehci_bus_resume,
419 #endif
420 };
421
422 static int setup_vbus_gpio(struct platform_device *pdev)
423 {
424 int err = 0;
425 int gpio;
426
427 if (!pdev->dev.of_node)
428 return 0;
429
430 gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0);
431 if (!gpio_is_valid(gpio))
432 return 0;
433
434 err = gpio_request(gpio, "vbus_gpio");
435 if (err) {
436 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
437 return err;
438 }
439 err = gpio_direction_output(gpio, 1);
440 if (err) {
441 dev_err(&pdev->dev, "can't enable vbus\n");
442 return err;
443 }
444
445 return err;
446 }
447
448 #ifdef CONFIG_PM
449
450 static int controller_suspend(struct device *dev)
451 {
452 struct tegra_ehci_hcd *tegra =
453 platform_get_drvdata(to_platform_device(dev));
454 struct ehci_hcd *ehci = tegra->ehci;
455 struct usb_hcd *hcd = ehci_to_hcd(ehci);
456 struct ehci_regs __iomem *hw = ehci->regs;
457 unsigned long flags;
458
459 if (time_before(jiffies, ehci->next_statechange))
460 msleep(10);
461
462 spin_lock_irqsave(&ehci->lock, flags);
463
464 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
465 ehci_halt(ehci);
466 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
467
468 spin_unlock_irqrestore(&ehci->lock, flags);
469
470 tegra_ehci_power_down(hcd);
471 return 0;
472 }
473
474 static int controller_resume(struct device *dev)
475 {
476 struct tegra_ehci_hcd *tegra =
477 platform_get_drvdata(to_platform_device(dev));
478 struct ehci_hcd *ehci = tegra->ehci;
479 struct usb_hcd *hcd = ehci_to_hcd(ehci);
480 struct ehci_regs __iomem *hw = ehci->regs;
481 unsigned long val;
482
483 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
484 tegra_ehci_power_up(hcd);
485
486 if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
487 /* Wait for the phy to detect new devices
488 * before we restart the controller */
489 msleep(10);
490 goto restart;
491 }
492
493 /* Force the phy to keep data lines in suspend state */
494 tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
495
496 /* Enable host mode */
497 tdi_reset(ehci);
498
499 /* Enable Port Power */
500 val = readl(&hw->port_status[0]);
501 val |= PORT_POWER;
502 writel(val, &hw->port_status[0]);
503 udelay(10);
504
505 /* Check if the phy resume from LP0. When the phy resume from LP0
506 * USB register will be reset. */
507 if (!readl(&hw->async_next)) {
508 /* Program the field PTC based on the saved speed mode */
509 val = readl(&hw->port_status[0]);
510 val &= ~PORT_TEST(~0);
511 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
512 val |= PORT_TEST_FORCE;
513 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
514 val |= PORT_TEST(6);
515 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
516 val |= PORT_TEST(7);
517 writel(val, &hw->port_status[0]);
518 udelay(10);
519
520 /* Disable test mode by setting PTC field to NORMAL_OP */
521 val = readl(&hw->port_status[0]);
522 val &= ~PORT_TEST(~0);
523 writel(val, &hw->port_status[0]);
524 udelay(10);
525 }
526
527 /* Poll until CCS is enabled */
528 if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
529 PORT_CONNECT, 2000)) {
530 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
531 goto restart;
532 }
533
534 /* Poll until PE is enabled */
535 if (handshake(ehci, &hw->port_status[0], PORT_PE,
536 PORT_PE, 2000)) {
537 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
538 goto restart;
539 }
540
541 /* Clear the PCI status, to avoid an interrupt taken upon resume */
542 val = readl(&hw->status);
543 val |= STS_PCD;
544 writel(val, &hw->status);
545
546 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
547 val = readl(&hw->port_status[0]);
548 if ((val & PORT_POWER) && (val & PORT_PE)) {
549 val |= PORT_SUSPEND;
550 writel(val, &hw->port_status[0]);
551
552 /* Wait until port suspend completes */
553 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
554 PORT_SUSPEND, 1000)) {
555 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
556 __func__);
557 goto restart;
558 }
559 }
560
561 tegra_ehci_phy_restore_end(tegra->phy);
562 goto done;
563
564 restart:
565 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
566 tegra_ehci_phy_restore_end(tegra->phy);
567
568 tegra_ehci_restart(hcd);
569
570 done:
571 tegra_usb_phy_preresume(tegra->phy);
572 tegra->port_resuming = 1;
573 return 0;
574 }
575
576 static int tegra_ehci_suspend(struct device *dev)
577 {
578 struct tegra_ehci_hcd *tegra =
579 platform_get_drvdata(to_platform_device(dev));
580 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
581 int rc = 0;
582
583 /*
584 * When system sleep is supported and USB controller wakeup is
585 * implemented: If the controller is runtime-suspended and the
586 * wakeup setting needs to be changed, call pm_runtime_resume().
587 */
588 if (HCD_HW_ACCESSIBLE(hcd))
589 rc = controller_suspend(dev);
590 return rc;
591 }
592
593 static int tegra_ehci_resume(struct device *dev)
594 {
595 int rc;
596
597 rc = controller_resume(dev);
598 if (rc == 0) {
599 pm_runtime_disable(dev);
600 pm_runtime_set_active(dev);
601 pm_runtime_enable(dev);
602 }
603 return rc;
604 }
605
606 static int tegra_ehci_runtime_suspend(struct device *dev)
607 {
608 return controller_suspend(dev);
609 }
610
611 static int tegra_ehci_runtime_resume(struct device *dev)
612 {
613 return controller_resume(dev);
614 }
615
616 static const struct dev_pm_ops tegra_ehci_pm_ops = {
617 .suspend = tegra_ehci_suspend,
618 .resume = tegra_ehci_resume,
619 .runtime_suspend = tegra_ehci_runtime_suspend,
620 .runtime_resume = tegra_ehci_runtime_resume,
621 };
622
623 #endif
624
625 static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
626
627 static int tegra_ehci_probe(struct platform_device *pdev)
628 {
629 struct resource *res;
630 struct usb_hcd *hcd;
631 struct tegra_ehci_hcd *tegra;
632 struct tegra_ehci_platform_data *pdata;
633 int err = 0;
634 int irq;
635 int instance = pdev->id;
636
637 pdata = pdev->dev.platform_data;
638 if (!pdata) {
639 dev_err(&pdev->dev, "Platform data missing\n");
640 return -EINVAL;
641 }
642
643 /* Right now device-tree probed devices don't get dma_mask set.
644 * Since shared usb code relies on it, set it here for now.
645 * Once we have dma capability bindings this can go away.
646 */
647 if (!pdev->dev.dma_mask)
648 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
649
650 setup_vbus_gpio(pdev);
651
652 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
653 if (!tegra)
654 return -ENOMEM;
655
656 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
657 dev_name(&pdev->dev));
658 if (!hcd) {
659 dev_err(&pdev->dev, "Unable to create HCD\n");
660 err = -ENOMEM;
661 goto fail_hcd;
662 }
663
664 platform_set_drvdata(pdev, tegra);
665
666 tegra->clk = clk_get(&pdev->dev, NULL);
667 if (IS_ERR(tegra->clk)) {
668 dev_err(&pdev->dev, "Can't get ehci clock\n");
669 err = PTR_ERR(tegra->clk);
670 goto fail_clk;
671 }
672
673 err = clk_enable(tegra->clk);
674 if (err)
675 goto fail_clken;
676
677 tegra->emc_clk = clk_get(&pdev->dev, "emc");
678 if (IS_ERR(tegra->emc_clk)) {
679 dev_err(&pdev->dev, "Can't get emc clock\n");
680 err = PTR_ERR(tegra->emc_clk);
681 goto fail_emc_clk;
682 }
683
684 clk_enable(tegra->emc_clk);
685 clk_set_rate(tegra->emc_clk, 400000000);
686
687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
688 if (!res) {
689 dev_err(&pdev->dev, "Failed to get I/O memory\n");
690 err = -ENXIO;
691 goto fail_io;
692 }
693 hcd->rsrc_start = res->start;
694 hcd->rsrc_len = resource_size(res);
695 hcd->regs = ioremap(res->start, resource_size(res));
696 if (!hcd->regs) {
697 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
698 err = -ENOMEM;
699 goto fail_io;
700 }
701
702 /* This is pretty ugly and needs to be fixed when we do only
703 * device-tree probing. Old code relies on the platform_device
704 * numbering that we lack for device-tree-instantiated devices.
705 */
706 if (instance < 0) {
707 switch (res->start) {
708 case TEGRA_USB_BASE:
709 instance = 0;
710 break;
711 case TEGRA_USB2_BASE:
712 instance = 1;
713 break;
714 case TEGRA_USB3_BASE:
715 instance = 2;
716 break;
717 default:
718 err = -ENODEV;
719 dev_err(&pdev->dev, "unknown usb instance\n");
720 goto fail_phy;
721 }
722 }
723
724 tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
725 TEGRA_USB_PHY_MODE_HOST);
726 if (IS_ERR(tegra->phy)) {
727 dev_err(&pdev->dev, "Failed to open USB phy\n");
728 err = -ENXIO;
729 goto fail_phy;
730 }
731
732 err = tegra_usb_phy_power_on(tegra->phy);
733 if (err) {
734 dev_err(&pdev->dev, "Failed to power on the phy\n");
735 goto fail;
736 }
737
738 tegra->host_resumed = 1;
739 tegra->ehci = hcd_to_ehci(hcd);
740
741 irq = platform_get_irq(pdev, 0);
742 if (!irq) {
743 dev_err(&pdev->dev, "Failed to get IRQ\n");
744 err = -ENODEV;
745 goto fail;
746 }
747
748 #ifdef CONFIG_USB_OTG_UTILS
749 if (pdata->operating_mode == TEGRA_USB_OTG) {
750 tegra->transceiver = usb_get_transceiver();
751 if (tegra->transceiver)
752 otg_set_host(tegra->transceiver->otg, &hcd->self);
753 }
754 #endif
755
756 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
757 if (err) {
758 dev_err(&pdev->dev, "Failed to add USB HCD\n");
759 goto fail;
760 }
761
762 pm_runtime_set_active(&pdev->dev);
763 pm_runtime_get_noresume(&pdev->dev);
764
765 /* Don't skip the pm_runtime_forbid call if wakeup isn't working */
766 /* if (!pdata->power_down_on_bus_suspend) */
767 pm_runtime_forbid(&pdev->dev);
768 pm_runtime_enable(&pdev->dev);
769 pm_runtime_put_sync(&pdev->dev);
770 return err;
771
772 fail:
773 #ifdef CONFIG_USB_OTG_UTILS
774 if (tegra->transceiver) {
775 otg_set_host(tegra->transceiver->otg, NULL);
776 usb_put_transceiver(tegra->transceiver);
777 }
778 #endif
779 tegra_usb_phy_close(tegra->phy);
780 fail_phy:
781 iounmap(hcd->regs);
782 fail_io:
783 clk_disable(tegra->emc_clk);
784 clk_put(tegra->emc_clk);
785 fail_emc_clk:
786 clk_disable(tegra->clk);
787 fail_clken:
788 clk_put(tegra->clk);
789 fail_clk:
790 usb_put_hcd(hcd);
791 fail_hcd:
792 kfree(tegra);
793 return err;
794 }
795
796 static int tegra_ehci_remove(struct platform_device *pdev)
797 {
798 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
799 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
800
801 if (tegra == NULL || hcd == NULL)
802 return -EINVAL;
803
804 pm_runtime_get_sync(&pdev->dev);
805 pm_runtime_disable(&pdev->dev);
806 pm_runtime_put_noidle(&pdev->dev);
807
808 #ifdef CONFIG_USB_OTG_UTILS
809 if (tegra->transceiver) {
810 otg_set_host(tegra->transceiver->otg, NULL);
811 usb_put_transceiver(tegra->transceiver);
812 }
813 #endif
814
815 usb_remove_hcd(hcd);
816 usb_put_hcd(hcd);
817
818 tegra_usb_phy_close(tegra->phy);
819 iounmap(hcd->regs);
820
821 clk_disable(tegra->clk);
822 clk_put(tegra->clk);
823
824 clk_disable(tegra->emc_clk);
825 clk_put(tegra->emc_clk);
826
827 kfree(tegra);
828 return 0;
829 }
830
831 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
832 {
833 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
834 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
835
836 if (hcd->driver->shutdown)
837 hcd->driver->shutdown(hcd);
838 }
839
840 static struct of_device_id tegra_ehci_of_match[] __devinitdata = {
841 { .compatible = "nvidia,tegra20-ehci", },
842 { },
843 };
844
845 static struct platform_driver tegra_ehci_driver = {
846 .probe = tegra_ehci_probe,
847 .remove = tegra_ehci_remove,
848 .shutdown = tegra_ehci_hcd_shutdown,
849 .driver = {
850 .name = "tegra-ehci",
851 .of_match_table = tegra_ehci_of_match,
852 #ifdef CONFIG_PM
853 .pm = &tegra_ehci_pm_ops,
854 #endif
855 }
856 };
Linux kernel - Deliverables
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