2 * Open Host Controller Interface (OHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
20 * This file is licenced under the GPL.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52 /*-------------------------------------------------------------------------*/
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
72 /*-------------------------------------------------------------------------*/
74 static const char hcd_name
[] = "ohci_hcd";
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
79 #include "pci-quirks.h"
81 static void ohci_dump (struct ohci_hcd
*ohci
, int verbose
);
82 static int ohci_init (struct ohci_hcd
*ohci
);
83 static void ohci_stop (struct usb_hcd
*hcd
);
85 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
86 static int ohci_restart (struct ohci_hcd
*ohci
);
90 static void sb800_prefetch(struct ohci_hcd
*ohci
, int on
);
92 static inline void sb800_prefetch(struct ohci_hcd
*ohci
, int on
)
100 #include "ohci-dbg.c"
101 #include "ohci-mem.c"
106 * On architectures with edge-triggered interrupts we must never return
109 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
110 #define IRQ_NOTMINE IRQ_HANDLED
112 #define IRQ_NOTMINE IRQ_NONE
116 /* Some boards misreport power switching/overcurrent */
117 static bool distrust_firmware
= 1;
118 module_param (distrust_firmware
, bool, 0);
119 MODULE_PARM_DESC (distrust_firmware
,
120 "true to distrust firmware power/overcurrent setup");
122 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
123 static bool no_handshake
= 0;
124 module_param (no_handshake
, bool, 0);
125 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
127 /*-------------------------------------------------------------------------*/
130 * queue up an urb for anything except the root hub
132 static int ohci_urb_enqueue (
137 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
139 urb_priv_t
*urb_priv
;
140 unsigned int pipe
= urb
->pipe
;
145 #ifdef OHCI_VERBOSE_DEBUG
146 urb_print(urb
, "SUB", usb_pipein(pipe
), -EINPROGRESS
);
149 /* every endpoint has a ed, locate and maybe (re)initialize it */
150 if (! (ed
= ed_get (ohci
, urb
->ep
, urb
->dev
, pipe
, urb
->interval
)))
153 /* for the private part of the URB we need the number of TDs (size) */
156 /* td_submit_urb() doesn't yet handle these */
157 if (urb
->transfer_buffer_length
> 4096)
160 /* 1 TD for setup, 1 for ACK, plus ... */
163 // case PIPE_INTERRUPT:
166 /* one TD for every 4096 Bytes (can be up to 8K) */
167 size
+= urb
->transfer_buffer_length
/ 4096;
168 /* ... and for any remaining bytes ... */
169 if ((urb
->transfer_buffer_length
% 4096) != 0)
171 /* ... and maybe a zero length packet to wrap it up */
174 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
175 && (urb
->transfer_buffer_length
176 % usb_maxpacket (urb
->dev
, pipe
,
177 usb_pipeout (pipe
))) == 0)
180 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
181 size
= urb
->number_of_packets
;
185 /* allocate the private part of the URB */
186 urb_priv
= kzalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
190 INIT_LIST_HEAD (&urb_priv
->pending
);
191 urb_priv
->length
= size
;
194 /* allocate the TDs (deferring hash chain updates) */
195 for (i
= 0; i
< size
; i
++) {
196 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
197 if (!urb_priv
->td
[i
]) {
198 urb_priv
->length
= i
;
199 urb_free_priv (ohci
, urb_priv
);
204 spin_lock_irqsave (&ohci
->lock
, flags
);
206 /* don't submit to a dead HC */
207 if (!HCD_HW_ACCESSIBLE(hcd
)) {
211 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
215 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
219 /* schedule the ed if needed */
220 if (ed
->state
== ED_IDLE
) {
221 retval
= ed_schedule (ohci
, ed
);
223 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
226 if (ed
->type
== PIPE_ISOCHRONOUS
) {
227 u16 frame
= ohci_frame_no(ohci
);
229 /* delay a few frames before the first TD */
230 frame
+= max_t (u16
, 8, ed
->interval
);
231 frame
&= ~(ed
->interval
- 1);
233 urb
->start_frame
= frame
;
235 } else if (ed
->type
== PIPE_ISOCHRONOUS
) {
236 u16 next
= ohci_frame_no(ohci
) + 2;
237 u16 frame
= ed
->last_iso
+ ed
->interval
;
239 /* Behind the scheduling threshold? */
240 if (unlikely(tick_before(frame
, next
))) {
242 /* USB_ISO_ASAP: Round up to the first available slot */
243 if (urb
->transfer_flags
& URB_ISO_ASAP
)
244 frame
+= (next
- frame
+ ed
->interval
- 1) &
248 * Not ASAP: Use the next slot in the stream. If
249 * the entire URB falls before the threshold, fail.
251 else if (tick_before(frame
+ ed
->interval
*
252 (urb
->number_of_packets
- 1), next
)) {
254 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
259 * Some OHCI hardware doesn't handle late TDs
260 * correctly. After retiring them it proceeds to
261 * the next ED instead of the next TD. Therefore
262 * we have to omit the late TDs entirely.
264 urb_priv
->td_cnt
= DIV_ROUND_UP(next
- frame
,
267 urb
->start_frame
= frame
;
270 /* fill the TDs and link them to the ed; and
271 * enable that part of the schedule, if needed
272 * and update count of queued periodic urbs
274 urb
->hcpriv
= urb_priv
;
275 td_submit_urb (ohci
, urb
);
279 urb_free_priv (ohci
, urb_priv
);
280 spin_unlock_irqrestore (&ohci
->lock
, flags
);
285 * decouple the URB from the HC queues (TDs, urb_priv).
286 * reporting is always done
287 * asynchronously, and we might be dealing with an urb that's
288 * partially transferred, or an ED with other urbs being unlinked.
290 static int ohci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
292 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
296 #ifdef OHCI_VERBOSE_DEBUG
297 urb_print(urb
, "UNLINK", 1, status
);
300 spin_lock_irqsave (&ohci
->lock
, flags
);
301 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
304 } else if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
305 urb_priv_t
*urb_priv
;
307 /* Unless an IRQ completed the unlink while it was being
308 * handed to us, flag it for unlink and giveback, and force
309 * some upcoming INTR_SF to call finish_unlinks()
311 urb_priv
= urb
->hcpriv
;
313 if (urb_priv
->ed
->state
== ED_OPER
)
314 start_ed_unlink (ohci
, urb_priv
->ed
);
318 * with HC dead, we won't respect hc queue pointers
319 * any more ... just clean up every urb's memory.
322 finish_urb(ohci
, urb
, status
);
324 spin_unlock_irqrestore (&ohci
->lock
, flags
);
328 /*-------------------------------------------------------------------------*/
330 /* frees config/altsetting state for endpoints,
331 * including ED memory, dummy TD, and bulk/intr data toggle
335 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
337 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
339 struct ed
*ed
= ep
->hcpriv
;
340 unsigned limit
= 1000;
342 /* ASSERT: any requests/urbs are being unlinked */
343 /* ASSERT: nobody can be submitting urbs for this any more */
349 spin_lock_irqsave (&ohci
->lock
, flags
);
351 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
354 if (quirk_zfmicro(ohci
) && ed
->type
== PIPE_INTERRUPT
)
355 ohci
->eds_scheduled
--;
356 finish_unlinks (ohci
, 0);
360 case ED_UNLINK
: /* wait for hw to finish? */
361 /* major IRQ delivery trouble loses INTR_SF too... */
363 ohci_warn(ohci
, "ED unlink timeout\n");
364 if (quirk_zfmicro(ohci
)) {
365 ohci_warn(ohci
, "Attempting ZF TD recovery\n");
366 ohci
->ed_to_check
= ed
;
371 spin_unlock_irqrestore (&ohci
->lock
, flags
);
372 schedule_timeout_uninterruptible(1);
374 case ED_IDLE
: /* fully unlinked */
375 if (list_empty (&ed
->td_list
)) {
376 td_free (ohci
, ed
->dummy
);
380 /* else FALL THROUGH */
382 /* caller was supposed to have unlinked any requests;
383 * that's not our job. can't recover; must leak ed.
385 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
386 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
387 list_empty (&ed
->td_list
) ? "" : " (has tds)");
388 td_free (ohci
, ed
->dummy
);
392 spin_unlock_irqrestore (&ohci
->lock
, flags
);
395 static int ohci_get_frame (struct usb_hcd
*hcd
)
397 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
399 return ohci_frame_no(ohci
);
402 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
404 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
405 ohci
->hc_control
&= OHCI_CTRL_RWC
;
406 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
407 ohci
->rh_state
= OHCI_RH_HALTED
;
410 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
411 * other cases where the next software may expect clean state from the
412 * "firmware". this is bus-neutral, unlike shutdown() methods.
415 ohci_shutdown (struct usb_hcd
*hcd
)
417 struct ohci_hcd
*ohci
;
419 ohci
= hcd_to_ohci (hcd
);
420 ohci_writel(ohci
, (u32
) ~0, &ohci
->regs
->intrdisable
);
422 /* Software reset, after which the controller goes into SUSPEND */
423 ohci_writel(ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
424 ohci_readl(ohci
, &ohci
->regs
->cmdstatus
); /* flush the writes */
427 ohci_writel(ohci
, ohci
->fminterval
, &ohci
->regs
->fminterval
);
430 static int check_ed(struct ohci_hcd
*ohci
, struct ed
*ed
)
432 return (hc32_to_cpu(ohci
, ed
->hwINFO
) & ED_IN
) != 0
433 && (hc32_to_cpu(ohci
, ed
->hwHeadP
) & TD_MASK
)
434 == (hc32_to_cpu(ohci
, ed
->hwTailP
) & TD_MASK
)
435 && !list_empty(&ed
->td_list
);
438 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
439 * an interrupt TD but neglects to add it to the donelist. On systems with
440 * this chipset, we need to periodically check the state of the queues to look
441 * for such "lost" TDs.
443 static void unlink_watchdog_func(unsigned long _ohci
)
447 unsigned seen_count
= 0;
449 struct ed
**seen
= NULL
;
450 struct ohci_hcd
*ohci
= (struct ohci_hcd
*) _ohci
;
452 spin_lock_irqsave(&ohci
->lock
, flags
);
453 max
= ohci
->eds_scheduled
;
457 if (ohci
->ed_to_check
)
460 seen
= kcalloc(max
, sizeof *seen
, GFP_ATOMIC
);
464 for (i
= 0; i
< NUM_INTS
; i
++) {
465 struct ed
*ed
= ohci
->periodic
[i
];
470 /* scan this branch of the periodic schedule tree */
471 for (temp
= 0; temp
< seen_count
; temp
++) {
472 if (seen
[temp
] == ed
) {
473 /* we've checked it and what's after */
480 seen
[seen_count
++] = ed
;
481 if (!check_ed(ohci
, ed
)) {
486 /* HC's TD list is empty, but HCD sees at least one
487 * TD that's not been sent through the donelist.
489 ohci
->ed_to_check
= ed
;
492 /* The HC may wait until the next frame to report the
493 * TD as done through the donelist and INTR_WDH. (We
494 * just *assume* it's not a multi-TD interrupt URB;
495 * those could defer the IRQ more than one frame, using
496 * DI...) Check again after the next INTR_SF.
498 ohci_writel(ohci
, OHCI_INTR_SF
,
499 &ohci
->regs
->intrstatus
);
500 ohci_writel(ohci
, OHCI_INTR_SF
,
501 &ohci
->regs
->intrenable
);
503 /* flush those writes */
504 (void) ohci_readl(ohci
, &ohci
->regs
->control
);
511 if (ohci
->eds_scheduled
)
512 mod_timer(&ohci
->unlink_watchdog
, round_jiffies(jiffies
+ HZ
));
514 spin_unlock_irqrestore(&ohci
->lock
, flags
);
517 /*-------------------------------------------------------------------------*
519 *-------------------------------------------------------------------------*/
521 /* init memory, and kick BIOS/SMM off */
523 static int ohci_init (struct ohci_hcd
*ohci
)
526 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
528 if (distrust_firmware
)
529 ohci
->flags
|= OHCI_QUIRK_HUB_POWER
;
531 ohci
->rh_state
= OHCI_RH_HALTED
;
532 ohci
->regs
= hcd
->regs
;
534 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
535 * was never needed for most non-PCI systems ... remove the code?
539 /* SMM owns the HC? not for long! */
540 if (!no_handshake
&& ohci_readl (ohci
,
541 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
544 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
546 /* this timeout is arbitrary. we make it long, so systems
547 * depending on usb keyboards may be usable even if the
548 * BIOS/SMM code seems pretty broken.
550 temp
= 500; /* arbitrary: five seconds */
552 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
553 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
554 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
557 ohci_err (ohci
, "USB HC takeover failed!"
558 " (BIOS/SMM bug)\n");
562 ohci_usb_reset (ohci
);
566 /* Disable HC interrupts */
567 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
569 /* flush the writes, and save key bits like RWC */
570 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
571 ohci
->hc_control
|= OHCI_CTRL_RWC
;
573 /* Read the number of ports unless overridden */
574 if (ohci
->num_ports
== 0)
575 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
580 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
581 sizeof *ohci
->hcca
, &ohci
->hcca_dma
, 0);
585 if ((ret
= ohci_mem_init (ohci
)) < 0)
588 create_debug_files (ohci
);
594 /*-------------------------------------------------------------------------*/
596 /* Start an OHCI controller, set the BUS operational
597 * resets USB and controller
600 static int ohci_run (struct ohci_hcd
*ohci
)
603 int first
= ohci
->fminterval
== 0;
604 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
606 ohci
->rh_state
= OHCI_RH_HALTED
;
608 /* boot firmware should have set this up (5.1.1.3.1) */
611 val
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
612 ohci
->fminterval
= val
& 0x3fff;
613 if (ohci
->fminterval
!= FI
)
614 ohci_dbg (ohci
, "fminterval delta %d\n",
615 ohci
->fminterval
- FI
);
616 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
617 /* also: power/overcurrent flags in roothub.a */
620 /* Reset USB nearly "by the book". RemoteWakeupConnected has
621 * to be checked in case boot firmware (BIOS/SMM/...) has set up
622 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
623 * If the bus glue detected wakeup capability then it should
624 * already be enabled; if so we'll just enable it again.
626 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0)
627 device_set_wakeup_capable(hcd
->self
.controller
, 1);
629 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
633 case OHCI_USB_SUSPEND
:
634 case OHCI_USB_RESUME
:
635 ohci
->hc_control
&= OHCI_CTRL_RWC
;
636 ohci
->hc_control
|= OHCI_USB_RESUME
;
637 val
= 10 /* msec wait */;
639 // case OHCI_USB_RESET:
641 ohci
->hc_control
&= OHCI_CTRL_RWC
;
642 ohci
->hc_control
|= OHCI_USB_RESET
;
643 val
= 50 /* msec wait */;
646 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
648 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
651 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
653 /* 2msec timelimit here means no irqs/preempt */
654 spin_lock_irq (&ohci
->lock
);
657 /* HC Reset requires max 10 us delay */
658 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
659 val
= 30; /* ... allow extra time */
660 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
662 spin_unlock_irq (&ohci
->lock
);
663 ohci_err (ohci
, "USB HC reset timed out!\n");
669 /* now we're in the SUSPEND state ... must go OPERATIONAL
670 * within 2msec else HC enters RESUME
672 * ... but some hardware won't init fmInterval "by the book"
673 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
674 * this if we write fmInterval after we're OPERATIONAL.
675 * Unclear about ALi, ServerWorks, and others ... this could
676 * easily be a longstanding bug in chip init on Linux.
678 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
679 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
680 // flush those writes
681 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
684 /* Tell the controller where the control and bulk lists are
685 * The lists are empty now. */
686 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
687 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
689 /* a reset clears this */
690 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
692 periodic_reinit (ohci
);
694 /* some OHCI implementations are finicky about how they init.
695 * bogus values here mean not even enumeration could work.
697 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
698 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
699 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
700 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
701 ohci_dbg (ohci
, "enabling initreset quirk\n");
704 spin_unlock_irq (&ohci
->lock
);
705 ohci_err (ohci
, "init err (%08x %04x)\n",
706 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
707 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
711 /* use rhsc irqs after khubd is fully initialized */
712 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
713 hcd
->uses_new_polling
= 1;
715 /* start controller operations */
716 ohci
->hc_control
&= OHCI_CTRL_RWC
;
717 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
718 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
719 ohci
->rh_state
= OHCI_RH_RUNNING
;
721 /* wake on ConnectStatusChange, matching external hubs */
722 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
724 /* Choose the interrupts we care about now, others later on demand */
725 mask
= OHCI_INTR_INIT
;
726 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
727 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
729 /* handle root hub init quirks ... */
730 val
= roothub_a (ohci
);
731 val
&= ~(RH_A_PSM
| RH_A_OCPM
);
732 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
733 /* NSC 87560 and maybe others */
735 val
&= ~(RH_A_POTPGT
| RH_A_NPS
);
736 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
737 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) ||
738 (ohci
->flags
& OHCI_QUIRK_HUB_POWER
)) {
739 /* hub power always on; required for AMD-756 and some
740 * Mac platforms. ganged overcurrent reporting, if any.
743 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
745 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
746 ohci_writel (ohci
, (val
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
747 &ohci
->regs
->roothub
.b
);
748 // flush those writes
749 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
751 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
752 spin_unlock_irq (&ohci
->lock
);
754 // POTPGT delay is bits 24-31, in 2 ms units.
755 mdelay ((val
>> 23) & 0x1fe);
757 if (quirk_zfmicro(ohci
)) {
758 /* Create timer to watch for bad queue state on ZF Micro */
759 setup_timer(&ohci
->unlink_watchdog
, unlink_watchdog_func
,
760 (unsigned long) ohci
);
762 ohci
->eds_scheduled
= 0;
763 ohci
->ed_to_check
= NULL
;
771 /*-------------------------------------------------------------------------*/
773 /* an interrupt happens */
775 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
777 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
778 struct ohci_regs __iomem
*regs
= ohci
->regs
;
781 /* Read interrupt status (and flush pending writes). We ignore the
782 * optimization of checking the LSB of hcca->done_head; it doesn't
783 * work on all systems (edge triggering for OHCI can be a factor).
785 ints
= ohci_readl(ohci
, ®s
->intrstatus
);
787 /* Check for an all 1's result which is a typical consequence
788 * of dead, unclocked, or unplugged (CardBus...) devices
790 if (ints
== ~(u32
)0) {
791 ohci
->rh_state
= OHCI_RH_HALTED
;
792 ohci_dbg (ohci
, "device removed!\n");
797 /* We only care about interrupts that are enabled */
798 ints
&= ohci_readl(ohci
, ®s
->intrenable
);
800 /* interrupt for some other device? */
801 if (ints
== 0 || unlikely(ohci
->rh_state
== OHCI_RH_HALTED
))
804 if (ints
& OHCI_INTR_UE
) {
805 // e.g. due to PCI Master/Target Abort
806 if (quirk_nec(ohci
)) {
807 /* Workaround for a silicon bug in some NEC chips used
808 * in Apple's PowerBooks. Adapted from Darwin code.
810 ohci_err (ohci
, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
812 ohci_writel (ohci
, OHCI_INTR_UE
, ®s
->intrdisable
);
814 schedule_work (&ohci
->nec_work
);
816 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
817 ohci
->rh_state
= OHCI_RH_HALTED
;
822 ohci_usb_reset (ohci
);
825 if (ints
& OHCI_INTR_RHSC
) {
826 ohci_vdbg(ohci
, "rhsc\n");
827 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
828 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
831 /* NOTE: Vendors didn't always make the same implementation
832 * choices for RHSC. Many followed the spec; RHSC triggers
833 * on an edge, like setting and maybe clearing a port status
834 * change bit. With others it's level-triggered, active
835 * until khubd clears all the port status change bits. We'll
836 * always disable it here and rely on polling until khubd
839 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
840 usb_hcd_poll_rh_status(hcd
);
843 /* For connect and disconnect events, we expect the controller
844 * to turn on RHSC along with RD. But for remote wakeup events
845 * this might not happen.
847 else if (ints
& OHCI_INTR_RD
) {
848 ohci_vdbg(ohci
, "resume detect\n");
849 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
850 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
851 if (ohci
->autostop
) {
852 spin_lock (&ohci
->lock
);
853 ohci_rh_resume (ohci
);
854 spin_unlock (&ohci
->lock
);
856 usb_hcd_resume_root_hub(hcd
);
859 if (ints
& OHCI_INTR_WDH
) {
860 spin_lock (&ohci
->lock
);
862 spin_unlock (&ohci
->lock
);
865 if (quirk_zfmicro(ohci
) && (ints
& OHCI_INTR_SF
)) {
866 spin_lock(&ohci
->lock
);
867 if (ohci
->ed_to_check
) {
868 struct ed
*ed
= ohci
->ed_to_check
;
870 if (check_ed(ohci
, ed
)) {
871 /* HC thinks the TD list is empty; HCD knows
872 * at least one TD is outstanding
874 if (--ohci
->zf_delay
== 0) {
875 struct td
*td
= list_entry(
879 "Reclaiming orphan TD %p\n",
881 takeback_td(ohci
, td
);
882 ohci
->ed_to_check
= NULL
;
885 ohci
->ed_to_check
= NULL
;
887 spin_unlock(&ohci
->lock
);
890 /* could track INTR_SO to reduce available PCI/... bandwidth */
892 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
893 * when there's still unlinking to be done (next frame).
895 spin_lock (&ohci
->lock
);
896 if (ohci
->ed_rm_list
)
897 finish_unlinks (ohci
, ohci_frame_no(ohci
));
898 if ((ints
& OHCI_INTR_SF
) != 0
900 && !ohci
->ed_to_check
901 && ohci
->rh_state
== OHCI_RH_RUNNING
)
902 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
903 spin_unlock (&ohci
->lock
);
905 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
906 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
907 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
908 // flush those writes
909 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
915 /*-------------------------------------------------------------------------*/
917 static void ohci_stop (struct usb_hcd
*hcd
)
919 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
924 flush_work(&ohci
->nec_work
);
926 ohci_usb_reset (ohci
);
927 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
928 free_irq(hcd
->irq
, hcd
);
931 if (quirk_zfmicro(ohci
))
932 del_timer(&ohci
->unlink_watchdog
);
933 if (quirk_amdiso(ohci
))
936 remove_debug_files (ohci
);
937 ohci_mem_cleanup (ohci
);
939 dma_free_coherent (hcd
->self
.controller
,
941 ohci
->hcca
, ohci
->hcca_dma
);
947 /*-------------------------------------------------------------------------*/
949 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
951 /* must not be called from interrupt context */
952 static int ohci_restart (struct ohci_hcd
*ohci
)
956 struct urb_priv
*priv
;
958 spin_lock_irq(&ohci
->lock
);
959 ohci
->rh_state
= OHCI_RH_HALTED
;
961 /* Recycle any "live" eds/tds (and urbs). */
962 if (!list_empty (&ohci
->pending
))
963 ohci_dbg(ohci
, "abort schedule...\n");
964 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
965 struct urb
*urb
= priv
->td
[0]->urb
;
966 struct ed
*ed
= priv
->ed
;
970 ed
->state
= ED_UNLINK
;
971 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
972 ed_deschedule (ohci
, ed
);
974 ed
->ed_next
= ohci
->ed_rm_list
;
976 ohci
->ed_rm_list
= ed
;
981 ohci_dbg(ohci
, "bogus ed %p state %d\n",
986 urb
->unlinked
= -ESHUTDOWN
;
988 finish_unlinks (ohci
, 0);
989 spin_unlock_irq(&ohci
->lock
);
991 /* paranoia, in case that didn't work: */
993 /* empty the interrupt branches */
994 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
995 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
997 /* no EDs to remove */
998 ohci
->ed_rm_list
= NULL
;
1000 /* empty control and bulk lists */
1001 ohci
->ed_controltail
= NULL
;
1002 ohci
->ed_bulktail
= NULL
;
1004 if ((temp
= ohci_run (ohci
)) < 0) {
1005 ohci_err (ohci
, "can't restart, %d\n", temp
);
1008 ohci_dbg(ohci
, "restart complete\n");
1016 static int __maybe_unused
ohci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
)
1018 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
1019 unsigned long flags
;
1022 /* Root hub was already suspended. Disable irq emission and
1023 * mark HW unaccessible, bail out if RH has been resumed. Use
1024 * the spinlock to properly synchronize with possible pending
1025 * RH suspend or resume activity.
1027 spin_lock_irqsave (&ohci
->lock
, flags
);
1028 if (ohci
->rh_state
!= OHCI_RH_SUSPENDED
) {
1032 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
1033 (void)ohci_readl(ohci
, &ohci
->regs
->intrdisable
);
1035 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1037 spin_unlock_irqrestore (&ohci
->lock
, flags
);
1043 static int __maybe_unused
ohci_resume(struct usb_hcd
*hcd
, bool hibernated
)
1045 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1047 /* Make sure resume from hibernation re-enumerates everything */
1049 ohci_usb_reset(hcd_to_ohci(hcd
));
1051 ohci_finish_controller_resume(hcd
);
1057 /*-------------------------------------------------------------------------*/
1059 MODULE_AUTHOR (DRIVER_AUTHOR
);
1060 MODULE_DESCRIPTION(DRIVER_DESC
);
1061 MODULE_LICENSE ("GPL");
1064 #include "ohci-pci.c"
1065 #define PCI_DRIVER ohci_pci_driver
1068 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1069 #include "ohci-sa1111.c"
1070 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1073 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1074 #include "ohci-s3c2410.c"
1075 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1078 #ifdef CONFIG_USB_OHCI_EXYNOS
1079 #include "ohci-exynos.c"
1080 #define PLATFORM_DRIVER exynos_ohci_driver
1083 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1084 #include "ohci-omap.c"
1085 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1088 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1089 #include "ohci-omap3.c"
1090 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1093 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1094 #include "ohci-pxa27x.c"
1095 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1098 #ifdef CONFIG_ARCH_EP93XX
1099 #include "ohci-ep93xx.c"
1100 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1103 #ifdef CONFIG_MIPS_ALCHEMY
1104 #include "ohci-au1xxx.c"
1105 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1108 #ifdef CONFIG_PNX8550
1109 #include "ohci-pnx8550.c"
1110 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1113 #ifdef CONFIG_ARCH_AT91
1114 #include "ohci-at91.c"
1115 #define PLATFORM_DRIVER ohci_hcd_at91_driver
1118 #ifdef CONFIG_ARCH_LPC32XX
1119 #include "ohci-nxp.c"
1120 #define PLATFORM_DRIVER usb_hcd_nxp_driver
1123 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1124 #include "ohci-da8xx.c"
1125 #define PLATFORM_DRIVER ohci_hcd_da8xx_driver
1128 #ifdef CONFIG_USB_OHCI_SH
1129 #include "ohci-sh.c"
1130 #define PLATFORM_DRIVER ohci_hcd_sh_driver
1134 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1135 #include "ohci-ppc-of.c"
1136 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1139 #ifdef CONFIG_PLAT_SPEAR
1140 #include "ohci-spear.c"
1141 #define PLATFORM_DRIVER spear_ohci_hcd_driver
1144 #ifdef CONFIG_PPC_PS3
1145 #include "ohci-ps3.c"
1146 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1149 #ifdef CONFIG_MFD_SM501
1150 #include "ohci-sm501.c"
1151 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1154 #ifdef CONFIG_MFD_TC6393XB
1155 #include "ohci-tmio.c"
1156 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1159 #ifdef CONFIG_MACH_JZ4740
1160 #include "ohci-jz4740.c"
1161 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1164 #ifdef CONFIG_USB_OCTEON_OHCI
1165 #include "ohci-octeon.c"
1166 #define PLATFORM_DRIVER ohci_octeon_driver
1169 #ifdef CONFIG_TILE_USB
1170 #include "ohci-tilegx.c"
1171 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1174 #ifdef CONFIG_USB_CNS3XXX_OHCI
1175 #include "ohci-cns3xxx.c"
1176 #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver
1179 #ifdef CONFIG_CPU_XLR
1180 #include "ohci-xls.c"
1181 #define PLATFORM_DRIVER ohci_xls_driver
1184 #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
1185 #include "ohci-platform.c"
1186 #define PLATFORM_DRIVER ohci_platform_driver
1189 #if !defined(PCI_DRIVER) && \
1190 !defined(PLATFORM_DRIVER) && \
1191 !defined(OMAP1_PLATFORM_DRIVER) && \
1192 !defined(OMAP3_PLATFORM_DRIVER) && \
1193 !defined(OF_PLATFORM_DRIVER) && \
1194 !defined(SA1111_DRIVER) && \
1195 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1196 !defined(SM501_OHCI_DRIVER) && \
1197 !defined(TMIO_OHCI_DRIVER)
1198 #error "missing bus glue for ohci-hcd"
1201 static int __init
ohci_hcd_mod_init(void)
1208 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1209 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name
,
1210 sizeof (struct ed
), sizeof (struct td
));
1211 set_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1214 ohci_debug_root
= debugfs_create_dir("ohci", usb_debug_root
);
1215 if (!ohci_debug_root
) {
1221 #ifdef PS3_SYSTEM_BUS_DRIVER
1222 retval
= ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1227 #ifdef PLATFORM_DRIVER
1228 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1230 goto error_platform
;
1233 #ifdef OMAP1_PLATFORM_DRIVER
1234 retval
= platform_driver_register(&OMAP1_PLATFORM_DRIVER
);
1236 goto error_omap1_platform
;
1239 #ifdef OMAP3_PLATFORM_DRIVER
1240 retval
= platform_driver_register(&OMAP3_PLATFORM_DRIVER
);
1242 goto error_omap3_platform
;
1245 #ifdef OF_PLATFORM_DRIVER
1246 retval
= platform_driver_register(&OF_PLATFORM_DRIVER
);
1248 goto error_of_platform
;
1251 #ifdef SA1111_DRIVER
1252 retval
= sa1111_driver_register(&SA1111_DRIVER
);
1258 retval
= pci_register_driver(&PCI_DRIVER
);
1263 #ifdef SM501_OHCI_DRIVER
1264 retval
= platform_driver_register(&SM501_OHCI_DRIVER
);
1269 #ifdef TMIO_OHCI_DRIVER
1270 retval
= platform_driver_register(&TMIO_OHCI_DRIVER
);
1278 #ifdef TMIO_OHCI_DRIVER
1279 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1282 #ifdef SM501_OHCI_DRIVER
1283 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1287 pci_unregister_driver(&PCI_DRIVER
);
1290 #ifdef SA1111_DRIVER
1291 sa1111_driver_unregister(&SA1111_DRIVER
);
1294 #ifdef OF_PLATFORM_DRIVER
1295 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1298 #ifdef PLATFORM_DRIVER
1299 platform_driver_unregister(&PLATFORM_DRIVER
);
1302 #ifdef OMAP1_PLATFORM_DRIVER
1303 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER
);
1304 error_omap1_platform
:
1306 #ifdef OMAP3_PLATFORM_DRIVER
1307 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER
);
1308 error_omap3_platform
:
1310 #ifdef PS3_SYSTEM_BUS_DRIVER
1311 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1315 debugfs_remove(ohci_debug_root
);
1316 ohci_debug_root
= NULL
;
1320 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1323 module_init(ohci_hcd_mod_init
);
1325 static void __exit
ohci_hcd_mod_exit(void)
1327 #ifdef TMIO_OHCI_DRIVER
1328 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1330 #ifdef SM501_OHCI_DRIVER
1331 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1334 pci_unregister_driver(&PCI_DRIVER
);
1336 #ifdef SA1111_DRIVER
1337 sa1111_driver_unregister(&SA1111_DRIVER
);
1339 #ifdef OF_PLATFORM_DRIVER
1340 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1342 #ifdef PLATFORM_DRIVER
1343 platform_driver_unregister(&PLATFORM_DRIVER
);
1345 #ifdef OMAP3_PLATFORM_DRIVER
1346 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER
);
1348 #ifdef PS3_SYSTEM_BUS_DRIVER
1349 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1352 debugfs_remove(ohci_debug_root
);
1354 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1356 module_exit(ohci_hcd_mod_exit
);
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