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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/nab/target...
[deliverable/linux.git] / drivers / usb / host / ohci-hcd.c
1 /*
2 * Open Host Controller Interface (OHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
8 *
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
13 *
14 *
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
19 *
20 * This file is licenced under the GPL.
21 */
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
42
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
47
48
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
55
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
61
62 #ifdef __hppa__
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
64 #define IR_DISABLE
65 #endif
66
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
69 #define IR_DISABLE
70 #endif
71
72 /*-------------------------------------------------------------------------*/
73
74 static const char hcd_name [] = "ohci_hcd";
75
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
77
78 #include "ohci.h"
79 #include "pci-quirks.h"
80
81 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
82 static void ohci_stop (struct usb_hcd *hcd);
83
84 #include "ohci-hub.c"
85 #include "ohci-dbg.c"
86 #include "ohci-mem.c"
87 #include "ohci-q.c"
88
89
90 /*
91 * On architectures with edge-triggered interrupts we must never return
92 * IRQ_NONE.
93 */
94 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
95 #define IRQ_NOTMINE IRQ_HANDLED
96 #else
97 #define IRQ_NOTMINE IRQ_NONE
98 #endif
99
100
101 /* Some boards misreport power switching/overcurrent */
102 static bool distrust_firmware = 1;
103 module_param (distrust_firmware, bool, 0);
104 MODULE_PARM_DESC (distrust_firmware,
105 "true to distrust firmware power/overcurrent setup");
106
107 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
108 static bool no_handshake = 0;
109 module_param (no_handshake, bool, 0);
110 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
111
112 /*-------------------------------------------------------------------------*/
113
114 /*
115 * queue up an urb for anything except the root hub
116 */
117 static int ohci_urb_enqueue (
118 struct usb_hcd *hcd,
119 struct urb *urb,
120 gfp_t mem_flags
121 ) {
122 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
123 struct ed *ed;
124 urb_priv_t *urb_priv;
125 unsigned int pipe = urb->pipe;
126 int i, size = 0;
127 unsigned long flags;
128 int retval = 0;
129
130 #ifdef OHCI_VERBOSE_DEBUG
131 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
132 #endif
133
134 /* every endpoint has a ed, locate and maybe (re)initialize it */
135 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
136 return -ENOMEM;
137
138 /* for the private part of the URB we need the number of TDs (size) */
139 switch (ed->type) {
140 case PIPE_CONTROL:
141 /* td_submit_urb() doesn't yet handle these */
142 if (urb->transfer_buffer_length > 4096)
143 return -EMSGSIZE;
144
145 /* 1 TD for setup, 1 for ACK, plus ... */
146 size = 2;
147 /* FALLTHROUGH */
148 // case PIPE_INTERRUPT:
149 // case PIPE_BULK:
150 default:
151 /* one TD for every 4096 Bytes (can be up to 8K) */
152 size += urb->transfer_buffer_length / 4096;
153 /* ... and for any remaining bytes ... */
154 if ((urb->transfer_buffer_length % 4096) != 0)
155 size++;
156 /* ... and maybe a zero length packet to wrap it up */
157 if (size == 0)
158 size++;
159 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
160 && (urb->transfer_buffer_length
161 % usb_maxpacket (urb->dev, pipe,
162 usb_pipeout (pipe))) == 0)
163 size++;
164 break;
165 case PIPE_ISOCHRONOUS: /* number of packets from URB */
166 size = urb->number_of_packets;
167 break;
168 }
169
170 /* allocate the private part of the URB */
171 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
172 mem_flags);
173 if (!urb_priv)
174 return -ENOMEM;
175 INIT_LIST_HEAD (&urb_priv->pending);
176 urb_priv->length = size;
177 urb_priv->ed = ed;
178
179 /* allocate the TDs (deferring hash chain updates) */
180 for (i = 0; i < size; i++) {
181 urb_priv->td [i] = td_alloc (ohci, mem_flags);
182 if (!urb_priv->td [i]) {
183 urb_priv->length = i;
184 urb_free_priv (ohci, urb_priv);
185 return -ENOMEM;
186 }
187 }
188
189 spin_lock_irqsave (&ohci->lock, flags);
190
191 /* don't submit to a dead HC */
192 if (!HCD_HW_ACCESSIBLE(hcd)) {
193 retval = -ENODEV;
194 goto fail;
195 }
196 if (ohci->rh_state != OHCI_RH_RUNNING) {
197 retval = -ENODEV;
198 goto fail;
199 }
200 retval = usb_hcd_link_urb_to_ep(hcd, urb);
201 if (retval)
202 goto fail;
203
204 /* schedule the ed if needed */
205 if (ed->state == ED_IDLE) {
206 retval = ed_schedule (ohci, ed);
207 if (retval < 0) {
208 usb_hcd_unlink_urb_from_ep(hcd, urb);
209 goto fail;
210 }
211 if (ed->type == PIPE_ISOCHRONOUS) {
212 u16 frame = ohci_frame_no(ohci);
213
214 /* delay a few frames before the first TD */
215 frame += max_t (u16, 8, ed->interval);
216 frame &= ~(ed->interval - 1);
217 frame |= ed->branch;
218 urb->start_frame = frame;
219 }
220 } else if (ed->type == PIPE_ISOCHRONOUS) {
221 u16 next = ohci_frame_no(ohci) + 1;
222 u16 frame = ed->last_iso + ed->interval;
223
224 /* Behind the scheduling threshold? */
225 if (unlikely(tick_before(frame, next))) {
226
227 /* USB_ISO_ASAP: Round up to the first available slot */
228 if (urb->transfer_flags & URB_ISO_ASAP) {
229 frame += (next - frame + ed->interval - 1) &
230 -ed->interval;
231
232 /*
233 * Not ASAP: Use the next slot in the stream. If
234 * the entire URB falls before the threshold, fail.
235 */
236 } else {
237 if (tick_before(frame + ed->interval *
238 (urb->number_of_packets - 1), next)) {
239 retval = -EXDEV;
240 usb_hcd_unlink_urb_from_ep(hcd, urb);
241 goto fail;
242 }
243
244 /*
245 * Some OHCI hardware doesn't handle late TDs
246 * correctly. After retiring them it proceeds
247 * to the next ED instead of the next TD.
248 * Therefore we have to omit the late TDs
249 * entirely.
250 */
251 urb_priv->td_cnt = DIV_ROUND_UP(
252 (u16) (next - frame),
253 ed->interval);
254 }
255 }
256 urb->start_frame = frame;
257 }
258
259 /* fill the TDs and link them to the ed; and
260 * enable that part of the schedule, if needed
261 * and update count of queued periodic urbs
262 */
263 urb->hcpriv = urb_priv;
264 td_submit_urb (ohci, urb);
265
266 fail:
267 if (retval)
268 urb_free_priv (ohci, urb_priv);
269 spin_unlock_irqrestore (&ohci->lock, flags);
270 return retval;
271 }
272
273 /*
274 * decouple the URB from the HC queues (TDs, urb_priv).
275 * reporting is always done
276 * asynchronously, and we might be dealing with an urb that's
277 * partially transferred, or an ED with other urbs being unlinked.
278 */
279 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
280 {
281 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
282 unsigned long flags;
283 int rc;
284
285 #ifdef OHCI_VERBOSE_DEBUG
286 urb_print(urb, "UNLINK", 1, status);
287 #endif
288
289 spin_lock_irqsave (&ohci->lock, flags);
290 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
291 if (rc) {
292 ; /* Do nothing */
293 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
294 urb_priv_t *urb_priv;
295
296 /* Unless an IRQ completed the unlink while it was being
297 * handed to us, flag it for unlink and giveback, and force
298 * some upcoming INTR_SF to call finish_unlinks()
299 */
300 urb_priv = urb->hcpriv;
301 if (urb_priv) {
302 if (urb_priv->ed->state == ED_OPER)
303 start_ed_unlink (ohci, urb_priv->ed);
304 }
305 } else {
306 /*
307 * with HC dead, we won't respect hc queue pointers
308 * any more ... just clean up every urb's memory.
309 */
310 if (urb->hcpriv)
311 finish_urb(ohci, urb, status);
312 }
313 spin_unlock_irqrestore (&ohci->lock, flags);
314 return rc;
315 }
316
317 /*-------------------------------------------------------------------------*/
318
319 /* frees config/altsetting state for endpoints,
320 * including ED memory, dummy TD, and bulk/intr data toggle
321 */
322
323 static void
324 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
325 {
326 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
327 unsigned long flags;
328 struct ed *ed = ep->hcpriv;
329 unsigned limit = 1000;
330
331 /* ASSERT: any requests/urbs are being unlinked */
332 /* ASSERT: nobody can be submitting urbs for this any more */
333
334 if (!ed)
335 return;
336
337 rescan:
338 spin_lock_irqsave (&ohci->lock, flags);
339
340 if (ohci->rh_state != OHCI_RH_RUNNING) {
341 sanitize:
342 ed->state = ED_IDLE;
343 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
344 ohci->eds_scheduled--;
345 finish_unlinks (ohci, 0);
346 }
347
348 switch (ed->state) {
349 case ED_UNLINK: /* wait for hw to finish? */
350 /* major IRQ delivery trouble loses INTR_SF too... */
351 if (limit-- == 0) {
352 ohci_warn(ohci, "ED unlink timeout\n");
353 if (quirk_zfmicro(ohci)) {
354 ohci_warn(ohci, "Attempting ZF TD recovery\n");
355 ohci->ed_to_check = ed;
356 ohci->zf_delay = 2;
357 }
358 goto sanitize;
359 }
360 spin_unlock_irqrestore (&ohci->lock, flags);
361 schedule_timeout_uninterruptible(1);
362 goto rescan;
363 case ED_IDLE: /* fully unlinked */
364 if (list_empty (&ed->td_list)) {
365 td_free (ohci, ed->dummy);
366 ed_free (ohci, ed);
367 break;
368 }
369 /* else FALL THROUGH */
370 default:
371 /* caller was supposed to have unlinked any requests;
372 * that's not our job. can't recover; must leak ed.
373 */
374 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
375 ed, ep->desc.bEndpointAddress, ed->state,
376 list_empty (&ed->td_list) ? "" : " (has tds)");
377 td_free (ohci, ed->dummy);
378 break;
379 }
380 ep->hcpriv = NULL;
381 spin_unlock_irqrestore (&ohci->lock, flags);
382 }
383
384 static int ohci_get_frame (struct usb_hcd *hcd)
385 {
386 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
387
388 return ohci_frame_no(ohci);
389 }
390
391 static void ohci_usb_reset (struct ohci_hcd *ohci)
392 {
393 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
394 ohci->hc_control &= OHCI_CTRL_RWC;
395 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
396 ohci->rh_state = OHCI_RH_HALTED;
397 }
398
399 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
400 * other cases where the next software may expect clean state from the
401 * "firmware". this is bus-neutral, unlike shutdown() methods.
402 */
403 static void
404 ohci_shutdown (struct usb_hcd *hcd)
405 {
406 struct ohci_hcd *ohci;
407
408 ohci = hcd_to_ohci (hcd);
409 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
410
411 /* Software reset, after which the controller goes into SUSPEND */
412 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
413 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
414 udelay(10);
415
416 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
417 }
418
419 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
420 {
421 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
422 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
423 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
424 && !list_empty(&ed->td_list);
425 }
426
427 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
428 * an interrupt TD but neglects to add it to the donelist. On systems with
429 * this chipset, we need to periodically check the state of the queues to look
430 * for such "lost" TDs.
431 */
432 static void unlink_watchdog_func(unsigned long _ohci)
433 {
434 unsigned long flags;
435 unsigned max;
436 unsigned seen_count = 0;
437 unsigned i;
438 struct ed **seen = NULL;
439 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
440
441 spin_lock_irqsave(&ohci->lock, flags);
442 max = ohci->eds_scheduled;
443 if (!max)
444 goto done;
445
446 if (ohci->ed_to_check)
447 goto out;
448
449 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
450 if (!seen)
451 goto out;
452
453 for (i = 0; i < NUM_INTS; i++) {
454 struct ed *ed = ohci->periodic[i];
455
456 while (ed) {
457 unsigned temp;
458
459 /* scan this branch of the periodic schedule tree */
460 for (temp = 0; temp < seen_count; temp++) {
461 if (seen[temp] == ed) {
462 /* we've checked it and what's after */
463 ed = NULL;
464 break;
465 }
466 }
467 if (!ed)
468 break;
469 seen[seen_count++] = ed;
470 if (!check_ed(ohci, ed)) {
471 ed = ed->ed_next;
472 continue;
473 }
474
475 /* HC's TD list is empty, but HCD sees at least one
476 * TD that's not been sent through the donelist.
477 */
478 ohci->ed_to_check = ed;
479 ohci->zf_delay = 2;
480
481 /* The HC may wait until the next frame to report the
482 * TD as done through the donelist and INTR_WDH. (We
483 * just *assume* it's not a multi-TD interrupt URB;
484 * those could defer the IRQ more than one frame, using
485 * DI...) Check again after the next INTR_SF.
486 */
487 ohci_writel(ohci, OHCI_INTR_SF,
488 &ohci->regs->intrstatus);
489 ohci_writel(ohci, OHCI_INTR_SF,
490 &ohci->regs->intrenable);
491
492 /* flush those writes */
493 (void) ohci_readl(ohci, &ohci->regs->control);
494
495 goto out;
496 }
497 }
498 out:
499 kfree(seen);
500 if (ohci->eds_scheduled)
501 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
502 done:
503 spin_unlock_irqrestore(&ohci->lock, flags);
504 }
505
506 /*-------------------------------------------------------------------------*
507 * HC functions
508 *-------------------------------------------------------------------------*/
509
510 /* init memory, and kick BIOS/SMM off */
511
512 static int ohci_init (struct ohci_hcd *ohci)
513 {
514 int ret;
515 struct usb_hcd *hcd = ohci_to_hcd(ohci);
516
517 if (distrust_firmware)
518 ohci->flags |= OHCI_QUIRK_HUB_POWER;
519
520 ohci->rh_state = OHCI_RH_HALTED;
521 ohci->regs = hcd->regs;
522
523 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
524 * was never needed for most non-PCI systems ... remove the code?
525 */
526
527 #ifndef IR_DISABLE
528 /* SMM owns the HC? not for long! */
529 if (!no_handshake && ohci_readl (ohci,
530 &ohci->regs->control) & OHCI_CTRL_IR) {
531 u32 temp;
532
533 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
534
535 /* this timeout is arbitrary. we make it long, so systems
536 * depending on usb keyboards may be usable even if the
537 * BIOS/SMM code seems pretty broken.
538 */
539 temp = 500; /* arbitrary: five seconds */
540
541 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
542 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
543 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
544 msleep (10);
545 if (--temp == 0) {
546 ohci_err (ohci, "USB HC takeover failed!"
547 " (BIOS/SMM bug)\n");
548 return -EBUSY;
549 }
550 }
551 ohci_usb_reset (ohci);
552 }
553 #endif
554
555 /* Disable HC interrupts */
556 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
557
558 /* flush the writes, and save key bits like RWC */
559 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
560 ohci->hc_control |= OHCI_CTRL_RWC;
561
562 /* Read the number of ports unless overridden */
563 if (ohci->num_ports == 0)
564 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
565
566 if (ohci->hcca)
567 return 0;
568
569 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
570 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
571 if (!ohci->hcca)
572 return -ENOMEM;
573
574 if ((ret = ohci_mem_init (ohci)) < 0)
575 ohci_stop (hcd);
576 else {
577 create_debug_files (ohci);
578 }
579
580 return ret;
581 }
582
583 /*-------------------------------------------------------------------------*/
584
585 /* Start an OHCI controller, set the BUS operational
586 * resets USB and controller
587 * enable interrupts
588 */
589 static int ohci_run (struct ohci_hcd *ohci)
590 {
591 u32 mask, val;
592 int first = ohci->fminterval == 0;
593 struct usb_hcd *hcd = ohci_to_hcd(ohci);
594
595 ohci->rh_state = OHCI_RH_HALTED;
596
597 /* boot firmware should have set this up (5.1.1.3.1) */
598 if (first) {
599
600 val = ohci_readl (ohci, &ohci->regs->fminterval);
601 ohci->fminterval = val & 0x3fff;
602 if (ohci->fminterval != FI)
603 ohci_dbg (ohci, "fminterval delta %d\n",
604 ohci->fminterval - FI);
605 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
606 /* also: power/overcurrent flags in roothub.a */
607 }
608
609 /* Reset USB nearly "by the book". RemoteWakeupConnected has
610 * to be checked in case boot firmware (BIOS/SMM/...) has set up
611 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
612 * If the bus glue detected wakeup capability then it should
613 * already be enabled; if so we'll just enable it again.
614 */
615 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
616 device_set_wakeup_capable(hcd->self.controller, 1);
617
618 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
619 case OHCI_USB_OPER:
620 val = 0;
621 break;
622 case OHCI_USB_SUSPEND:
623 case OHCI_USB_RESUME:
624 ohci->hc_control &= OHCI_CTRL_RWC;
625 ohci->hc_control |= OHCI_USB_RESUME;
626 val = 10 /* msec wait */;
627 break;
628 // case OHCI_USB_RESET:
629 default:
630 ohci->hc_control &= OHCI_CTRL_RWC;
631 ohci->hc_control |= OHCI_USB_RESET;
632 val = 50 /* msec wait */;
633 break;
634 }
635 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
636 // flush the writes
637 (void) ohci_readl (ohci, &ohci->regs->control);
638 msleep(val);
639
640 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
641
642 /* 2msec timelimit here means no irqs/preempt */
643 spin_lock_irq (&ohci->lock);
644
645 retry:
646 /* HC Reset requires max 10 us delay */
647 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
648 val = 30; /* ... allow extra time */
649 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
650 if (--val == 0) {
651 spin_unlock_irq (&ohci->lock);
652 ohci_err (ohci, "USB HC reset timed out!\n");
653 return -1;
654 }
655 udelay (1);
656 }
657
658 /* now we're in the SUSPEND state ... must go OPERATIONAL
659 * within 2msec else HC enters RESUME
660 *
661 * ... but some hardware won't init fmInterval "by the book"
662 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
663 * this if we write fmInterval after we're OPERATIONAL.
664 * Unclear about ALi, ServerWorks, and others ... this could
665 * easily be a longstanding bug in chip init on Linux.
666 */
667 if (ohci->flags & OHCI_QUIRK_INITRESET) {
668 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
669 // flush those writes
670 (void) ohci_readl (ohci, &ohci->regs->control);
671 }
672
673 /* Tell the controller where the control and bulk lists are
674 * The lists are empty now. */
675 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
676 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
677
678 /* a reset clears this */
679 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
680
681 periodic_reinit (ohci);
682
683 /* some OHCI implementations are finicky about how they init.
684 * bogus values here mean not even enumeration could work.
685 */
686 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
687 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
688 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
689 ohci->flags |= OHCI_QUIRK_INITRESET;
690 ohci_dbg (ohci, "enabling initreset quirk\n");
691 goto retry;
692 }
693 spin_unlock_irq (&ohci->lock);
694 ohci_err (ohci, "init err (%08x %04x)\n",
695 ohci_readl (ohci, &ohci->regs->fminterval),
696 ohci_readl (ohci, &ohci->regs->periodicstart));
697 return -EOVERFLOW;
698 }
699
700 /* use rhsc irqs after khubd is fully initialized */
701 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
702 hcd->uses_new_polling = 1;
703
704 /* start controller operations */
705 ohci->hc_control &= OHCI_CTRL_RWC;
706 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
707 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
708 ohci->rh_state = OHCI_RH_RUNNING;
709
710 /* wake on ConnectStatusChange, matching external hubs */
711 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
712
713 /* Choose the interrupts we care about now, others later on demand */
714 mask = OHCI_INTR_INIT;
715 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
716 ohci_writel (ohci, mask, &ohci->regs->intrenable);
717
718 /* handle root hub init quirks ... */
719 val = roothub_a (ohci);
720 val &= ~(RH_A_PSM | RH_A_OCPM);
721 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
722 /* NSC 87560 and maybe others */
723 val |= RH_A_NOCP;
724 val &= ~(RH_A_POTPGT | RH_A_NPS);
725 ohci_writel (ohci, val, &ohci->regs->roothub.a);
726 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
727 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
728 /* hub power always on; required for AMD-756 and some
729 * Mac platforms. ganged overcurrent reporting, if any.
730 */
731 val |= RH_A_NPS;
732 ohci_writel (ohci, val, &ohci->regs->roothub.a);
733 }
734 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
735 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
736 &ohci->regs->roothub.b);
737 // flush those writes
738 (void) ohci_readl (ohci, &ohci->regs->control);
739
740 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
741 spin_unlock_irq (&ohci->lock);
742
743 // POTPGT delay is bits 24-31, in 2 ms units.
744 mdelay ((val >> 23) & 0x1fe);
745
746 if (quirk_zfmicro(ohci)) {
747 /* Create timer to watch for bad queue state on ZF Micro */
748 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
749 (unsigned long) ohci);
750
751 ohci->eds_scheduled = 0;
752 ohci->ed_to_check = NULL;
753 }
754
755 ohci_dump (ohci, 1);
756
757 return 0;
758 }
759
760 /* ohci_setup routine for generic controller initialization */
761
762 int ohci_setup(struct usb_hcd *hcd)
763 {
764 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
765
766 ohci_hcd_init(ohci);
767
768 return ohci_init(ohci);
769 }
770 EXPORT_SYMBOL_GPL(ohci_setup);
771
772 /* ohci_start routine for generic controller start of all OHCI bus glue */
773 static int ohci_start(struct usb_hcd *hcd)
774 {
775 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
776 int ret;
777
778 ret = ohci_run(ohci);
779 if (ret < 0) {
780 ohci_err(ohci, "can't start\n");
781 ohci_stop(hcd);
782 }
783 return ret;
784 }
785
786 /*-------------------------------------------------------------------------*/
787
788 /* an interrupt happens */
789
790 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
791 {
792 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
793 struct ohci_regs __iomem *regs = ohci->regs;
794 int ints;
795
796 /* Read interrupt status (and flush pending writes). We ignore the
797 * optimization of checking the LSB of hcca->done_head; it doesn't
798 * work on all systems (edge triggering for OHCI can be a factor).
799 */
800 ints = ohci_readl(ohci, &regs->intrstatus);
801
802 /* Check for an all 1's result which is a typical consequence
803 * of dead, unclocked, or unplugged (CardBus...) devices
804 */
805 if (ints == ~(u32)0) {
806 ohci->rh_state = OHCI_RH_HALTED;
807 ohci_dbg (ohci, "device removed!\n");
808 usb_hc_died(hcd);
809 return IRQ_HANDLED;
810 }
811
812 /* We only care about interrupts that are enabled */
813 ints &= ohci_readl(ohci, &regs->intrenable);
814
815 /* interrupt for some other device? */
816 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
817 return IRQ_NOTMINE;
818
819 if (ints & OHCI_INTR_UE) {
820 // e.g. due to PCI Master/Target Abort
821 if (quirk_nec(ohci)) {
822 /* Workaround for a silicon bug in some NEC chips used
823 * in Apple's PowerBooks. Adapted from Darwin code.
824 */
825 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
826
827 ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
828
829 schedule_work (&ohci->nec_work);
830 } else {
831 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
832 ohci->rh_state = OHCI_RH_HALTED;
833 usb_hc_died(hcd);
834 }
835
836 ohci_dump (ohci, 1);
837 ohci_usb_reset (ohci);
838 }
839
840 if (ints & OHCI_INTR_RHSC) {
841 ohci_vdbg(ohci, "rhsc\n");
842 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
843 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
844 &regs->intrstatus);
845
846 /* NOTE: Vendors didn't always make the same implementation
847 * choices for RHSC. Many followed the spec; RHSC triggers
848 * on an edge, like setting and maybe clearing a port status
849 * change bit. With others it's level-triggered, active
850 * until khubd clears all the port status change bits. We'll
851 * always disable it here and rely on polling until khubd
852 * re-enables it.
853 */
854 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
855 usb_hcd_poll_rh_status(hcd);
856 }
857
858 /* For connect and disconnect events, we expect the controller
859 * to turn on RHSC along with RD. But for remote wakeup events
860 * this might not happen.
861 */
862 else if (ints & OHCI_INTR_RD) {
863 ohci_vdbg(ohci, "resume detect\n");
864 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
865 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
866 if (ohci->autostop) {
867 spin_lock (&ohci->lock);
868 ohci_rh_resume (ohci);
869 spin_unlock (&ohci->lock);
870 } else
871 usb_hcd_resume_root_hub(hcd);
872 }
873
874 if (ints & OHCI_INTR_WDH) {
875 spin_lock (&ohci->lock);
876 dl_done_list (ohci);
877 spin_unlock (&ohci->lock);
878 }
879
880 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
881 spin_lock(&ohci->lock);
882 if (ohci->ed_to_check) {
883 struct ed *ed = ohci->ed_to_check;
884
885 if (check_ed(ohci, ed)) {
886 /* HC thinks the TD list is empty; HCD knows
887 * at least one TD is outstanding
888 */
889 if (--ohci->zf_delay == 0) {
890 struct td *td = list_entry(
891 ed->td_list.next,
892 struct td, td_list);
893 ohci_warn(ohci,
894 "Reclaiming orphan TD %p\n",
895 td);
896 takeback_td(ohci, td);
897 ohci->ed_to_check = NULL;
898 }
899 } else
900 ohci->ed_to_check = NULL;
901 }
902 spin_unlock(&ohci->lock);
903 }
904
905 /* could track INTR_SO to reduce available PCI/... bandwidth */
906
907 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
908 * when there's still unlinking to be done (next frame).
909 */
910 spin_lock (&ohci->lock);
911 if (ohci->ed_rm_list)
912 finish_unlinks (ohci, ohci_frame_no(ohci));
913 if ((ints & OHCI_INTR_SF) != 0
914 && !ohci->ed_rm_list
915 && !ohci->ed_to_check
916 && ohci->rh_state == OHCI_RH_RUNNING)
917 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
918 spin_unlock (&ohci->lock);
919
920 if (ohci->rh_state == OHCI_RH_RUNNING) {
921 ohci_writel (ohci, ints, &regs->intrstatus);
922 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
923 // flush those writes
924 (void) ohci_readl (ohci, &ohci->regs->control);
925 }
926
927 return IRQ_HANDLED;
928 }
929
930 /*-------------------------------------------------------------------------*/
931
932 static void ohci_stop (struct usb_hcd *hcd)
933 {
934 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
935
936 ohci_dump (ohci, 1);
937
938 if (quirk_nec(ohci))
939 flush_work(&ohci->nec_work);
940
941 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
942 ohci_usb_reset(ohci);
943 free_irq(hcd->irq, hcd);
944 hcd->irq = 0;
945
946 if (quirk_zfmicro(ohci))
947 del_timer(&ohci->unlink_watchdog);
948 if (quirk_amdiso(ohci))
949 usb_amd_dev_put();
950
951 remove_debug_files (ohci);
952 ohci_mem_cleanup (ohci);
953 if (ohci->hcca) {
954 dma_free_coherent (hcd->self.controller,
955 sizeof *ohci->hcca,
956 ohci->hcca, ohci->hcca_dma);
957 ohci->hcca = NULL;
958 ohci->hcca_dma = 0;
959 }
960 }
961
962 /*-------------------------------------------------------------------------*/
963
964 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
965
966 /* must not be called from interrupt context */
967 int ohci_restart(struct ohci_hcd *ohci)
968 {
969 int temp;
970 int i;
971 struct urb_priv *priv;
972
973 ohci_init(ohci);
974 spin_lock_irq(&ohci->lock);
975 ohci->rh_state = OHCI_RH_HALTED;
976
977 /* Recycle any "live" eds/tds (and urbs). */
978 if (!list_empty (&ohci->pending))
979 ohci_dbg(ohci, "abort schedule...\n");
980 list_for_each_entry (priv, &ohci->pending, pending) {
981 struct urb *urb = priv->td[0]->urb;
982 struct ed *ed = priv->ed;
983
984 switch (ed->state) {
985 case ED_OPER:
986 ed->state = ED_UNLINK;
987 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
988 ed_deschedule (ohci, ed);
989
990 ed->ed_next = ohci->ed_rm_list;
991 ed->ed_prev = NULL;
992 ohci->ed_rm_list = ed;
993 /* FALLTHROUGH */
994 case ED_UNLINK:
995 break;
996 default:
997 ohci_dbg(ohci, "bogus ed %p state %d\n",
998 ed, ed->state);
999 }
1000
1001 if (!urb->unlinked)
1002 urb->unlinked = -ESHUTDOWN;
1003 }
1004 finish_unlinks (ohci, 0);
1005 spin_unlock_irq(&ohci->lock);
1006
1007 /* paranoia, in case that didn't work: */
1008
1009 /* empty the interrupt branches */
1010 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1011 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1012
1013 /* no EDs to remove */
1014 ohci->ed_rm_list = NULL;
1015
1016 /* empty control and bulk lists */
1017 ohci->ed_controltail = NULL;
1018 ohci->ed_bulktail = NULL;
1019
1020 if ((temp = ohci_run (ohci)) < 0) {
1021 ohci_err (ohci, "can't restart, %d\n", temp);
1022 return temp;
1023 }
1024 ohci_dbg(ohci, "restart complete\n");
1025 return 0;
1026 }
1027 EXPORT_SYMBOL_GPL(ohci_restart);
1028
1029 #endif
1030
1031 #ifdef CONFIG_PM
1032
1033 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1034 {
1035 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1036 unsigned long flags;
1037
1038 /* Disable irq emission and mark HW unaccessible. Use
1039 * the spinlock to properly synchronize with possible pending
1040 * RH suspend or resume activity.
1041 */
1042 spin_lock_irqsave (&ohci->lock, flags);
1043 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1044 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1045
1046 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1047 spin_unlock_irqrestore (&ohci->lock, flags);
1048
1049 return 0;
1050 }
1051 EXPORT_SYMBOL_GPL(ohci_suspend);
1052
1053
1054 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1055 {
1056 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1057 int port;
1058 bool need_reinit = false;
1059
1060 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1061
1062 /* Make sure resume from hibernation re-enumerates everything */
1063 if (hibernated)
1064 ohci_usb_reset(ohci);
1065
1066 /* See if the controller is already running or has been reset */
1067 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1068 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1069 need_reinit = true;
1070 } else {
1071 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1072 case OHCI_USB_OPER:
1073 case OHCI_USB_RESET:
1074 need_reinit = true;
1075 }
1076 }
1077
1078 /* If needed, reinitialize and suspend the root hub */
1079 if (need_reinit) {
1080 spin_lock_irq(&ohci->lock);
1081 ohci_rh_resume(ohci);
1082 ohci_rh_suspend(ohci, 0);
1083 spin_unlock_irq(&ohci->lock);
1084 }
1085
1086 /* Normally just turn on port power and enable interrupts */
1087 else {
1088 ohci_dbg(ohci, "powerup ports\n");
1089 for (port = 0; port < ohci->num_ports; port++)
1090 ohci_writel(ohci, RH_PS_PPS,
1091 &ohci->regs->roothub.portstatus[port]);
1092
1093 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1094 ohci_readl(ohci, &ohci->regs->intrenable);
1095 msleep(20);
1096 }
1097
1098 usb_hcd_resume_root_hub(hcd);
1099
1100 return 0;
1101 }
1102 EXPORT_SYMBOL_GPL(ohci_resume);
1103
1104 #endif
1105
1106 /*-------------------------------------------------------------------------*/
1107
1108 /*
1109 * Generic structure: This gets copied for platform drivers so that
1110 * individual entries can be overridden as needed.
1111 */
1112
1113 static const struct hc_driver ohci_hc_driver = {
1114 .description = hcd_name,
1115 .product_desc = "OHCI Host Controller",
1116 .hcd_priv_size = sizeof(struct ohci_hcd),
1117
1118 /*
1119 * generic hardware linkage
1120 */
1121 .irq = ohci_irq,
1122 .flags = HCD_MEMORY | HCD_USB11,
1123
1124 /*
1125 * basic lifecycle operations
1126 */
1127 .reset = ohci_setup,
1128 .start = ohci_start,
1129 .stop = ohci_stop,
1130 .shutdown = ohci_shutdown,
1131
1132 /*
1133 * managing i/o requests and associated device resources
1134 */
1135 .urb_enqueue = ohci_urb_enqueue,
1136 .urb_dequeue = ohci_urb_dequeue,
1137 .endpoint_disable = ohci_endpoint_disable,
1138
1139 /*
1140 * scheduling support
1141 */
1142 .get_frame_number = ohci_get_frame,
1143
1144 /*
1145 * root hub support
1146 */
1147 .hub_status_data = ohci_hub_status_data,
1148 .hub_control = ohci_hub_control,
1149 #ifdef CONFIG_PM
1150 .bus_suspend = ohci_bus_suspend,
1151 .bus_resume = ohci_bus_resume,
1152 #endif
1153 .start_port_reset = ohci_start_port_reset,
1154 };
1155
1156 void ohci_init_driver(struct hc_driver *drv,
1157 const struct ohci_driver_overrides *over)
1158 {
1159 /* Copy the generic table to drv and then apply the overrides */
1160 *drv = ohci_hc_driver;
1161
1162 drv->product_desc = over->product_desc;
1163 drv->hcd_priv_size += over->extra_priv_size;
1164 if (over->reset)
1165 drv->reset = over->reset;
1166 }
1167 EXPORT_SYMBOL_GPL(ohci_init_driver);
1168
1169 /*-------------------------------------------------------------------------*/
1170
1171 MODULE_AUTHOR (DRIVER_AUTHOR);
1172 MODULE_DESCRIPTION(DRIVER_DESC);
1173 MODULE_LICENSE ("GPL");
1174
1175 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1176 #include "ohci-sa1111.c"
1177 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1178 #endif
1179
1180 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1181 #include "ohci-s3c2410.c"
1182 #define S3C2410_PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1183 #endif
1184
1185 #ifdef CONFIG_USB_OHCI_EXYNOS
1186 #include "ohci-exynos.c"
1187 #define EXYNOS_PLATFORM_DRIVER exynos_ohci_driver
1188 #endif
1189
1190 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1191 #include "ohci-omap.c"
1192 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1193 #endif
1194
1195 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1196 #include "ohci-omap3.c"
1197 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1198 #endif
1199
1200 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1201 #include "ohci-pxa27x.c"
1202 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1203 #endif
1204
1205 #ifdef CONFIG_ARCH_EP93XX
1206 #include "ohci-ep93xx.c"
1207 #define EP93XX_PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1208 #endif
1209
1210 #ifdef CONFIG_ARCH_AT91
1211 #include "ohci-at91.c"
1212 #define AT91_PLATFORM_DRIVER ohci_hcd_at91_driver
1213 #endif
1214
1215 #ifdef CONFIG_ARCH_LPC32XX
1216 #include "ohci-nxp.c"
1217 #define NXP_PLATFORM_DRIVER usb_hcd_nxp_driver
1218 #endif
1219
1220 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1221 #include "ohci-da8xx.c"
1222 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1223 #endif
1224
1225 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1226 #include "ohci-ppc-of.c"
1227 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1228 #endif
1229
1230 #ifdef CONFIG_PLAT_SPEAR
1231 #include "ohci-spear.c"
1232 #define SPEAR_PLATFORM_DRIVER spear_ohci_hcd_driver
1233 #endif
1234
1235 #ifdef CONFIG_PPC_PS3
1236 #include "ohci-ps3.c"
1237 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1238 #endif
1239
1240 #ifdef CONFIG_MFD_SM501
1241 #include "ohci-sm501.c"
1242 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1243 #endif
1244
1245 #ifdef CONFIG_MFD_TC6393XB
1246 #include "ohci-tmio.c"
1247 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1248 #endif
1249
1250 #ifdef CONFIG_MACH_JZ4740
1251 #include "ohci-jz4740.c"
1252 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1253 #endif
1254
1255 #ifdef CONFIG_USB_OCTEON_OHCI
1256 #include "ohci-octeon.c"
1257 #define PLATFORM_DRIVER ohci_octeon_driver
1258 #endif
1259
1260 #ifdef CONFIG_TILE_USB
1261 #include "ohci-tilegx.c"
1262 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1263 #endif
1264
1265 static int __init ohci_hcd_mod_init(void)
1266 {
1267 int retval = 0;
1268
1269 if (usb_disabled())
1270 return -ENODEV;
1271
1272 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1273 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1274 sizeof (struct ed), sizeof (struct td));
1275 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1276
1277 #ifdef DEBUG
1278 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1279 if (!ohci_debug_root) {
1280 retval = -ENOENT;
1281 goto error_debug;
1282 }
1283 #endif
1284
1285 #ifdef PS3_SYSTEM_BUS_DRIVER
1286 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1287 if (retval < 0)
1288 goto error_ps3;
1289 #endif
1290
1291 #ifdef PLATFORM_DRIVER
1292 retval = platform_driver_register(&PLATFORM_DRIVER);
1293 if (retval < 0)
1294 goto error_platform;
1295 #endif
1296
1297 #ifdef OMAP1_PLATFORM_DRIVER
1298 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1299 if (retval < 0)
1300 goto error_omap1_platform;
1301 #endif
1302
1303 #ifdef OMAP3_PLATFORM_DRIVER
1304 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1305 if (retval < 0)
1306 goto error_omap3_platform;
1307 #endif
1308
1309 #ifdef OF_PLATFORM_DRIVER
1310 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1311 if (retval < 0)
1312 goto error_of_platform;
1313 #endif
1314
1315 #ifdef SA1111_DRIVER
1316 retval = sa1111_driver_register(&SA1111_DRIVER);
1317 if (retval < 0)
1318 goto error_sa1111;
1319 #endif
1320
1321 #ifdef SM501_OHCI_DRIVER
1322 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1323 if (retval < 0)
1324 goto error_sm501;
1325 #endif
1326
1327 #ifdef TMIO_OHCI_DRIVER
1328 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1329 if (retval < 0)
1330 goto error_tmio;
1331 #endif
1332
1333 #ifdef S3C2410_PLATFORM_DRIVER
1334 retval = platform_driver_register(&S3C2410_PLATFORM_DRIVER);
1335 if (retval < 0)
1336 goto error_s3c2410;
1337 #endif
1338
1339 #ifdef EXYNOS_PLATFORM_DRIVER
1340 retval = platform_driver_register(&EXYNOS_PLATFORM_DRIVER);
1341 if (retval < 0)
1342 goto error_exynos;
1343 #endif
1344
1345 #ifdef EP93XX_PLATFORM_DRIVER
1346 retval = platform_driver_register(&EP93XX_PLATFORM_DRIVER);
1347 if (retval < 0)
1348 goto error_ep93xx;
1349 #endif
1350
1351 #ifdef AT91_PLATFORM_DRIVER
1352 retval = platform_driver_register(&AT91_PLATFORM_DRIVER);
1353 if (retval < 0)
1354 goto error_at91;
1355 #endif
1356
1357 #ifdef NXP_PLATFORM_DRIVER
1358 retval = platform_driver_register(&NXP_PLATFORM_DRIVER);
1359 if (retval < 0)
1360 goto error_nxp;
1361 #endif
1362
1363 #ifdef DAVINCI_PLATFORM_DRIVER
1364 retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1365 if (retval < 0)
1366 goto error_davinci;
1367 #endif
1368
1369 #ifdef SPEAR_PLATFORM_DRIVER
1370 retval = platform_driver_register(&SPEAR_PLATFORM_DRIVER);
1371 if (retval < 0)
1372 goto error_spear;
1373 #endif
1374
1375 return retval;
1376
1377 /* Error path */
1378 #ifdef SPEAR_PLATFORM_DRIVER
1379 platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1380 error_spear:
1381 #endif
1382 #ifdef DAVINCI_PLATFORM_DRIVER
1383 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1384 error_davinci:
1385 #endif
1386 #ifdef NXP_PLATFORM_DRIVER
1387 platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1388 error_nxp:
1389 #endif
1390 #ifdef AT91_PLATFORM_DRIVER
1391 platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1392 error_at91:
1393 #endif
1394 #ifdef EP93XX_PLATFORM_DRIVER
1395 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1396 error_ep93xx:
1397 #endif
1398 #ifdef EXYNOS_PLATFORM_DRIVER
1399 platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1400 error_exynos:
1401 #endif
1402 #ifdef S3C2410_PLATFORM_DRIVER
1403 platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1404 error_s3c2410:
1405 #endif
1406 #ifdef TMIO_OHCI_DRIVER
1407 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1408 error_tmio:
1409 #endif
1410 #ifdef SM501_OHCI_DRIVER
1411 platform_driver_unregister(&SM501_OHCI_DRIVER);
1412 error_sm501:
1413 #endif
1414 #ifdef SA1111_DRIVER
1415 sa1111_driver_unregister(&SA1111_DRIVER);
1416 error_sa1111:
1417 #endif
1418 #ifdef OF_PLATFORM_DRIVER
1419 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1420 error_of_platform:
1421 #endif
1422 #ifdef OMAP3_PLATFORM_DRIVER
1423 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1424 error_omap3_platform:
1425 #endif
1426 #ifdef OMAP1_PLATFORM_DRIVER
1427 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1428 error_omap1_platform:
1429 #endif
1430 #ifdef PLATFORM_DRIVER
1431 platform_driver_unregister(&PLATFORM_DRIVER);
1432 error_platform:
1433 #endif
1434 #ifdef PS3_SYSTEM_BUS_DRIVER
1435 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1436 error_ps3:
1437 #endif
1438 #ifdef DEBUG
1439 debugfs_remove(ohci_debug_root);
1440 ohci_debug_root = NULL;
1441 error_debug:
1442 #endif
1443
1444 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1445 return retval;
1446 }
1447 module_init(ohci_hcd_mod_init);
1448
1449 static void __exit ohci_hcd_mod_exit(void)
1450 {
1451 #ifdef SPEAR_PLATFORM_DRIVER
1452 platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1453 #endif
1454 #ifdef DAVINCI_PLATFORM_DRIVER
1455 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1456 #endif
1457 #ifdef NXP_PLATFORM_DRIVER
1458 platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1459 #endif
1460 #ifdef AT91_PLATFORM_DRIVER
1461 platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1462 #endif
1463 #ifdef EP93XX_PLATFORM_DRIVER
1464 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1465 #endif
1466 #ifdef EXYNOS_PLATFORM_DRIVER
1467 platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1468 #endif
1469 #ifdef S3C2410_PLATFORM_DRIVER
1470 platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1471 #endif
1472 #ifdef TMIO_OHCI_DRIVER
1473 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1474 #endif
1475 #ifdef SM501_OHCI_DRIVER
1476 platform_driver_unregister(&SM501_OHCI_DRIVER);
1477 #endif
1478 #ifdef SA1111_DRIVER
1479 sa1111_driver_unregister(&SA1111_DRIVER);
1480 #endif
1481 #ifdef OF_PLATFORM_DRIVER
1482 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1483 #endif
1484 #ifdef OMAP3_PLATFORM_DRIVER
1485 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1486 #endif
1487 #ifdef OMAP1_PLATFORM_DRIVER
1488 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1489 #endif
1490 #ifdef PLATFORM_DRIVER
1491 platform_driver_unregister(&PLATFORM_DRIVER);
1492 #endif
1493 #ifdef PS3_SYSTEM_BUS_DRIVER
1494 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1495 #endif
1496 #ifdef DEBUG
1497 debugfs_remove(ohci_debug_root);
1498 #endif
1499 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1500 }
1501 module_exit(ohci_hcd_mod_exit);
1502
Linux kernel - Deliverables
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