2 * Open Host Controller Interface (OHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
20 * This file is licenced under the GPL.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52 /*-------------------------------------------------------------------------*/
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
72 /*-------------------------------------------------------------------------*/
74 static const char hcd_name
[] = "ohci_hcd";
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
79 #include "pci-quirks.h"
81 static void ohci_dump (struct ohci_hcd
*ohci
, int verbose
);
82 static int ohci_init (struct ohci_hcd
*ohci
);
83 static void ohci_stop (struct usb_hcd
*hcd
);
85 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
86 static int ohci_restart (struct ohci_hcd
*ohci
);
90 static void sb800_prefetch(struct ohci_hcd
*ohci
, int on
);
92 static inline void sb800_prefetch(struct ohci_hcd
*ohci
, int on
)
100 #include "ohci-dbg.c"
101 #include "ohci-mem.c"
106 * On architectures with edge-triggered interrupts we must never return
109 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
110 #define IRQ_NOTMINE IRQ_HANDLED
112 #define IRQ_NOTMINE IRQ_NONE
116 /* Some boards misreport power switching/overcurrent */
117 static bool distrust_firmware
= 1;
118 module_param (distrust_firmware
, bool, 0);
119 MODULE_PARM_DESC (distrust_firmware
,
120 "true to distrust firmware power/overcurrent setup");
122 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
123 static bool no_handshake
= 0;
124 module_param (no_handshake
, bool, 0);
125 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
127 /*-------------------------------------------------------------------------*/
130 * queue up an urb for anything except the root hub
132 static int ohci_urb_enqueue (
137 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
139 urb_priv_t
*urb_priv
;
140 unsigned int pipe
= urb
->pipe
;
145 #ifdef OHCI_VERBOSE_DEBUG
146 urb_print(urb
, "SUB", usb_pipein(pipe
), -EINPROGRESS
);
149 /* every endpoint has a ed, locate and maybe (re)initialize it */
150 if (! (ed
= ed_get (ohci
, urb
->ep
, urb
->dev
, pipe
, urb
->interval
)))
153 /* for the private part of the URB we need the number of TDs (size) */
156 /* td_submit_urb() doesn't yet handle these */
157 if (urb
->transfer_buffer_length
> 4096)
160 /* 1 TD for setup, 1 for ACK, plus ... */
163 // case PIPE_INTERRUPT:
166 /* one TD for every 4096 Bytes (can be up to 8K) */
167 size
+= urb
->transfer_buffer_length
/ 4096;
168 /* ... and for any remaining bytes ... */
169 if ((urb
->transfer_buffer_length
% 4096) != 0)
171 /* ... and maybe a zero length packet to wrap it up */
174 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
175 && (urb
->transfer_buffer_length
176 % usb_maxpacket (urb
->dev
, pipe
,
177 usb_pipeout (pipe
))) == 0)
180 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
181 size
= urb
->number_of_packets
;
185 /* allocate the private part of the URB */
186 urb_priv
= kzalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
190 INIT_LIST_HEAD (&urb_priv
->pending
);
191 urb_priv
->length
= size
;
194 /* allocate the TDs (deferring hash chain updates) */
195 for (i
= 0; i
< size
; i
++) {
196 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
197 if (!urb_priv
->td
[i
]) {
198 urb_priv
->length
= i
;
199 urb_free_priv (ohci
, urb_priv
);
204 spin_lock_irqsave (&ohci
->lock
, flags
);
206 /* don't submit to a dead HC */
207 if (!HCD_HW_ACCESSIBLE(hcd
)) {
211 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
215 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
219 /* schedule the ed if needed */
220 if (ed
->state
== ED_IDLE
) {
221 retval
= ed_schedule (ohci
, ed
);
223 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
226 if (ed
->type
== PIPE_ISOCHRONOUS
) {
227 u16 frame
= ohci_frame_no(ohci
);
229 /* delay a few frames before the first TD */
230 frame
+= max_t (u16
, 8, ed
->interval
);
231 frame
&= ~(ed
->interval
- 1);
233 urb
->start_frame
= frame
;
235 /* yes, only URB_ISO_ASAP is supported, and
236 * urb->start_frame is never used as input.
239 } else if (ed
->type
== PIPE_ISOCHRONOUS
)
240 urb
->start_frame
= ed
->last_iso
+ ed
->interval
;
242 /* fill the TDs and link them to the ed; and
243 * enable that part of the schedule, if needed
244 * and update count of queued periodic urbs
246 urb
->hcpriv
= urb_priv
;
247 td_submit_urb (ohci
, urb
);
251 urb_free_priv (ohci
, urb_priv
);
252 spin_unlock_irqrestore (&ohci
->lock
, flags
);
257 * decouple the URB from the HC queues (TDs, urb_priv).
258 * reporting is always done
259 * asynchronously, and we might be dealing with an urb that's
260 * partially transferred, or an ED with other urbs being unlinked.
262 static int ohci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
264 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
268 #ifdef OHCI_VERBOSE_DEBUG
269 urb_print(urb
, "UNLINK", 1, status
);
272 spin_lock_irqsave (&ohci
->lock
, flags
);
273 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
276 } else if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
277 urb_priv_t
*urb_priv
;
279 /* Unless an IRQ completed the unlink while it was being
280 * handed to us, flag it for unlink and giveback, and force
281 * some upcoming INTR_SF to call finish_unlinks()
283 urb_priv
= urb
->hcpriv
;
285 if (urb_priv
->ed
->state
== ED_OPER
)
286 start_ed_unlink (ohci
, urb_priv
->ed
);
290 * with HC dead, we won't respect hc queue pointers
291 * any more ... just clean up every urb's memory.
294 finish_urb(ohci
, urb
, status
);
296 spin_unlock_irqrestore (&ohci
->lock
, flags
);
300 /*-------------------------------------------------------------------------*/
302 /* frees config/altsetting state for endpoints,
303 * including ED memory, dummy TD, and bulk/intr data toggle
307 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
309 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
311 struct ed
*ed
= ep
->hcpriv
;
312 unsigned limit
= 1000;
314 /* ASSERT: any requests/urbs are being unlinked */
315 /* ASSERT: nobody can be submitting urbs for this any more */
321 spin_lock_irqsave (&ohci
->lock
, flags
);
323 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
326 if (quirk_zfmicro(ohci
) && ed
->type
== PIPE_INTERRUPT
)
327 ohci
->eds_scheduled
--;
328 finish_unlinks (ohci
, 0);
332 case ED_UNLINK
: /* wait for hw to finish? */
333 /* major IRQ delivery trouble loses INTR_SF too... */
335 ohci_warn(ohci
, "ED unlink timeout\n");
336 if (quirk_zfmicro(ohci
)) {
337 ohci_warn(ohci
, "Attempting ZF TD recovery\n");
338 ohci
->ed_to_check
= ed
;
343 spin_unlock_irqrestore (&ohci
->lock
, flags
);
344 schedule_timeout_uninterruptible(1);
346 case ED_IDLE
: /* fully unlinked */
347 if (list_empty (&ed
->td_list
)) {
348 td_free (ohci
, ed
->dummy
);
352 /* else FALL THROUGH */
354 /* caller was supposed to have unlinked any requests;
355 * that's not our job. can't recover; must leak ed.
357 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
358 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
359 list_empty (&ed
->td_list
) ? "" : " (has tds)");
360 td_free (ohci
, ed
->dummy
);
364 spin_unlock_irqrestore (&ohci
->lock
, flags
);
367 static int ohci_get_frame (struct usb_hcd
*hcd
)
369 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
371 return ohci_frame_no(ohci
);
374 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
376 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
377 ohci
->hc_control
&= OHCI_CTRL_RWC
;
378 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
379 ohci
->rh_state
= OHCI_RH_HALTED
;
382 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
383 * other cases where the next software may expect clean state from the
384 * "firmware". this is bus-neutral, unlike shutdown() methods.
387 ohci_shutdown (struct usb_hcd
*hcd
)
389 struct ohci_hcd
*ohci
;
391 ohci
= hcd_to_ohci (hcd
);
392 ohci_writel(ohci
, (u32
) ~0, &ohci
->regs
->intrdisable
);
394 /* Software reset, after which the controller goes into SUSPEND */
395 ohci_writel(ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
396 ohci_readl(ohci
, &ohci
->regs
->cmdstatus
); /* flush the writes */
399 ohci_writel(ohci
, ohci
->fminterval
, &ohci
->regs
->fminterval
);
402 static int check_ed(struct ohci_hcd
*ohci
, struct ed
*ed
)
404 return (hc32_to_cpu(ohci
, ed
->hwINFO
) & ED_IN
) != 0
405 && (hc32_to_cpu(ohci
, ed
->hwHeadP
) & TD_MASK
)
406 == (hc32_to_cpu(ohci
, ed
->hwTailP
) & TD_MASK
)
407 && !list_empty(&ed
->td_list
);
410 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
411 * an interrupt TD but neglects to add it to the donelist. On systems with
412 * this chipset, we need to periodically check the state of the queues to look
413 * for such "lost" TDs.
415 static void unlink_watchdog_func(unsigned long _ohci
)
419 unsigned seen_count
= 0;
421 struct ed
**seen
= NULL
;
422 struct ohci_hcd
*ohci
= (struct ohci_hcd
*) _ohci
;
424 spin_lock_irqsave(&ohci
->lock
, flags
);
425 max
= ohci
->eds_scheduled
;
429 if (ohci
->ed_to_check
)
432 seen
= kcalloc(max
, sizeof *seen
, GFP_ATOMIC
);
436 for (i
= 0; i
< NUM_INTS
; i
++) {
437 struct ed
*ed
= ohci
->periodic
[i
];
442 /* scan this branch of the periodic schedule tree */
443 for (temp
= 0; temp
< seen_count
; temp
++) {
444 if (seen
[temp
] == ed
) {
445 /* we've checked it and what's after */
452 seen
[seen_count
++] = ed
;
453 if (!check_ed(ohci
, ed
)) {
458 /* HC's TD list is empty, but HCD sees at least one
459 * TD that's not been sent through the donelist.
461 ohci
->ed_to_check
= ed
;
464 /* The HC may wait until the next frame to report the
465 * TD as done through the donelist and INTR_WDH. (We
466 * just *assume* it's not a multi-TD interrupt URB;
467 * those could defer the IRQ more than one frame, using
468 * DI...) Check again after the next INTR_SF.
470 ohci_writel(ohci
, OHCI_INTR_SF
,
471 &ohci
->regs
->intrstatus
);
472 ohci_writel(ohci
, OHCI_INTR_SF
,
473 &ohci
->regs
->intrenable
);
475 /* flush those writes */
476 (void) ohci_readl(ohci
, &ohci
->regs
->control
);
483 if (ohci
->eds_scheduled
)
484 mod_timer(&ohci
->unlink_watchdog
, round_jiffies(jiffies
+ HZ
));
486 spin_unlock_irqrestore(&ohci
->lock
, flags
);
489 /*-------------------------------------------------------------------------*
491 *-------------------------------------------------------------------------*/
493 /* init memory, and kick BIOS/SMM off */
495 static int ohci_init (struct ohci_hcd
*ohci
)
498 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
500 if (distrust_firmware
)
501 ohci
->flags
|= OHCI_QUIRK_HUB_POWER
;
503 ohci
->rh_state
= OHCI_RH_HALTED
;
504 ohci
->regs
= hcd
->regs
;
506 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
507 * was never needed for most non-PCI systems ... remove the code?
511 /* SMM owns the HC? not for long! */
512 if (!no_handshake
&& ohci_readl (ohci
,
513 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
516 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
518 /* this timeout is arbitrary. we make it long, so systems
519 * depending on usb keyboards may be usable even if the
520 * BIOS/SMM code seems pretty broken.
522 temp
= 500; /* arbitrary: five seconds */
524 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
525 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
526 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
529 ohci_err (ohci
, "USB HC takeover failed!"
530 " (BIOS/SMM bug)\n");
534 ohci_usb_reset (ohci
);
538 /* Disable HC interrupts */
539 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
541 /* flush the writes, and save key bits like RWC */
542 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
543 ohci
->hc_control
|= OHCI_CTRL_RWC
;
545 /* Read the number of ports unless overridden */
546 if (ohci
->num_ports
== 0)
547 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
552 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
553 sizeof *ohci
->hcca
, &ohci
->hcca_dma
, 0);
557 if ((ret
= ohci_mem_init (ohci
)) < 0)
560 create_debug_files (ohci
);
566 /*-------------------------------------------------------------------------*/
568 /* Start an OHCI controller, set the BUS operational
569 * resets USB and controller
572 static int ohci_run (struct ohci_hcd
*ohci
)
575 int first
= ohci
->fminterval
== 0;
576 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
578 ohci
->rh_state
= OHCI_RH_HALTED
;
580 /* boot firmware should have set this up (5.1.1.3.1) */
583 val
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
584 ohci
->fminterval
= val
& 0x3fff;
585 if (ohci
->fminterval
!= FI
)
586 ohci_dbg (ohci
, "fminterval delta %d\n",
587 ohci
->fminterval
- FI
);
588 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
589 /* also: power/overcurrent flags in roothub.a */
592 /* Reset USB nearly "by the book". RemoteWakeupConnected has
593 * to be checked in case boot firmware (BIOS/SMM/...) has set up
594 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
595 * If the bus glue detected wakeup capability then it should
596 * already be enabled; if so we'll just enable it again.
598 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0)
599 device_set_wakeup_capable(hcd
->self
.controller
, 1);
601 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
605 case OHCI_USB_SUSPEND
:
606 case OHCI_USB_RESUME
:
607 ohci
->hc_control
&= OHCI_CTRL_RWC
;
608 ohci
->hc_control
|= OHCI_USB_RESUME
;
609 val
= 10 /* msec wait */;
611 // case OHCI_USB_RESET:
613 ohci
->hc_control
&= OHCI_CTRL_RWC
;
614 ohci
->hc_control
|= OHCI_USB_RESET
;
615 val
= 50 /* msec wait */;
618 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
620 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
623 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
625 /* 2msec timelimit here means no irqs/preempt */
626 spin_lock_irq (&ohci
->lock
);
629 /* HC Reset requires max 10 us delay */
630 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
631 val
= 30; /* ... allow extra time */
632 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
634 spin_unlock_irq (&ohci
->lock
);
635 ohci_err (ohci
, "USB HC reset timed out!\n");
641 /* now we're in the SUSPEND state ... must go OPERATIONAL
642 * within 2msec else HC enters RESUME
644 * ... but some hardware won't init fmInterval "by the book"
645 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
646 * this if we write fmInterval after we're OPERATIONAL.
647 * Unclear about ALi, ServerWorks, and others ... this could
648 * easily be a longstanding bug in chip init on Linux.
650 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
651 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
652 // flush those writes
653 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
656 /* Tell the controller where the control and bulk lists are
657 * The lists are empty now. */
658 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
659 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
661 /* a reset clears this */
662 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
664 periodic_reinit (ohci
);
666 /* some OHCI implementations are finicky about how they init.
667 * bogus values here mean not even enumeration could work.
669 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
670 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
671 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
672 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
673 ohci_dbg (ohci
, "enabling initreset quirk\n");
676 spin_unlock_irq (&ohci
->lock
);
677 ohci_err (ohci
, "init err (%08x %04x)\n",
678 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
679 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
683 /* use rhsc irqs after khubd is fully initialized */
684 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
685 hcd
->uses_new_polling
= 1;
687 /* start controller operations */
688 ohci
->hc_control
&= OHCI_CTRL_RWC
;
689 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
690 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
691 ohci
->rh_state
= OHCI_RH_RUNNING
;
693 /* wake on ConnectStatusChange, matching external hubs */
694 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
696 /* Choose the interrupts we care about now, others later on demand */
697 mask
= OHCI_INTR_INIT
;
698 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
699 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
701 /* handle root hub init quirks ... */
702 val
= roothub_a (ohci
);
703 val
&= ~(RH_A_PSM
| RH_A_OCPM
);
704 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
705 /* NSC 87560 and maybe others */
707 val
&= ~(RH_A_POTPGT
| RH_A_NPS
);
708 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
709 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) ||
710 (ohci
->flags
& OHCI_QUIRK_HUB_POWER
)) {
711 /* hub power always on; required for AMD-756 and some
712 * Mac platforms. ganged overcurrent reporting, if any.
715 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
717 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
718 ohci_writel (ohci
, (val
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
719 &ohci
->regs
->roothub
.b
);
720 // flush those writes
721 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
723 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
724 spin_unlock_irq (&ohci
->lock
);
726 // POTPGT delay is bits 24-31, in 2 ms units.
727 mdelay ((val
>> 23) & 0x1fe);
729 if (quirk_zfmicro(ohci
)) {
730 /* Create timer to watch for bad queue state on ZF Micro */
731 setup_timer(&ohci
->unlink_watchdog
, unlink_watchdog_func
,
732 (unsigned long) ohci
);
734 ohci
->eds_scheduled
= 0;
735 ohci
->ed_to_check
= NULL
;
743 /*-------------------------------------------------------------------------*/
745 /* an interrupt happens */
747 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
749 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
750 struct ohci_regs __iomem
*regs
= ohci
->regs
;
753 /* Read interrupt status (and flush pending writes). We ignore the
754 * optimization of checking the LSB of hcca->done_head; it doesn't
755 * work on all systems (edge triggering for OHCI can be a factor).
757 ints
= ohci_readl(ohci
, ®s
->intrstatus
);
759 /* Check for an all 1's result which is a typical consequence
760 * of dead, unclocked, or unplugged (CardBus...) devices
762 if (ints
== ~(u32
)0) {
763 ohci
->rh_state
= OHCI_RH_HALTED
;
764 ohci_dbg (ohci
, "device removed!\n");
769 /* We only care about interrupts that are enabled */
770 ints
&= ohci_readl(ohci
, ®s
->intrenable
);
772 /* interrupt for some other device? */
773 if (ints
== 0 || unlikely(ohci
->rh_state
== OHCI_RH_HALTED
))
776 if (ints
& OHCI_INTR_UE
) {
777 // e.g. due to PCI Master/Target Abort
778 if (quirk_nec(ohci
)) {
779 /* Workaround for a silicon bug in some NEC chips used
780 * in Apple's PowerBooks. Adapted from Darwin code.
782 ohci_err (ohci
, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
784 ohci_writel (ohci
, OHCI_INTR_UE
, ®s
->intrdisable
);
786 schedule_work (&ohci
->nec_work
);
788 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
789 ohci
->rh_state
= OHCI_RH_HALTED
;
794 ohci_usb_reset (ohci
);
797 if (ints
& OHCI_INTR_RHSC
) {
798 ohci_vdbg(ohci
, "rhsc\n");
799 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
800 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
803 /* NOTE: Vendors didn't always make the same implementation
804 * choices for RHSC. Many followed the spec; RHSC triggers
805 * on an edge, like setting and maybe clearing a port status
806 * change bit. With others it's level-triggered, active
807 * until khubd clears all the port status change bits. We'll
808 * always disable it here and rely on polling until khubd
811 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
812 usb_hcd_poll_rh_status(hcd
);
815 /* For connect and disconnect events, we expect the controller
816 * to turn on RHSC along with RD. But for remote wakeup events
817 * this might not happen.
819 else if (ints
& OHCI_INTR_RD
) {
820 ohci_vdbg(ohci
, "resume detect\n");
821 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
822 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
823 if (ohci
->autostop
) {
824 spin_lock (&ohci
->lock
);
825 ohci_rh_resume (ohci
);
826 spin_unlock (&ohci
->lock
);
828 usb_hcd_resume_root_hub(hcd
);
831 if (ints
& OHCI_INTR_WDH
) {
832 spin_lock (&ohci
->lock
);
834 spin_unlock (&ohci
->lock
);
837 if (quirk_zfmicro(ohci
) && (ints
& OHCI_INTR_SF
)) {
838 spin_lock(&ohci
->lock
);
839 if (ohci
->ed_to_check
) {
840 struct ed
*ed
= ohci
->ed_to_check
;
842 if (check_ed(ohci
, ed
)) {
843 /* HC thinks the TD list is empty; HCD knows
844 * at least one TD is outstanding
846 if (--ohci
->zf_delay
== 0) {
847 struct td
*td
= list_entry(
851 "Reclaiming orphan TD %p\n",
853 takeback_td(ohci
, td
);
854 ohci
->ed_to_check
= NULL
;
857 ohci
->ed_to_check
= NULL
;
859 spin_unlock(&ohci
->lock
);
862 /* could track INTR_SO to reduce available PCI/... bandwidth */
864 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
865 * when there's still unlinking to be done (next frame).
867 spin_lock (&ohci
->lock
);
868 if (ohci
->ed_rm_list
)
869 finish_unlinks (ohci
, ohci_frame_no(ohci
));
870 if ((ints
& OHCI_INTR_SF
) != 0
872 && !ohci
->ed_to_check
873 && ohci
->rh_state
== OHCI_RH_RUNNING
)
874 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
875 spin_unlock (&ohci
->lock
);
877 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
878 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
879 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
880 // flush those writes
881 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
887 /*-------------------------------------------------------------------------*/
889 static void ohci_stop (struct usb_hcd
*hcd
)
891 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
896 flush_work_sync(&ohci
->nec_work
);
898 ohci_usb_reset (ohci
);
899 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
900 free_irq(hcd
->irq
, hcd
);
903 if (quirk_zfmicro(ohci
))
904 del_timer(&ohci
->unlink_watchdog
);
905 if (quirk_amdiso(ohci
))
908 remove_debug_files (ohci
);
909 ohci_mem_cleanup (ohci
);
911 dma_free_coherent (hcd
->self
.controller
,
913 ohci
->hcca
, ohci
->hcca_dma
);
919 /*-------------------------------------------------------------------------*/
921 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
923 /* must not be called from interrupt context */
924 static int ohci_restart (struct ohci_hcd
*ohci
)
928 struct urb_priv
*priv
;
930 spin_lock_irq(&ohci
->lock
);
931 ohci
->rh_state
= OHCI_RH_HALTED
;
933 /* Recycle any "live" eds/tds (and urbs). */
934 if (!list_empty (&ohci
->pending
))
935 ohci_dbg(ohci
, "abort schedule...\n");
936 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
937 struct urb
*urb
= priv
->td
[0]->urb
;
938 struct ed
*ed
= priv
->ed
;
942 ed
->state
= ED_UNLINK
;
943 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
944 ed_deschedule (ohci
, ed
);
946 ed
->ed_next
= ohci
->ed_rm_list
;
948 ohci
->ed_rm_list
= ed
;
953 ohci_dbg(ohci
, "bogus ed %p state %d\n",
958 urb
->unlinked
= -ESHUTDOWN
;
960 finish_unlinks (ohci
, 0);
961 spin_unlock_irq(&ohci
->lock
);
963 /* paranoia, in case that didn't work: */
965 /* empty the interrupt branches */
966 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
967 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
969 /* no EDs to remove */
970 ohci
->ed_rm_list
= NULL
;
972 /* empty control and bulk lists */
973 ohci
->ed_controltail
= NULL
;
974 ohci
->ed_bulktail
= NULL
;
976 if ((temp
= ohci_run (ohci
)) < 0) {
977 ohci_err (ohci
, "can't restart, %d\n", temp
);
980 ohci_dbg(ohci
, "restart complete\n");
986 /*-------------------------------------------------------------------------*/
988 MODULE_AUTHOR (DRIVER_AUTHOR
);
989 MODULE_DESCRIPTION(DRIVER_DESC
);
990 MODULE_LICENSE ("GPL");
993 #include "ohci-pci.c"
994 #define PCI_DRIVER ohci_pci_driver
997 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
998 #include "ohci-sa1111.c"
999 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1002 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1003 #include "ohci-s3c2410.c"
1004 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1007 #ifdef CONFIG_USB_OHCI_EXYNOS
1008 #include "ohci-exynos.c"
1009 #define PLATFORM_DRIVER exynos_ohci_driver
1012 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1013 #include "ohci-omap.c"
1014 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1017 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1018 #include "ohci-omap3.c"
1019 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1022 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1023 #include "ohci-pxa27x.c"
1024 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1027 #ifdef CONFIG_ARCH_EP93XX
1028 #include "ohci-ep93xx.c"
1029 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1032 #ifdef CONFIG_MIPS_ALCHEMY
1033 #include "ohci-au1xxx.c"
1034 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1037 #ifdef CONFIG_PNX8550
1038 #include "ohci-pnx8550.c"
1039 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1042 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1043 #include "ohci-ppc-soc.c"
1044 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
1047 #ifdef CONFIG_ARCH_AT91
1048 #include "ohci-at91.c"
1049 #define PLATFORM_DRIVER ohci_hcd_at91_driver
1052 #ifdef CONFIG_ARCH_LPC32XX
1053 #include "ohci-nxp.c"
1054 #define PLATFORM_DRIVER usb_hcd_nxp_driver
1057 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1058 #include "ohci-da8xx.c"
1059 #define PLATFORM_DRIVER ohci_hcd_da8xx_driver
1062 #ifdef CONFIG_USB_OHCI_SH
1063 #include "ohci-sh.c"
1064 #define PLATFORM_DRIVER ohci_hcd_sh_driver
1068 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1069 #include "ohci-ppc-of.c"
1070 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1073 #ifdef CONFIG_PLAT_SPEAR
1074 #include "ohci-spear.c"
1075 #define PLATFORM_DRIVER spear_ohci_hcd_driver
1078 #ifdef CONFIG_PPC_PS3
1079 #include "ohci-ps3.c"
1080 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1083 #ifdef CONFIG_MFD_SM501
1084 #include "ohci-sm501.c"
1085 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1088 #ifdef CONFIG_MFD_TC6393XB
1089 #include "ohci-tmio.c"
1090 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1093 #ifdef CONFIG_MACH_JZ4740
1094 #include "ohci-jz4740.c"
1095 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1098 #ifdef CONFIG_USB_OCTEON_OHCI
1099 #include "ohci-octeon.c"
1100 #define PLATFORM_DRIVER ohci_octeon_driver
1103 #ifdef CONFIG_TILE_USB
1104 #include "ohci-tilegx.c"
1105 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1108 #ifdef CONFIG_USB_CNS3XXX_OHCI
1109 #include "ohci-cns3xxx.c"
1110 #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver
1113 #ifdef CONFIG_CPU_XLR
1114 #include "ohci-xls.c"
1115 #define PLATFORM_DRIVER ohci_xls_driver
1118 #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
1119 #include "ohci-platform.c"
1120 #define PLATFORM_DRIVER ohci_platform_driver
1123 #if !defined(PCI_DRIVER) && \
1124 !defined(PLATFORM_DRIVER) && \
1125 !defined(OMAP1_PLATFORM_DRIVER) && \
1126 !defined(OMAP3_PLATFORM_DRIVER) && \
1127 !defined(OF_PLATFORM_DRIVER) && \
1128 !defined(SA1111_DRIVER) && \
1129 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1130 !defined(SM501_OHCI_DRIVER) && \
1131 !defined(TMIO_OHCI_DRIVER)
1132 #error "missing bus glue for ohci-hcd"
1135 static int __init
ohci_hcd_mod_init(void)
1142 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1143 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name
,
1144 sizeof (struct ed
), sizeof (struct td
));
1145 set_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1148 ohci_debug_root
= debugfs_create_dir("ohci", usb_debug_root
);
1149 if (!ohci_debug_root
) {
1155 #ifdef PS3_SYSTEM_BUS_DRIVER
1156 retval
= ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1161 #ifdef PLATFORM_DRIVER
1162 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1164 goto error_platform
;
1167 #ifdef OMAP1_PLATFORM_DRIVER
1168 retval
= platform_driver_register(&OMAP1_PLATFORM_DRIVER
);
1170 goto error_omap1_platform
;
1173 #ifdef OMAP3_PLATFORM_DRIVER
1174 retval
= platform_driver_register(&OMAP3_PLATFORM_DRIVER
);
1176 goto error_omap3_platform
;
1179 #ifdef OF_PLATFORM_DRIVER
1180 retval
= platform_driver_register(&OF_PLATFORM_DRIVER
);
1182 goto error_of_platform
;
1185 #ifdef SA1111_DRIVER
1186 retval
= sa1111_driver_register(&SA1111_DRIVER
);
1192 retval
= pci_register_driver(&PCI_DRIVER
);
1197 #ifdef SM501_OHCI_DRIVER
1198 retval
= platform_driver_register(&SM501_OHCI_DRIVER
);
1203 #ifdef TMIO_OHCI_DRIVER
1204 retval
= platform_driver_register(&TMIO_OHCI_DRIVER
);
1212 #ifdef TMIO_OHCI_DRIVER
1213 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1216 #ifdef SM501_OHCI_DRIVER
1217 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1221 pci_unregister_driver(&PCI_DRIVER
);
1224 #ifdef SA1111_DRIVER
1225 sa1111_driver_unregister(&SA1111_DRIVER
);
1228 #ifdef OF_PLATFORM_DRIVER
1229 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1232 #ifdef PLATFORM_DRIVER
1233 platform_driver_unregister(&PLATFORM_DRIVER
);
1236 #ifdef OMAP1_PLATFORM_DRIVER
1237 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER
);
1238 error_omap1_platform
:
1240 #ifdef OMAP3_PLATFORM_DRIVER
1241 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER
);
1242 error_omap3_platform
:
1244 #ifdef PS3_SYSTEM_BUS_DRIVER
1245 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1249 debugfs_remove(ohci_debug_root
);
1250 ohci_debug_root
= NULL
;
1254 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1257 module_init(ohci_hcd_mod_init
);
1259 static void __exit
ohci_hcd_mod_exit(void)
1261 #ifdef TMIO_OHCI_DRIVER
1262 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1264 #ifdef SM501_OHCI_DRIVER
1265 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1268 pci_unregister_driver(&PCI_DRIVER
);
1270 #ifdef SA1111_DRIVER
1271 sa1111_driver_unregister(&SA1111_DRIVER
);
1273 #ifdef OF_PLATFORM_DRIVER
1274 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1276 #ifdef PLATFORM_DRIVER
1277 platform_driver_unregister(&PLATFORM_DRIVER
);
1279 #ifdef OMAP3_PLATFORM_DRIVER
1280 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER
);
1282 #ifdef PS3_SYSTEM_BUS_DRIVER
1283 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1286 debugfs_remove(ohci_debug_root
);
1288 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1290 module_exit(ohci_hcd_mod_exit
);
This page took 0.075142 seconds and 6 git commands to generate.