2 * Open Host Controller Interface (OHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
20 * This file is licenced under the GPL.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52 /*-------------------------------------------------------------------------*/
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
72 /*-------------------------------------------------------------------------*/
74 static const char hcd_name
[] = "ohci_hcd";
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
79 #include "pci-quirks.h"
81 static void ohci_dump (struct ohci_hcd
*ohci
, int verbose
);
82 static void ohci_stop (struct usb_hcd
*hcd
);
91 * On architectures with edge-triggered interrupts we must never return
94 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
95 #define IRQ_NOTMINE IRQ_HANDLED
97 #define IRQ_NOTMINE IRQ_NONE
101 /* Some boards misreport power switching/overcurrent */
102 static bool distrust_firmware
= 1;
103 module_param (distrust_firmware
, bool, 0);
104 MODULE_PARM_DESC (distrust_firmware
,
105 "true to distrust firmware power/overcurrent setup");
107 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
108 static bool no_handshake
= 0;
109 module_param (no_handshake
, bool, 0);
110 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
112 /*-------------------------------------------------------------------------*/
115 * queue up an urb for anything except the root hub
117 static int ohci_urb_enqueue (
122 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
124 urb_priv_t
*urb_priv
;
125 unsigned int pipe
= urb
->pipe
;
130 #ifdef OHCI_VERBOSE_DEBUG
131 urb_print(urb
, "SUB", usb_pipein(pipe
), -EINPROGRESS
);
134 /* every endpoint has a ed, locate and maybe (re)initialize it */
135 if (! (ed
= ed_get (ohci
, urb
->ep
, urb
->dev
, pipe
, urb
->interval
)))
138 /* for the private part of the URB we need the number of TDs (size) */
141 /* td_submit_urb() doesn't yet handle these */
142 if (urb
->transfer_buffer_length
> 4096)
145 /* 1 TD for setup, 1 for ACK, plus ... */
148 // case PIPE_INTERRUPT:
151 /* one TD for every 4096 Bytes (can be up to 8K) */
152 size
+= urb
->transfer_buffer_length
/ 4096;
153 /* ... and for any remaining bytes ... */
154 if ((urb
->transfer_buffer_length
% 4096) != 0)
156 /* ... and maybe a zero length packet to wrap it up */
159 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
160 && (urb
->transfer_buffer_length
161 % usb_maxpacket (urb
->dev
, pipe
,
162 usb_pipeout (pipe
))) == 0)
165 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
166 size
= urb
->number_of_packets
;
170 /* allocate the private part of the URB */
171 urb_priv
= kzalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
175 INIT_LIST_HEAD (&urb_priv
->pending
);
176 urb_priv
->length
= size
;
179 /* allocate the TDs (deferring hash chain updates) */
180 for (i
= 0; i
< size
; i
++) {
181 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
182 if (!urb_priv
->td
[i
]) {
183 urb_priv
->length
= i
;
184 urb_free_priv (ohci
, urb_priv
);
189 spin_lock_irqsave (&ohci
->lock
, flags
);
191 /* don't submit to a dead HC */
192 if (!HCD_HW_ACCESSIBLE(hcd
)) {
196 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
200 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
204 /* schedule the ed if needed */
205 if (ed
->state
== ED_IDLE
) {
206 retval
= ed_schedule (ohci
, ed
);
208 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
211 if (ed
->type
== PIPE_ISOCHRONOUS
) {
212 u16 frame
= ohci_frame_no(ohci
);
214 /* delay a few frames before the first TD */
215 frame
+= max_t (u16
, 8, ed
->interval
);
216 frame
&= ~(ed
->interval
- 1);
218 urb
->start_frame
= frame
;
220 } else if (ed
->type
== PIPE_ISOCHRONOUS
) {
221 u16 next
= ohci_frame_no(ohci
) + 1;
222 u16 frame
= ed
->last_iso
+ ed
->interval
;
224 /* Behind the scheduling threshold? */
225 if (unlikely(tick_before(frame
, next
))) {
227 /* USB_ISO_ASAP: Round up to the first available slot */
228 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
229 frame
+= (next
- frame
+ ed
->interval
- 1) &
233 * Not ASAP: Use the next slot in the stream. If
234 * the entire URB falls before the threshold, fail.
237 if (tick_before(frame
+ ed
->interval
*
238 (urb
->number_of_packets
- 1), next
)) {
240 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
245 * Some OHCI hardware doesn't handle late TDs
246 * correctly. After retiring them it proceeds
247 * to the next ED instead of the next TD.
248 * Therefore we have to omit the late TDs
251 urb_priv
->td_cnt
= DIV_ROUND_UP(
252 (u16
) (next
- frame
),
256 urb
->start_frame
= frame
;
259 /* fill the TDs and link them to the ed; and
260 * enable that part of the schedule, if needed
261 * and update count of queued periodic urbs
263 urb
->hcpriv
= urb_priv
;
264 td_submit_urb (ohci
, urb
);
268 urb_free_priv (ohci
, urb_priv
);
269 spin_unlock_irqrestore (&ohci
->lock
, flags
);
274 * decouple the URB from the HC queues (TDs, urb_priv).
275 * reporting is always done
276 * asynchronously, and we might be dealing with an urb that's
277 * partially transferred, or an ED with other urbs being unlinked.
279 static int ohci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
281 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
285 #ifdef OHCI_VERBOSE_DEBUG
286 urb_print(urb
, "UNLINK", 1, status
);
289 spin_lock_irqsave (&ohci
->lock
, flags
);
290 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
293 } else if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
294 urb_priv_t
*urb_priv
;
296 /* Unless an IRQ completed the unlink while it was being
297 * handed to us, flag it for unlink and giveback, and force
298 * some upcoming INTR_SF to call finish_unlinks()
300 urb_priv
= urb
->hcpriv
;
302 if (urb_priv
->ed
->state
== ED_OPER
)
303 start_ed_unlink (ohci
, urb_priv
->ed
);
307 * with HC dead, we won't respect hc queue pointers
308 * any more ... just clean up every urb's memory.
311 finish_urb(ohci
, urb
, status
);
313 spin_unlock_irqrestore (&ohci
->lock
, flags
);
317 /*-------------------------------------------------------------------------*/
319 /* frees config/altsetting state for endpoints,
320 * including ED memory, dummy TD, and bulk/intr data toggle
324 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
326 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
328 struct ed
*ed
= ep
->hcpriv
;
329 unsigned limit
= 1000;
331 /* ASSERT: any requests/urbs are being unlinked */
332 /* ASSERT: nobody can be submitting urbs for this any more */
338 spin_lock_irqsave (&ohci
->lock
, flags
);
340 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
343 if (quirk_zfmicro(ohci
) && ed
->type
== PIPE_INTERRUPT
)
344 ohci
->eds_scheduled
--;
345 finish_unlinks (ohci
, 0);
349 case ED_UNLINK
: /* wait for hw to finish? */
350 /* major IRQ delivery trouble loses INTR_SF too... */
352 ohci_warn(ohci
, "ED unlink timeout\n");
353 if (quirk_zfmicro(ohci
)) {
354 ohci_warn(ohci
, "Attempting ZF TD recovery\n");
355 ohci
->ed_to_check
= ed
;
360 spin_unlock_irqrestore (&ohci
->lock
, flags
);
361 schedule_timeout_uninterruptible(1);
363 case ED_IDLE
: /* fully unlinked */
364 if (list_empty (&ed
->td_list
)) {
365 td_free (ohci
, ed
->dummy
);
369 /* else FALL THROUGH */
371 /* caller was supposed to have unlinked any requests;
372 * that's not our job. can't recover; must leak ed.
374 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
375 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
376 list_empty (&ed
->td_list
) ? "" : " (has tds)");
377 td_free (ohci
, ed
->dummy
);
381 spin_unlock_irqrestore (&ohci
->lock
, flags
);
384 static int ohci_get_frame (struct usb_hcd
*hcd
)
386 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
388 return ohci_frame_no(ohci
);
391 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
393 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
394 ohci
->hc_control
&= OHCI_CTRL_RWC
;
395 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
396 ohci
->rh_state
= OHCI_RH_HALTED
;
399 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
400 * other cases where the next software may expect clean state from the
401 * "firmware". this is bus-neutral, unlike shutdown() methods.
404 ohci_shutdown (struct usb_hcd
*hcd
)
406 struct ohci_hcd
*ohci
;
408 ohci
= hcd_to_ohci (hcd
);
409 ohci_writel(ohci
, (u32
) ~0, &ohci
->regs
->intrdisable
);
411 /* Software reset, after which the controller goes into SUSPEND */
412 ohci_writel(ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
413 ohci_readl(ohci
, &ohci
->regs
->cmdstatus
); /* flush the writes */
416 ohci_writel(ohci
, ohci
->fminterval
, &ohci
->regs
->fminterval
);
419 static int check_ed(struct ohci_hcd
*ohci
, struct ed
*ed
)
421 return (hc32_to_cpu(ohci
, ed
->hwINFO
) & ED_IN
) != 0
422 && (hc32_to_cpu(ohci
, ed
->hwHeadP
) & TD_MASK
)
423 == (hc32_to_cpu(ohci
, ed
->hwTailP
) & TD_MASK
)
424 && !list_empty(&ed
->td_list
);
427 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
428 * an interrupt TD but neglects to add it to the donelist. On systems with
429 * this chipset, we need to periodically check the state of the queues to look
430 * for such "lost" TDs.
432 static void unlink_watchdog_func(unsigned long _ohci
)
436 unsigned seen_count
= 0;
438 struct ed
**seen
= NULL
;
439 struct ohci_hcd
*ohci
= (struct ohci_hcd
*) _ohci
;
441 spin_lock_irqsave(&ohci
->lock
, flags
);
442 max
= ohci
->eds_scheduled
;
446 if (ohci
->ed_to_check
)
449 seen
= kcalloc(max
, sizeof *seen
, GFP_ATOMIC
);
453 for (i
= 0; i
< NUM_INTS
; i
++) {
454 struct ed
*ed
= ohci
->periodic
[i
];
459 /* scan this branch of the periodic schedule tree */
460 for (temp
= 0; temp
< seen_count
; temp
++) {
461 if (seen
[temp
] == ed
) {
462 /* we've checked it and what's after */
469 seen
[seen_count
++] = ed
;
470 if (!check_ed(ohci
, ed
)) {
475 /* HC's TD list is empty, but HCD sees at least one
476 * TD that's not been sent through the donelist.
478 ohci
->ed_to_check
= ed
;
481 /* The HC may wait until the next frame to report the
482 * TD as done through the donelist and INTR_WDH. (We
483 * just *assume* it's not a multi-TD interrupt URB;
484 * those could defer the IRQ more than one frame, using
485 * DI...) Check again after the next INTR_SF.
487 ohci_writel(ohci
, OHCI_INTR_SF
,
488 &ohci
->regs
->intrstatus
);
489 ohci_writel(ohci
, OHCI_INTR_SF
,
490 &ohci
->regs
->intrenable
);
492 /* flush those writes */
493 (void) ohci_readl(ohci
, &ohci
->regs
->control
);
500 if (ohci
->eds_scheduled
)
501 mod_timer(&ohci
->unlink_watchdog
, round_jiffies(jiffies
+ HZ
));
503 spin_unlock_irqrestore(&ohci
->lock
, flags
);
506 /*-------------------------------------------------------------------------*
508 *-------------------------------------------------------------------------*/
510 /* init memory, and kick BIOS/SMM off */
512 static int ohci_init (struct ohci_hcd
*ohci
)
515 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
517 if (distrust_firmware
)
518 ohci
->flags
|= OHCI_QUIRK_HUB_POWER
;
520 ohci
->rh_state
= OHCI_RH_HALTED
;
521 ohci
->regs
= hcd
->regs
;
523 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
524 * was never needed for most non-PCI systems ... remove the code?
528 /* SMM owns the HC? not for long! */
529 if (!no_handshake
&& ohci_readl (ohci
,
530 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
533 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
535 /* this timeout is arbitrary. we make it long, so systems
536 * depending on usb keyboards may be usable even if the
537 * BIOS/SMM code seems pretty broken.
539 temp
= 500; /* arbitrary: five seconds */
541 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
542 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
543 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
546 ohci_err (ohci
, "USB HC takeover failed!"
547 " (BIOS/SMM bug)\n");
551 ohci_usb_reset (ohci
);
555 /* Disable HC interrupts */
556 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
558 /* flush the writes, and save key bits like RWC */
559 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
560 ohci
->hc_control
|= OHCI_CTRL_RWC
;
562 /* Read the number of ports unless overridden */
563 if (ohci
->num_ports
== 0)
564 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
569 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
570 sizeof *ohci
->hcca
, &ohci
->hcca_dma
, 0);
574 if ((ret
= ohci_mem_init (ohci
)) < 0)
577 create_debug_files (ohci
);
583 /*-------------------------------------------------------------------------*/
585 /* Start an OHCI controller, set the BUS operational
586 * resets USB and controller
589 static int ohci_run (struct ohci_hcd
*ohci
)
592 int first
= ohci
->fminterval
== 0;
593 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
595 ohci
->rh_state
= OHCI_RH_HALTED
;
597 /* boot firmware should have set this up (5.1.1.3.1) */
600 val
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
601 ohci
->fminterval
= val
& 0x3fff;
602 if (ohci
->fminterval
!= FI
)
603 ohci_dbg (ohci
, "fminterval delta %d\n",
604 ohci
->fminterval
- FI
);
605 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
606 /* also: power/overcurrent flags in roothub.a */
609 /* Reset USB nearly "by the book". RemoteWakeupConnected has
610 * to be checked in case boot firmware (BIOS/SMM/...) has set up
611 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
612 * If the bus glue detected wakeup capability then it should
613 * already be enabled; if so we'll just enable it again.
615 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0)
616 device_set_wakeup_capable(hcd
->self
.controller
, 1);
618 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
622 case OHCI_USB_SUSPEND
:
623 case OHCI_USB_RESUME
:
624 ohci
->hc_control
&= OHCI_CTRL_RWC
;
625 ohci
->hc_control
|= OHCI_USB_RESUME
;
626 val
= 10 /* msec wait */;
628 // case OHCI_USB_RESET:
630 ohci
->hc_control
&= OHCI_CTRL_RWC
;
631 ohci
->hc_control
|= OHCI_USB_RESET
;
632 val
= 50 /* msec wait */;
635 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
637 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
640 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
642 /* 2msec timelimit here means no irqs/preempt */
643 spin_lock_irq (&ohci
->lock
);
646 /* HC Reset requires max 10 us delay */
647 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
648 val
= 30; /* ... allow extra time */
649 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
651 spin_unlock_irq (&ohci
->lock
);
652 ohci_err (ohci
, "USB HC reset timed out!\n");
658 /* now we're in the SUSPEND state ... must go OPERATIONAL
659 * within 2msec else HC enters RESUME
661 * ... but some hardware won't init fmInterval "by the book"
662 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
663 * this if we write fmInterval after we're OPERATIONAL.
664 * Unclear about ALi, ServerWorks, and others ... this could
665 * easily be a longstanding bug in chip init on Linux.
667 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
668 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
669 // flush those writes
670 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
673 /* Tell the controller where the control and bulk lists are
674 * The lists are empty now. */
675 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
676 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
678 /* a reset clears this */
679 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
681 periodic_reinit (ohci
);
683 /* some OHCI implementations are finicky about how they init.
684 * bogus values here mean not even enumeration could work.
686 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
687 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
688 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
689 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
690 ohci_dbg (ohci
, "enabling initreset quirk\n");
693 spin_unlock_irq (&ohci
->lock
);
694 ohci_err (ohci
, "init err (%08x %04x)\n",
695 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
696 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
700 /* use rhsc irqs after khubd is fully initialized */
701 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
702 hcd
->uses_new_polling
= 1;
704 /* start controller operations */
705 ohci
->hc_control
&= OHCI_CTRL_RWC
;
706 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
707 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
708 ohci
->rh_state
= OHCI_RH_RUNNING
;
710 /* wake on ConnectStatusChange, matching external hubs */
711 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
713 /* Choose the interrupts we care about now, others later on demand */
714 mask
= OHCI_INTR_INIT
;
715 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
716 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
718 /* handle root hub init quirks ... */
719 val
= roothub_a (ohci
);
720 val
&= ~(RH_A_PSM
| RH_A_OCPM
);
721 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
722 /* NSC 87560 and maybe others */
724 val
&= ~(RH_A_POTPGT
| RH_A_NPS
);
725 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
726 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) ||
727 (ohci
->flags
& OHCI_QUIRK_HUB_POWER
)) {
728 /* hub power always on; required for AMD-756 and some
729 * Mac platforms. ganged overcurrent reporting, if any.
732 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
734 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
735 ohci_writel (ohci
, (val
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
736 &ohci
->regs
->roothub
.b
);
737 // flush those writes
738 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
740 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
741 spin_unlock_irq (&ohci
->lock
);
743 // POTPGT delay is bits 24-31, in 2 ms units.
744 mdelay ((val
>> 23) & 0x1fe);
746 if (quirk_zfmicro(ohci
)) {
747 /* Create timer to watch for bad queue state on ZF Micro */
748 setup_timer(&ohci
->unlink_watchdog
, unlink_watchdog_func
,
749 (unsigned long) ohci
);
751 ohci
->eds_scheduled
= 0;
752 ohci
->ed_to_check
= NULL
;
760 /* ohci_setup routine for generic controller initialization */
762 int ohci_setup(struct usb_hcd
*hcd
)
764 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
768 return ohci_init(ohci
);
770 EXPORT_SYMBOL_GPL(ohci_setup
);
772 /* ohci_start routine for generic controller start of all OHCI bus glue */
773 static int ohci_start(struct usb_hcd
*hcd
)
775 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
778 ret
= ohci_run(ohci
);
780 ohci_err(ohci
, "can't start\n");
786 /*-------------------------------------------------------------------------*/
788 /* an interrupt happens */
790 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
792 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
793 struct ohci_regs __iomem
*regs
= ohci
->regs
;
796 /* Read interrupt status (and flush pending writes). We ignore the
797 * optimization of checking the LSB of hcca->done_head; it doesn't
798 * work on all systems (edge triggering for OHCI can be a factor).
800 ints
= ohci_readl(ohci
, ®s
->intrstatus
);
802 /* Check for an all 1's result which is a typical consequence
803 * of dead, unclocked, or unplugged (CardBus...) devices
805 if (ints
== ~(u32
)0) {
806 ohci
->rh_state
= OHCI_RH_HALTED
;
807 ohci_dbg (ohci
, "device removed!\n");
812 /* We only care about interrupts that are enabled */
813 ints
&= ohci_readl(ohci
, ®s
->intrenable
);
815 /* interrupt for some other device? */
816 if (ints
== 0 || unlikely(ohci
->rh_state
== OHCI_RH_HALTED
))
819 if (ints
& OHCI_INTR_UE
) {
820 // e.g. due to PCI Master/Target Abort
821 if (quirk_nec(ohci
)) {
822 /* Workaround for a silicon bug in some NEC chips used
823 * in Apple's PowerBooks. Adapted from Darwin code.
825 ohci_err (ohci
, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
827 ohci_writel (ohci
, OHCI_INTR_UE
, ®s
->intrdisable
);
829 schedule_work (&ohci
->nec_work
);
831 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
832 ohci
->rh_state
= OHCI_RH_HALTED
;
837 ohci_usb_reset (ohci
);
840 if (ints
& OHCI_INTR_RHSC
) {
841 ohci_vdbg(ohci
, "rhsc\n");
842 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
843 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
846 /* NOTE: Vendors didn't always make the same implementation
847 * choices for RHSC. Many followed the spec; RHSC triggers
848 * on an edge, like setting and maybe clearing a port status
849 * change bit. With others it's level-triggered, active
850 * until khubd clears all the port status change bits. We'll
851 * always disable it here and rely on polling until khubd
854 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
855 usb_hcd_poll_rh_status(hcd
);
858 /* For connect and disconnect events, we expect the controller
859 * to turn on RHSC along with RD. But for remote wakeup events
860 * this might not happen.
862 else if (ints
& OHCI_INTR_RD
) {
863 ohci_vdbg(ohci
, "resume detect\n");
864 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
865 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
866 if (ohci
->autostop
) {
867 spin_lock (&ohci
->lock
);
868 ohci_rh_resume (ohci
);
869 spin_unlock (&ohci
->lock
);
871 usb_hcd_resume_root_hub(hcd
);
874 if (ints
& OHCI_INTR_WDH
) {
875 spin_lock (&ohci
->lock
);
877 spin_unlock (&ohci
->lock
);
880 if (quirk_zfmicro(ohci
) && (ints
& OHCI_INTR_SF
)) {
881 spin_lock(&ohci
->lock
);
882 if (ohci
->ed_to_check
) {
883 struct ed
*ed
= ohci
->ed_to_check
;
885 if (check_ed(ohci
, ed
)) {
886 /* HC thinks the TD list is empty; HCD knows
887 * at least one TD is outstanding
889 if (--ohci
->zf_delay
== 0) {
890 struct td
*td
= list_entry(
894 "Reclaiming orphan TD %p\n",
896 takeback_td(ohci
, td
);
897 ohci
->ed_to_check
= NULL
;
900 ohci
->ed_to_check
= NULL
;
902 spin_unlock(&ohci
->lock
);
905 /* could track INTR_SO to reduce available PCI/... bandwidth */
907 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
908 * when there's still unlinking to be done (next frame).
910 spin_lock (&ohci
->lock
);
911 if (ohci
->ed_rm_list
)
912 finish_unlinks (ohci
, ohci_frame_no(ohci
));
913 if ((ints
& OHCI_INTR_SF
) != 0
915 && !ohci
->ed_to_check
916 && ohci
->rh_state
== OHCI_RH_RUNNING
)
917 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
918 spin_unlock (&ohci
->lock
);
920 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
921 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
922 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
923 // flush those writes
924 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
930 /*-------------------------------------------------------------------------*/
932 static void ohci_stop (struct usb_hcd
*hcd
)
934 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
939 flush_work(&ohci
->nec_work
);
941 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
942 ohci_usb_reset(ohci
);
943 free_irq(hcd
->irq
, hcd
);
946 if (quirk_zfmicro(ohci
))
947 del_timer(&ohci
->unlink_watchdog
);
948 if (quirk_amdiso(ohci
))
951 remove_debug_files (ohci
);
952 ohci_mem_cleanup (ohci
);
954 dma_free_coherent (hcd
->self
.controller
,
956 ohci
->hcca
, ohci
->hcca_dma
);
962 /*-------------------------------------------------------------------------*/
964 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
966 /* must not be called from interrupt context */
967 int ohci_restart(struct ohci_hcd
*ohci
)
971 struct urb_priv
*priv
;
974 spin_lock_irq(&ohci
->lock
);
975 ohci
->rh_state
= OHCI_RH_HALTED
;
977 /* Recycle any "live" eds/tds (and urbs). */
978 if (!list_empty (&ohci
->pending
))
979 ohci_dbg(ohci
, "abort schedule...\n");
980 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
981 struct urb
*urb
= priv
->td
[0]->urb
;
982 struct ed
*ed
= priv
->ed
;
986 ed
->state
= ED_UNLINK
;
987 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
988 ed_deschedule (ohci
, ed
);
990 ed
->ed_next
= ohci
->ed_rm_list
;
992 ohci
->ed_rm_list
= ed
;
997 ohci_dbg(ohci
, "bogus ed %p state %d\n",
1002 urb
->unlinked
= -ESHUTDOWN
;
1004 finish_unlinks (ohci
, 0);
1005 spin_unlock_irq(&ohci
->lock
);
1007 /* paranoia, in case that didn't work: */
1009 /* empty the interrupt branches */
1010 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
1011 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
1013 /* no EDs to remove */
1014 ohci
->ed_rm_list
= NULL
;
1016 /* empty control and bulk lists */
1017 ohci
->ed_controltail
= NULL
;
1018 ohci
->ed_bulktail
= NULL
;
1020 if ((temp
= ohci_run (ohci
)) < 0) {
1021 ohci_err (ohci
, "can't restart, %d\n", temp
);
1024 ohci_dbg(ohci
, "restart complete\n");
1027 EXPORT_SYMBOL_GPL(ohci_restart
);
1033 int ohci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
)
1035 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
1036 unsigned long flags
;
1038 /* Disable irq emission and mark HW unaccessible. Use
1039 * the spinlock to properly synchronize with possible pending
1040 * RH suspend or resume activity.
1042 spin_lock_irqsave (&ohci
->lock
, flags
);
1043 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
1044 (void)ohci_readl(ohci
, &ohci
->regs
->intrdisable
);
1046 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1047 spin_unlock_irqrestore (&ohci
->lock
, flags
);
1051 EXPORT_SYMBOL_GPL(ohci_suspend
);
1054 int ohci_resume(struct usb_hcd
*hcd
, bool hibernated
)
1056 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
1058 bool need_reinit
= false;
1060 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1062 /* Make sure resume from hibernation re-enumerates everything */
1064 ohci_usb_reset(ohci
);
1066 /* See if the controller is already running or has been reset */
1067 ohci
->hc_control
= ohci_readl(ohci
, &ohci
->regs
->control
);
1068 if (ohci
->hc_control
& (OHCI_CTRL_IR
| OHCI_SCHED_ENABLES
)) {
1071 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
1073 case OHCI_USB_RESET
:
1078 /* If needed, reinitialize and suspend the root hub */
1080 spin_lock_irq(&ohci
->lock
);
1081 ohci_rh_resume(ohci
);
1082 ohci_rh_suspend(ohci
, 0);
1083 spin_unlock_irq(&ohci
->lock
);
1086 /* Normally just turn on port power and enable interrupts */
1088 ohci_dbg(ohci
, "powerup ports\n");
1089 for (port
= 0; port
< ohci
->num_ports
; port
++)
1090 ohci_writel(ohci
, RH_PS_PPS
,
1091 &ohci
->regs
->roothub
.portstatus
[port
]);
1093 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrenable
);
1094 ohci_readl(ohci
, &ohci
->regs
->intrenable
);
1098 usb_hcd_resume_root_hub(hcd
);
1102 EXPORT_SYMBOL_GPL(ohci_resume
);
1106 /*-------------------------------------------------------------------------*/
1109 * Generic structure: This gets copied for platform drivers so that
1110 * individual entries can be overridden as needed.
1113 static const struct hc_driver ohci_hc_driver
= {
1114 .description
= hcd_name
,
1115 .product_desc
= "OHCI Host Controller",
1116 .hcd_priv_size
= sizeof(struct ohci_hcd
),
1119 * generic hardware linkage
1122 .flags
= HCD_MEMORY
| HCD_USB11
,
1125 * basic lifecycle operations
1127 .reset
= ohci_setup
,
1128 .start
= ohci_start
,
1130 .shutdown
= ohci_shutdown
,
1133 * managing i/o requests and associated device resources
1135 .urb_enqueue
= ohci_urb_enqueue
,
1136 .urb_dequeue
= ohci_urb_dequeue
,
1137 .endpoint_disable
= ohci_endpoint_disable
,
1140 * scheduling support
1142 .get_frame_number
= ohci_get_frame
,
1147 .hub_status_data
= ohci_hub_status_data
,
1148 .hub_control
= ohci_hub_control
,
1150 .bus_suspend
= ohci_bus_suspend
,
1151 .bus_resume
= ohci_bus_resume
,
1153 .start_port_reset
= ohci_start_port_reset
,
1156 void ohci_init_driver(struct hc_driver
*drv
,
1157 const struct ohci_driver_overrides
*over
)
1159 /* Copy the generic table to drv and then apply the overrides */
1160 *drv
= ohci_hc_driver
;
1162 drv
->product_desc
= over
->product_desc
;
1163 drv
->hcd_priv_size
+= over
->extra_priv_size
;
1165 drv
->reset
= over
->reset
;
1167 EXPORT_SYMBOL_GPL(ohci_init_driver
);
1169 /*-------------------------------------------------------------------------*/
1171 MODULE_AUTHOR (DRIVER_AUTHOR
);
1172 MODULE_DESCRIPTION(DRIVER_DESC
);
1173 MODULE_LICENSE ("GPL");
1175 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1176 #include "ohci-sa1111.c"
1177 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1180 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1181 #include "ohci-pxa27x.c"
1182 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1185 #ifdef CONFIG_ARCH_EP93XX
1186 #include "ohci-ep93xx.c"
1187 #define EP93XX_PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1190 #ifdef CONFIG_ARCH_LPC32XX
1191 #include "ohci-nxp.c"
1192 #define NXP_PLATFORM_DRIVER usb_hcd_nxp_driver
1195 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1196 #include "ohci-da8xx.c"
1197 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1200 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1201 #include "ohci-ppc-of.c"
1202 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1205 #ifdef CONFIG_PPC_PS3
1206 #include "ohci-ps3.c"
1207 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1210 #ifdef CONFIG_MFD_SM501
1211 #include "ohci-sm501.c"
1212 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1215 #ifdef CONFIG_MFD_TC6393XB
1216 #include "ohci-tmio.c"
1217 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1220 #ifdef CONFIG_MACH_JZ4740
1221 #include "ohci-jz4740.c"
1222 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1225 #ifdef CONFIG_USB_OCTEON_OHCI
1226 #include "ohci-octeon.c"
1227 #define PLATFORM_DRIVER ohci_octeon_driver
1230 #ifdef CONFIG_TILE_USB
1231 #include "ohci-tilegx.c"
1232 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1235 static int __init
ohci_hcd_mod_init(void)
1242 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1243 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name
,
1244 sizeof (struct ed
), sizeof (struct td
));
1245 set_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1248 ohci_debug_root
= debugfs_create_dir("ohci", usb_debug_root
);
1249 if (!ohci_debug_root
) {
1255 #ifdef PS3_SYSTEM_BUS_DRIVER
1256 retval
= ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1261 #ifdef PLATFORM_DRIVER
1262 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1264 goto error_platform
;
1267 #ifdef OF_PLATFORM_DRIVER
1268 retval
= platform_driver_register(&OF_PLATFORM_DRIVER
);
1270 goto error_of_platform
;
1273 #ifdef SA1111_DRIVER
1274 retval
= sa1111_driver_register(&SA1111_DRIVER
);
1279 #ifdef SM501_OHCI_DRIVER
1280 retval
= platform_driver_register(&SM501_OHCI_DRIVER
);
1285 #ifdef TMIO_OHCI_DRIVER
1286 retval
= platform_driver_register(&TMIO_OHCI_DRIVER
);
1291 #ifdef EP93XX_PLATFORM_DRIVER
1292 retval
= platform_driver_register(&EP93XX_PLATFORM_DRIVER
);
1297 #ifdef NXP_PLATFORM_DRIVER
1298 retval
= platform_driver_register(&NXP_PLATFORM_DRIVER
);
1303 #ifdef DAVINCI_PLATFORM_DRIVER
1304 retval
= platform_driver_register(&DAVINCI_PLATFORM_DRIVER
);
1312 #ifdef DAVINCI_PLATFORM_DRIVER
1313 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER
);
1316 #ifdef NXP_PLATFORM_DRIVER
1317 platform_driver_unregister(&NXP_PLATFORM_DRIVER
);
1320 #ifdef EP93XX_PLATFORM_DRIVER
1321 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER
);
1324 #ifdef TMIO_OHCI_DRIVER
1325 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1328 #ifdef SM501_OHCI_DRIVER
1329 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1332 #ifdef SA1111_DRIVER
1333 sa1111_driver_unregister(&SA1111_DRIVER
);
1336 #ifdef OF_PLATFORM_DRIVER
1337 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1340 #ifdef PLATFORM_DRIVER
1341 platform_driver_unregister(&PLATFORM_DRIVER
);
1344 #ifdef PS3_SYSTEM_BUS_DRIVER
1345 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1349 debugfs_remove(ohci_debug_root
);
1350 ohci_debug_root
= NULL
;
1354 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1357 module_init(ohci_hcd_mod_init
);
1359 static void __exit
ohci_hcd_mod_exit(void)
1361 #ifdef DAVINCI_PLATFORM_DRIVER
1362 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER
);
1364 #ifdef NXP_PLATFORM_DRIVER
1365 platform_driver_unregister(&NXP_PLATFORM_DRIVER
);
1367 #ifdef EP93XX_PLATFORM_DRIVER
1368 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER
);
1370 #ifdef TMIO_OHCI_DRIVER
1371 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1373 #ifdef SM501_OHCI_DRIVER
1374 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1376 #ifdef SA1111_DRIVER
1377 sa1111_driver_unregister(&SA1111_DRIVER
);
1379 #ifdef OF_PLATFORM_DRIVER
1380 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1382 #ifdef PLATFORM_DRIVER
1383 platform_driver_unregister(&PLATFORM_DRIVER
);
1385 #ifdef PS3_SYSTEM_BUS_DRIVER
1386 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1389 debugfs_remove(ohci_debug_root
);
1391 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1393 module_exit(ohci_hcd_mod_exit
);
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