drivers/usb/host/ohci-pci.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * [ Initialisation is based on Linus'  ]
   8  * [ uhci code and gregs ohci fragments ]
   9  * [ (C) Copyright 1999 Linus Torvalds  ]
  10  * [ (C) Copyright 1999 Gregory P. Smith]
  11  *
  12  * PCI Bus Glue
  13  *
  14  * This file is licenced under the GPL.
  15  */
  16
  17 #ifndef CONFIG_PCI
  18 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  19 #endif
  20
  21 /*-------------------------------------------------------------------------*/
  22
  23 static int broken_suspend(struct usb_hcd *hcd)
  24 {
  25         device_init_wakeup(&hcd->self.root_hub->dev, 0);
  26         return 0;
  27 }
  28
  29 /* AMD 756, for most chips (early revs), corrupts register
  30  * values on read ... so enable the vendor workaround.
  31  */
  32 static int ohci_quirk_amd756(struct usb_hcd *hcd)
  33 {
  34         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  35
  36         ohci->flags = OHCI_QUIRK_AMD756;
  37         ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
  38
  39         /* also erratum 10 (suspend/resume issues) */
  40         return broken_suspend(hcd);
  41 }
  42
  43 /* Apple's OHCI driver has a lot of bizarre workarounds
  44  * for this chip.  Evidently control and bulk lists
  45  * can get confused.  (B&W G3 models, and ...)
  46  */
  47 static int ohci_quirk_opti(struct usb_hcd *hcd)
  48 {
  49         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  50
  51         ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
  52
  53         return 0;
  54 }
  55
  56 /* Check for NSC87560. We have to look at the bridge (fn1) to
  57  * identify the USB (fn2). This quirk might apply to more or
  58  * even all NSC stuff.
  59  */
  60 static int ohci_quirk_ns(struct usb_hcd *hcd)
  61 {
  62         struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  63         struct pci_dev  *b;
  64
  65         b  = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
  66         if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
  67             && b->vendor == PCI_VENDOR_ID_NS) {
  68                 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  69
  70                 ohci->flags |= OHCI_QUIRK_SUPERIO;
  71                 ohci_dbg (ohci, "Using NSC SuperIO setup\n");
  72         }
  73         pci_dev_put(b);
  74
  75         return 0;
  76 }
  77
  78 /* Check for Compaq's ZFMicro chipset, which needs short
  79  * delays before control or bulk queues get re-activated
  80  * in finish_unlinks()
  81  */
  82 static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
  83 {
  84         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  85
  86         ohci->flags |= OHCI_QUIRK_ZFMICRO;
  87         ohci_dbg (ohci, "enabled Compaq ZFMicro chipset quirk\n");
  88
  89         return 0;
  90 }
  91
  92 /* Check for Toshiba SCC OHCI which has big endian registers
  93  * and little endian in memory data structures
  94  */
  95 static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
  96 {
  97         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  98
  99         /* That chip is only present in the southbridge of some
 100          * cell based platforms which are supposed to select
 101          * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
 102          * that was the case though.
 103          */
 104 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
 105         ohci->flags |= OHCI_QUIRK_BE_MMIO;
 106         ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
 107         return 0;
 108 #else
 109         ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
 110         return -ENXIO;
 111 #endif
 112 }
 113
 114 /* List of quirks for OHCI */
 115 static const struct pci_device_id ohci_pci_quirks[] = {
 116         {
 117                 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
 118                 .driver_data = (unsigned long)ohci_quirk_amd756,
 119         },
 120         {
 121                 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
 122                 .driver_data = (unsigned long)ohci_quirk_opti,
 123         },
 124         {
 125                 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
 126                 .driver_data = (unsigned long)ohci_quirk_ns,
 127         },
 128         {
 129                 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
 130                 .driver_data = (unsigned long)ohci_quirk_zfmicro,
 131         },
 132         {
 133                 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
 134                 .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
 135         },
 136         {
 137                 /* Toshiba portege 4000 */
 138                 .vendor         = PCI_VENDOR_ID_AL,
 139                 .device         = 0x5237,
 140                 .subvendor      = PCI_VENDOR_ID_TOSHIBA_2,
 141                 .subdevice      = 0x0004,
 142                 .driver_data    = (unsigned long) broken_suspend,
 143         },
 144         {
 145                 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
 146                 .driver_data = (unsigned long) broken_suspend,
 147         },
 148         /* FIXME for some of the early AMD 760 southbridges, OHCI
 149          * won't work at all.  blacklist them.
 150          */
 151
 152         {},
 153 };
 154
 155 static int ohci_pci_reset (struct usb_hcd *hcd)
 156 {
 157         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 158         int ret = 0;
 159
 160         if (hcd->self.controller) {
 161                 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 162                 const struct pci_device_id *quirk_id;
 163
 164                 quirk_id = pci_match_id(ohci_pci_quirks, pdev);
 165                 if (quirk_id != NULL) {
 166                         int (*quirk)(struct usb_hcd *ohci);
 167                         quirk = (void *)quirk_id->driver_data;
 168                         ret = quirk(hcd);
 169                 }
 170         }
 171         if (ret == 0) {
 172                 ohci_hcd_init (ohci);
 173                 return ohci_init (ohci);
 174         }
 175         return ret;
 176 }
 177
 178
 179 static int __devinit ohci_pci_start (struct usb_hcd *hcd)
 180 {
 181         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 182         int             ret;
 183
 184 #ifdef CONFIG_PM /* avoid warnings about unused pdev */
 185         if (hcd->self.controller) {
 186                 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 187
 188                 /* RWC may not be set for add-in PCI cards, since boot
 189                  * firmware probably ignored them.  This transfers PCI
 190                  * PM wakeup capabilities (once the PCI layer is fixed).
 191                  */
 192                 if (device_may_wakeup(&pdev->dev))
 193                         ohci->hc_control |= OHCI_CTRL_RWC;
 194         }
 195 #endif /* CONFIG_PM */
 196
 197         ret = ohci_run (ohci);
 198         if (ret < 0) {
 199                 ohci_err (ohci, "can't start\n");
 200                 ohci_stop (hcd);
 201         }
 202         return ret;
 203 }
 204
 205 #ifdef  CONFIG_PM
 206
 207 static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
 208 {
 209         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 210         unsigned long   flags;
 211         int             rc = 0;
 212
 213         /* Root hub was already suspended. Disable irq emission and
 214          * mark HW unaccessible, bail out if RH has been resumed. Use
 215          * the spinlock to properly synchronize with possible pending
 216          * RH suspend or resume activity.
 217          *
 218          * This is still racy as hcd->state is manipulated outside of
 219          * any locks =P But that will be a different fix.
 220          */
 221         spin_lock_irqsave (&ohci->lock, flags);
 222         if (hcd->state != HC_STATE_SUSPENDED) {
 223                 rc = -EINVAL;
 224                 goto bail;
 225         }
 226         ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 227         (void)ohci_readl(ohci, &ohci->regs->intrdisable);
 228
 229         /* make sure snapshot being resumed re-enumerates everything */
 230         if (message.event == PM_EVENT_PRETHAW)
 231                 ohci_usb_reset(ohci);
 232
 233         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 234  bail:
 235         spin_unlock_irqrestore (&ohci->lock, flags);
 236
 237         return rc;
 238 }
 239
 240
 241 static int ohci_pci_resume (struct usb_hcd *hcd)
 242 {
 243         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 244         usb_hcd_resume_root_hub(hcd);
 245         return 0;
 246 }
 247
 248 #endif  /* CONFIG_PM */
 249
 250
 251 /*-------------------------------------------------------------------------*/
 252
 253 static const struct hc_driver ohci_pci_hc_driver = {
 254         .description =          hcd_name,
 255         .product_desc =         "OHCI Host Controller",
 256         .hcd_priv_size =        sizeof(struct ohci_hcd),
 257
 258         /*
 259          * generic hardware linkage
 260          */
 261         .irq =                  ohci_irq,
 262         .flags =                HCD_MEMORY | HCD_USB11,
 263
 264         /*
 265          * basic lifecycle operations
 266          */
 267         .reset =                ohci_pci_reset,
 268         .start =                ohci_pci_start,
 269         .stop =                 ohci_stop,
 270         .shutdown =             ohci_shutdown,
 271
 272 #ifdef  CONFIG_PM
 273         /* these suspend/resume entries are for upstream PCI glue ONLY */
 274         .suspend =              ohci_pci_suspend,
 275         .resume =               ohci_pci_resume,
 276 #endif
 277
 278         /*
 279          * managing i/o requests and associated device resources
 280          */
 281         .urb_enqueue =          ohci_urb_enqueue,
 282         .urb_dequeue =          ohci_urb_dequeue,
 283         .endpoint_disable =     ohci_endpoint_disable,
 284
 285         /*
 286          * scheduling support
 287          */
 288         .get_frame_number =     ohci_get_frame,
 289
 290         /*
 291          * root hub support
 292          */
 293         .hub_status_data =      ohci_hub_status_data,
 294         .hub_control =          ohci_hub_control,
 295         .hub_irq_enable =       ohci_rhsc_enable,
 296 #ifdef  CONFIG_PM
 297         .bus_suspend =          ohci_bus_suspend,
 298         .bus_resume =           ohci_bus_resume,
 299 #endif
 300         .start_port_reset =     ohci_start_port_reset,
 301 };
 302
 303 /*-------------------------------------------------------------------------*/
 304
 305
 306 static const struct pci_device_id pci_ids [] = { {
 307         /* handle any USB OHCI controller */
 308         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
 309         .driver_data =  (unsigned long) &ohci_pci_hc_driver,
 310         }, { /* end: all zeroes */ }
 311 };
 312 MODULE_DEVICE_TABLE (pci, pci_ids);
 313
 314 /* pci driver glue; this is a "new style" PCI driver module */
 315 static struct pci_driver ohci_pci_driver = {
 316         .name =         (char *) hcd_name,
 317         .id_table =     pci_ids,
 318
 319         .probe =        usb_hcd_pci_probe,
 320         .remove =       usb_hcd_pci_remove,
 321
 322 #ifdef  CONFIG_PM
 323         .suspend =      usb_hcd_pci_suspend,
 324         .resume =       usb_hcd_pci_resume,
 325 #endif
 326
 327         .shutdown =     usb_hcd_pci_shutdown,
 328 };
 329