2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * This file is licenced under the GPL.
10 #include <linux/irq.h>
11 #include <linux/slab.h>
13 static void urb_free_priv (struct ohci_hcd
*hc
, urb_priv_t
*urb_priv
)
15 int last
= urb_priv
->length
- 1;
21 for (i
= 0; i
<= last
; i
++) {
22 td
= urb_priv
->td
[i
];
28 list_del (&urb_priv
->pending
);
32 /*-------------------------------------------------------------------------*/
35 * URB goes back to driver, and isn't reissued.
36 * It's completely gone from HC data structures.
37 * PRECONDITION: ohci lock held, irqs blocked.
40 finish_urb(struct ohci_hcd
*ohci
, struct urb
*urb
, int status
)
41 __releases(ohci
->lock
)
42 __acquires(ohci
->lock
)
44 struct device
*dev
= ohci_to_hcd(ohci
)->self
.controller
;
45 struct usb_host_endpoint
*ep
= urb
->ep
;
46 struct urb_priv
*urb_priv
;
48 // ASSERT (urb->hcpriv != 0);
51 urb_free_priv (ohci
, urb
->hcpriv
);
53 if (likely(status
== -EINPROGRESS
))
56 switch (usb_pipetype (urb
->pipe
)) {
57 case PIPE_ISOCHRONOUS
:
58 ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
--;
59 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0) {
60 if (quirk_amdiso(ohci
))
61 usb_amd_quirk_pll_enable();
62 if (quirk_amdprefetch(ohci
))
63 sb800_prefetch(dev
, 0);
67 ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
--;
71 /* urb->complete() can reenter this HCD */
72 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci
), urb
);
73 spin_unlock (&ohci
->lock
);
74 usb_hcd_giveback_urb(ohci_to_hcd(ohci
), urb
, status
);
75 spin_lock (&ohci
->lock
);
77 /* stop periodic dma if it's not needed */
78 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0
79 && ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
== 0) {
80 ohci
->hc_control
&= ~(OHCI_CTRL_PLE
|OHCI_CTRL_IE
);
81 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
85 * An isochronous URB that is sumitted too late won't have any TDs
86 * (marked by the fact that the td_cnt value is larger than the
87 * actual number of TDs). If the next URB on this endpoint is like
88 * that, give it back now.
90 if (!list_empty(&ep
->urb_list
)) {
91 urb
= list_first_entry(&ep
->urb_list
, struct urb
, urb_list
);
92 urb_priv
= urb
->hcpriv
;
93 if (urb_priv
->td_cnt
> urb_priv
->length
) {
101 /*-------------------------------------------------------------------------*
102 * ED handling functions
103 *-------------------------------------------------------------------------*/
105 /* search for the right schedule branch to use for a periodic ed.
106 * does some load balancing; returns the branch, or negative errno.
108 static int balance (struct ohci_hcd
*ohci
, int interval
, int load
)
110 int i
, branch
= -ENOSPC
;
112 /* iso periods can be huge; iso tds specify frame numbers */
113 if (interval
> NUM_INTS
)
116 /* search for the least loaded schedule branch of that period
117 * that has enough bandwidth left unreserved.
119 for (i
= 0; i
< interval
; i
++) {
120 if (branch
< 0 || ohci
->load
[branch
] > ohci
->load
[i
]) {
123 /* usb 1.1 says 90% of one frame */
124 for (j
= i
; j
< NUM_INTS
; j
+= interval
) {
125 if ((ohci
->load
[j
] + load
) > 900)
136 /*-------------------------------------------------------------------------*/
138 /* both iso and interrupt requests have periods; this routine puts them
139 * into the schedule tree in the apppropriate place. most iso devices use
140 * 1msec periods, but that's not required.
142 static void periodic_link (struct ohci_hcd
*ohci
, struct ed
*ed
)
146 ohci_dbg(ohci
, "link %sed %p branch %d [%dus.], interval %d\n",
147 (ed
->hwINFO
& cpu_to_hc32 (ohci
, ED_ISO
)) ? "iso " : "",
148 ed
, ed
->branch
, ed
->load
, ed
->interval
);
150 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
151 struct ed
**prev
= &ohci
->periodic
[i
];
152 __hc32
*prev_p
= &ohci
->hcca
->int_table
[i
];
153 struct ed
*here
= *prev
;
155 /* sorting each branch by period (slow before fast)
156 * lets us share the faster parts of the tree.
157 * (plus maybe: put interrupt eds before iso)
159 while (here
&& ed
!= here
) {
160 if (ed
->interval
> here
->interval
)
162 prev
= &here
->ed_next
;
163 prev_p
= &here
->hwNextED
;
169 ed
->hwNextED
= *prev_p
;
172 *prev_p
= cpu_to_hc32(ohci
, ed
->dma
);
175 ohci
->load
[i
] += ed
->load
;
177 ohci_to_hcd(ohci
)->self
.bandwidth_allocated
+= ed
->load
/ ed
->interval
;
180 /* link an ed into one of the HC chains */
182 static int ed_schedule (struct ohci_hcd
*ohci
, struct ed
*ed
)
192 /* we care about rm_list when setting CLE/BLE in case the HC was at
193 * work on some TD when CLE/BLE was turned off, and isn't quiesced
194 * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
196 * control and bulk EDs are doubly linked (ed_next, ed_prev), but
197 * periodic ones are singly linked (ed_next). that's because the
198 * periodic schedule encodes a tree like figure 3-5 in the ohci
199 * spec: each qh can have several "previous" nodes, and the tree
200 * doesn't have unused/idle descriptors.
204 if (ohci
->ed_controltail
== NULL
) {
205 WARN_ON (ohci
->hc_control
& OHCI_CTRL_CLE
);
206 ohci_writel (ohci
, ed
->dma
,
207 &ohci
->regs
->ed_controlhead
);
209 ohci
->ed_controltail
->ed_next
= ed
;
210 ohci
->ed_controltail
->hwNextED
= cpu_to_hc32 (ohci
,
213 ed
->ed_prev
= ohci
->ed_controltail
;
214 if (!ohci
->ed_controltail
&& !ohci
->ed_rm_list
) {
216 ohci
->hc_control
|= OHCI_CTRL_CLE
;
217 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlcurrent
);
218 ohci_writel (ohci
, ohci
->hc_control
,
219 &ohci
->regs
->control
);
221 ohci
->ed_controltail
= ed
;
225 if (ohci
->ed_bulktail
== NULL
) {
226 WARN_ON (ohci
->hc_control
& OHCI_CTRL_BLE
);
227 ohci_writel (ohci
, ed
->dma
, &ohci
->regs
->ed_bulkhead
);
229 ohci
->ed_bulktail
->ed_next
= ed
;
230 ohci
->ed_bulktail
->hwNextED
= cpu_to_hc32 (ohci
,
233 ed
->ed_prev
= ohci
->ed_bulktail
;
234 if (!ohci
->ed_bulktail
&& !ohci
->ed_rm_list
) {
236 ohci
->hc_control
|= OHCI_CTRL_BLE
;
237 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkcurrent
);
238 ohci_writel (ohci
, ohci
->hc_control
,
239 &ohci
->regs
->control
);
241 ohci
->ed_bulktail
= ed
;
244 // case PIPE_INTERRUPT:
245 // case PIPE_ISOCHRONOUS:
247 branch
= balance (ohci
, ed
->interval
, ed
->load
);
250 "ERR %d, interval %d msecs, load %d\n",
251 branch
, ed
->interval
, ed
->load
);
252 // FIXME if there are TDs queued, fail them!
256 periodic_link (ohci
, ed
);
259 /* the HC may not see the schedule updates yet, but if it does
260 * then they'll be properly ordered.
265 /*-------------------------------------------------------------------------*/
267 /* scan the periodic table to find and unlink this ED */
268 static void periodic_unlink (struct ohci_hcd
*ohci
, struct ed
*ed
)
272 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
274 struct ed
**prev
= &ohci
->periodic
[i
];
275 __hc32
*prev_p
= &ohci
->hcca
->int_table
[i
];
277 while (*prev
&& (temp
= *prev
) != ed
) {
278 prev_p
= &temp
->hwNextED
;
279 prev
= &temp
->ed_next
;
282 *prev_p
= ed
->hwNextED
;
285 ohci
->load
[i
] -= ed
->load
;
287 ohci_to_hcd(ohci
)->self
.bandwidth_allocated
-= ed
->load
/ ed
->interval
;
289 ohci_dbg(ohci
, "unlink %sed %p branch %d [%dus.], interval %d\n",
290 (ed
->hwINFO
& cpu_to_hc32 (ohci
, ED_ISO
)) ? "iso " : "",
291 ed
, ed
->branch
, ed
->load
, ed
->interval
);
294 /* unlink an ed from one of the HC chains.
295 * just the link to the ed is unlinked.
296 * the link from the ed still points to another operational ed or 0
297 * so the HC can eventually finish the processing of the unlinked ed
298 * (assuming it already started that, which needn't be true).
300 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
301 * it won't. ED_SKIP means the HC will finish its current transaction,
302 * but won't start anything new. The TD queue may still grow; device
303 * drivers don't know about this HCD-internal state.
305 * When the HC can't see the ED, something changes ED_UNLINK to one of:
307 * - ED_OPER: when there's any request queued, the ED gets rescheduled
308 * immediately. HC should be working on them.
310 * - ED_IDLE: when there's no TD queue or the HC isn't running.
312 * When finish_unlinks() runs later, after SOF interrupt, it will often
313 * complete one or more URB unlinks before making that state change.
315 static void ed_deschedule (struct ohci_hcd
*ohci
, struct ed
*ed
)
317 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_SKIP
);
319 ed
->state
= ED_UNLINK
;
321 /* To deschedule something from the control or bulk list, just
322 * clear CLE/BLE and wait. There's no safe way to scrub out list
323 * head/current registers until later, and "later" isn't very
324 * tightly specified. Figure 6-5 and Section 6.4.2.2 show how
325 * the HC is reading the ED queues (while we modify them).
327 * For now, ed_schedule() is "later". It might be good paranoia
328 * to scrub those registers in finish_unlinks(), in case of bugs
329 * that make the HC try to use them.
333 /* remove ED from the HC's list: */
334 if (ed
->ed_prev
== NULL
) {
336 ohci
->hc_control
&= ~OHCI_CTRL_CLE
;
337 ohci_writel (ohci
, ohci
->hc_control
,
338 &ohci
->regs
->control
);
339 // a ohci_readl() later syncs CLE with the HC
342 hc32_to_cpup (ohci
, &ed
->hwNextED
),
343 &ohci
->regs
->ed_controlhead
);
345 ed
->ed_prev
->ed_next
= ed
->ed_next
;
346 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
348 /* remove ED from the HCD's list: */
349 if (ohci
->ed_controltail
== ed
) {
350 ohci
->ed_controltail
= ed
->ed_prev
;
351 if (ohci
->ed_controltail
)
352 ohci
->ed_controltail
->ed_next
= NULL
;
353 } else if (ed
->ed_next
) {
354 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
359 /* remove ED from the HC's list: */
360 if (ed
->ed_prev
== NULL
) {
362 ohci
->hc_control
&= ~OHCI_CTRL_BLE
;
363 ohci_writel (ohci
, ohci
->hc_control
,
364 &ohci
->regs
->control
);
365 // a ohci_readl() later syncs BLE with the HC
368 hc32_to_cpup (ohci
, &ed
->hwNextED
),
369 &ohci
->regs
->ed_bulkhead
);
371 ed
->ed_prev
->ed_next
= ed
->ed_next
;
372 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
374 /* remove ED from the HCD's list: */
375 if (ohci
->ed_bulktail
== ed
) {
376 ohci
->ed_bulktail
= ed
->ed_prev
;
377 if (ohci
->ed_bulktail
)
378 ohci
->ed_bulktail
->ed_next
= NULL
;
379 } else if (ed
->ed_next
) {
380 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
384 // case PIPE_INTERRUPT:
385 // case PIPE_ISOCHRONOUS:
387 periodic_unlink (ohci
, ed
);
393 /*-------------------------------------------------------------------------*/
395 /* get and maybe (re)init an endpoint. init _should_ be done only as part
396 * of enumeration, usb_set_configuration() or usb_set_interface().
398 static struct ed
*ed_get (
399 struct ohci_hcd
*ohci
,
400 struct usb_host_endpoint
*ep
,
401 struct usb_device
*udev
,
408 spin_lock_irqsave (&ohci
->lock
, flags
);
410 if (!(ed
= ep
->hcpriv
)) {
415 ed
= ed_alloc (ohci
, GFP_ATOMIC
);
421 /* dummy td; end of td list for ed */
422 td
= td_alloc (ohci
, GFP_ATOMIC
);
430 ed
->hwTailP
= cpu_to_hc32 (ohci
, td
->td_dma
);
431 ed
->hwHeadP
= ed
->hwTailP
; /* ED_C, ED_H zeroed */
434 is_out
= !(ep
->desc
.bEndpointAddress
& USB_DIR_IN
);
436 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
437 * succeeds ... otherwise we wouldn't need "pipe".
439 info
= usb_pipedevice (pipe
);
440 ed
->type
= usb_pipetype(pipe
);
442 info
|= (ep
->desc
.bEndpointAddress
& ~USB_DIR_IN
) << 7;
443 info
|= usb_endpoint_maxp(&ep
->desc
) << 16;
444 if (udev
->speed
== USB_SPEED_LOW
)
446 /* only control transfers store pids in tds */
447 if (ed
->type
!= PIPE_CONTROL
) {
448 info
|= is_out
? ED_OUT
: ED_IN
;
449 if (ed
->type
!= PIPE_BULK
) {
450 /* periodic transfers... */
451 if (ed
->type
== PIPE_ISOCHRONOUS
)
453 else if (interval
> 32) /* iso can be bigger */
455 ed
->interval
= interval
;
456 ed
->load
= usb_calc_bus_time (
457 udev
->speed
, !is_out
,
458 ed
->type
== PIPE_ISOCHRONOUS
,
459 usb_endpoint_maxp(&ep
->desc
))
463 ed
->hwINFO
= cpu_to_hc32(ohci
, info
);
469 spin_unlock_irqrestore (&ohci
->lock
, flags
);
473 /*-------------------------------------------------------------------------*/
475 /* request unlinking of an endpoint from an operational HC.
476 * put the ep on the rm_list
477 * real work is done at the next start frame (SF) hardware interrupt
478 * caller guarantees HCD is running, so hardware access is safe,
479 * and that ed->state is ED_OPER
481 static void start_ed_unlink (struct ohci_hcd
*ohci
, struct ed
*ed
)
483 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_DEQUEUE
);
484 ed_deschedule (ohci
, ed
);
486 /* rm_list is just singly linked, for simplicity */
487 ed
->ed_next
= ohci
->ed_rm_list
;
489 ohci
->ed_rm_list
= ed
;
491 /* enable SOF interrupt */
492 ohci_writel (ohci
, OHCI_INTR_SF
, &ohci
->regs
->intrstatus
);
493 ohci_writel (ohci
, OHCI_INTR_SF
, &ohci
->regs
->intrenable
);
494 // flush those writes, and get latest HCCA contents
495 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
497 /* SF interrupt might get delayed; record the frame counter value that
498 * indicates when the HC isn't looking at it, so concurrent unlinks
499 * behave. frame_no wraps every 2^16 msec, and changes right before
502 ed
->tick
= ohci_frame_no(ohci
) + 1;
506 /*-------------------------------------------------------------------------*
507 * TD handling functions
508 *-------------------------------------------------------------------------*/
510 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
513 td_fill (struct ohci_hcd
*ohci
, u32 info
,
514 dma_addr_t data
, int len
,
515 struct urb
*urb
, int index
)
517 struct td
*td
, *td_pt
;
518 struct urb_priv
*urb_priv
= urb
->hcpriv
;
519 int is_iso
= info
& TD_ISO
;
522 // ASSERT (index < urb_priv->length);
524 /* aim for only one interrupt per urb. mostly applies to control
525 * and iso; other urbs rarely need more than one TD per urb.
526 * this way, only final tds (or ones with an error) cause IRQs.
527 * at least immediately; use DI=6 in case any control request is
528 * tempted to die part way through. (and to force the hc to flush
529 * its donelist soonish, even on unlink paths.)
531 * NOTE: could delay interrupts even for the last TD, and get fewer
532 * interrupts ... increasing per-urb latency by sharing interrupts.
533 * Drivers that queue bulk urbs may request that behavior.
535 if (index
!= (urb_priv
->length
- 1)
536 || (urb
->transfer_flags
& URB_NO_INTERRUPT
))
537 info
|= TD_DI_SET (6);
539 /* use this td as the next dummy */
540 td_pt
= urb_priv
->td
[index
];
542 /* fill the old dummy TD */
543 td
= urb_priv
->td
[index
] = urb_priv
->ed
->dummy
;
544 urb_priv
->ed
->dummy
= td_pt
;
546 td
->ed
= urb_priv
->ed
;
547 td
->next_dl_td
= NULL
;
554 td
->hwINFO
= cpu_to_hc32 (ohci
, info
);
556 td
->hwCBP
= cpu_to_hc32 (ohci
, data
& 0xFFFFF000);
557 *ohci_hwPSWp(ohci
, td
, 0) = cpu_to_hc16 (ohci
,
558 (data
& 0x0FFF) | 0xE000);
560 td
->hwCBP
= cpu_to_hc32 (ohci
, data
);
563 td
->hwBE
= cpu_to_hc32 (ohci
, data
+ len
- 1);
566 td
->hwNextTD
= cpu_to_hc32 (ohci
, td_pt
->td_dma
);
568 /* append to queue */
569 list_add_tail (&td
->td_list
, &td
->ed
->td_list
);
571 /* hash it for later reverse mapping */
572 hash
= TD_HASH_FUNC (td
->td_dma
);
573 td
->td_hash
= ohci
->td_hash
[hash
];
574 ohci
->td_hash
[hash
] = td
;
576 /* HC might read the TD (or cachelines) right away ... */
578 td
->ed
->hwTailP
= td
->hwNextTD
;
581 /*-------------------------------------------------------------------------*/
583 /* Prepare all TDs of a transfer, and queue them onto the ED.
584 * Caller guarantees HC is active.
585 * Usually the ED is already on the schedule, so TDs might be
586 * processed as soon as they're queued.
588 static void td_submit_urb (
589 struct ohci_hcd
*ohci
,
592 struct urb_priv
*urb_priv
= urb
->hcpriv
;
593 struct device
*dev
= ohci_to_hcd(ohci
)->self
.controller
;
595 int data_len
= urb
->transfer_buffer_length
;
598 int is_out
= usb_pipeout (urb
->pipe
);
600 int i
, this_sg_len
, n
;
601 struct scatterlist
*sg
;
603 /* OHCI handles the bulk/interrupt data toggles itself. We just
604 * use the device toggle bits for resetting, and rely on the fact
605 * that resetting toggle is meaningless if the endpoint is active.
607 if (!usb_gettoggle (urb
->dev
, usb_pipeendpoint (urb
->pipe
), is_out
)) {
608 usb_settoggle (urb
->dev
, usb_pipeendpoint (urb
->pipe
),
610 urb_priv
->ed
->hwHeadP
&= ~cpu_to_hc32 (ohci
, ED_C
);
613 list_add (&urb_priv
->pending
, &ohci
->pending
);
615 i
= urb
->num_mapped_sgs
;
616 if (data_len
> 0 && i
> 0) {
618 data
= sg_dma_address(sg
);
621 * urb->transfer_buffer_length may be smaller than the
622 * size of the scatterlist (or vice versa)
624 this_sg_len
= min_t(int, sg_dma_len(sg
), data_len
);
628 data
= urb
->transfer_dma
;
631 this_sg_len
= data_len
;
634 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
635 * using TD_CC_GET, as well as by seeing them on the done list.
636 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
638 switch (urb_priv
->ed
->type
) {
640 /* Bulk and interrupt are identical except for where in the schedule
644 /* ... and periodic urbs have extra accounting */
645 periodic
= ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
++ == 0
646 && ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0;
650 ? TD_T_TOGGLE
| TD_CC
| TD_DP_OUT
651 : TD_T_TOGGLE
| TD_CC
| TD_DP_IN
;
652 /* TDs _could_ transfer up to 8K each */
654 n
= min(this_sg_len
, 4096);
656 /* maybe avoid ED halt on final TD short read */
657 if (n
>= data_len
|| (i
== 1 && n
>= this_sg_len
)) {
658 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
661 td_fill(ohci
, info
, data
, n
, urb
, cnt
);
667 if (this_sg_len
<= 0) {
668 if (--i
<= 0 || data_len
<= 0)
671 data
= sg_dma_address(sg
);
672 this_sg_len
= min_t(int, sg_dma_len(sg
),
676 if ((urb
->transfer_flags
& URB_ZERO_PACKET
)
677 && cnt
< urb_priv
->length
) {
678 td_fill (ohci
, info
, 0, 0, urb
, cnt
);
681 /* maybe kickstart bulk list */
682 if (urb_priv
->ed
->type
== PIPE_BULK
) {
684 ohci_writel (ohci
, OHCI_BLF
, &ohci
->regs
->cmdstatus
);
688 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
689 * any DATA phase works normally, and the STATUS ack is special.
692 info
= TD_CC
| TD_DP_SETUP
| TD_T_DATA0
;
693 td_fill (ohci
, info
, urb
->setup_dma
, 8, urb
, cnt
++);
695 info
= TD_CC
| TD_R
| TD_T_DATA1
;
696 info
|= is_out
? TD_DP_OUT
: TD_DP_IN
;
697 /* NOTE: mishandles transfers >8K, some >4K */
698 td_fill (ohci
, info
, data
, data_len
, urb
, cnt
++);
700 info
= (is_out
|| data_len
== 0)
701 ? TD_CC
| TD_DP_IN
| TD_T_DATA1
702 : TD_CC
| TD_DP_OUT
| TD_T_DATA1
;
703 td_fill (ohci
, info
, data
, 0, urb
, cnt
++);
704 /* maybe kickstart control list */
706 ohci_writel (ohci
, OHCI_CLF
, &ohci
->regs
->cmdstatus
);
709 /* ISO has no retransmit, so no toggle; and it uses special TDs.
710 * Each TD could handle multiple consecutive frames (interval 1);
711 * we could often reduce the number of TDs here.
713 case PIPE_ISOCHRONOUS
:
714 for (cnt
= urb_priv
->td_cnt
; cnt
< urb
->number_of_packets
;
716 int frame
= urb
->start_frame
;
718 // FIXME scheduling should handle frame counter
719 // roll-around ... exotic case (and OHCI has
720 // a 2^16 iso range, vs other HCs max of 2^10)
721 frame
+= cnt
* urb
->interval
;
723 td_fill (ohci
, TD_CC
| TD_ISO
| frame
,
724 data
+ urb
->iso_frame_desc
[cnt
].offset
,
725 urb
->iso_frame_desc
[cnt
].length
, urb
, cnt
);
727 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0) {
728 if (quirk_amdiso(ohci
))
729 usb_amd_quirk_pll_disable();
730 if (quirk_amdprefetch(ohci
))
731 sb800_prefetch(dev
, 1);
733 periodic
= ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
++ == 0
734 && ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
== 0;
738 /* start periodic dma if needed */
741 ohci
->hc_control
|= OHCI_CTRL_PLE
|OHCI_CTRL_IE
;
742 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
745 // ASSERT (urb_priv->length == cnt);
748 /*-------------------------------------------------------------------------*
749 * Done List handling functions
750 *-------------------------------------------------------------------------*/
752 /* calculate transfer length/status and update the urb */
753 static int td_done(struct ohci_hcd
*ohci
, struct urb
*urb
, struct td
*td
)
755 u32 tdINFO
= hc32_to_cpup (ohci
, &td
->hwINFO
);
757 int status
= -EINPROGRESS
;
759 list_del (&td
->td_list
);
761 /* ISO ... drivers see per-TD length/status */
762 if (tdINFO
& TD_ISO
) {
763 u16 tdPSW
= ohci_hwPSW(ohci
, td
, 0);
766 /* NOTE: assumes FC in tdINFO == 0, and that
767 * only the first of 0..MAXPSW psws is used.
770 cc
= (tdPSW
>> 12) & 0xF;
771 if (tdINFO
& TD_CC
) /* hc didn't touch? */
774 if (usb_pipeout (urb
->pipe
))
775 dlen
= urb
->iso_frame_desc
[td
->index
].length
;
777 /* short reads are always OK for ISO */
778 if (cc
== TD_DATAUNDERRUN
)
780 dlen
= tdPSW
& 0x3ff;
782 urb
->actual_length
+= dlen
;
783 urb
->iso_frame_desc
[td
->index
].actual_length
= dlen
;
784 urb
->iso_frame_desc
[td
->index
].status
= cc_to_error
[cc
];
786 if (cc
!= TD_CC_NOERROR
)
788 "urb %p iso td %p (%d) len %d cc %d\n",
789 urb
, td
, 1 + td
->index
, dlen
, cc
);
791 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
792 * except that "setup" bytes aren't counted and "short" transfers
793 * might not be reported as errors.
796 int type
= usb_pipetype (urb
->pipe
);
797 u32 tdBE
= hc32_to_cpup (ohci
, &td
->hwBE
);
799 cc
= TD_CC_GET (tdINFO
);
801 /* update packet status if needed (short is normally ok) */
802 if (cc
== TD_DATAUNDERRUN
803 && !(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
805 if (cc
!= TD_CC_NOERROR
&& cc
< 0x0E)
806 status
= cc_to_error
[cc
];
808 /* count all non-empty packets except control SETUP packet */
809 if ((type
!= PIPE_CONTROL
|| td
->index
!= 0) && tdBE
!= 0) {
811 urb
->actual_length
+= tdBE
- td
->data_dma
+ 1;
813 urb
->actual_length
+=
814 hc32_to_cpup (ohci
, &td
->hwCBP
)
818 if (cc
!= TD_CC_NOERROR
&& cc
< 0x0E)
820 "urb %p td %p (%d) cc %d, len=%d/%d\n",
821 urb
, td
, 1 + td
->index
, cc
,
823 urb
->transfer_buffer_length
);
828 /*-------------------------------------------------------------------------*/
830 static void ed_halted(struct ohci_hcd
*ohci
, struct td
*td
, int cc
)
832 struct urb
*urb
= td
->urb
;
833 urb_priv_t
*urb_priv
= urb
->hcpriv
;
834 struct ed
*ed
= td
->ed
;
835 struct list_head
*tmp
= td
->td_list
.next
;
836 __hc32 toggle
= ed
->hwHeadP
& cpu_to_hc32 (ohci
, ED_C
);
838 /* clear ed halt; this is the td that caused it, but keep it inactive
839 * until its urb->complete() has a chance to clean up.
841 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_SKIP
);
843 ed
->hwHeadP
&= ~cpu_to_hc32 (ohci
, ED_H
);
845 /* Get rid of all later tds from this urb. We don't have
846 * to be careful: no errors and nothing was transferred.
847 * Also patch the ed so it looks as if those tds completed normally.
849 while (tmp
!= &ed
->td_list
) {
852 next
= list_entry (tmp
, struct td
, td_list
);
853 tmp
= next
->td_list
.next
;
855 if (next
->urb
!= urb
)
858 /* NOTE: if multi-td control DATA segments get supported,
859 * this urb had one of them, this td wasn't the last td
860 * in that segment (TD_R clear), this ed halted because
861 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
862 * then we need to leave the control STATUS packet queued
866 list_del(&next
->td_list
);
868 ed
->hwHeadP
= next
->hwNextTD
| toggle
;
871 /* help for troubleshooting: report anything that
872 * looks odd ... that doesn't include protocol stalls
873 * (or maybe some other things)
876 case TD_DATAUNDERRUN
:
877 if ((urb
->transfer_flags
& URB_SHORT_NOT_OK
) == 0)
881 if (usb_pipecontrol (urb
->pipe
))
886 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
887 urb
, urb
->dev
->devpath
,
888 usb_pipeendpoint (urb
->pipe
),
889 usb_pipein (urb
->pipe
) ? "in" : "out",
890 hc32_to_cpu (ohci
, td
->hwINFO
),
891 cc
, cc_to_error
[cc
]);
895 /* Add a TD to the done list */
896 static void add_to_done_list(struct ohci_hcd
*ohci
, struct td
*td
)
898 struct td
*td2
, *td_prev
;
902 return; /* Already on the list */
904 /* Add all the TDs going back until we reach one that's on the list */
907 list_for_each_entry_continue_reverse(td2
, &ed
->td_list
, td_list
) {
910 td2
->next_dl_td
= td_prev
;
915 ohci
->dl_end
->next_dl_td
= td_prev
;
917 ohci
->dl_start
= td_prev
;
920 * Make td->next_dl_td point to td itself, to mark the fact
921 * that td is on the done list.
923 ohci
->dl_end
= td
->next_dl_td
= td
;
925 /* Did we just add the latest pending TD? */
926 td2
= ed
->pending_td
;
927 if (td2
&& td2
->next_dl_td
)
928 ed
->pending_td
= NULL
;
931 /* Get the entries on the hardware done queue and put them on our list */
932 static void update_done_list(struct ohci_hcd
*ohci
)
935 struct td
*td
= NULL
;
937 td_dma
= hc32_to_cpup (ohci
, &ohci
->hcca
->done_head
);
938 ohci
->hcca
->done_head
= 0;
941 /* get TD from hc's singly linked list, and
942 * add to ours. ed->td_list changes later.
947 td
= dma_to_td (ohci
, td_dma
);
949 ohci_err (ohci
, "bad entry %8x\n", td_dma
);
953 td
->hwINFO
|= cpu_to_hc32 (ohci
, TD_DONE
);
954 cc
= TD_CC_GET (hc32_to_cpup (ohci
, &td
->hwINFO
));
956 /* Non-iso endpoints can halt on error; un-halt,
957 * and dequeue any other TDs from this urb.
958 * No other TD could have caused the halt.
960 if (cc
!= TD_CC_NOERROR
961 && (td
->ed
->hwHeadP
& cpu_to_hc32 (ohci
, ED_H
)))
962 ed_halted(ohci
, td
, cc
);
964 td_dma
= hc32_to_cpup (ohci
, &td
->hwNextTD
);
965 add_to_done_list(ohci
, td
);
969 /*-------------------------------------------------------------------------*/
971 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
972 static void finish_unlinks(struct ohci_hcd
*ohci
)
974 unsigned tick
= ohci_frame_no(ohci
);
975 struct ed
*ed
, **last
;
978 for (last
= &ohci
->ed_rm_list
, ed
= *last
; ed
!= NULL
; ed
= *last
) {
979 struct list_head
*entry
, *tmp
;
980 int completed
, modified
;
983 /* Is this ED already invisible to the hardware? */
984 if (ed
->state
== ED_IDLE
)
987 /* only take off EDs that the HC isn't using, accounting for
988 * frame counter wraps and EDs with partially retired TDs
990 if (likely(ohci
->rh_state
== OHCI_RH_RUNNING
) &&
991 tick_before(tick
, ed
->tick
)) {
996 if (!list_empty(&ed
->td_list
)) {
1000 td
= list_first_entry(&ed
->td_list
, struct td
, td_list
);
1002 /* INTR_WDH may need to clean up first */
1003 head
= hc32_to_cpu(ohci
, ed
->hwHeadP
) & TD_MASK
;
1004 if (td
->td_dma
!= head
&&
1005 ohci
->rh_state
== OHCI_RH_RUNNING
)
1008 /* Don't mess up anything already on the done list */
1013 /* ED's now officially unlinked, hc doesn't see */
1014 ed
->state
= ED_IDLE
;
1015 ed
->hwHeadP
&= ~cpu_to_hc32(ohci
, ED_H
);
1018 ed
->hwINFO
&= ~cpu_to_hc32(ohci
, ED_SKIP
| ED_DEQUEUE
);
1021 /* reentrancy: if we drop the schedule lock, someone might
1022 * have modified this list. normally it's just prepending
1023 * entries (which we'd ignore), but paranoia won't hurt.
1027 /* unlink urbs as requested, but rescan the list after
1028 * we call a completion since it might have unlinked
1029 * another (earlier) urb
1031 * When we get here, the HC doesn't see this ed. But it
1032 * must not be rescheduled until all completed URBs have
1033 * been given back to the driver.
1037 prev
= &ed
->hwHeadP
;
1038 list_for_each_safe (entry
, tmp
, &ed
->td_list
) {
1041 urb_priv_t
*urb_priv
;
1045 td
= list_entry (entry
, struct td
, td_list
);
1047 urb_priv
= td
->urb
->hcpriv
;
1049 if (!urb
->unlinked
) {
1050 prev
= &td
->hwNextTD
;
1054 /* patch pointer hc uses */
1055 savebits
= *prev
& ~cpu_to_hc32 (ohci
, TD_MASK
);
1056 *prev
= td
->hwNextTD
| savebits
;
1058 /* If this was unlinked, the TD may not have been
1059 * retired ... so manually save the data toggle.
1060 * The controller ignores the value we save for
1061 * control and ISO endpoints.
1063 tdINFO
= hc32_to_cpup(ohci
, &td
->hwINFO
);
1064 if ((tdINFO
& TD_T
) == TD_T_DATA0
)
1065 ed
->hwHeadP
&= ~cpu_to_hc32(ohci
, ED_C
);
1066 else if ((tdINFO
& TD_T
) == TD_T_DATA1
)
1067 ed
->hwHeadP
|= cpu_to_hc32(ohci
, ED_C
);
1069 /* HC may have partly processed this TD */
1070 td_done (ohci
, urb
, td
);
1073 /* if URB is done, clean up */
1074 if (urb_priv
->td_cnt
>= urb_priv
->length
) {
1075 modified
= completed
= 1;
1076 finish_urb(ohci
, urb
, 0);
1079 if (completed
&& !list_empty (&ed
->td_list
))
1083 * If no TDs are queued, take ED off the ed_rm_list.
1084 * Otherwise, if the HC is running, reschedule.
1085 * If not, leave it on the list for further dequeues.
1087 if (list_empty(&ed
->td_list
)) {
1088 *last
= ed
->ed_next
;
1090 list_del(&ed
->in_use_list
);
1091 } else if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
1092 *last
= ed
->ed_next
;
1094 ed_schedule(ohci
, ed
);
1096 last
= &ed
->ed_next
;
1103 /* maybe reenable control and bulk lists */
1104 if (ohci
->rh_state
== OHCI_RH_RUNNING
&& !ohci
->ed_rm_list
) {
1105 u32 command
= 0, control
= 0;
1107 if (ohci
->ed_controltail
) {
1108 command
|= OHCI_CLF
;
1109 if (quirk_zfmicro(ohci
))
1111 if (!(ohci
->hc_control
& OHCI_CTRL_CLE
)) {
1112 control
|= OHCI_CTRL_CLE
;
1113 ohci_writel (ohci
, 0,
1114 &ohci
->regs
->ed_controlcurrent
);
1117 if (ohci
->ed_bulktail
) {
1118 command
|= OHCI_BLF
;
1119 if (quirk_zfmicro(ohci
))
1121 if (!(ohci
->hc_control
& OHCI_CTRL_BLE
)) {
1122 control
|= OHCI_CTRL_BLE
;
1123 ohci_writel (ohci
, 0,
1124 &ohci
->regs
->ed_bulkcurrent
);
1128 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1130 ohci
->hc_control
|= control
;
1131 if (quirk_zfmicro(ohci
))
1133 ohci_writel (ohci
, ohci
->hc_control
,
1134 &ohci
->regs
->control
);
1137 if (quirk_zfmicro(ohci
))
1139 ohci_writel (ohci
, command
, &ohci
->regs
->cmdstatus
);
1146 /*-------------------------------------------------------------------------*/
1148 /* Take back a TD from the host controller */
1149 static void takeback_td(struct ohci_hcd
*ohci
, struct td
*td
)
1151 struct urb
*urb
= td
->urb
;
1152 urb_priv_t
*urb_priv
= urb
->hcpriv
;
1153 struct ed
*ed
= td
->ed
;
1156 /* update URB's length and status from TD */
1157 status
= td_done(ohci
, urb
, td
);
1160 /* If all this urb's TDs are done, call complete() */
1161 if (urb_priv
->td_cnt
>= urb_priv
->length
)
1162 finish_urb(ohci
, urb
, status
);
1164 /* clean schedule: unlink EDs that are no longer busy */
1165 if (list_empty(&ed
->td_list
)) {
1166 if (ed
->state
== ED_OPER
)
1167 start_ed_unlink(ohci
, ed
);
1169 /* ... reenabling halted EDs only after fault cleanup */
1170 } else if ((ed
->hwINFO
& cpu_to_hc32(ohci
, ED_SKIP
| ED_DEQUEUE
))
1171 == cpu_to_hc32(ohci
, ED_SKIP
)) {
1172 td
= list_entry(ed
->td_list
.next
, struct td
, td_list
);
1173 if (!(td
->hwINFO
& cpu_to_hc32(ohci
, TD_DONE
))) {
1174 ed
->hwINFO
&= ~cpu_to_hc32(ohci
, ED_SKIP
);
1175 /* ... hc may need waking-up */
1178 ohci_writel(ohci
, OHCI_CLF
,
1179 &ohci
->regs
->cmdstatus
);
1182 ohci_writel(ohci
, OHCI_BLF
,
1183 &ohci
->regs
->cmdstatus
);
1191 * Process normal completions (error or success) and clean the schedules.
1193 * This is the main path for handing urbs back to drivers. The only other
1194 * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1195 * instead of scanning the (re-reversed) donelist as this does.
1197 static void process_done_list(struct ohci_hcd
*ohci
)
1201 while (ohci
->dl_start
) {
1202 td
= ohci
->dl_start
;
1203 if (td
== ohci
->dl_end
)
1204 ohci
->dl_start
= ohci
->dl_end
= NULL
;
1206 ohci
->dl_start
= td
->next_dl_td
;
1208 takeback_td(ohci
, td
);
1213 * TD takeback and URB giveback must be single-threaded.
1214 * This routine takes care of it all.
1216 static void ohci_work(struct ohci_hcd
*ohci
)
1218 if (ohci
->working
) {
1219 ohci
->restart_work
= 1;
1225 process_done_list(ohci
);
1226 if (ohci
->ed_rm_list
)
1227 finish_unlinks(ohci
);
1229 if (ohci
->restart_work
) {
1230 ohci
->restart_work
= 0;
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