2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
18 * Intel documents this fairly well, and as far as I know there
19 * are no royalties or anything like that, but even so there are
20 * people who decided that they want to do the same thing in a
21 * completely different way.
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/unistd.h>
34 #include <linux/interrupt.h>
35 #include <linux/spinlock.h>
36 #include <linux/debugfs.h>
38 #include <linux/dmapool.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/usb.h>
41 #include <linux/usb/hcd.h>
42 #include <linux/bitops.h>
43 #include <linux/dmi.h>
45 #include <asm/uaccess.h>
48 #include <asm/system.h>
55 #define DRIVER_AUTHOR \
56 "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \
57 "Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \
58 "Roman Weissgaerber, Alan Stern"
59 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
61 /* for flakey hardware, ignore overcurrent indicators */
62 static bool ignore_oc
;
63 module_param(ignore_oc
, bool, S_IRUGO
);
64 MODULE_PARM_DESC(ignore_oc
, "ignore hardware overcurrent indications");
67 * debug = 0, no debugging messages
68 * debug = 1, dump failed URBs except for stalls
69 * debug = 2, dump all failed URBs (including stalls)
70 * show all queues in /sys/kernel/debug/uhci/[pci_addr]
71 * debug = 3, show all TDs in URBs when dumping
74 #define DEBUG_CONFIGURED 1
76 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
77 MODULE_PARM_DESC(debug
, "Debug level");
80 #define DEBUG_CONFIGURED 0
85 #define ERRBUF_LEN (32 * 1024)
87 static struct kmem_cache
*uhci_up_cachep
; /* urb_priv */
89 static void suspend_rh(struct uhci_hcd
*uhci
, enum uhci_rh_state new_state
);
90 static void wakeup_rh(struct uhci_hcd
*uhci
);
91 static void uhci_get_current_frame_number(struct uhci_hcd
*uhci
);
94 * Calculate the link pointer DMA value for the first Skeleton QH in a frame.
96 static __hc32
uhci_frame_skel_link(struct uhci_hcd
*uhci
, int frame
)
101 * The interrupt queues will be interleaved as evenly as possible.
102 * There's not much to be done about period-1 interrupts; they have
103 * to occur in every frame. But we can schedule period-2 interrupts
104 * in odd-numbered frames, period-4 interrupts in frames congruent
105 * to 2 (mod 4), and so on. This way each frame only has two
106 * interrupt QHs, which will help spread out bandwidth utilization.
108 * ffs (Find First bit Set) does exactly what we need:
109 * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8],
110 * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc.
111 * ffs >= 7 => not on any high-period queue, so use
112 * period-1 QH = skelqh[9].
113 * Add in UHCI_NUMFRAMES to insure at least one bit is set.
115 skelnum
= 8 - (int) __ffs(frame
| UHCI_NUMFRAMES
);
118 return LINK_TO_QH(uhci
, uhci
->skelqh
[skelnum
]);
121 #include "uhci-debug.c"
123 #include "uhci-hub.c"
126 * Finish up a host controller reset and update the recorded state.
128 static void finish_reset(struct uhci_hcd
*uhci
)
132 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
133 * bits in the port status and control registers.
134 * We have to clear them by hand.
136 for (port
= 0; port
< uhci
->rh_numports
; ++port
)
137 uhci_writew(uhci
, 0, USBPORTSC1
+ (port
* 2));
139 uhci
->port_c_suspend
= uhci
->resuming_ports
= 0;
140 uhci
->rh_state
= UHCI_RH_RESET
;
141 uhci
->is_stopped
= UHCI_IS_STOPPED
;
142 clear_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
146 * Last rites for a defunct/nonfunctional controller
147 * or one we don't want to use any more.
149 static void uhci_hc_died(struct uhci_hcd
*uhci
)
151 uhci_get_current_frame_number(uhci
);
152 uhci
->reset_hc(uhci
);
156 /* The current frame may already be partway finished */
157 ++uhci
->frame_number
;
161 * Initialize a controller that was newly discovered or has lost power
162 * or otherwise been reset while it was suspended. In none of these cases
163 * can we be sure of its previous state.
165 static void check_and_reset_hc(struct uhci_hcd
*uhci
)
167 if (uhci
->check_and_reset_hc(uhci
))
171 #if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC)
173 * The two functions below are generic reset functions that are used on systems
174 * that do not have keyboard and mouse legacy support. We assume that we are
175 * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined.
179 * Make sure the controller is completely inactive, unable to
180 * generate interrupts or do DMA.
182 static void uhci_generic_reset_hc(struct uhci_hcd
*uhci
)
184 /* Reset the HC - this will force us to get a
185 * new notification of any already connected
186 * ports due to the virtual disconnect that it
189 uhci_writew(uhci
, USBCMD_HCRESET
, USBCMD
);
192 if (uhci_readw(uhci
, USBCMD
) & USBCMD_HCRESET
)
193 dev_warn(uhci_dev(uhci
), "HCRESET not completed yet!\n");
195 /* Just to be safe, disable interrupt requests and
196 * make sure the controller is stopped.
198 uhci_writew(uhci
, 0, USBINTR
);
199 uhci_writew(uhci
, 0, USBCMD
);
203 * Initialize a controller that was newly discovered or has just been
204 * resumed. In either case we can't be sure of its previous state.
206 * Returns: 1 if the controller was reset, 0 otherwise.
208 static int uhci_generic_check_and_reset_hc(struct uhci_hcd
*uhci
)
210 unsigned int cmd
, intr
;
213 * When restarting a suspended controller, we expect all the
214 * settings to be the same as we left them:
216 * Controller is stopped and configured with EGSM set;
217 * No interrupts enabled except possibly Resume Detect.
219 * If any of these conditions are violated we do a complete reset.
222 cmd
= uhci_readw(uhci
, USBCMD
);
223 if ((cmd
& USBCMD_RS
) || !(cmd
& USBCMD_CF
) || !(cmd
& USBCMD_EGSM
)) {
224 dev_dbg(uhci_dev(uhci
), "%s: cmd = 0x%04x\n",
229 intr
= uhci_readw(uhci
, USBINTR
);
230 if (intr
& (~USBINTR_RESUME
)) {
231 dev_dbg(uhci_dev(uhci
), "%s: intr = 0x%04x\n",
238 dev_dbg(uhci_dev(uhci
), "Performing full reset\n");
239 uhci_generic_reset_hc(uhci
);
242 #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
245 * Store the basic register settings needed by the controller.
247 static void configure_hc(struct uhci_hcd
*uhci
)
249 /* Set the frame length to the default: 1 ms exactly */
250 uhci_writeb(uhci
, USBSOF_DEFAULT
, USBSOF
);
252 /* Store the frame list base address */
253 uhci_writel(uhci
, uhci
->frame_dma_handle
, USBFLBASEADD
);
255 /* Set the current frame number */
256 uhci_writew(uhci
, uhci
->frame_number
& UHCI_MAX_SOF_NUMBER
,
259 /* perform any arch/bus specific configuration */
260 if (uhci
->configure_hc
)
261 uhci
->configure_hc(uhci
);
264 static int resume_detect_interrupts_are_broken(struct uhci_hcd
*uhci
)
266 /* If we have to ignore overcurrent events then almost by definition
267 * we can't depend on resume-detect interrupts. */
271 return uhci
->resume_detect_interrupts_are_broken
?
272 uhci
->resume_detect_interrupts_are_broken(uhci
) : 0;
275 static int global_suspend_mode_is_broken(struct uhci_hcd
*uhci
)
277 return uhci
->global_suspend_mode_is_broken
?
278 uhci
->global_suspend_mode_is_broken(uhci
) : 0;
281 static void suspend_rh(struct uhci_hcd
*uhci
, enum uhci_rh_state new_state
)
282 __releases(uhci
->lock
)
283 __acquires(uhci
->lock
)
286 int int_enable
, egsm_enable
, wakeup_enable
;
287 struct usb_device
*rhdev
= uhci_to_hcd(uhci
)->self
.root_hub
;
289 auto_stop
= (new_state
== UHCI_RH_AUTO_STOPPED
);
290 dev_dbg(&rhdev
->dev
, "%s%s\n", __func__
,
291 (auto_stop
? " (auto-stop)" : ""));
293 /* Start off by assuming Resume-Detect interrupts and EGSM work
294 * and that remote wakeups should be enabled.
296 egsm_enable
= USBCMD_EGSM
;
297 int_enable
= USBINTR_RESUME
;
301 * In auto-stop mode, we must be able to detect new connections.
302 * The user can force us to poll by disabling remote wakeup;
303 * otherwise we will use the EGSM/RD mechanism.
306 if (!device_may_wakeup(&rhdev
->dev
))
307 egsm_enable
= int_enable
= 0;
312 * In bus-suspend mode, we use the wakeup setting specified
316 if (!rhdev
->do_remote_wakeup
)
322 * UHCI doesn't distinguish between wakeup requests from downstream
323 * devices and local connect/disconnect events. There's no way to
324 * enable one without the other; both are controlled by EGSM. Thus
325 * if wakeups are disallowed then EGSM must be turned off -- in which
326 * case remote wakeup requests from downstream during system sleep
329 * In addition, if EGSM is broken then we can't use it. Likewise,
330 * if Resume-Detect interrupts are broken then we can't use them.
332 * Finally, neither EGSM nor RD is useful by itself. Without EGSM,
333 * the RD status bit will never get set. Without RD, the controller
334 * won't generate interrupts to tell the system about wakeup events.
336 if (!wakeup_enable
|| global_suspend_mode_is_broken(uhci
) ||
337 resume_detect_interrupts_are_broken(uhci
))
338 egsm_enable
= int_enable
= 0;
340 uhci
->RD_enable
= !!int_enable
;
341 uhci_writew(uhci
, int_enable
, USBINTR
);
342 uhci_writew(uhci
, egsm_enable
| USBCMD_CF
, USBCMD
);
346 /* If we're auto-stopping then no devices have been attached
347 * for a while, so there shouldn't be any active URBs and the
348 * controller should stop after a few microseconds. Otherwise
349 * we will give the controller one frame to stop.
351 if (!auto_stop
&& !(uhci_readw(uhci
, USBSTS
) & USBSTS_HCH
)) {
352 uhci
->rh_state
= UHCI_RH_SUSPENDING
;
353 spin_unlock_irq(&uhci
->lock
);
355 spin_lock_irq(&uhci
->lock
);
359 if (!(uhci_readw(uhci
, USBSTS
) & USBSTS_HCH
))
360 dev_warn(uhci_dev(uhci
), "Controller not stopped yet!\n");
362 uhci_get_current_frame_number(uhci
);
364 uhci
->rh_state
= new_state
;
365 uhci
->is_stopped
= UHCI_IS_STOPPED
;
368 * If remote wakeup is enabled but either EGSM or RD interrupts
369 * doesn't work, then we won't get an interrupt when a wakeup event
370 * occurs. Thus the suspended root hub needs to be polled.
372 if (wakeup_enable
&& (!int_enable
|| !egsm_enable
))
373 set_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
375 clear_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
377 uhci_scan_schedule(uhci
);
381 static void start_rh(struct uhci_hcd
*uhci
)
383 uhci
->is_stopped
= 0;
385 /* Mark it configured and running with a 64-byte max packet.
386 * All interrupts are enabled, even though RESUME won't do anything.
388 uhci_writew(uhci
, USBCMD_RS
| USBCMD_CF
| USBCMD_MAXP
, USBCMD
);
389 uhci_writew(uhci
, USBINTR_TIMEOUT
| USBINTR_RESUME
|
390 USBINTR_IOC
| USBINTR_SP
, USBINTR
);
392 uhci
->rh_state
= UHCI_RH_RUNNING
;
393 set_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
396 static void wakeup_rh(struct uhci_hcd
*uhci
)
397 __releases(uhci
->lock
)
398 __acquires(uhci
->lock
)
400 dev_dbg(&uhci_to_hcd(uhci
)->self
.root_hub
->dev
,
402 uhci
->rh_state
== UHCI_RH_AUTO_STOPPED
?
403 " (auto-start)" : "");
405 /* If we are auto-stopped then no devices are attached so there's
406 * no need for wakeup signals. Otherwise we send Global Resume
409 if (uhci
->rh_state
== UHCI_RH_SUSPENDED
) {
412 /* Keep EGSM on if it was set before */
413 egsm
= uhci_readw(uhci
, USBCMD
) & USBCMD_EGSM
;
414 uhci
->rh_state
= UHCI_RH_RESUMING
;
415 uhci_writew(uhci
, USBCMD_FGR
| USBCMD_CF
| egsm
, USBCMD
);
416 spin_unlock_irq(&uhci
->lock
);
418 spin_lock_irq(&uhci
->lock
);
422 /* End Global Resume and wait for EOP to be sent */
423 uhci_writew(uhci
, USBCMD_CF
, USBCMD
);
426 if (uhci_readw(uhci
, USBCMD
) & USBCMD_FGR
)
427 dev_warn(uhci_dev(uhci
), "FGR not stopped yet!\n");
432 /* Restart root hub polling */
433 mod_timer(&uhci_to_hcd(uhci
)->rh_timer
, jiffies
);
436 static irqreturn_t
uhci_irq(struct usb_hcd
*hcd
)
438 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
439 unsigned short status
;
442 * Read the interrupt status, and write it back to clear the
443 * interrupt cause. Contrary to the UHCI specification, the
444 * "HC Halted" status bit is persistent: it is RO, not R/WC.
446 status
= uhci_readw(uhci
, USBSTS
);
447 if (!(status
& ~USBSTS_HCH
)) /* shared interrupt, not mine */
449 uhci_writew(uhci
, status
, USBSTS
); /* Clear it */
451 if (status
& ~(USBSTS_USBINT
| USBSTS_ERROR
| USBSTS_RD
)) {
452 if (status
& USBSTS_HSE
)
453 dev_err(uhci_dev(uhci
), "host system error, "
455 if (status
& USBSTS_HCPE
)
456 dev_err(uhci_dev(uhci
), "host controller process "
457 "error, something bad happened!\n");
458 if (status
& USBSTS_HCH
) {
459 spin_lock(&uhci
->lock
);
460 if (uhci
->rh_state
>= UHCI_RH_RUNNING
) {
461 dev_err(uhci_dev(uhci
),
462 "host controller halted, "
464 if (debug
> 1 && errbuf
) {
465 /* Print the schedule for debugging */
466 uhci_sprint_schedule(uhci
,
473 /* Force a callback in case there are
475 mod_timer(&hcd
->rh_timer
, jiffies
);
477 spin_unlock(&uhci
->lock
);
481 if (status
& USBSTS_RD
)
482 usb_hcd_poll_rh_status(hcd
);
484 spin_lock(&uhci
->lock
);
485 uhci_scan_schedule(uhci
);
486 spin_unlock(&uhci
->lock
);
493 * Store the current frame number in uhci->frame_number if the controller
494 * is running. Expand from 11 bits (of which we use only 10) to a
495 * full-sized integer.
497 * Like many other parts of the driver, this code relies on being polled
498 * more than once per second as long as the controller is running.
500 static void uhci_get_current_frame_number(struct uhci_hcd
*uhci
)
502 if (!uhci
->is_stopped
) {
505 delta
= (uhci_readw(uhci
, USBFRNUM
) - uhci
->frame_number
) &
506 (UHCI_NUMFRAMES
- 1);
507 uhci
->frame_number
+= delta
;
512 * De-allocate all resources
514 static void release_uhci(struct uhci_hcd
*uhci
)
518 if (DEBUG_CONFIGURED
) {
519 spin_lock_irq(&uhci
->lock
);
520 uhci
->is_initialized
= 0;
521 spin_unlock_irq(&uhci
->lock
);
523 debugfs_remove(uhci
->dentry
);
526 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++)
527 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
529 uhci_free_td(uhci
, uhci
->term_td
);
531 dma_pool_destroy(uhci
->qh_pool
);
533 dma_pool_destroy(uhci
->td_pool
);
535 kfree(uhci
->frame_cpu
);
537 dma_free_coherent(uhci_dev(uhci
),
538 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
539 uhci
->frame
, uhci
->frame_dma_handle
);
543 * Allocate a frame list, and then setup the skeleton
545 * The hardware doesn't really know any difference
546 * in the queues, but the order does matter for the
547 * protocols higher up. The order in which the queues
548 * are encountered by the hardware is:
550 * - All isochronous events are handled before any
551 * of the queues. We don't do that here, because
552 * we'll create the actual TD entries on demand.
553 * - The first queue is the high-period interrupt queue.
554 * - The second queue is the period-1 interrupt and async
555 * (low-speed control, full-speed control, then bulk) queue.
556 * - The third queue is the terminating bandwidth reclamation queue,
557 * which contains no members, loops back to itself, and is present
558 * only when FSBR is on and there are no full-speed control or bulk QHs.
560 static int uhci_start(struct usb_hcd
*hcd
)
562 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
565 struct dentry __maybe_unused
*dentry
;
567 hcd
->uses_new_polling
= 1;
568 /* Accept arbitrarily long scatter-gather lists */
569 if (!(hcd
->driver
->flags
& HCD_LOCAL_MEM
))
570 hcd
->self
.sg_tablesize
= ~0;
572 spin_lock_init(&uhci
->lock
);
573 setup_timer(&uhci
->fsbr_timer
, uhci_fsbr_timeout
,
574 (unsigned long) uhci
);
575 INIT_LIST_HEAD(&uhci
->idle_qh_list
);
576 init_waitqueue_head(&uhci
->waitqh
);
578 #ifdef UHCI_DEBUG_OPS
579 dentry
= debugfs_create_file(hcd
->self
.bus_name
,
580 S_IFREG
|S_IRUGO
|S_IWUSR
, uhci_debugfs_root
,
581 uhci
, &uhci_debug_operations
);
583 dev_err(uhci_dev(uhci
), "couldn't create uhci debugfs entry\n");
586 uhci
->dentry
= dentry
;
589 uhci
->frame
= dma_alloc_coherent(uhci_dev(uhci
),
590 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
591 &uhci
->frame_dma_handle
, 0);
593 dev_err(uhci_dev(uhci
), "unable to allocate "
594 "consistent memory for frame list\n");
595 goto err_alloc_frame
;
597 memset(uhci
->frame
, 0, UHCI_NUMFRAMES
* sizeof(*uhci
->frame
));
599 uhci
->frame_cpu
= kcalloc(UHCI_NUMFRAMES
, sizeof(*uhci
->frame_cpu
),
601 if (!uhci
->frame_cpu
) {
602 dev_err(uhci_dev(uhci
), "unable to allocate "
603 "memory for frame pointers\n");
604 goto err_alloc_frame_cpu
;
607 uhci
->td_pool
= dma_pool_create("uhci_td", uhci_dev(uhci
),
608 sizeof(struct uhci_td
), 16, 0);
609 if (!uhci
->td_pool
) {
610 dev_err(uhci_dev(uhci
), "unable to create td dma_pool\n");
611 goto err_create_td_pool
;
614 uhci
->qh_pool
= dma_pool_create("uhci_qh", uhci_dev(uhci
),
615 sizeof(struct uhci_qh
), 16, 0);
616 if (!uhci
->qh_pool
) {
617 dev_err(uhci_dev(uhci
), "unable to create qh dma_pool\n");
618 goto err_create_qh_pool
;
621 uhci
->term_td
= uhci_alloc_td(uhci
);
622 if (!uhci
->term_td
) {
623 dev_err(uhci_dev(uhci
), "unable to allocate terminating TD\n");
624 goto err_alloc_term_td
;
627 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++) {
628 uhci
->skelqh
[i
] = uhci_alloc_qh(uhci
, NULL
, NULL
);
629 if (!uhci
->skelqh
[i
]) {
630 dev_err(uhci_dev(uhci
), "unable to allocate QH\n");
631 goto err_alloc_skelqh
;
636 * 8 Interrupt queues; link all higher int queues to int1 = async
638 for (i
= SKEL_ISO
+ 1; i
< SKEL_ASYNC
; ++i
)
639 uhci
->skelqh
[i
]->link
= LINK_TO_QH(uhci
, uhci
->skel_async_qh
);
640 uhci
->skel_async_qh
->link
= UHCI_PTR_TERM(uhci
);
641 uhci
->skel_term_qh
->link
= LINK_TO_QH(uhci
, uhci
->skel_term_qh
);
643 /* This dummy TD is to work around a bug in Intel PIIX controllers */
644 uhci_fill_td(uhci
, uhci
->term_td
, 0, uhci_explen(0) |
645 (0x7f << TD_TOKEN_DEVADDR_SHIFT
) | USB_PID_IN
, 0);
646 uhci
->term_td
->link
= UHCI_PTR_TERM(uhci
);
647 uhci
->skel_async_qh
->element
= uhci
->skel_term_qh
->element
=
648 LINK_TO_TD(uhci
, uhci
->term_td
);
651 * Fill the frame list: make all entries point to the proper
654 for (i
= 0; i
< UHCI_NUMFRAMES
; i
++) {
656 /* Only place we don't use the frame list routines */
657 uhci
->frame
[i
] = uhci_frame_skel_link(uhci
, i
);
661 * Some architectures require a full mb() to enforce completion of
662 * the memory writes above before the I/O transfers in configure_hc().
667 uhci
->is_initialized
= 1;
668 spin_lock_irq(&uhci
->lock
);
670 spin_unlock_irq(&uhci
->lock
);
677 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++) {
679 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
682 uhci_free_td(uhci
, uhci
->term_td
);
685 dma_pool_destroy(uhci
->qh_pool
);
688 dma_pool_destroy(uhci
->td_pool
);
691 kfree(uhci
->frame_cpu
);
694 dma_free_coherent(uhci_dev(uhci
),
695 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
696 uhci
->frame
, uhci
->frame_dma_handle
);
699 debugfs_remove(uhci
->dentry
);
704 static void uhci_stop(struct usb_hcd
*hcd
)
706 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
708 spin_lock_irq(&uhci
->lock
);
709 if (HCD_HW_ACCESSIBLE(hcd
) && !uhci
->dead
)
711 uhci_scan_schedule(uhci
);
712 spin_unlock_irq(&uhci
->lock
);
713 synchronize_irq(hcd
->irq
);
715 del_timer_sync(&uhci
->fsbr_timer
);
720 static int uhci_rh_suspend(struct usb_hcd
*hcd
)
722 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
725 spin_lock_irq(&uhci
->lock
);
726 if (!HCD_HW_ACCESSIBLE(hcd
))
729 ; /* Dead controllers tell no tales */
731 /* Once the controller is stopped, port resumes that are already
732 * in progress won't complete. Hence if remote wakeup is enabled
733 * for the root hub and any ports are in the middle of a resume or
734 * remote wakeup, we must fail the suspend.
736 else if (hcd
->self
.root_hub
->do_remote_wakeup
&&
737 uhci
->resuming_ports
) {
738 dev_dbg(uhci_dev(uhci
), "suspend failed because a port "
742 suspend_rh(uhci
, UHCI_RH_SUSPENDED
);
743 spin_unlock_irq(&uhci
->lock
);
747 static int uhci_rh_resume(struct usb_hcd
*hcd
)
749 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
752 spin_lock_irq(&uhci
->lock
);
753 if (!HCD_HW_ACCESSIBLE(hcd
))
755 else if (!uhci
->dead
)
757 spin_unlock_irq(&uhci
->lock
);
763 /* Wait until a particular device/endpoint's QH is idle, and free it */
764 static void uhci_hcd_endpoint_disable(struct usb_hcd
*hcd
,
765 struct usb_host_endpoint
*hep
)
767 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
770 spin_lock_irq(&uhci
->lock
);
771 qh
= (struct uhci_qh
*) hep
->hcpriv
;
775 while (qh
->state
!= QH_STATE_IDLE
) {
777 spin_unlock_irq(&uhci
->lock
);
778 wait_event_interruptible(uhci
->waitqh
,
779 qh
->state
== QH_STATE_IDLE
);
780 spin_lock_irq(&uhci
->lock
);
784 uhci_free_qh(uhci
, qh
);
786 spin_unlock_irq(&uhci
->lock
);
789 static int uhci_hcd_get_frame_number(struct usb_hcd
*hcd
)
791 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
792 unsigned frame_number
;
795 /* Minimize latency by avoiding the spinlock */
796 frame_number
= uhci
->frame_number
;
798 delta
= (uhci_readw(uhci
, USBFRNUM
) - frame_number
) &
799 (UHCI_NUMFRAMES
- 1);
800 return frame_number
+ delta
;
803 /* Determines number of ports on controller */
804 static int uhci_count_ports(struct usb_hcd
*hcd
)
806 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
807 unsigned io_size
= (unsigned) hcd
->rsrc_len
;
810 /* The UHCI spec says devices must have 2 ports, and goes on to say
811 * they may have more but gives no way to determine how many there
812 * are. However according to the UHCI spec, Bit 7 of the port
813 * status and control register is always set to 1. So we try to
814 * use this to our advantage. Another common failure mode when
815 * a nonexistent register is addressed is to return all ones, so
816 * we test for that also.
818 for (port
= 0; port
< (io_size
- USBPORTSC1
) / 2; port
++) {
819 unsigned int portstatus
;
821 portstatus
= uhci_readw(uhci
, USBPORTSC1
+ (port
* 2));
822 if (!(portstatus
& 0x0080) || portstatus
== 0xffff)
826 dev_info(uhci_dev(uhci
), "detected %d ports\n", port
);
828 /* Anything greater than 7 is weird so we'll ignore it. */
829 if (port
> UHCI_RH_MAXCHILD
) {
830 dev_info(uhci_dev(uhci
), "port count misdetected? "
831 "forcing to 2 ports\n");
838 static const char hcd_name
[] = "uhci_hcd";
841 #include "uhci-pci.c"
842 #define PCI_DRIVER uhci_pci_driver
845 #ifdef CONFIG_SPARC_LEON
846 #include "uhci-grlib.c"
847 #define PLATFORM_DRIVER uhci_grlib_driver
850 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
851 #error "missing bus glue for uhci-hcd"
854 static int __init
uhci_hcd_init(void)
856 int retval
= -ENOMEM
;
861 printk(KERN_INFO
"uhci_hcd: " DRIVER_DESC
"%s\n",
862 ignore_oc
? ", overcurrent ignored" : "");
863 set_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
865 if (DEBUG_CONFIGURED
) {
866 errbuf
= kmalloc(ERRBUF_LEN
, GFP_KERNEL
);
869 uhci_debugfs_root
= debugfs_create_dir("uhci", usb_debug_root
);
870 if (!uhci_debugfs_root
)
874 uhci_up_cachep
= kmem_cache_create("uhci_urb_priv",
875 sizeof(struct urb_priv
), 0, 0, NULL
);
879 #ifdef PLATFORM_DRIVER
880 retval
= platform_driver_register(&PLATFORM_DRIVER
);
886 retval
= pci_register_driver(&PCI_DRIVER
);
896 #ifdef PLATFORM_DRIVER
897 platform_driver_unregister(&PLATFORM_DRIVER
);
900 kmem_cache_destroy(uhci_up_cachep
);
903 debugfs_remove(uhci_debugfs_root
);
910 clear_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
914 static void __exit
uhci_hcd_cleanup(void)
916 #ifdef PLATFORM_DRIVER
917 platform_driver_unregister(&PLATFORM_DRIVER
);
920 pci_unregister_driver(&PCI_DRIVER
);
922 kmem_cache_destroy(uhci_up_cachep
);
923 debugfs_remove(uhci_debugfs_root
);
925 clear_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
928 module_init(uhci_hcd_init
);
929 module_exit(uhci_hcd_cleanup
);
931 MODULE_AUTHOR(DRIVER_AUTHOR
);
932 MODULE_DESCRIPTION(DRIVER_DESC
);
933 MODULE_LICENSE("GPL");