2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
18 * Intel documents this fairly well, and as far as I know there
19 * are no royalties or anything like that, but even so there are
20 * people who decided that they want to do the same thing in a
21 * completely different way.
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/unistd.h>
34 #include <linux/interrupt.h>
35 #include <linux/spinlock.h>
36 #include <linux/debugfs.h>
38 #include <linux/dmapool.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/usb.h>
41 #include <linux/usb/hcd.h>
42 #include <linux/bitops.h>
43 #include <linux/dmi.h>
45 #include <asm/uaccess.h>
54 #define DRIVER_AUTHOR \
55 "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \
56 "Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \
57 "Roman Weissgaerber, Alan Stern"
58 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
60 /* for flakey hardware, ignore overcurrent indicators */
61 static bool ignore_oc
;
62 module_param(ignore_oc
, bool, S_IRUGO
);
63 MODULE_PARM_DESC(ignore_oc
, "ignore hardware overcurrent indications");
66 * debug = 0, no debugging messages
67 * debug = 1, dump failed URBs except for stalls
68 * debug = 2, dump all failed URBs (including stalls)
69 * show all queues in /sys/kernel/debug/uhci/[pci_addr]
70 * debug = 3, show all TDs in URBs when dumping
73 #define DEBUG_CONFIGURED 1
75 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
76 MODULE_PARM_DESC(debug
, "Debug level");
79 #define DEBUG_CONFIGURED 0
84 #define ERRBUF_LEN (32 * 1024)
86 static struct kmem_cache
*uhci_up_cachep
; /* urb_priv */
88 static void suspend_rh(struct uhci_hcd
*uhci
, enum uhci_rh_state new_state
);
89 static void wakeup_rh(struct uhci_hcd
*uhci
);
90 static void uhci_get_current_frame_number(struct uhci_hcd
*uhci
);
93 * Calculate the link pointer DMA value for the first Skeleton QH in a frame.
95 static __hc32
uhci_frame_skel_link(struct uhci_hcd
*uhci
, int frame
)
100 * The interrupt queues will be interleaved as evenly as possible.
101 * There's not much to be done about period-1 interrupts; they have
102 * to occur in every frame. But we can schedule period-2 interrupts
103 * in odd-numbered frames, period-4 interrupts in frames congruent
104 * to 2 (mod 4), and so on. This way each frame only has two
105 * interrupt QHs, which will help spread out bandwidth utilization.
107 * ffs (Find First bit Set) does exactly what we need:
108 * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8],
109 * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc.
110 * ffs >= 7 => not on any high-period queue, so use
111 * period-1 QH = skelqh[9].
112 * Add in UHCI_NUMFRAMES to insure at least one bit is set.
114 skelnum
= 8 - (int) __ffs(frame
| UHCI_NUMFRAMES
);
117 return LINK_TO_QH(uhci
, uhci
->skelqh
[skelnum
]);
120 #include "uhci-debug.c"
122 #include "uhci-hub.c"
125 * Finish up a host controller reset and update the recorded state.
127 static void finish_reset(struct uhci_hcd
*uhci
)
131 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
132 * bits in the port status and control registers.
133 * We have to clear them by hand.
135 for (port
= 0; port
< uhci
->rh_numports
; ++port
)
136 uhci_writew(uhci
, 0, USBPORTSC1
+ (port
* 2));
138 uhci
->port_c_suspend
= uhci
->resuming_ports
= 0;
139 uhci
->rh_state
= UHCI_RH_RESET
;
140 uhci
->is_stopped
= UHCI_IS_STOPPED
;
141 clear_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
145 * Last rites for a defunct/nonfunctional controller
146 * or one we don't want to use any more.
148 static void uhci_hc_died(struct uhci_hcd
*uhci
)
150 uhci_get_current_frame_number(uhci
);
151 uhci
->reset_hc(uhci
);
155 /* The current frame may already be partway finished */
156 ++uhci
->frame_number
;
160 * Initialize a controller that was newly discovered or has lost power
161 * or otherwise been reset while it was suspended. In none of these cases
162 * can we be sure of its previous state.
164 static void check_and_reset_hc(struct uhci_hcd
*uhci
)
166 if (uhci
->check_and_reset_hc(uhci
))
170 #if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC)
172 * The two functions below are generic reset functions that are used on systems
173 * that do not have keyboard and mouse legacy support. We assume that we are
174 * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined.
178 * Make sure the controller is completely inactive, unable to
179 * generate interrupts or do DMA.
181 static void uhci_generic_reset_hc(struct uhci_hcd
*uhci
)
183 /* Reset the HC - this will force us to get a
184 * new notification of any already connected
185 * ports due to the virtual disconnect that it
188 uhci_writew(uhci
, USBCMD_HCRESET
, USBCMD
);
191 if (uhci_readw(uhci
, USBCMD
) & USBCMD_HCRESET
)
192 dev_warn(uhci_dev(uhci
), "HCRESET not completed yet!\n");
194 /* Just to be safe, disable interrupt requests and
195 * make sure the controller is stopped.
197 uhci_writew(uhci
, 0, USBINTR
);
198 uhci_writew(uhci
, 0, USBCMD
);
202 * Initialize a controller that was newly discovered or has just been
203 * resumed. In either case we can't be sure of its previous state.
205 * Returns: 1 if the controller was reset, 0 otherwise.
207 static int uhci_generic_check_and_reset_hc(struct uhci_hcd
*uhci
)
209 unsigned int cmd
, intr
;
212 * When restarting a suspended controller, we expect all the
213 * settings to be the same as we left them:
215 * Controller is stopped and configured with EGSM set;
216 * No interrupts enabled except possibly Resume Detect.
218 * If any of these conditions are violated we do a complete reset.
221 cmd
= uhci_readw(uhci
, USBCMD
);
222 if ((cmd
& USBCMD_RS
) || !(cmd
& USBCMD_CF
) || !(cmd
& USBCMD_EGSM
)) {
223 dev_dbg(uhci_dev(uhci
), "%s: cmd = 0x%04x\n",
228 intr
= uhci_readw(uhci
, USBINTR
);
229 if (intr
& (~USBINTR_RESUME
)) {
230 dev_dbg(uhci_dev(uhci
), "%s: intr = 0x%04x\n",
237 dev_dbg(uhci_dev(uhci
), "Performing full reset\n");
238 uhci_generic_reset_hc(uhci
);
241 #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
244 * Store the basic register settings needed by the controller.
246 static void configure_hc(struct uhci_hcd
*uhci
)
248 /* Set the frame length to the default: 1 ms exactly */
249 uhci_writeb(uhci
, USBSOF_DEFAULT
, USBSOF
);
251 /* Store the frame list base address */
252 uhci_writel(uhci
, uhci
->frame_dma_handle
, USBFLBASEADD
);
254 /* Set the current frame number */
255 uhci_writew(uhci
, uhci
->frame_number
& UHCI_MAX_SOF_NUMBER
,
258 /* perform any arch/bus specific configuration */
259 if (uhci
->configure_hc
)
260 uhci
->configure_hc(uhci
);
263 static int resume_detect_interrupts_are_broken(struct uhci_hcd
*uhci
)
265 /* If we have to ignore overcurrent events then almost by definition
266 * we can't depend on resume-detect interrupts. */
270 return uhci
->resume_detect_interrupts_are_broken
?
271 uhci
->resume_detect_interrupts_are_broken(uhci
) : 0;
274 static int global_suspend_mode_is_broken(struct uhci_hcd
*uhci
)
276 return uhci
->global_suspend_mode_is_broken
?
277 uhci
->global_suspend_mode_is_broken(uhci
) : 0;
280 static void suspend_rh(struct uhci_hcd
*uhci
, enum uhci_rh_state new_state
)
281 __releases(uhci
->lock
)
282 __acquires(uhci
->lock
)
285 int int_enable
, egsm_enable
, wakeup_enable
;
286 struct usb_device
*rhdev
= uhci_to_hcd(uhci
)->self
.root_hub
;
288 auto_stop
= (new_state
== UHCI_RH_AUTO_STOPPED
);
289 dev_dbg(&rhdev
->dev
, "%s%s\n", __func__
,
290 (auto_stop
? " (auto-stop)" : ""));
292 /* Start off by assuming Resume-Detect interrupts and EGSM work
293 * and that remote wakeups should be enabled.
295 egsm_enable
= USBCMD_EGSM
;
296 int_enable
= USBINTR_RESUME
;
300 * In auto-stop mode, we must be able to detect new connections.
301 * The user can force us to poll by disabling remote wakeup;
302 * otherwise we will use the EGSM/RD mechanism.
305 if (!device_may_wakeup(&rhdev
->dev
))
306 egsm_enable
= int_enable
= 0;
311 * In bus-suspend mode, we use the wakeup setting specified
315 if (!rhdev
->do_remote_wakeup
)
321 * UHCI doesn't distinguish between wakeup requests from downstream
322 * devices and local connect/disconnect events. There's no way to
323 * enable one without the other; both are controlled by EGSM. Thus
324 * if wakeups are disallowed then EGSM must be turned off -- in which
325 * case remote wakeup requests from downstream during system sleep
328 * In addition, if EGSM is broken then we can't use it. Likewise,
329 * if Resume-Detect interrupts are broken then we can't use them.
331 * Finally, neither EGSM nor RD is useful by itself. Without EGSM,
332 * the RD status bit will never get set. Without RD, the controller
333 * won't generate interrupts to tell the system about wakeup events.
335 if (!wakeup_enable
|| global_suspend_mode_is_broken(uhci
) ||
336 resume_detect_interrupts_are_broken(uhci
))
337 egsm_enable
= int_enable
= 0;
339 uhci
->RD_enable
= !!int_enable
;
340 uhci_writew(uhci
, int_enable
, USBINTR
);
341 uhci_writew(uhci
, egsm_enable
| USBCMD_CF
, USBCMD
);
345 /* If we're auto-stopping then no devices have been attached
346 * for a while, so there shouldn't be any active URBs and the
347 * controller should stop after a few microseconds. Otherwise
348 * we will give the controller one frame to stop.
350 if (!auto_stop
&& !(uhci_readw(uhci
, USBSTS
) & USBSTS_HCH
)) {
351 uhci
->rh_state
= UHCI_RH_SUSPENDING
;
352 spin_unlock_irq(&uhci
->lock
);
354 spin_lock_irq(&uhci
->lock
);
358 if (!(uhci_readw(uhci
, USBSTS
) & USBSTS_HCH
))
359 dev_warn(uhci_dev(uhci
), "Controller not stopped yet!\n");
361 uhci_get_current_frame_number(uhci
);
363 uhci
->rh_state
= new_state
;
364 uhci
->is_stopped
= UHCI_IS_STOPPED
;
367 * If remote wakeup is enabled but either EGSM or RD interrupts
368 * doesn't work, then we won't get an interrupt when a wakeup event
369 * occurs. Thus the suspended root hub needs to be polled.
371 if (wakeup_enable
&& (!int_enable
|| !egsm_enable
))
372 set_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
374 clear_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
376 uhci_scan_schedule(uhci
);
380 static void start_rh(struct uhci_hcd
*uhci
)
382 uhci
->is_stopped
= 0;
384 /* Mark it configured and running with a 64-byte max packet.
385 * All interrupts are enabled, even though RESUME won't do anything.
387 uhci_writew(uhci
, USBCMD_RS
| USBCMD_CF
| USBCMD_MAXP
, USBCMD
);
388 uhci_writew(uhci
, USBINTR_TIMEOUT
| USBINTR_RESUME
|
389 USBINTR_IOC
| USBINTR_SP
, USBINTR
);
391 uhci
->rh_state
= UHCI_RH_RUNNING
;
392 set_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
395 static void wakeup_rh(struct uhci_hcd
*uhci
)
396 __releases(uhci
->lock
)
397 __acquires(uhci
->lock
)
399 dev_dbg(&uhci_to_hcd(uhci
)->self
.root_hub
->dev
,
401 uhci
->rh_state
== UHCI_RH_AUTO_STOPPED
?
402 " (auto-start)" : "");
404 /* If we are auto-stopped then no devices are attached so there's
405 * no need for wakeup signals. Otherwise we send Global Resume
408 if (uhci
->rh_state
== UHCI_RH_SUSPENDED
) {
411 /* Keep EGSM on if it was set before */
412 egsm
= uhci_readw(uhci
, USBCMD
) & USBCMD_EGSM
;
413 uhci
->rh_state
= UHCI_RH_RESUMING
;
414 uhci_writew(uhci
, USBCMD_FGR
| USBCMD_CF
| egsm
, USBCMD
);
415 spin_unlock_irq(&uhci
->lock
);
417 spin_lock_irq(&uhci
->lock
);
421 /* End Global Resume and wait for EOP to be sent */
422 uhci_writew(uhci
, USBCMD_CF
, USBCMD
);
425 if (uhci_readw(uhci
, USBCMD
) & USBCMD_FGR
)
426 dev_warn(uhci_dev(uhci
), "FGR not stopped yet!\n");
431 /* Restart root hub polling */
432 mod_timer(&uhci_to_hcd(uhci
)->rh_timer
, jiffies
);
435 static irqreturn_t
uhci_irq(struct usb_hcd
*hcd
)
437 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
438 unsigned short status
;
441 * Read the interrupt status, and write it back to clear the
442 * interrupt cause. Contrary to the UHCI specification, the
443 * "HC Halted" status bit is persistent: it is RO, not R/WC.
445 status
= uhci_readw(uhci
, USBSTS
);
446 if (!(status
& ~USBSTS_HCH
)) /* shared interrupt, not mine */
448 uhci_writew(uhci
, status
, USBSTS
); /* Clear it */
450 if (status
& ~(USBSTS_USBINT
| USBSTS_ERROR
| USBSTS_RD
)) {
451 if (status
& USBSTS_HSE
)
452 dev_err(uhci_dev(uhci
), "host system error, "
454 if (status
& USBSTS_HCPE
)
455 dev_err(uhci_dev(uhci
), "host controller process "
456 "error, something bad happened!\n");
457 if (status
& USBSTS_HCH
) {
458 spin_lock(&uhci
->lock
);
459 if (uhci
->rh_state
>= UHCI_RH_RUNNING
) {
460 dev_err(uhci_dev(uhci
),
461 "host controller halted, "
463 if (debug
> 1 && errbuf
) {
464 /* Print the schedule for debugging */
465 uhci_sprint_schedule(uhci
,
472 /* Force a callback in case there are
474 mod_timer(&hcd
->rh_timer
, jiffies
);
476 spin_unlock(&uhci
->lock
);
480 if (status
& USBSTS_RD
)
481 usb_hcd_poll_rh_status(hcd
);
483 spin_lock(&uhci
->lock
);
484 uhci_scan_schedule(uhci
);
485 spin_unlock(&uhci
->lock
);
492 * Store the current frame number in uhci->frame_number if the controller
493 * is running. Expand from 11 bits (of which we use only 10) to a
494 * full-sized integer.
496 * Like many other parts of the driver, this code relies on being polled
497 * more than once per second as long as the controller is running.
499 static void uhci_get_current_frame_number(struct uhci_hcd
*uhci
)
501 if (!uhci
->is_stopped
) {
504 delta
= (uhci_readw(uhci
, USBFRNUM
) - uhci
->frame_number
) &
505 (UHCI_NUMFRAMES
- 1);
506 uhci
->frame_number
+= delta
;
511 * De-allocate all resources
513 static void release_uhci(struct uhci_hcd
*uhci
)
517 if (DEBUG_CONFIGURED
) {
518 spin_lock_irq(&uhci
->lock
);
519 uhci
->is_initialized
= 0;
520 spin_unlock_irq(&uhci
->lock
);
522 debugfs_remove(uhci
->dentry
);
525 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++)
526 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
528 uhci_free_td(uhci
, uhci
->term_td
);
530 dma_pool_destroy(uhci
->qh_pool
);
532 dma_pool_destroy(uhci
->td_pool
);
534 kfree(uhci
->frame_cpu
);
536 dma_free_coherent(uhci_dev(uhci
),
537 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
538 uhci
->frame
, uhci
->frame_dma_handle
);
542 * Allocate a frame list, and then setup the skeleton
544 * The hardware doesn't really know any difference
545 * in the queues, but the order does matter for the
546 * protocols higher up. The order in which the queues
547 * are encountered by the hardware is:
549 * - All isochronous events are handled before any
550 * of the queues. We don't do that here, because
551 * we'll create the actual TD entries on demand.
552 * - The first queue is the high-period interrupt queue.
553 * - The second queue is the period-1 interrupt and async
554 * (low-speed control, full-speed control, then bulk) queue.
555 * - The third queue is the terminating bandwidth reclamation queue,
556 * which contains no members, loops back to itself, and is present
557 * only when FSBR is on and there are no full-speed control or bulk QHs.
559 static int uhci_start(struct usb_hcd
*hcd
)
561 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
564 struct dentry __maybe_unused
*dentry
;
566 hcd
->uses_new_polling
= 1;
567 /* Accept arbitrarily long scatter-gather lists */
568 if (!(hcd
->driver
->flags
& HCD_LOCAL_MEM
))
569 hcd
->self
.sg_tablesize
= ~0;
571 spin_lock_init(&uhci
->lock
);
572 setup_timer(&uhci
->fsbr_timer
, uhci_fsbr_timeout
,
573 (unsigned long) uhci
);
574 INIT_LIST_HEAD(&uhci
->idle_qh_list
);
575 init_waitqueue_head(&uhci
->waitqh
);
577 #ifdef UHCI_DEBUG_OPS
578 dentry
= debugfs_create_file(hcd
->self
.bus_name
,
579 S_IFREG
|S_IRUGO
|S_IWUSR
, uhci_debugfs_root
,
580 uhci
, &uhci_debug_operations
);
582 dev_err(uhci_dev(uhci
), "couldn't create uhci debugfs entry\n");
585 uhci
->dentry
= dentry
;
588 uhci
->frame
= dma_alloc_coherent(uhci_dev(uhci
),
589 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
590 &uhci
->frame_dma_handle
, 0);
592 dev_err(uhci_dev(uhci
), "unable to allocate "
593 "consistent memory for frame list\n");
594 goto err_alloc_frame
;
596 memset(uhci
->frame
, 0, UHCI_NUMFRAMES
* sizeof(*uhci
->frame
));
598 uhci
->frame_cpu
= kcalloc(UHCI_NUMFRAMES
, sizeof(*uhci
->frame_cpu
),
600 if (!uhci
->frame_cpu
) {
601 dev_err(uhci_dev(uhci
), "unable to allocate "
602 "memory for frame pointers\n");
603 goto err_alloc_frame_cpu
;
606 uhci
->td_pool
= dma_pool_create("uhci_td", uhci_dev(uhci
),
607 sizeof(struct uhci_td
), 16, 0);
608 if (!uhci
->td_pool
) {
609 dev_err(uhci_dev(uhci
), "unable to create td dma_pool\n");
610 goto err_create_td_pool
;
613 uhci
->qh_pool
= dma_pool_create("uhci_qh", uhci_dev(uhci
),
614 sizeof(struct uhci_qh
), 16, 0);
615 if (!uhci
->qh_pool
) {
616 dev_err(uhci_dev(uhci
), "unable to create qh dma_pool\n");
617 goto err_create_qh_pool
;
620 uhci
->term_td
= uhci_alloc_td(uhci
);
621 if (!uhci
->term_td
) {
622 dev_err(uhci_dev(uhci
), "unable to allocate terminating TD\n");
623 goto err_alloc_term_td
;
626 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++) {
627 uhci
->skelqh
[i
] = uhci_alloc_qh(uhci
, NULL
, NULL
);
628 if (!uhci
->skelqh
[i
]) {
629 dev_err(uhci_dev(uhci
), "unable to allocate QH\n");
630 goto err_alloc_skelqh
;
635 * 8 Interrupt queues; link all higher int queues to int1 = async
637 for (i
= SKEL_ISO
+ 1; i
< SKEL_ASYNC
; ++i
)
638 uhci
->skelqh
[i
]->link
= LINK_TO_QH(uhci
, uhci
->skel_async_qh
);
639 uhci
->skel_async_qh
->link
= UHCI_PTR_TERM(uhci
);
640 uhci
->skel_term_qh
->link
= LINK_TO_QH(uhci
, uhci
->skel_term_qh
);
642 /* This dummy TD is to work around a bug in Intel PIIX controllers */
643 uhci_fill_td(uhci
, uhci
->term_td
, 0, uhci_explen(0) |
644 (0x7f << TD_TOKEN_DEVADDR_SHIFT
) | USB_PID_IN
, 0);
645 uhci
->term_td
->link
= UHCI_PTR_TERM(uhci
);
646 uhci
->skel_async_qh
->element
= uhci
->skel_term_qh
->element
=
647 LINK_TO_TD(uhci
, uhci
->term_td
);
650 * Fill the frame list: make all entries point to the proper
653 for (i
= 0; i
< UHCI_NUMFRAMES
; i
++) {
655 /* Only place we don't use the frame list routines */
656 uhci
->frame
[i
] = uhci_frame_skel_link(uhci
, i
);
660 * Some architectures require a full mb() to enforce completion of
661 * the memory writes above before the I/O transfers in configure_hc().
666 uhci
->is_initialized
= 1;
667 spin_lock_irq(&uhci
->lock
);
669 spin_unlock_irq(&uhci
->lock
);
676 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++) {
678 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
681 uhci_free_td(uhci
, uhci
->term_td
);
684 dma_pool_destroy(uhci
->qh_pool
);
687 dma_pool_destroy(uhci
->td_pool
);
690 kfree(uhci
->frame_cpu
);
693 dma_free_coherent(uhci_dev(uhci
),
694 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
695 uhci
->frame
, uhci
->frame_dma_handle
);
698 debugfs_remove(uhci
->dentry
);
703 static void uhci_stop(struct usb_hcd
*hcd
)
705 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
707 spin_lock_irq(&uhci
->lock
);
708 if (HCD_HW_ACCESSIBLE(hcd
) && !uhci
->dead
)
710 uhci_scan_schedule(uhci
);
711 spin_unlock_irq(&uhci
->lock
);
712 synchronize_irq(hcd
->irq
);
714 del_timer_sync(&uhci
->fsbr_timer
);
719 static int uhci_rh_suspend(struct usb_hcd
*hcd
)
721 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
724 spin_lock_irq(&uhci
->lock
);
725 if (!HCD_HW_ACCESSIBLE(hcd
))
728 ; /* Dead controllers tell no tales */
730 /* Once the controller is stopped, port resumes that are already
731 * in progress won't complete. Hence if remote wakeup is enabled
732 * for the root hub and any ports are in the middle of a resume or
733 * remote wakeup, we must fail the suspend.
735 else if (hcd
->self
.root_hub
->do_remote_wakeup
&&
736 uhci
->resuming_ports
) {
737 dev_dbg(uhci_dev(uhci
), "suspend failed because a port "
741 suspend_rh(uhci
, UHCI_RH_SUSPENDED
);
742 spin_unlock_irq(&uhci
->lock
);
746 static int uhci_rh_resume(struct usb_hcd
*hcd
)
748 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
751 spin_lock_irq(&uhci
->lock
);
752 if (!HCD_HW_ACCESSIBLE(hcd
))
754 else if (!uhci
->dead
)
756 spin_unlock_irq(&uhci
->lock
);
762 /* Wait until a particular device/endpoint's QH is idle, and free it */
763 static void uhci_hcd_endpoint_disable(struct usb_hcd
*hcd
,
764 struct usb_host_endpoint
*hep
)
766 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
769 spin_lock_irq(&uhci
->lock
);
770 qh
= (struct uhci_qh
*) hep
->hcpriv
;
774 while (qh
->state
!= QH_STATE_IDLE
) {
776 spin_unlock_irq(&uhci
->lock
);
777 wait_event_interruptible(uhci
->waitqh
,
778 qh
->state
== QH_STATE_IDLE
);
779 spin_lock_irq(&uhci
->lock
);
783 uhci_free_qh(uhci
, qh
);
785 spin_unlock_irq(&uhci
->lock
);
788 static int uhci_hcd_get_frame_number(struct usb_hcd
*hcd
)
790 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
791 unsigned frame_number
;
794 /* Minimize latency by avoiding the spinlock */
795 frame_number
= uhci
->frame_number
;
797 delta
= (uhci_readw(uhci
, USBFRNUM
) - frame_number
) &
798 (UHCI_NUMFRAMES
- 1);
799 return frame_number
+ delta
;
802 /* Determines number of ports on controller */
803 static int uhci_count_ports(struct usb_hcd
*hcd
)
805 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
806 unsigned io_size
= (unsigned) hcd
->rsrc_len
;
809 /* The UHCI spec says devices must have 2 ports, and goes on to say
810 * they may have more but gives no way to determine how many there
811 * are. However according to the UHCI spec, Bit 7 of the port
812 * status and control register is always set to 1. So we try to
813 * use this to our advantage. Another common failure mode when
814 * a nonexistent register is addressed is to return all ones, so
815 * we test for that also.
817 for (port
= 0; port
< (io_size
- USBPORTSC1
) / 2; port
++) {
818 unsigned int portstatus
;
820 portstatus
= uhci_readw(uhci
, USBPORTSC1
+ (port
* 2));
821 if (!(portstatus
& 0x0080) || portstatus
== 0xffff)
825 dev_info(uhci_dev(uhci
), "detected %d ports\n", port
);
827 /* Anything greater than 7 is weird so we'll ignore it. */
828 if (port
> UHCI_RH_MAXCHILD
) {
829 dev_info(uhci_dev(uhci
), "port count misdetected? "
830 "forcing to 2 ports\n");
837 static const char hcd_name
[] = "uhci_hcd";
840 #include "uhci-pci.c"
841 #define PCI_DRIVER uhci_pci_driver
844 #ifdef CONFIG_SPARC_LEON
845 #include "uhci-grlib.c"
846 #define PLATFORM_DRIVER uhci_grlib_driver
849 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
850 #error "missing bus glue for uhci-hcd"
853 static int __init
uhci_hcd_init(void)
855 int retval
= -ENOMEM
;
860 printk(KERN_INFO
"uhci_hcd: " DRIVER_DESC
"%s\n",
861 ignore_oc
? ", overcurrent ignored" : "");
862 set_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
864 if (DEBUG_CONFIGURED
) {
865 errbuf
= kmalloc(ERRBUF_LEN
, GFP_KERNEL
);
868 uhci_debugfs_root
= debugfs_create_dir("uhci", usb_debug_root
);
869 if (!uhci_debugfs_root
)
873 uhci_up_cachep
= kmem_cache_create("uhci_urb_priv",
874 sizeof(struct urb_priv
), 0, 0, NULL
);
878 #ifdef PLATFORM_DRIVER
879 retval
= platform_driver_register(&PLATFORM_DRIVER
);
885 retval
= pci_register_driver(&PCI_DRIVER
);
895 #ifdef PLATFORM_DRIVER
896 platform_driver_unregister(&PLATFORM_DRIVER
);
899 kmem_cache_destroy(uhci_up_cachep
);
902 debugfs_remove(uhci_debugfs_root
);
909 clear_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
913 static void __exit
uhci_hcd_cleanup(void)
915 #ifdef PLATFORM_DRIVER
916 platform_driver_unregister(&PLATFORM_DRIVER
);
919 pci_unregister_driver(&PCI_DRIVER
);
921 kmem_cache_destroy(uhci_up_cachep
);
922 debugfs_remove(uhci_debugfs_root
);
924 clear_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
927 module_init(uhci_hcd_init
);
928 module_exit(uhci_hcd_cleanup
);
930 MODULE_AUTHOR(DRIVER_AUTHOR
);
931 MODULE_DESCRIPTION(DRIVER_DESC
);
932 MODULE_LICENSE("GPL");