2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define XHCI_INIT_VALUE 0x0
27 /* Add verbose debugging later, just print everything for now */
29 void xhci_dbg_regs(struct xhci_hcd
*xhci
)
33 xhci_dbg(xhci
, "// xHCI capability registers at %p:\n",
35 temp
= readl(&xhci
->cap_regs
->hc_capbase
);
36 xhci_dbg(xhci
, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
37 &xhci
->cap_regs
->hc_capbase
, temp
);
38 xhci_dbg(xhci
, "// CAPLENGTH: 0x%x\n",
39 (unsigned int) HC_LENGTH(temp
));
41 xhci_dbg(xhci
, "// HCIVERSION: 0x%x\n",
42 (unsigned int) HC_VERSION(temp
));
45 xhci_dbg(xhci
, "// xHCI operational registers at %p:\n", xhci
->op_regs
);
47 temp
= readl(&xhci
->cap_regs
->run_regs_off
);
48 xhci_dbg(xhci
, "// @%p = 0x%x RTSOFF\n",
49 &xhci
->cap_regs
->run_regs_off
,
50 (unsigned int) temp
& RTSOFF_MASK
);
51 xhci_dbg(xhci
, "// xHCI runtime registers at %p:\n", xhci
->run_regs
);
53 temp
= readl(&xhci
->cap_regs
->db_off
);
54 xhci_dbg(xhci
, "// @%p = 0x%x DBOFF\n", &xhci
->cap_regs
->db_off
, temp
);
55 xhci_dbg(xhci
, "// Doorbell array at %p:\n", xhci
->dba
);
58 static void xhci_print_cap_regs(struct xhci_hcd
*xhci
)
62 xhci_dbg(xhci
, "xHCI capability registers at %p:\n", xhci
->cap_regs
);
64 temp
= readl(&xhci
->cap_regs
->hc_capbase
);
65 xhci_dbg(xhci
, "CAPLENGTH AND HCIVERSION 0x%x:\n",
67 xhci_dbg(xhci
, "CAPLENGTH: 0x%x\n",
68 (unsigned int) HC_LENGTH(temp
));
69 xhci_dbg(xhci
, "HCIVERSION: 0x%x\n",
70 (unsigned int) HC_VERSION(temp
));
72 temp
= readl(&xhci
->cap_regs
->hcs_params1
);
73 xhci_dbg(xhci
, "HCSPARAMS 1: 0x%x\n",
75 xhci_dbg(xhci
, " Max device slots: %u\n",
76 (unsigned int) HCS_MAX_SLOTS(temp
));
77 xhci_dbg(xhci
, " Max interrupters: %u\n",
78 (unsigned int) HCS_MAX_INTRS(temp
));
79 xhci_dbg(xhci
, " Max ports: %u\n",
80 (unsigned int) HCS_MAX_PORTS(temp
));
82 temp
= readl(&xhci
->cap_regs
->hcs_params2
);
83 xhci_dbg(xhci
, "HCSPARAMS 2: 0x%x\n",
85 xhci_dbg(xhci
, " Isoc scheduling threshold: %u\n",
86 (unsigned int) HCS_IST(temp
));
87 xhci_dbg(xhci
, " Maximum allowed segments in event ring: %u\n",
88 (unsigned int) HCS_ERST_MAX(temp
));
90 temp
= readl(&xhci
->cap_regs
->hcs_params3
);
91 xhci_dbg(xhci
, "HCSPARAMS 3 0x%x:\n",
93 xhci_dbg(xhci
, " Worst case U1 device exit latency: %u\n",
94 (unsigned int) HCS_U1_LATENCY(temp
));
95 xhci_dbg(xhci
, " Worst case U2 device exit latency: %u\n",
96 (unsigned int) HCS_U2_LATENCY(temp
));
98 temp
= readl(&xhci
->cap_regs
->hcc_params
);
99 xhci_dbg(xhci
, "HCC PARAMS 0x%x:\n", (unsigned int) temp
);
100 xhci_dbg(xhci
, " HC generates %s bit addresses\n",
101 HCC_64BIT_ADDR(temp
) ? "64" : "32");
102 xhci_dbg(xhci
, " HC %s Contiguous Frame ID Capability\n",
103 HCC_CFC(temp
) ? "has" : "hasn't");
104 xhci_dbg(xhci
, " HC %s generate Stopped - Short Package event\n",
105 HCC_SPC(temp
) ? "can" : "can't");
107 xhci_dbg(xhci
, " FIXME: more HCCPARAMS debugging\n");
109 temp
= readl(&xhci
->cap_regs
->run_regs_off
);
110 xhci_dbg(xhci
, "RTSOFF 0x%x:\n", temp
& RTSOFF_MASK
);
113 static void xhci_print_command_reg(struct xhci_hcd
*xhci
)
117 temp
= readl(&xhci
->op_regs
->command
);
118 xhci_dbg(xhci
, "USBCMD 0x%x:\n", temp
);
119 xhci_dbg(xhci
, " HC is %s\n",
120 (temp
& CMD_RUN
) ? "running" : "being stopped");
121 xhci_dbg(xhci
, " HC has %sfinished hard reset\n",
122 (temp
& CMD_RESET
) ? "not " : "");
123 xhci_dbg(xhci
, " Event Interrupts %s\n",
124 (temp
& CMD_EIE
) ? "enabled " : "disabled");
125 xhci_dbg(xhci
, " Host System Error Interrupts %s\n",
126 (temp
& CMD_HSEIE
) ? "enabled " : "disabled");
127 xhci_dbg(xhci
, " HC has %sfinished light reset\n",
128 (temp
& CMD_LRESET
) ? "not " : "");
131 static void xhci_print_status(struct xhci_hcd
*xhci
)
135 temp
= readl(&xhci
->op_regs
->status
);
136 xhci_dbg(xhci
, "USBSTS 0x%x:\n", temp
);
137 xhci_dbg(xhci
, " Event ring is %sempty\n",
138 (temp
& STS_EINT
) ? "not " : "");
139 xhci_dbg(xhci
, " %sHost System Error\n",
140 (temp
& STS_FATAL
) ? "WARNING: " : "No ");
141 xhci_dbg(xhci
, " HC is %s\n",
142 (temp
& STS_HALT
) ? "halted" : "running");
145 static void xhci_print_op_regs(struct xhci_hcd
*xhci
)
147 xhci_dbg(xhci
, "xHCI operational registers at %p:\n", xhci
->op_regs
);
148 xhci_print_command_reg(xhci
);
149 xhci_print_status(xhci
);
152 static void xhci_print_ports(struct xhci_hcd
*xhci
)
154 __le32 __iomem
*addr
;
157 char *names
[NUM_PORT_REGS
] = {
164 ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
165 addr
= &xhci
->op_regs
->port_status_base
;
166 for (i
= 0; i
< ports
; i
++) {
167 for (j
= 0; j
< NUM_PORT_REGS
; ++j
) {
168 xhci_dbg(xhci
, "%p port %s reg = 0x%x\n",
170 (unsigned int) readl(addr
));
176 void xhci_print_ir_set(struct xhci_hcd
*xhci
, int set_num
)
178 struct xhci_intr_reg __iomem
*ir_set
= &xhci
->run_regs
->ir_set
[set_num
];
183 addr
= &ir_set
->irq_pending
;
185 if (temp
== XHCI_INIT_VALUE
)
188 xhci_dbg(xhci
, " %p: ir_set[%i]\n", ir_set
, set_num
);
190 xhci_dbg(xhci
, " %p: ir_set.pending = 0x%x\n", addr
,
193 addr
= &ir_set
->irq_control
;
195 xhci_dbg(xhci
, " %p: ir_set.control = 0x%x\n", addr
,
198 addr
= &ir_set
->erst_size
;
200 xhci_dbg(xhci
, " %p: ir_set.erst_size = 0x%x\n", addr
,
203 addr
= &ir_set
->rsvd
;
205 if (temp
!= XHCI_INIT_VALUE
)
206 xhci_dbg(xhci
, " WARN: %p: ir_set.rsvd = 0x%x\n",
207 addr
, (unsigned int)temp
);
209 addr
= &ir_set
->erst_base
;
210 temp_64
= xhci_read_64(xhci
, addr
);
211 xhci_dbg(xhci
, " %p: ir_set.erst_base = @%08llx\n",
214 addr
= &ir_set
->erst_dequeue
;
215 temp_64
= xhci_read_64(xhci
, addr
);
216 xhci_dbg(xhci
, " %p: ir_set.erst_dequeue = @%08llx\n",
220 void xhci_print_run_regs(struct xhci_hcd
*xhci
)
225 xhci_dbg(xhci
, "xHCI runtime registers at %p:\n", xhci
->run_regs
);
226 temp
= readl(&xhci
->run_regs
->microframe_index
);
227 xhci_dbg(xhci
, " %p: Microframe index = 0x%x\n",
228 &xhci
->run_regs
->microframe_index
,
229 (unsigned int) temp
);
230 for (i
= 0; i
< 7; ++i
) {
231 temp
= readl(&xhci
->run_regs
->rsvd
[i
]);
232 if (temp
!= XHCI_INIT_VALUE
)
233 xhci_dbg(xhci
, " WARN: %p: Rsvd[%i] = 0x%x\n",
234 &xhci
->run_regs
->rsvd
[i
],
235 i
, (unsigned int) temp
);
239 void xhci_print_registers(struct xhci_hcd
*xhci
)
241 xhci_print_cap_regs(xhci
);
242 xhci_print_op_regs(xhci
);
243 xhci_print_ports(xhci
);
246 void xhci_print_trb_offsets(struct xhci_hcd
*xhci
, union xhci_trb
*trb
)
249 for (i
= 0; i
< 4; ++i
)
250 xhci_dbg(xhci
, "Offset 0x%x = 0x%x\n",
251 i
*4, trb
->generic
.field
[i
]);
255 * Debug a transfer request block (TRB).
257 void xhci_debug_trb(struct xhci_hcd
*xhci
, union xhci_trb
*trb
)
260 u32 type
= le32_to_cpu(trb
->link
.control
) & TRB_TYPE_BITMASK
;
263 case TRB_TYPE(TRB_LINK
):
264 xhci_dbg(xhci
, "Link TRB:\n");
265 xhci_print_trb_offsets(xhci
, trb
);
267 address
= le64_to_cpu(trb
->link
.segment_ptr
);
268 xhci_dbg(xhci
, "Next ring segment DMA address = 0x%llx\n", address
);
270 xhci_dbg(xhci
, "Interrupter target = 0x%x\n",
271 GET_INTR_TARGET(le32_to_cpu(trb
->link
.intr_target
)));
272 xhci_dbg(xhci
, "Cycle bit = %u\n",
273 le32_to_cpu(trb
->link
.control
) & TRB_CYCLE
);
274 xhci_dbg(xhci
, "Toggle cycle bit = %u\n",
275 le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
);
276 xhci_dbg(xhci
, "No Snoop bit = %u\n",
277 le32_to_cpu(trb
->link
.control
) & TRB_NO_SNOOP
);
279 case TRB_TYPE(TRB_TRANSFER
):
280 address
= le64_to_cpu(trb
->trans_event
.buffer
);
282 * FIXME: look at flags to figure out if it's an address or if
283 * the data is directly in the buffer field.
285 xhci_dbg(xhci
, "DMA address or buffer contents= %llu\n", address
);
287 case TRB_TYPE(TRB_COMPLETION
):
288 address
= le64_to_cpu(trb
->event_cmd
.cmd_trb
);
289 xhci_dbg(xhci
, "Command TRB pointer = %llu\n", address
);
290 xhci_dbg(xhci
, "Completion status = %u\n",
291 GET_COMP_CODE(le32_to_cpu(trb
->event_cmd
.status
)));
292 xhci_dbg(xhci
, "Flags = 0x%x\n",
293 le32_to_cpu(trb
->event_cmd
.flags
));
296 xhci_dbg(xhci
, "Unknown TRB with TRB type ID %u\n",
297 (unsigned int) type
>>10);
298 xhci_print_trb_offsets(xhci
, trb
);
304 * Debug a segment with an xHCI ring.
306 * @return The Link TRB of the segment, or NULL if there is no Link TRB
307 * (which is a bug, since all segments must have a Link TRB).
309 * Prints out all TRBs in the segment, even those after the Link TRB.
311 * XXX: should we print out TRBs that the HC owns? As long as we don't
312 * write, that should be fine... We shouldn't expect that the memory pointed to
313 * by the TRB is valid at all. Do we care about ones the HC owns? Probably,
316 void xhci_debug_segment(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
320 union xhci_trb
*trb
= seg
->trbs
;
322 for (i
= 0; i
< TRBS_PER_SEGMENT
; ++i
) {
324 xhci_dbg(xhci
, "@%016llx %08x %08x %08x %08x\n", addr
,
325 lower_32_bits(le64_to_cpu(trb
->link
.segment_ptr
)),
326 upper_32_bits(le64_to_cpu(trb
->link
.segment_ptr
)),
327 le32_to_cpu(trb
->link
.intr_target
),
328 le32_to_cpu(trb
->link
.control
));
329 addr
+= sizeof(*trb
);
333 void xhci_dbg_ring_ptrs(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
335 xhci_dbg(xhci
, "Ring deq = %p (virt), 0x%llx (dma)\n",
337 (unsigned long long)xhci_trb_virt_to_dma(ring
->deq_seg
,
339 xhci_dbg(xhci
, "Ring deq updated %u times\n",
341 xhci_dbg(xhci
, "Ring enq = %p (virt), 0x%llx (dma)\n",
343 (unsigned long long)xhci_trb_virt_to_dma(ring
->enq_seg
,
345 xhci_dbg(xhci
, "Ring enq updated %u times\n",
350 * Debugging for an xHCI ring, which is a queue broken into multiple segments.
352 * Print out each segment in the ring. Check that the DMA address in
353 * each link segment actually matches the segment's stored DMA address.
354 * Check that the link end bit is only set at the end of the ring.
355 * Check that the dequeue and enqueue pointers point to real data in this ring
356 * (not some other ring).
358 void xhci_debug_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
360 /* FIXME: Throw an error if any segment doesn't have a Link TRB */
361 struct xhci_segment
*seg
;
362 struct xhci_segment
*first_seg
= ring
->first_seg
;
363 xhci_debug_segment(xhci
, first_seg
);
365 if (!ring
->enq_updates
&& !ring
->deq_updates
) {
366 xhci_dbg(xhci
, " Ring has not been updated\n");
369 for (seg
= first_seg
->next
; seg
!= first_seg
; seg
= seg
->next
)
370 xhci_debug_segment(xhci
, seg
);
373 void xhci_dbg_ep_rings(struct xhci_hcd
*xhci
,
374 unsigned int slot_id
, unsigned int ep_index
,
375 struct xhci_virt_ep
*ep
)
378 struct xhci_ring
*ring
;
380 if (ep
->ep_state
& EP_HAS_STREAMS
) {
381 for (i
= 1; i
< ep
->stream_info
->num_streams
; i
++) {
382 ring
= ep
->stream_info
->stream_rings
[i
];
383 xhci_dbg(xhci
, "Dev %d endpoint %d stream ID %d:\n",
384 slot_id
, ep_index
, i
);
385 xhci_debug_segment(xhci
, ring
->deq_seg
);
391 xhci_dbg(xhci
, "Dev %d endpoint ring %d:\n",
393 xhci_debug_segment(xhci
, ring
->deq_seg
);
397 void xhci_dbg_erst(struct xhci_hcd
*xhci
, struct xhci_erst
*erst
)
399 u64 addr
= erst
->erst_dma_addr
;
401 struct xhci_erst_entry
*entry
;
403 for (i
= 0; i
< erst
->num_entries
; ++i
) {
404 entry
= &erst
->entries
[i
];
405 xhci_dbg(xhci
, "@%016llx %08x %08x %08x %08x\n",
407 lower_32_bits(le64_to_cpu(entry
->seg_addr
)),
408 upper_32_bits(le64_to_cpu(entry
->seg_addr
)),
409 le32_to_cpu(entry
->seg_size
),
410 le32_to_cpu(entry
->rsvd
));
411 addr
+= sizeof(*entry
);
415 void xhci_dbg_cmd_ptrs(struct xhci_hcd
*xhci
)
419 val
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
420 xhci_dbg(xhci
, "// xHC command ring deq ptr low bits + flags = @%08x\n",
422 xhci_dbg(xhci
, "// xHC command ring deq ptr high bits = @%08x\n",
426 /* Print the last 32 bytes for 64-byte contexts */
427 static void dbg_rsvd64(struct xhci_hcd
*xhci
, u64
*ctx
, dma_addr_t dma
)
430 for (i
= 0; i
< 4; ++i
) {
431 xhci_dbg(xhci
, "@%p (virt) @%08llx "
432 "(dma) %#08llx - rsvd64[%d]\n",
433 &ctx
[4 + i
], (unsigned long long)dma
,
439 char *xhci_get_slot_state(struct xhci_hcd
*xhci
,
440 struct xhci_container_ctx
*ctx
)
442 struct xhci_slot_ctx
*slot_ctx
= xhci_get_slot_ctx(xhci
, ctx
);
444 switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
))) {
445 case SLOT_STATE_ENABLED
:
446 return "enabled/disabled";
447 case SLOT_STATE_DEFAULT
:
449 case SLOT_STATE_ADDRESSED
:
451 case SLOT_STATE_CONFIGURED
:
458 static void xhci_dbg_slot_ctx(struct xhci_hcd
*xhci
, struct xhci_container_ctx
*ctx
)
460 /* Fields are 32 bits wide, DMA addresses are in bytes */
461 int field_size
= 32 / 8;
464 struct xhci_slot_ctx
*slot_ctx
= xhci_get_slot_ctx(xhci
, ctx
);
465 dma_addr_t dma
= ctx
->dma
+
466 ((unsigned long)slot_ctx
- (unsigned long)ctx
->bytes
);
467 int csz
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
);
469 xhci_dbg(xhci
, "Slot Context:\n");
470 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
472 (unsigned long long)dma
, slot_ctx
->dev_info
);
474 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
475 &slot_ctx
->dev_info2
,
476 (unsigned long long)dma
, slot_ctx
->dev_info2
);
478 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
480 (unsigned long long)dma
, slot_ctx
->tt_info
);
482 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
483 &slot_ctx
->dev_state
,
484 (unsigned long long)dma
, slot_ctx
->dev_state
);
486 for (i
= 0; i
< 4; ++i
) {
487 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
488 &slot_ctx
->reserved
[i
], (unsigned long long)dma
,
489 slot_ctx
->reserved
[i
], i
);
494 dbg_rsvd64(xhci
, (u64
*)slot_ctx
, dma
);
497 static void xhci_dbg_ep_ctx(struct xhci_hcd
*xhci
,
498 struct xhci_container_ctx
*ctx
,
499 unsigned int last_ep
)
502 int last_ep_ctx
= 31;
503 /* Fields are 32 bits wide, DMA addresses are in bytes */
504 int field_size
= 32 / 8;
505 int csz
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
);
508 last_ep_ctx
= last_ep
+ 1;
509 for (i
= 0; i
< last_ep_ctx
; ++i
) {
510 unsigned int epaddr
= xhci_get_endpoint_address(i
);
511 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, ctx
, i
);
512 dma_addr_t dma
= ctx
->dma
+
513 ((unsigned long)ep_ctx
- (unsigned long)ctx
->bytes
);
515 xhci_dbg(xhci
, "%s Endpoint %02d Context (ep_index %02d):\n",
516 usb_endpoint_out(epaddr
) ? "OUT" : "IN",
517 epaddr
& USB_ENDPOINT_NUMBER_MASK
, i
);
518 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
520 (unsigned long long)dma
, ep_ctx
->ep_info
);
522 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
524 (unsigned long long)dma
, ep_ctx
->ep_info2
);
526 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
528 (unsigned long long)dma
, ep_ctx
->deq
);
530 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
532 (unsigned long long)dma
, ep_ctx
->tx_info
);
534 for (j
= 0; j
< 3; ++j
) {
535 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
536 &ep_ctx
->reserved
[j
],
537 (unsigned long long)dma
,
538 ep_ctx
->reserved
[j
], j
);
543 dbg_rsvd64(xhci
, (u64
*)ep_ctx
, dma
);
547 void xhci_dbg_ctx(struct xhci_hcd
*xhci
,
548 struct xhci_container_ctx
*ctx
,
549 unsigned int last_ep
)
552 /* Fields are 32 bits wide, DMA addresses are in bytes */
553 int field_size
= 32 / 8;
554 dma_addr_t dma
= ctx
->dma
;
555 int csz
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
);
557 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
) {
558 struct xhci_input_control_ctx
*ctrl_ctx
=
559 xhci_get_input_control_ctx(ctx
);
561 xhci_warn(xhci
, "Could not get input context, bad type.\n");
565 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
566 &ctrl_ctx
->drop_flags
, (unsigned long long)dma
,
567 ctrl_ctx
->drop_flags
);
569 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
570 &ctrl_ctx
->add_flags
, (unsigned long long)dma
,
571 ctrl_ctx
->add_flags
);
573 for (i
= 0; i
< 6; ++i
) {
574 xhci_dbg(xhci
, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
575 &ctrl_ctx
->rsvd2
[i
], (unsigned long long)dma
,
576 ctrl_ctx
->rsvd2
[i
], i
);
581 dbg_rsvd64(xhci
, (u64
*)ctrl_ctx
, dma
);
584 xhci_dbg_slot_ctx(xhci
, ctx
);
585 xhci_dbg_ep_ctx(xhci
, ctx
, last_ep
);
588 void xhci_dbg_trace(struct xhci_hcd
*xhci
, void (*trace
)(struct va_format
*),
589 const char *fmt
, ...)
591 struct va_format vaf
;
597 xhci_dbg(xhci
, "%pV\n", &vaf
);
601 EXPORT_SYMBOL_GPL(xhci_dbg_trace
);
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