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Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / usb / host / xhci-hub.c
1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/gfp.h>
24 #include <asm/unaligned.h>
25
26 #include "xhci.h"
27
28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
31
32 /* usb 1.1 root hub device descriptor */
33 static u8 usb_bos_descriptor [] = {
34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
45 USB 3.0 speed only */
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
48 };
49
50
51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
52 struct usb_hub_descriptor *desc, int ports)
53 {
54 u16 temp;
55
56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
57 desc->bHubContrCurrent = 0;
58
59 desc->bNbrPorts = ports;
60 temp = 0;
61 /* Bits 1:0 - support per-port power switching, or power always on */
62 if (HCC_PPC(xhci->hcc_params))
63 temp |= HUB_CHAR_INDV_PORT_LPSM;
64 else
65 temp |= HUB_CHAR_NO_LPSM;
66 /* Bit 2 - root hubs are not part of a compound device */
67 /* Bits 4:3 - individual port over current protection */
68 temp |= HUB_CHAR_INDV_PORT_OCPM;
69 /* Bits 6:5 - no TTs in root ports */
70 /* Bit 7 - no port indicators */
71 desc->wHubCharacteristics = cpu_to_le16(temp);
72 }
73
74 /* Fill in the USB 2.0 roothub descriptor */
75 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
76 struct usb_hub_descriptor *desc)
77 {
78 int ports;
79 u16 temp;
80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
81 u32 portsc;
82 unsigned int i;
83
84 ports = xhci->num_usb2_ports;
85
86 xhci_common_hub_descriptor(xhci, desc, ports);
87 desc->bDescriptorType = USB_DT_HUB;
88 temp = 1 + (ports / 8);
89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
90
91 /* The Device Removable bits are reported on a byte granularity.
92 * If the port doesn't exist within that byte, the bit is set to 0.
93 */
94 memset(port_removable, 0, sizeof(port_removable));
95 for (i = 0; i < ports; i++) {
96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
97 /* If a device is removable, PORTSC reports a 0, same as in the
98 * hub descriptor DeviceRemovable bits.
99 */
100 if (portsc & PORT_DEV_REMOVE)
101 /* This math is hairy because bit 0 of DeviceRemovable
102 * is reserved, and bit 1 is for port 1, etc.
103 */
104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
105 }
106
107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
108 * ports on it. The USB 2.0 specification says that there are two
109 * variable length fields at the end of the hub descriptor:
110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
113 * 0xFF, so we initialize the both arrays (DeviceRemovable and
114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
115 * set of ports that actually exist.
116 */
117 memset(desc->u.hs.DeviceRemovable, 0xff,
118 sizeof(desc->u.hs.DeviceRemovable));
119 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
120 sizeof(desc->u.hs.PortPwrCtrlMask));
121
122 for (i = 0; i < (ports + 1 + 7) / 8; i++)
123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
124 sizeof(__u8));
125 }
126
127 /* Fill in the USB 3.0 roothub descriptor */
128 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
129 struct usb_hub_descriptor *desc)
130 {
131 int ports;
132 u16 port_removable;
133 u32 portsc;
134 unsigned int i;
135
136 ports = xhci->num_usb3_ports;
137 xhci_common_hub_descriptor(xhci, desc, ports);
138 desc->bDescriptorType = USB_DT_SS_HUB;
139 desc->bDescLength = USB_DT_SS_HUB_SIZE;
140
141 /* header decode latency should be zero for roothubs,
142 * see section 4.23.5.2.
143 */
144 desc->u.ss.bHubHdrDecLat = 0;
145 desc->u.ss.wHubDelay = 0;
146
147 port_removable = 0;
148 /* bit 0 is reserved, bit 1 is for port 1, etc. */
149 for (i = 0; i < ports; i++) {
150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
151 if (portsc & PORT_DEV_REMOVE)
152 port_removable |= 1 << (i + 1);
153 }
154 memset(&desc->u.ss.DeviceRemovable,
155 (__force __u16) cpu_to_le16(port_removable),
156 sizeof(__u16));
157 }
158
159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
160 struct usb_hub_descriptor *desc)
161 {
162
163 if (hcd->speed == HCD_USB3)
164 xhci_usb3_hub_descriptor(hcd, xhci, desc);
165 else
166 xhci_usb2_hub_descriptor(hcd, xhci, desc);
167
168 }
169
170 static unsigned int xhci_port_speed(unsigned int port_status)
171 {
172 if (DEV_LOWSPEED(port_status))
173 return USB_PORT_STAT_LOW_SPEED;
174 if (DEV_HIGHSPEED(port_status))
175 return USB_PORT_STAT_HIGH_SPEED;
176 /*
177 * FIXME: Yes, we should check for full speed, but the core uses that as
178 * a default in portspeed() in usb/core/hub.c (which is the only place
179 * USB_PORT_STAT_*_SPEED is used).
180 */
181 return 0;
182 }
183
184 /*
185 * These bits are Read Only (RO) and should be saved and written to the
186 * registers: 0, 3, 10:13, 30
187 * connect status, over-current status, port speed, and device removable.
188 * connect status and port speed are also sticky - meaning they're in
189 * the AUX well and they aren't changed by a hot, warm, or cold reset.
190 */
191 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
192 /*
193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
194 * bits 5:8, 9, 14:15, 25:27
195 * link state, port power, port indicator state, "wake on" enable state
196 */
197 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
198 /*
199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
200 * bit 4 (port reset)
201 */
202 #define XHCI_PORT_RW1S ((1<<4))
203 /*
204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
205 * bits 1, 17, 18, 19, 20, 21, 22, 23
206 * port enable/disable, and
207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
208 * over-current, reset, link state, and L1 change
209 */
210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
211 /*
212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
213 * latched in
214 */
215 #define XHCI_PORT_RW ((1<<16))
216 /*
217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
218 * bits 2, 24, 28:31
219 */
220 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
221
222 /*
223 * Given a port state, this function returns a value that would result in the
224 * port being in the same state, if the value was written to the port status
225 * control register.
226 * Save Read Only (RO) bits and save read/write bits where
227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
229 */
230 u32 xhci_port_state_to_neutral(u32 state)
231 {
232 /* Save read-only status and port state */
233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
234 }
235
236 /*
237 * find slot id based on port number.
238 * @port: The one-based port number from one of the two split roothubs.
239 */
240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 u16 port)
242 {
243 int slot_id;
244 int i;
245 enum usb_device_speed speed;
246
247 slot_id = 0;
248 for (i = 0; i < MAX_HC_SLOTS; i++) {
249 if (!xhci->devs[i])
250 continue;
251 speed = xhci->devs[i]->udev->speed;
252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
253 && xhci->devs[i]->fake_port == port) {
254 slot_id = i;
255 break;
256 }
257 }
258
259 return slot_id;
260 }
261
262 /*
263 * Stop device
264 * It issues stop endpoint command for EP 0 to 30. And wait the last command
265 * to complete.
266 * suspend will set to 1, if suspend bit need to set in command.
267 */
268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
269 {
270 struct xhci_virt_device *virt_dev;
271 struct xhci_command *cmd;
272 unsigned long flags;
273 int timeleft;
274 int ret;
275 int i;
276
277 ret = 0;
278 virt_dev = xhci->devs[slot_id];
279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
280 if (!cmd) {
281 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
282 return -ENOMEM;
283 }
284
285 spin_lock_irqsave(&xhci->lock, flags);
286 for (i = LAST_EP_INDEX; i > 0; i--) {
287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
289 }
290 cmd->command_trb = xhci->cmd_ring->enqueue;
291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
293 xhci_ring_cmd_db(xhci);
294 spin_unlock_irqrestore(&xhci->lock, flags);
295
296 /* Wait for last stop endpoint command to finish */
297 timeleft = wait_for_completion_interruptible_timeout(
298 cmd->completion,
299 USB_CTRL_SET_TIMEOUT);
300 if (timeleft <= 0) {
301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
302 timeleft == 0 ? "Timeout" : "Signal");
303 spin_lock_irqsave(&xhci->lock, flags);
304 /* The timeout might have raced with the event ring handler, so
305 * only delete from the list if the item isn't poisoned.
306 */
307 if (cmd->cmd_list.next != LIST_POISON1)
308 list_del(&cmd->cmd_list);
309 spin_unlock_irqrestore(&xhci->lock, flags);
310 ret = -ETIME;
311 goto command_cleanup;
312 }
313
314 command_cleanup:
315 xhci_free_command(xhci, cmd);
316 return ret;
317 }
318
319 /*
320 * Ring device, it rings the all doorbells unconditionally.
321 */
322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
323 {
324 int i;
325
326 for (i = 0; i < LAST_EP_INDEX + 1; i++)
327 if (xhci->devs[slot_id]->eps[i].ring &&
328 xhci->devs[slot_id]->eps[i].ring->dequeue)
329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
330
331 return;
332 }
333
334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
335 u16 wIndex, __le32 __iomem *addr, u32 port_status)
336 {
337 /* Don't allow the USB core to disable SuperSpeed ports. */
338 if (hcd->speed == HCD_USB3) {
339 xhci_dbg(xhci, "Ignoring request to disable "
340 "SuperSpeed port.\n");
341 return;
342 }
343
344 /* Write 1 to disable the port */
345 xhci_writel(xhci, port_status | PORT_PE, addr);
346 port_status = xhci_readl(xhci, addr);
347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
348 wIndex, port_status);
349 }
350
351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
352 u16 wIndex, __le32 __iomem *addr, u32 port_status)
353 {
354 char *port_change_bit;
355 u32 status;
356
357 switch (wValue) {
358 case USB_PORT_FEAT_C_RESET:
359 status = PORT_RC;
360 port_change_bit = "reset";
361 break;
362 case USB_PORT_FEAT_C_BH_PORT_RESET:
363 status = PORT_WRC;
364 port_change_bit = "warm(BH) reset";
365 break;
366 case USB_PORT_FEAT_C_CONNECTION:
367 status = PORT_CSC;
368 port_change_bit = "connect";
369 break;
370 case USB_PORT_FEAT_C_OVER_CURRENT:
371 status = PORT_OCC;
372 port_change_bit = "over-current";
373 break;
374 case USB_PORT_FEAT_C_ENABLE:
375 status = PORT_PEC;
376 port_change_bit = "enable/disable";
377 break;
378 case USB_PORT_FEAT_C_SUSPEND:
379 status = PORT_PLC;
380 port_change_bit = "suspend/resume";
381 break;
382 case USB_PORT_FEAT_C_PORT_LINK_STATE:
383 status = PORT_PLC;
384 port_change_bit = "link state";
385 break;
386 default:
387 /* Should never happen */
388 return;
389 }
390 /* Change bits are all write 1 to clear */
391 xhci_writel(xhci, port_status | status, addr);
392 port_status = xhci_readl(xhci, addr);
393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
394 port_change_bit, wIndex, port_status);
395 }
396
397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
398 {
399 int max_ports;
400 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
401
402 if (hcd->speed == HCD_USB3) {
403 max_ports = xhci->num_usb3_ports;
404 *port_array = xhci->usb3_ports;
405 } else {
406 max_ports = xhci->num_usb2_ports;
407 *port_array = xhci->usb2_ports;
408 }
409
410 return max_ports;
411 }
412
413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
414 int port_id, u32 link_state)
415 {
416 u32 temp;
417
418 temp = xhci_readl(xhci, port_array[port_id]);
419 temp = xhci_port_state_to_neutral(temp);
420 temp &= ~PORT_PLS_MASK;
421 temp |= PORT_LINK_STROBE | link_state;
422 xhci_writel(xhci, temp, port_array[port_id]);
423 }
424
425 void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
426 __le32 __iomem **port_array, int port_id, u16 wake_mask)
427 {
428 u32 temp;
429
430 temp = xhci_readl(xhci, port_array[port_id]);
431 temp = xhci_port_state_to_neutral(temp);
432
433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
434 temp |= PORT_WKCONN_E;
435 else
436 temp &= ~PORT_WKCONN_E;
437
438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
439 temp |= PORT_WKDISC_E;
440 else
441 temp &= ~PORT_WKDISC_E;
442
443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
444 temp |= PORT_WKOC_E;
445 else
446 temp &= ~PORT_WKOC_E;
447
448 xhci_writel(xhci, temp, port_array[port_id]);
449 }
450
451 /* Test and clear port RWC bit */
452 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
453 int port_id, u32 port_bit)
454 {
455 u32 temp;
456
457 temp = xhci_readl(xhci, port_array[port_id]);
458 if (temp & port_bit) {
459 temp = xhci_port_state_to_neutral(temp);
460 temp |= port_bit;
461 xhci_writel(xhci, temp, port_array[port_id]);
462 }
463 }
464
465 /* Updates Link Status for super Speed port */
466 static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
467 {
468 u32 pls = status_reg & PORT_PLS_MASK;
469
470 /* resume state is a xHCI internal state.
471 * Do not report it to usb core.
472 */
473 if (pls == XDEV_RESUME)
474 return;
475
476 /* When the CAS bit is set then warm reset
477 * should be performed on port
478 */
479 if (status_reg & PORT_CAS) {
480 /* The CAS bit can be set while the port is
481 * in any link state.
482 * Only roothubs have CAS bit, so we
483 * pretend to be in compliance mode
484 * unless we're already in compliance
485 * or the inactive state.
486 */
487 if (pls != USB_SS_PORT_LS_COMP_MOD &&
488 pls != USB_SS_PORT_LS_SS_INACTIVE) {
489 pls = USB_SS_PORT_LS_COMP_MOD;
490 }
491 /* Return also connection bit -
492 * hub state machine resets port
493 * when this bit is set.
494 */
495 pls |= USB_PORT_STAT_CONNECTION;
496 }
497 /* update status field */
498 *status |= pls;
499 }
500
501 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
502 u16 wIndex, char *buf, u16 wLength)
503 {
504 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
505 int max_ports;
506 unsigned long flags;
507 u32 temp, status;
508 int retval = 0;
509 __le32 __iomem **port_array;
510 int slot_id;
511 struct xhci_bus_state *bus_state;
512 u16 link_state = 0;
513 u16 wake_mask = 0;
514 u16 timeout = 0;
515
516 max_ports = xhci_get_ports(hcd, &port_array);
517 bus_state = &xhci->bus_state[hcd_index(hcd)];
518
519 spin_lock_irqsave(&xhci->lock, flags);
520 switch (typeReq) {
521 case GetHubStatus:
522 /* No power source, over-current reported per port */
523 memset(buf, 0, 4);
524 break;
525 case GetHubDescriptor:
526 /* Check to make sure userspace is asking for the USB 3.0 hub
527 * descriptor for the USB 3.0 roothub. If not, we stall the
528 * endpoint, like external hubs do.
529 */
530 if (hcd->speed == HCD_USB3 &&
531 (wLength < USB_DT_SS_HUB_SIZE ||
532 wValue != (USB_DT_SS_HUB << 8))) {
533 xhci_dbg(xhci, "Wrong hub descriptor type for "
534 "USB 3.0 roothub.\n");
535 goto error;
536 }
537 xhci_hub_descriptor(hcd, xhci,
538 (struct usb_hub_descriptor *) buf);
539 break;
540 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
541 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
542 goto error;
543
544 if (hcd->speed != HCD_USB3)
545 goto error;
546
547 memcpy(buf, &usb_bos_descriptor,
548 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
549 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
550 buf[12] = HCS_U1_LATENCY(temp);
551 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
552
553 spin_unlock_irqrestore(&xhci->lock, flags);
554 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
555 case GetPortStatus:
556 if (!wIndex || wIndex > max_ports)
557 goto error;
558 wIndex--;
559 status = 0;
560 temp = xhci_readl(xhci, port_array[wIndex]);
561 if (temp == 0xffffffff) {
562 retval = -ENODEV;
563 break;
564 }
565 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
566
567 /* wPortChange bits */
568 if (temp & PORT_CSC)
569 status |= USB_PORT_STAT_C_CONNECTION << 16;
570 if (temp & PORT_PEC)
571 status |= USB_PORT_STAT_C_ENABLE << 16;
572 if ((temp & PORT_OCC))
573 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
574 if ((temp & PORT_RC))
575 status |= USB_PORT_STAT_C_RESET << 16;
576 /* USB3.0 only */
577 if (hcd->speed == HCD_USB3) {
578 if ((temp & PORT_PLC))
579 status |= USB_PORT_STAT_C_LINK_STATE << 16;
580 if ((temp & PORT_WRC))
581 status |= USB_PORT_STAT_C_BH_RESET << 16;
582 }
583
584 if (hcd->speed != HCD_USB3) {
585 if ((temp & PORT_PLS_MASK) == XDEV_U3
586 && (temp & PORT_POWER))
587 status |= USB_PORT_STAT_SUSPEND;
588 }
589 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
590 !DEV_SUPERSPEED(temp)) {
591 if ((temp & PORT_RESET) || !(temp & PORT_PE))
592 goto error;
593 if (time_after_eq(jiffies,
594 bus_state->resume_done[wIndex])) {
595 xhci_dbg(xhci, "Resume USB2 port %d\n",
596 wIndex + 1);
597 bus_state->resume_done[wIndex] = 0;
598 clear_bit(wIndex, &bus_state->resuming_ports);
599 xhci_set_link_state(xhci, port_array, wIndex,
600 XDEV_U0);
601 xhci_dbg(xhci, "set port %d resume\n",
602 wIndex + 1);
603 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
604 wIndex + 1);
605 if (!slot_id) {
606 xhci_dbg(xhci, "slot_id is zero\n");
607 goto error;
608 }
609 xhci_ring_device(xhci, slot_id);
610 bus_state->port_c_suspend |= 1 << wIndex;
611 bus_state->suspended_ports &= ~(1 << wIndex);
612 } else {
613 /*
614 * The resume has been signaling for less than
615 * 20ms. Report the port status as SUSPEND,
616 * let the usbcore check port status again
617 * and clear resume signaling later.
618 */
619 status |= USB_PORT_STAT_SUSPEND;
620 }
621 }
622 if ((temp & PORT_PLS_MASK) == XDEV_U0
623 && (temp & PORT_POWER)
624 && (bus_state->suspended_ports & (1 << wIndex))) {
625 bus_state->suspended_ports &= ~(1 << wIndex);
626 if (hcd->speed != HCD_USB3)
627 bus_state->port_c_suspend |= 1 << wIndex;
628 }
629 if (temp & PORT_CONNECT) {
630 status |= USB_PORT_STAT_CONNECTION;
631 status |= xhci_port_speed(temp);
632 }
633 if (temp & PORT_PE)
634 status |= USB_PORT_STAT_ENABLE;
635 if (temp & PORT_OC)
636 status |= USB_PORT_STAT_OVERCURRENT;
637 if (temp & PORT_RESET)
638 status |= USB_PORT_STAT_RESET;
639 if (temp & PORT_POWER) {
640 if (hcd->speed == HCD_USB3)
641 status |= USB_SS_PORT_STAT_POWER;
642 else
643 status |= USB_PORT_STAT_POWER;
644 }
645 /* Update Port Link State for super speed ports*/
646 if (hcd->speed == HCD_USB3) {
647 xhci_hub_report_link_state(&status, temp);
648 }
649 if (bus_state->port_c_suspend & (1 << wIndex))
650 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
651 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
652 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
653 break;
654 case SetPortFeature:
655 if (wValue == USB_PORT_FEAT_LINK_STATE)
656 link_state = (wIndex & 0xff00) >> 3;
657 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
658 wake_mask = wIndex & 0xff00;
659 /* The MSB of wIndex is the U1/U2 timeout */
660 timeout = (wIndex & 0xff00) >> 8;
661 wIndex &= 0xff;
662 if (!wIndex || wIndex > max_ports)
663 goto error;
664 wIndex--;
665 temp = xhci_readl(xhci, port_array[wIndex]);
666 if (temp == 0xffffffff) {
667 retval = -ENODEV;
668 break;
669 }
670 temp = xhci_port_state_to_neutral(temp);
671 /* FIXME: What new port features do we need to support? */
672 switch (wValue) {
673 case USB_PORT_FEAT_SUSPEND:
674 temp = xhci_readl(xhci, port_array[wIndex]);
675 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
676 /* Resume the port to U0 first */
677 xhci_set_link_state(xhci, port_array, wIndex,
678 XDEV_U0);
679 spin_unlock_irqrestore(&xhci->lock, flags);
680 msleep(10);
681 spin_lock_irqsave(&xhci->lock, flags);
682 }
683 /* In spec software should not attempt to suspend
684 * a port unless the port reports that it is in the
685 * enabled (PED = ‘1’,PLS < ‘3’) state.
686 */
687 temp = xhci_readl(xhci, port_array[wIndex]);
688 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
689 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
690 xhci_warn(xhci, "USB core suspending device "
691 "not in U0/U1/U2.\n");
692 goto error;
693 }
694
695 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
696 wIndex + 1);
697 if (!slot_id) {
698 xhci_warn(xhci, "slot_id is zero\n");
699 goto error;
700 }
701 /* unlock to execute stop endpoint commands */
702 spin_unlock_irqrestore(&xhci->lock, flags);
703 xhci_stop_device(xhci, slot_id, 1);
704 spin_lock_irqsave(&xhci->lock, flags);
705
706 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
707
708 spin_unlock_irqrestore(&xhci->lock, flags);
709 msleep(10); /* wait device to enter */
710 spin_lock_irqsave(&xhci->lock, flags);
711
712 temp = xhci_readl(xhci, port_array[wIndex]);
713 bus_state->suspended_ports |= 1 << wIndex;
714 break;
715 case USB_PORT_FEAT_LINK_STATE:
716 temp = xhci_readl(xhci, port_array[wIndex]);
717 /* Software should not attempt to set
718 * port link state above '5' (Rx.Detect) and the port
719 * must be enabled.
720 */
721 if ((temp & PORT_PE) == 0 ||
722 (link_state > USB_SS_PORT_LS_RX_DETECT)) {
723 xhci_warn(xhci, "Cannot set link state.\n");
724 goto error;
725 }
726
727 if (link_state == USB_SS_PORT_LS_U3) {
728 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
729 wIndex + 1);
730 if (slot_id) {
731 /* unlock to execute stop endpoint
732 * commands */
733 spin_unlock_irqrestore(&xhci->lock,
734 flags);
735 xhci_stop_device(xhci, slot_id, 1);
736 spin_lock_irqsave(&xhci->lock, flags);
737 }
738 }
739
740 xhci_set_link_state(xhci, port_array, wIndex,
741 link_state);
742
743 spin_unlock_irqrestore(&xhci->lock, flags);
744 msleep(20); /* wait device to enter */
745 spin_lock_irqsave(&xhci->lock, flags);
746
747 temp = xhci_readl(xhci, port_array[wIndex]);
748 if (link_state == USB_SS_PORT_LS_U3)
749 bus_state->suspended_ports |= 1 << wIndex;
750 break;
751 case USB_PORT_FEAT_POWER:
752 /*
753 * Turn on ports, even if there isn't per-port switching.
754 * HC will report connect events even before this is set.
755 * However, khubd will ignore the roothub events until
756 * the roothub is registered.
757 */
758 xhci_writel(xhci, temp | PORT_POWER,
759 port_array[wIndex]);
760
761 temp = xhci_readl(xhci, port_array[wIndex]);
762 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
763 break;
764 case USB_PORT_FEAT_RESET:
765 temp = (temp | PORT_RESET);
766 xhci_writel(xhci, temp, port_array[wIndex]);
767
768 temp = xhci_readl(xhci, port_array[wIndex]);
769 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
770 break;
771 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
772 xhci_set_remote_wake_mask(xhci, port_array,
773 wIndex, wake_mask);
774 temp = xhci_readl(xhci, port_array[wIndex]);
775 xhci_dbg(xhci, "set port remote wake mask, "
776 "actual port %d status = 0x%x\n",
777 wIndex, temp);
778 break;
779 case USB_PORT_FEAT_BH_PORT_RESET:
780 temp |= PORT_WR;
781 xhci_writel(xhci, temp, port_array[wIndex]);
782
783 temp = xhci_readl(xhci, port_array[wIndex]);
784 break;
785 case USB_PORT_FEAT_U1_TIMEOUT:
786 if (hcd->speed != HCD_USB3)
787 goto error;
788 temp = xhci_readl(xhci, port_array[wIndex] + 1);
789 temp &= ~PORT_U1_TIMEOUT_MASK;
790 temp |= PORT_U1_TIMEOUT(timeout);
791 xhci_writel(xhci, temp, port_array[wIndex] + 1);
792 break;
793 case USB_PORT_FEAT_U2_TIMEOUT:
794 if (hcd->speed != HCD_USB3)
795 goto error;
796 temp = xhci_readl(xhci, port_array[wIndex] + 1);
797 temp &= ~PORT_U2_TIMEOUT_MASK;
798 temp |= PORT_U2_TIMEOUT(timeout);
799 xhci_writel(xhci, temp, port_array[wIndex] + 1);
800 break;
801 default:
802 goto error;
803 }
804 /* unblock any posted writes */
805 temp = xhci_readl(xhci, port_array[wIndex]);
806 break;
807 case ClearPortFeature:
808 if (!wIndex || wIndex > max_ports)
809 goto error;
810 wIndex--;
811 temp = xhci_readl(xhci, port_array[wIndex]);
812 if (temp == 0xffffffff) {
813 retval = -ENODEV;
814 break;
815 }
816 /* FIXME: What new port features do we need to support? */
817 temp = xhci_port_state_to_neutral(temp);
818 switch (wValue) {
819 case USB_PORT_FEAT_SUSPEND:
820 temp = xhci_readl(xhci, port_array[wIndex]);
821 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
822 xhci_dbg(xhci, "PORTSC %04x\n", temp);
823 if (temp & PORT_RESET)
824 goto error;
825 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
826 if ((temp & PORT_PE) == 0)
827 goto error;
828
829 xhci_set_link_state(xhci, port_array, wIndex,
830 XDEV_RESUME);
831 spin_unlock_irqrestore(&xhci->lock, flags);
832 msleep(20);
833 spin_lock_irqsave(&xhci->lock, flags);
834 xhci_set_link_state(xhci, port_array, wIndex,
835 XDEV_U0);
836 }
837 bus_state->port_c_suspend |= 1 << wIndex;
838
839 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
840 wIndex + 1);
841 if (!slot_id) {
842 xhci_dbg(xhci, "slot_id is zero\n");
843 goto error;
844 }
845 xhci_ring_device(xhci, slot_id);
846 break;
847 case USB_PORT_FEAT_C_SUSPEND:
848 bus_state->port_c_suspend &= ~(1 << wIndex);
849 case USB_PORT_FEAT_C_RESET:
850 case USB_PORT_FEAT_C_BH_PORT_RESET:
851 case USB_PORT_FEAT_C_CONNECTION:
852 case USB_PORT_FEAT_C_OVER_CURRENT:
853 case USB_PORT_FEAT_C_ENABLE:
854 case USB_PORT_FEAT_C_PORT_LINK_STATE:
855 xhci_clear_port_change_bit(xhci, wValue, wIndex,
856 port_array[wIndex], temp);
857 break;
858 case USB_PORT_FEAT_ENABLE:
859 xhci_disable_port(hcd, xhci, wIndex,
860 port_array[wIndex], temp);
861 break;
862 default:
863 goto error;
864 }
865 break;
866 default:
867 error:
868 /* "stall" on error */
869 retval = -EPIPE;
870 }
871 spin_unlock_irqrestore(&xhci->lock, flags);
872 return retval;
873 }
874
875 /*
876 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
877 * Ports are 0-indexed from the HCD point of view,
878 * and 1-indexed from the USB core pointer of view.
879 *
880 * Note that the status change bits will be cleared as soon as a port status
881 * change event is generated, so we use the saved status from that event.
882 */
883 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
884 {
885 unsigned long flags;
886 u32 temp, status;
887 u32 mask;
888 int i, retval;
889 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
890 int max_ports;
891 __le32 __iomem **port_array;
892 struct xhci_bus_state *bus_state;
893
894 max_ports = xhci_get_ports(hcd, &port_array);
895 bus_state = &xhci->bus_state[hcd_index(hcd)];
896
897 /* Initial status is no changes */
898 retval = (max_ports + 8) / 8;
899 memset(buf, 0, retval);
900
901 /*
902 * Inform the usbcore about resume-in-progress by returning
903 * a non-zero value even if there are no status changes.
904 */
905 status = bus_state->resuming_ports;
906
907 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
908
909 spin_lock_irqsave(&xhci->lock, flags);
910 /* For each port, did anything change? If so, set that bit in buf. */
911 for (i = 0; i < max_ports; i++) {
912 temp = xhci_readl(xhci, port_array[i]);
913 if (temp == 0xffffffff) {
914 retval = -ENODEV;
915 break;
916 }
917 if ((temp & mask) != 0 ||
918 (bus_state->port_c_suspend & 1 << i) ||
919 (bus_state->resume_done[i] && time_after_eq(
920 jiffies, bus_state->resume_done[i]))) {
921 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
922 status = 1;
923 }
924 }
925 spin_unlock_irqrestore(&xhci->lock, flags);
926 return status ? retval : 0;
927 }
928
929 #ifdef CONFIG_PM
930
931 int xhci_bus_suspend(struct usb_hcd *hcd)
932 {
933 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
934 int max_ports, port_index;
935 __le32 __iomem **port_array;
936 struct xhci_bus_state *bus_state;
937 unsigned long flags;
938
939 max_ports = xhci_get_ports(hcd, &port_array);
940 bus_state = &xhci->bus_state[hcd_index(hcd)];
941
942 spin_lock_irqsave(&xhci->lock, flags);
943
944 if (hcd->self.root_hub->do_remote_wakeup) {
945 if (bus_state->resuming_ports) {
946 spin_unlock_irqrestore(&xhci->lock, flags);
947 xhci_dbg(xhci, "suspend failed because "
948 "a port is resuming\n");
949 return -EBUSY;
950 }
951 }
952
953 port_index = max_ports;
954 bus_state->bus_suspended = 0;
955 while (port_index--) {
956 /* suspend the port if the port is not suspended */
957 u32 t1, t2;
958 int slot_id;
959
960 t1 = xhci_readl(xhci, port_array[port_index]);
961 t2 = xhci_port_state_to_neutral(t1);
962
963 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
964 xhci_dbg(xhci, "port %d not suspended\n", port_index);
965 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
966 port_index + 1);
967 if (slot_id) {
968 spin_unlock_irqrestore(&xhci->lock, flags);
969 xhci_stop_device(xhci, slot_id, 1);
970 spin_lock_irqsave(&xhci->lock, flags);
971 }
972 t2 &= ~PORT_PLS_MASK;
973 t2 |= PORT_LINK_STROBE | XDEV_U3;
974 set_bit(port_index, &bus_state->bus_suspended);
975 }
976 /* USB core sets remote wake mask for USB 3.0 hubs,
977 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
978 * is enabled, so also enable remote wake here.
979 */
980 if (hcd->self.root_hub->do_remote_wakeup) {
981 if (t1 & PORT_CONNECT) {
982 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
983 t2 &= ~PORT_WKCONN_E;
984 } else {
985 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
986 t2 &= ~PORT_WKDISC_E;
987 }
988 } else
989 t2 &= ~PORT_WAKE_BITS;
990
991 t1 = xhci_port_state_to_neutral(t1);
992 if (t1 != t2)
993 xhci_writel(xhci, t2, port_array[port_index]);
994
995 if (hcd->speed != HCD_USB3) {
996 /* enable remote wake up for USB 2.0 */
997 __le32 __iomem *addr;
998 u32 tmp;
999
1000 /* Add one to the port status register address to get
1001 * the port power control register address.
1002 */
1003 addr = port_array[port_index] + 1;
1004 tmp = xhci_readl(xhci, addr);
1005 tmp |= PORT_RWE;
1006 xhci_writel(xhci, tmp, addr);
1007 }
1008 }
1009 hcd->state = HC_STATE_SUSPENDED;
1010 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1011 spin_unlock_irqrestore(&xhci->lock, flags);
1012 return 0;
1013 }
1014
1015 int xhci_bus_resume(struct usb_hcd *hcd)
1016 {
1017 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1018 int max_ports, port_index;
1019 __le32 __iomem **port_array;
1020 struct xhci_bus_state *bus_state;
1021 u32 temp;
1022 unsigned long flags;
1023
1024 max_ports = xhci_get_ports(hcd, &port_array);
1025 bus_state = &xhci->bus_state[hcd_index(hcd)];
1026
1027 if (time_before(jiffies, bus_state->next_statechange))
1028 msleep(5);
1029
1030 spin_lock_irqsave(&xhci->lock, flags);
1031 if (!HCD_HW_ACCESSIBLE(hcd)) {
1032 spin_unlock_irqrestore(&xhci->lock, flags);
1033 return -ESHUTDOWN;
1034 }
1035
1036 /* delay the irqs */
1037 temp = xhci_readl(xhci, &xhci->op_regs->command);
1038 temp &= ~CMD_EIE;
1039 xhci_writel(xhci, temp, &xhci->op_regs->command);
1040
1041 port_index = max_ports;
1042 while (port_index--) {
1043 /* Check whether need resume ports. If needed
1044 resume port and disable remote wakeup */
1045 u32 temp;
1046 int slot_id;
1047
1048 temp = xhci_readl(xhci, port_array[port_index]);
1049 if (DEV_SUPERSPEED(temp))
1050 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1051 else
1052 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1053 if (test_bit(port_index, &bus_state->bus_suspended) &&
1054 (temp & PORT_PLS_MASK)) {
1055 if (DEV_SUPERSPEED(temp)) {
1056 xhci_set_link_state(xhci, port_array,
1057 port_index, XDEV_U0);
1058 } else {
1059 xhci_set_link_state(xhci, port_array,
1060 port_index, XDEV_RESUME);
1061
1062 spin_unlock_irqrestore(&xhci->lock, flags);
1063 msleep(20);
1064 spin_lock_irqsave(&xhci->lock, flags);
1065
1066 xhci_set_link_state(xhci, port_array,
1067 port_index, XDEV_U0);
1068 }
1069 /* wait for the port to enter U0 and report port link
1070 * state change.
1071 */
1072 spin_unlock_irqrestore(&xhci->lock, flags);
1073 msleep(20);
1074 spin_lock_irqsave(&xhci->lock, flags);
1075
1076 /* Clear PLC */
1077 xhci_test_and_clear_bit(xhci, port_array, port_index,
1078 PORT_PLC);
1079
1080 slot_id = xhci_find_slot_id_by_port(hcd,
1081 xhci, port_index + 1);
1082 if (slot_id)
1083 xhci_ring_device(xhci, slot_id);
1084 } else
1085 xhci_writel(xhci, temp, port_array[port_index]);
1086
1087 if (hcd->speed != HCD_USB3) {
1088 /* disable remote wake up for USB 2.0 */
1089 __le32 __iomem *addr;
1090 u32 tmp;
1091
1092 /* Add one to the port status register address to get
1093 * the port power control register address.
1094 */
1095 addr = port_array[port_index] + 1;
1096 tmp = xhci_readl(xhci, addr);
1097 tmp &= ~PORT_RWE;
1098 xhci_writel(xhci, tmp, addr);
1099 }
1100 }
1101
1102 (void) xhci_readl(xhci, &xhci->op_regs->command);
1103
1104 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1105 /* re-enable irqs */
1106 temp = xhci_readl(xhci, &xhci->op_regs->command);
1107 temp |= CMD_EIE;
1108 xhci_writel(xhci, temp, &xhci->op_regs->command);
1109 temp = xhci_readl(xhci, &xhci->op_regs->command);
1110
1111 spin_unlock_irqrestore(&xhci->lock, flags);
1112 return 0;
1113 }
1114
1115 #endif /* CONFIG_PM */
Linux kernel - Deliverables
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