2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/gfp.h>
24 #include <asm/unaligned.h>
28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
32 /* usb 1.1 root hub device descriptor */
33 static u8 usb_bos_descriptor
[] = {
34 USB_DT_BOS_SIZE
, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS
, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE
, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
41 USB_SS_CAP_TYPE
, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION
, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
51 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
52 struct usb_hub_descriptor
*desc
, int ports
)
56 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
57 desc
->bHubContrCurrent
= 0;
59 desc
->bNbrPorts
= ports
;
61 /* Bits 1:0 - support per-port power switching, or power always on */
62 if (HCC_PPC(xhci
->hcc_params
))
63 temp
|= HUB_CHAR_INDV_PORT_LPSM
;
65 temp
|= HUB_CHAR_NO_LPSM
;
66 /* Bit 2 - root hubs are not part of a compound device */
67 /* Bits 4:3 - individual port over current protection */
68 temp
|= HUB_CHAR_INDV_PORT_OCPM
;
69 /* Bits 6:5 - no TTs in root ports */
70 /* Bit 7 - no port indicators */
71 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
74 /* Fill in the USB 2.0 roothub descriptor */
75 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
76 struct usb_hub_descriptor
*desc
)
80 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
84 ports
= xhci
->num_usb2_ports
;
86 xhci_common_hub_descriptor(xhci
, desc
, ports
);
87 desc
->bDescriptorType
= USB_DT_HUB
;
88 temp
= 1 + (ports
/ 8);
89 desc
->bDescLength
= USB_DT_HUB_NONVAR_SIZE
+ 2 * temp
;
91 /* The Device Removable bits are reported on a byte granularity.
92 * If the port doesn't exist within that byte, the bit is set to 0.
94 memset(port_removable
, 0, sizeof(port_removable
));
95 for (i
= 0; i
< ports
; i
++) {
96 portsc
= xhci_readl(xhci
, xhci
->usb2_ports
[i
]);
97 /* If a device is removable, PORTSC reports a 0, same as in the
98 * hub descriptor DeviceRemovable bits.
100 if (portsc
& PORT_DEV_REMOVE
)
101 /* This math is hairy because bit 0 of DeviceRemovable
102 * is reserved, and bit 1 is for port 1, etc.
104 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
108 * ports on it. The USB 2.0 specification says that there are two
109 * variable length fields at the end of the hub descriptor:
110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
113 * 0xFF, so we initialize the both arrays (DeviceRemovable and
114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
115 * set of ports that actually exist.
117 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
118 sizeof(desc
->u
.hs
.DeviceRemovable
));
119 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
120 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
122 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
123 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
127 /* Fill in the USB 3.0 roothub descriptor */
128 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
129 struct usb_hub_descriptor
*desc
)
136 ports
= xhci
->num_usb3_ports
;
137 xhci_common_hub_descriptor(xhci
, desc
, ports
);
138 desc
->bDescriptorType
= USB_DT_SS_HUB
;
139 desc
->bDescLength
= USB_DT_SS_HUB_SIZE
;
141 /* header decode latency should be zero for roothubs,
142 * see section 4.23.5.2.
144 desc
->u
.ss
.bHubHdrDecLat
= 0;
145 desc
->u
.ss
.wHubDelay
= 0;
148 /* bit 0 is reserved, bit 1 is for port 1, etc. */
149 for (i
= 0; i
< ports
; i
++) {
150 portsc
= xhci_readl(xhci
, xhci
->usb3_ports
[i
]);
151 if (portsc
& PORT_DEV_REMOVE
)
152 port_removable
|= 1 << (i
+ 1);
154 memset(&desc
->u
.ss
.DeviceRemovable
,
155 (__force __u16
) cpu_to_le16(port_removable
),
159 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
160 struct usb_hub_descriptor
*desc
)
163 if (hcd
->speed
== HCD_USB3
)
164 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
166 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
170 static unsigned int xhci_port_speed(unsigned int port_status
)
172 if (DEV_LOWSPEED(port_status
))
173 return USB_PORT_STAT_LOW_SPEED
;
174 if (DEV_HIGHSPEED(port_status
))
175 return USB_PORT_STAT_HIGH_SPEED
;
177 * FIXME: Yes, we should check for full speed, but the core uses that as
178 * a default in portspeed() in usb/core/hub.c (which is the only place
179 * USB_PORT_STAT_*_SPEED is used).
185 * These bits are Read Only (RO) and should be saved and written to the
186 * registers: 0, 3, 10:13, 30
187 * connect status, over-current status, port speed, and device removable.
188 * connect status and port speed are also sticky - meaning they're in
189 * the AUX well and they aren't changed by a hot, warm, or cold reset.
191 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
194 * bits 5:8, 9, 14:15, 25:27
195 * link state, port power, port indicator state, "wake on" enable state
197 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
202 #define XHCI_PORT_RW1S ((1<<4))
204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
205 * bits 1, 17, 18, 19, 20, 21, 22, 23
206 * port enable/disable, and
207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
208 * over-current, reset, link state, and L1 change
210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
215 #define XHCI_PORT_RW ((1<<16))
217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
220 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
223 * Given a port state, this function returns a value that would result in the
224 * port being in the same state, if the value was written to the port status
226 * Save Read Only (RO) bits and save read/write bits where
227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
230 u32
xhci_port_state_to_neutral(u32 state
)
232 /* Save read-only status and port state */
233 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
237 * find slot id based on port number.
238 * @port: The one-based port number from one of the two split roothubs.
240 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
245 enum usb_device_speed speed
;
248 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
251 speed
= xhci
->devs
[i
]->udev
->speed
;
252 if (((speed
== USB_SPEED_SUPER
) == (hcd
->speed
== HCD_USB3
))
253 && xhci
->devs
[i
]->fake_port
== port
) {
264 * It issues stop endpoint command for EP 0 to 30. And wait the last command
266 * suspend will set to 1, if suspend bit need to set in command.
268 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
270 struct xhci_virt_device
*virt_dev
;
271 struct xhci_command
*cmd
;
278 virt_dev
= xhci
->devs
[slot_id
];
279 cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
281 xhci_dbg(xhci
, "Couldn't allocate command structure.\n");
285 spin_lock_irqsave(&xhci
->lock
, flags
);
286 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
287 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
)
288 xhci_queue_stop_endpoint(xhci
, slot_id
, i
, suspend
);
290 cmd
->command_trb
= xhci
->cmd_ring
->enqueue
;
291 list_add_tail(&cmd
->cmd_list
, &virt_dev
->cmd_list
);
292 xhci_queue_stop_endpoint(xhci
, slot_id
, 0, suspend
);
293 xhci_ring_cmd_db(xhci
);
294 spin_unlock_irqrestore(&xhci
->lock
, flags
);
296 /* Wait for last stop endpoint command to finish */
297 timeleft
= wait_for_completion_interruptible_timeout(
299 USB_CTRL_SET_TIMEOUT
);
301 xhci_warn(xhci
, "%s while waiting for stop endpoint command\n",
302 timeleft
== 0 ? "Timeout" : "Signal");
303 spin_lock_irqsave(&xhci
->lock
, flags
);
304 /* The timeout might have raced with the event ring handler, so
305 * only delete from the list if the item isn't poisoned.
307 if (cmd
->cmd_list
.next
!= LIST_POISON1
)
308 list_del(&cmd
->cmd_list
);
309 spin_unlock_irqrestore(&xhci
->lock
, flags
);
311 goto command_cleanup
;
315 xhci_free_command(xhci
, cmd
);
320 * Ring device, it rings the all doorbells unconditionally.
322 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
326 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++)
327 if (xhci
->devs
[slot_id
]->eps
[i
].ring
&&
328 xhci
->devs
[slot_id
]->eps
[i
].ring
->dequeue
)
329 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
334 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
335 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
337 /* Don't allow the USB core to disable SuperSpeed ports. */
338 if (hcd
->speed
== HCD_USB3
) {
339 xhci_dbg(xhci
, "Ignoring request to disable "
340 "SuperSpeed port.\n");
344 /* Write 1 to disable the port */
345 xhci_writel(xhci
, port_status
| PORT_PE
, addr
);
346 port_status
= xhci_readl(xhci
, addr
);
347 xhci_dbg(xhci
, "disable port, actual port %d status = 0x%x\n",
348 wIndex
, port_status
);
351 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
352 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
354 char *port_change_bit
;
358 case USB_PORT_FEAT_C_RESET
:
360 port_change_bit
= "reset";
362 case USB_PORT_FEAT_C_BH_PORT_RESET
:
364 port_change_bit
= "warm(BH) reset";
366 case USB_PORT_FEAT_C_CONNECTION
:
368 port_change_bit
= "connect";
370 case USB_PORT_FEAT_C_OVER_CURRENT
:
372 port_change_bit
= "over-current";
374 case USB_PORT_FEAT_C_ENABLE
:
376 port_change_bit
= "enable/disable";
378 case USB_PORT_FEAT_C_SUSPEND
:
380 port_change_bit
= "suspend/resume";
382 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
384 port_change_bit
= "link state";
387 /* Should never happen */
390 /* Change bits are all write 1 to clear */
391 xhci_writel(xhci
, port_status
| status
, addr
);
392 port_status
= xhci_readl(xhci
, addr
);
393 xhci_dbg(xhci
, "clear port %s change, actual port %d status = 0x%x\n",
394 port_change_bit
, wIndex
, port_status
);
397 static int xhci_get_ports(struct usb_hcd
*hcd
, __le32 __iomem
***port_array
)
400 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
402 if (hcd
->speed
== HCD_USB3
) {
403 max_ports
= xhci
->num_usb3_ports
;
404 *port_array
= xhci
->usb3_ports
;
406 max_ports
= xhci
->num_usb2_ports
;
407 *port_array
= xhci
->usb2_ports
;
413 void xhci_set_link_state(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
414 int port_id
, u32 link_state
)
418 temp
= xhci_readl(xhci
, port_array
[port_id
]);
419 temp
= xhci_port_state_to_neutral(temp
);
420 temp
&= ~PORT_PLS_MASK
;
421 temp
|= PORT_LINK_STROBE
| link_state
;
422 xhci_writel(xhci
, temp
, port_array
[port_id
]);
425 void xhci_set_remote_wake_mask(struct xhci_hcd
*xhci
,
426 __le32 __iomem
**port_array
, int port_id
, u16 wake_mask
)
430 temp
= xhci_readl(xhci
, port_array
[port_id
]);
431 temp
= xhci_port_state_to_neutral(temp
);
433 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_CONNECT
)
434 temp
|= PORT_WKCONN_E
;
436 temp
&= ~PORT_WKCONN_E
;
438 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
)
439 temp
|= PORT_WKDISC_E
;
441 temp
&= ~PORT_WKDISC_E
;
443 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
)
446 temp
&= ~PORT_WKOC_E
;
448 xhci_writel(xhci
, temp
, port_array
[port_id
]);
451 /* Test and clear port RWC bit */
452 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
453 int port_id
, u32 port_bit
)
457 temp
= xhci_readl(xhci
, port_array
[port_id
]);
458 if (temp
& port_bit
) {
459 temp
= xhci_port_state_to_neutral(temp
);
461 xhci_writel(xhci
, temp
, port_array
[port_id
]);
465 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
466 u16 wIndex
, char *buf
, u16 wLength
)
468 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
473 __le32 __iomem
**port_array
;
475 struct xhci_bus_state
*bus_state
;
480 max_ports
= xhci_get_ports(hcd
, &port_array
);
481 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
483 spin_lock_irqsave(&xhci
->lock
, flags
);
486 /* No power source, over-current reported per port */
489 case GetHubDescriptor
:
490 /* Check to make sure userspace is asking for the USB 3.0 hub
491 * descriptor for the USB 3.0 roothub. If not, we stall the
492 * endpoint, like external hubs do.
494 if (hcd
->speed
== HCD_USB3
&&
495 (wLength
< USB_DT_SS_HUB_SIZE
||
496 wValue
!= (USB_DT_SS_HUB
<< 8))) {
497 xhci_dbg(xhci
, "Wrong hub descriptor type for "
498 "USB 3.0 roothub.\n");
501 xhci_hub_descriptor(hcd
, xhci
,
502 (struct usb_hub_descriptor
*) buf
);
504 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
505 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
508 if (hcd
->speed
!= HCD_USB3
)
511 memcpy(buf
, &usb_bos_descriptor
,
512 USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
);
513 temp
= xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params3
);
514 buf
[12] = HCS_U1_LATENCY(temp
);
515 put_unaligned_le16(HCS_U2_LATENCY(temp
), &buf
[13]);
517 spin_unlock_irqrestore(&xhci
->lock
, flags
);
518 return USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
520 if (!wIndex
|| wIndex
> max_ports
)
524 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
525 if (temp
== 0xffffffff) {
529 xhci_dbg(xhci
, "get port status, actual port %d status = 0x%x\n", wIndex
, temp
);
531 /* wPortChange bits */
533 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
535 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
536 if ((temp
& PORT_OCC
))
537 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
538 if ((temp
& PORT_RC
))
539 status
|= USB_PORT_STAT_C_RESET
<< 16;
541 if (hcd
->speed
== HCD_USB3
) {
542 if ((temp
& PORT_PLC
))
543 status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
544 if ((temp
& PORT_WRC
))
545 status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
548 if (hcd
->speed
!= HCD_USB3
) {
549 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
550 && (temp
& PORT_POWER
))
551 status
|= USB_PORT_STAT_SUSPEND
;
553 if ((temp
& PORT_PLS_MASK
) == XDEV_RESUME
&&
554 !DEV_SUPERSPEED(temp
)) {
555 if ((temp
& PORT_RESET
) || !(temp
& PORT_PE
))
557 if (time_after_eq(jiffies
,
558 bus_state
->resume_done
[wIndex
])) {
559 xhci_dbg(xhci
, "Resume USB2 port %d\n",
561 bus_state
->resume_done
[wIndex
] = 0;
562 clear_bit(wIndex
, &bus_state
->resuming_ports
);
563 xhci_set_link_state(xhci
, port_array
, wIndex
,
565 xhci_dbg(xhci
, "set port %d resume\n",
567 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
570 xhci_dbg(xhci
, "slot_id is zero\n");
573 xhci_ring_device(xhci
, slot_id
);
574 bus_state
->port_c_suspend
|= 1 << wIndex
;
575 bus_state
->suspended_ports
&= ~(1 << wIndex
);
578 * The resume has been signaling for less than
579 * 20ms. Report the port status as SUSPEND,
580 * let the usbcore check port status again
581 * and clear resume signaling later.
583 status
|= USB_PORT_STAT_SUSPEND
;
586 if ((temp
& PORT_PLS_MASK
) == XDEV_U0
587 && (temp
& PORT_POWER
)
588 && (bus_state
->suspended_ports
& (1 << wIndex
))) {
589 bus_state
->suspended_ports
&= ~(1 << wIndex
);
590 if (hcd
->speed
!= HCD_USB3
)
591 bus_state
->port_c_suspend
|= 1 << wIndex
;
593 if (temp
& PORT_CONNECT
) {
594 status
|= USB_PORT_STAT_CONNECTION
;
595 status
|= xhci_port_speed(temp
);
598 status
|= USB_PORT_STAT_ENABLE
;
600 status
|= USB_PORT_STAT_OVERCURRENT
;
601 if (temp
& PORT_RESET
)
602 status
|= USB_PORT_STAT_RESET
;
603 if (temp
& PORT_POWER
) {
604 if (hcd
->speed
== HCD_USB3
)
605 status
|= USB_SS_PORT_STAT_POWER
;
607 status
|= USB_PORT_STAT_POWER
;
609 /* Port Link State */
610 if (hcd
->speed
== HCD_USB3
) {
611 /* resume state is a xHCI internal state.
612 * Do not report it to usb core.
614 if ((temp
& PORT_PLS_MASK
) != XDEV_RESUME
)
615 status
|= (temp
& PORT_PLS_MASK
);
617 if (bus_state
->port_c_suspend
& (1 << wIndex
))
618 status
|= 1 << USB_PORT_FEAT_C_SUSPEND
;
619 xhci_dbg(xhci
, "Get port status returned 0x%x\n", status
);
620 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
623 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
624 link_state
= (wIndex
& 0xff00) >> 3;
625 if (wValue
== USB_PORT_FEAT_REMOTE_WAKE_MASK
)
626 wake_mask
= wIndex
& 0xff00;
627 /* The MSB of wIndex is the U1/U2 timeout */
628 timeout
= (wIndex
& 0xff00) >> 8;
630 if (!wIndex
|| wIndex
> max_ports
)
633 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
634 if (temp
== 0xffffffff) {
638 temp
= xhci_port_state_to_neutral(temp
);
639 /* FIXME: What new port features do we need to support? */
641 case USB_PORT_FEAT_SUSPEND
:
642 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
643 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
644 /* Resume the port to U0 first */
645 xhci_set_link_state(xhci
, port_array
, wIndex
,
647 spin_unlock_irqrestore(&xhci
->lock
, flags
);
649 spin_lock_irqsave(&xhci
->lock
, flags
);
651 /* In spec software should not attempt to suspend
652 * a port unless the port reports that it is in the
653 * enabled (PED = ‘1’,PLS < ‘3’) state.
655 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
656 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
657 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
658 xhci_warn(xhci
, "USB core suspending device "
659 "not in U0/U1/U2.\n");
663 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
666 xhci_warn(xhci
, "slot_id is zero\n");
669 /* unlock to execute stop endpoint commands */
670 spin_unlock_irqrestore(&xhci
->lock
, flags
);
671 xhci_stop_device(xhci
, slot_id
, 1);
672 spin_lock_irqsave(&xhci
->lock
, flags
);
674 xhci_set_link_state(xhci
, port_array
, wIndex
, XDEV_U3
);
676 spin_unlock_irqrestore(&xhci
->lock
, flags
);
677 msleep(10); /* wait device to enter */
678 spin_lock_irqsave(&xhci
->lock
, flags
);
680 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
681 bus_state
->suspended_ports
|= 1 << wIndex
;
683 case USB_PORT_FEAT_LINK_STATE
:
684 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
685 /* Software should not attempt to set
686 * port link state above '5' (Rx.Detect) and the port
689 if ((temp
& PORT_PE
) == 0 ||
690 (link_state
> USB_SS_PORT_LS_RX_DETECT
)) {
691 xhci_warn(xhci
, "Cannot set link state.\n");
695 if (link_state
== USB_SS_PORT_LS_U3
) {
696 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
699 /* unlock to execute stop endpoint
701 spin_unlock_irqrestore(&xhci
->lock
,
703 xhci_stop_device(xhci
, slot_id
, 1);
704 spin_lock_irqsave(&xhci
->lock
, flags
);
708 xhci_set_link_state(xhci
, port_array
, wIndex
,
711 spin_unlock_irqrestore(&xhci
->lock
, flags
);
712 msleep(20); /* wait device to enter */
713 spin_lock_irqsave(&xhci
->lock
, flags
);
715 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
716 if (link_state
== USB_SS_PORT_LS_U3
)
717 bus_state
->suspended_ports
|= 1 << wIndex
;
719 case USB_PORT_FEAT_POWER
:
721 * Turn on ports, even if there isn't per-port switching.
722 * HC will report connect events even before this is set.
723 * However, khubd will ignore the roothub events until
724 * the roothub is registered.
726 xhci_writel(xhci
, temp
| PORT_POWER
,
729 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
730 xhci_dbg(xhci
, "set port power, actual port %d status = 0x%x\n", wIndex
, temp
);
732 case USB_PORT_FEAT_RESET
:
733 temp
= (temp
| PORT_RESET
);
734 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
736 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
737 xhci_dbg(xhci
, "set port reset, actual port %d status = 0x%x\n", wIndex
, temp
);
739 case USB_PORT_FEAT_REMOTE_WAKE_MASK
:
740 xhci_set_remote_wake_mask(xhci
, port_array
,
742 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
743 xhci_dbg(xhci
, "set port remote wake mask, "
744 "actual port %d status = 0x%x\n",
747 case USB_PORT_FEAT_BH_PORT_RESET
:
749 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
751 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
753 case USB_PORT_FEAT_U1_TIMEOUT
:
754 if (hcd
->speed
!= HCD_USB3
)
756 temp
= xhci_readl(xhci
, port_array
[wIndex
] + 1);
757 temp
&= ~PORT_U1_TIMEOUT_MASK
;
758 temp
|= PORT_U1_TIMEOUT(timeout
);
759 xhci_writel(xhci
, temp
, port_array
[wIndex
] + 1);
761 case USB_PORT_FEAT_U2_TIMEOUT
:
762 if (hcd
->speed
!= HCD_USB3
)
764 temp
= xhci_readl(xhci
, port_array
[wIndex
] + 1);
765 temp
&= ~PORT_U2_TIMEOUT_MASK
;
766 temp
|= PORT_U2_TIMEOUT(timeout
);
767 xhci_writel(xhci
, temp
, port_array
[wIndex
] + 1);
772 /* unblock any posted writes */
773 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
775 case ClearPortFeature
:
776 if (!wIndex
|| wIndex
> max_ports
)
779 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
780 if (temp
== 0xffffffff) {
784 /* FIXME: What new port features do we need to support? */
785 temp
= xhci_port_state_to_neutral(temp
);
787 case USB_PORT_FEAT_SUSPEND
:
788 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
789 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
790 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
791 if (temp
& PORT_RESET
)
793 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
794 if ((temp
& PORT_PE
) == 0)
797 xhci_set_link_state(xhci
, port_array
, wIndex
,
799 spin_unlock_irqrestore(&xhci
->lock
, flags
);
801 spin_lock_irqsave(&xhci
->lock
, flags
);
802 xhci_set_link_state(xhci
, port_array
, wIndex
,
805 bus_state
->port_c_suspend
|= 1 << wIndex
;
807 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
810 xhci_dbg(xhci
, "slot_id is zero\n");
813 xhci_ring_device(xhci
, slot_id
);
815 case USB_PORT_FEAT_C_SUSPEND
:
816 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
817 case USB_PORT_FEAT_C_RESET
:
818 case USB_PORT_FEAT_C_BH_PORT_RESET
:
819 case USB_PORT_FEAT_C_CONNECTION
:
820 case USB_PORT_FEAT_C_OVER_CURRENT
:
821 case USB_PORT_FEAT_C_ENABLE
:
822 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
823 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
824 port_array
[wIndex
], temp
);
826 case USB_PORT_FEAT_ENABLE
:
827 xhci_disable_port(hcd
, xhci
, wIndex
,
828 port_array
[wIndex
], temp
);
836 /* "stall" on error */
839 spin_unlock_irqrestore(&xhci
->lock
, flags
);
844 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
845 * Ports are 0-indexed from the HCD point of view,
846 * and 1-indexed from the USB core pointer of view.
848 * Note that the status change bits will be cleared as soon as a port status
849 * change event is generated, so we use the saved status from that event.
851 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
857 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
859 __le32 __iomem
**port_array
;
860 struct xhci_bus_state
*bus_state
;
862 max_ports
= xhci_get_ports(hcd
, &port_array
);
863 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
865 /* Initial status is no changes */
866 retval
= (max_ports
+ 8) / 8;
867 memset(buf
, 0, retval
);
870 * Inform the usbcore about resume-in-progress by returning
871 * a non-zero value even if there are no status changes.
873 status
= bus_state
->resuming_ports
;
875 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
;
877 spin_lock_irqsave(&xhci
->lock
, flags
);
878 /* For each port, did anything change? If so, set that bit in buf. */
879 for (i
= 0; i
< max_ports
; i
++) {
880 temp
= xhci_readl(xhci
, port_array
[i
]);
881 if (temp
== 0xffffffff) {
885 if ((temp
& mask
) != 0 ||
886 (bus_state
->port_c_suspend
& 1 << i
) ||
887 (bus_state
->resume_done
[i
] && time_after_eq(
888 jiffies
, bus_state
->resume_done
[i
]))) {
889 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
893 spin_unlock_irqrestore(&xhci
->lock
, flags
);
894 return status
? retval
: 0;
899 int xhci_bus_suspend(struct usb_hcd
*hcd
)
901 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
902 int max_ports
, port_index
;
903 __le32 __iomem
**port_array
;
904 struct xhci_bus_state
*bus_state
;
907 max_ports
= xhci_get_ports(hcd
, &port_array
);
908 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
910 spin_lock_irqsave(&xhci
->lock
, flags
);
912 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
913 if (bus_state
->resuming_ports
) {
914 spin_unlock_irqrestore(&xhci
->lock
, flags
);
915 xhci_dbg(xhci
, "suspend failed because "
916 "a port is resuming\n");
921 port_index
= max_ports
;
922 bus_state
->bus_suspended
= 0;
923 while (port_index
--) {
924 /* suspend the port if the port is not suspended */
928 t1
= xhci_readl(xhci
, port_array
[port_index
]);
929 t2
= xhci_port_state_to_neutral(t1
);
931 if ((t1
& PORT_PE
) && !(t1
& PORT_PLS_MASK
)) {
932 xhci_dbg(xhci
, "port %d not suspended\n", port_index
);
933 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
936 spin_unlock_irqrestore(&xhci
->lock
, flags
);
937 xhci_stop_device(xhci
, slot_id
, 1);
938 spin_lock_irqsave(&xhci
->lock
, flags
);
940 t2
&= ~PORT_PLS_MASK
;
941 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
942 set_bit(port_index
, &bus_state
->bus_suspended
);
944 /* USB core sets remote wake mask for USB 3.0 hubs,
945 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
946 * is enabled, so also enable remote wake here.
948 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
949 if (t1
& PORT_CONNECT
) {
950 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
951 t2
&= ~PORT_WKCONN_E
;
953 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
954 t2
&= ~PORT_WKDISC_E
;
957 t2
&= ~PORT_WAKE_BITS
;
959 t1
= xhci_port_state_to_neutral(t1
);
961 xhci_writel(xhci
, t2
, port_array
[port_index
]);
963 if (hcd
->speed
!= HCD_USB3
) {
964 /* enable remote wake up for USB 2.0 */
965 __le32 __iomem
*addr
;
968 /* Add one to the port status register address to get
969 * the port power control register address.
971 addr
= port_array
[port_index
] + 1;
972 tmp
= xhci_readl(xhci
, addr
);
974 xhci_writel(xhci
, tmp
, addr
);
977 hcd
->state
= HC_STATE_SUSPENDED
;
978 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
979 spin_unlock_irqrestore(&xhci
->lock
, flags
);
983 int xhci_bus_resume(struct usb_hcd
*hcd
)
985 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
986 int max_ports
, port_index
;
987 __le32 __iomem
**port_array
;
988 struct xhci_bus_state
*bus_state
;
992 max_ports
= xhci_get_ports(hcd
, &port_array
);
993 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
995 if (time_before(jiffies
, bus_state
->next_statechange
))
998 spin_lock_irqsave(&xhci
->lock
, flags
);
999 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1000 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1004 /* delay the irqs */
1005 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1007 xhci_writel(xhci
, temp
, &xhci
->op_regs
->command
);
1009 port_index
= max_ports
;
1010 while (port_index
--) {
1011 /* Check whether need resume ports. If needed
1012 resume port and disable remote wakeup */
1016 temp
= xhci_readl(xhci
, port_array
[port_index
]);
1017 if (DEV_SUPERSPEED(temp
))
1018 temp
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1020 temp
&= ~(PORT_RWC_BITS
| PORT_WAKE_BITS
);
1021 if (test_bit(port_index
, &bus_state
->bus_suspended
) &&
1022 (temp
& PORT_PLS_MASK
)) {
1023 if (DEV_SUPERSPEED(temp
)) {
1024 xhci_set_link_state(xhci
, port_array
,
1025 port_index
, XDEV_U0
);
1027 xhci_set_link_state(xhci
, port_array
,
1028 port_index
, XDEV_RESUME
);
1030 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1032 spin_lock_irqsave(&xhci
->lock
, flags
);
1034 xhci_set_link_state(xhci
, port_array
,
1035 port_index
, XDEV_U0
);
1037 /* wait for the port to enter U0 and report port link
1040 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1042 spin_lock_irqsave(&xhci
->lock
, flags
);
1045 xhci_test_and_clear_bit(xhci
, port_array
, port_index
,
1048 slot_id
= xhci_find_slot_id_by_port(hcd
,
1049 xhci
, port_index
+ 1);
1051 xhci_ring_device(xhci
, slot_id
);
1053 xhci_writel(xhci
, temp
, port_array
[port_index
]);
1055 if (hcd
->speed
!= HCD_USB3
) {
1056 /* disable remote wake up for USB 2.0 */
1057 __le32 __iomem
*addr
;
1060 /* Add one to the port status register address to get
1061 * the port power control register address.
1063 addr
= port_array
[port_index
] + 1;
1064 tmp
= xhci_readl(xhci
, addr
);
1066 xhci_writel(xhci
, tmp
, addr
);
1070 (void) xhci_readl(xhci
, &xhci
->op_regs
->command
);
1072 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1073 /* re-enable irqs */
1074 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1076 xhci_writel(xhci
, temp
, &xhci
->op_regs
->command
);
1077 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1079 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1083 #endif /* CONFIG_PM */