2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
31 * Allocates a generic ring segment from the ring pool, sets the dma address,
32 * initializes the segment to zero, and sets the private next pointer to NULL.
35 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
37 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
,
38 unsigned int cycle_state
, gfp_t flags
)
40 struct xhci_segment
*seg
;
44 seg
= kzalloc(sizeof *seg
, flags
);
48 seg
->trbs
= dma_pool_alloc(xhci
->segment_pool
, flags
, &dma
);
54 memset(seg
->trbs
, 0, TRB_SEGMENT_SIZE
);
55 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
56 if (cycle_state
== 0) {
57 for (i
= 0; i
< TRBS_PER_SEGMENT
; i
++)
58 seg
->trbs
[i
].link
.control
|= TRB_CYCLE
;
66 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
69 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
75 static void xhci_free_segments_for_ring(struct xhci_hcd
*xhci
,
76 struct xhci_segment
*first
)
78 struct xhci_segment
*seg
;
81 while (seg
!= first
) {
82 struct xhci_segment
*next
= seg
->next
;
83 xhci_segment_free(xhci
, seg
);
86 xhci_segment_free(xhci
, first
);
90 * Make the prev segment point to the next segment.
92 * Change the last TRB in the prev segment to be a Link TRB which points to the
93 * DMA address of the next segment. The caller needs to set any Link TRB
94 * related flags, such as End TRB, Toggle Cycle, and no snoop.
96 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
97 struct xhci_segment
*next
, enum xhci_ring_type type
)
104 if (type
!= TYPE_EVENT
) {
105 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
=
106 cpu_to_le64(next
->dma
);
108 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
109 val
= le32_to_cpu(prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
);
110 val
&= ~TRB_TYPE_BITMASK
;
111 val
|= TRB_TYPE(TRB_LINK
);
112 /* Always set the chain bit with 0.95 hardware */
113 /* Set chain bit for isoc rings on AMD 0.96 host */
114 if (xhci_link_trb_quirk(xhci
) ||
115 (type
== TYPE_ISOC
&&
116 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
118 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= cpu_to_le32(val
);
123 * Link the ring to the new segments.
124 * Set Toggle Cycle for the new ring if needed.
126 static void xhci_link_rings(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
127 struct xhci_segment
*first
, struct xhci_segment
*last
,
128 unsigned int num_segs
)
130 struct xhci_segment
*next
;
132 if (!ring
|| !first
|| !last
)
135 next
= ring
->enq_seg
->next
;
136 xhci_link_segments(xhci
, ring
->enq_seg
, first
, ring
->type
);
137 xhci_link_segments(xhci
, last
, next
, ring
->type
);
138 ring
->num_segs
+= num_segs
;
139 ring
->num_trbs_free
+= (TRBS_PER_SEGMENT
- 1) * num_segs
;
141 if (ring
->type
!= TYPE_EVENT
&& ring
->enq_seg
== ring
->last_seg
) {
142 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
143 &= ~cpu_to_le32(LINK_TOGGLE
);
144 last
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
145 |= cpu_to_le32(LINK_TOGGLE
);
146 ring
->last_seg
= last
;
150 /* XXX: Do we need the hcd structure in all these functions? */
151 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
157 xhci_free_segments_for_ring(xhci
, ring
->first_seg
);
162 static void xhci_initialize_ring_info(struct xhci_ring
*ring
,
163 unsigned int cycle_state
)
165 /* The ring is empty, so the enqueue pointer == dequeue pointer */
166 ring
->enqueue
= ring
->first_seg
->trbs
;
167 ring
->enq_seg
= ring
->first_seg
;
168 ring
->dequeue
= ring
->enqueue
;
169 ring
->deq_seg
= ring
->first_seg
;
170 /* The ring is initialized to 0. The producer must write 1 to the cycle
171 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
172 * compare CCS to the cycle bit to check ownership, so CCS = 1.
174 * New rings are initialized with cycle state equal to 1; if we are
175 * handling ring expansion, set the cycle state equal to the old ring.
177 ring
->cycle_state
= cycle_state
;
178 /* Not necessary for new rings, but needed for re-initialized rings */
179 ring
->enq_updates
= 0;
180 ring
->deq_updates
= 0;
183 * Each segment has a link TRB, and leave an extra TRB for SW
186 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
189 /* Allocate segments and link them for a ring */
190 static int xhci_alloc_segments_for_ring(struct xhci_hcd
*xhci
,
191 struct xhci_segment
**first
, struct xhci_segment
**last
,
192 unsigned int num_segs
, unsigned int cycle_state
,
193 enum xhci_ring_type type
, gfp_t flags
)
195 struct xhci_segment
*prev
;
197 prev
= xhci_segment_alloc(xhci
, cycle_state
, flags
);
203 while (num_segs
> 0) {
204 struct xhci_segment
*next
;
206 next
= xhci_segment_alloc(xhci
, cycle_state
, flags
);
211 xhci_segment_free(xhci
, prev
);
216 xhci_link_segments(xhci
, prev
, next
, type
);
221 xhci_link_segments(xhci
, prev
, *first
, type
);
228 * Create a new ring with zero or more segments.
230 * Link each segment together into a ring.
231 * Set the end flag and the cycle toggle bit on the last segment.
232 * See section 4.9.1 and figures 15 and 16.
234 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
235 unsigned int num_segs
, unsigned int cycle_state
,
236 enum xhci_ring_type type
, gfp_t flags
)
238 struct xhci_ring
*ring
;
241 ring
= kzalloc(sizeof *(ring
), flags
);
245 ring
->num_segs
= num_segs
;
246 INIT_LIST_HEAD(&ring
->td_list
);
251 ret
= xhci_alloc_segments_for_ring(xhci
, &ring
->first_seg
,
252 &ring
->last_seg
, num_segs
, cycle_state
, type
, flags
);
256 /* Only event ring does not use link TRB */
257 if (type
!= TYPE_EVENT
) {
258 /* See section 4.9.2.1 and 6.4.4.1 */
259 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
|=
260 cpu_to_le32(LINK_TOGGLE
);
262 xhci_initialize_ring_info(ring
, cycle_state
);
270 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd
*xhci
,
271 struct xhci_virt_device
*virt_dev
,
272 unsigned int ep_index
)
276 rings_cached
= virt_dev
->num_rings_cached
;
277 if (rings_cached
< XHCI_MAX_RINGS_CACHED
) {
278 virt_dev
->ring_cache
[rings_cached
] =
279 virt_dev
->eps
[ep_index
].ring
;
280 virt_dev
->num_rings_cached
++;
281 xhci_dbg(xhci
, "Cached old ring, "
282 "%d ring%s cached\n",
283 virt_dev
->num_rings_cached
,
284 (virt_dev
->num_rings_cached
> 1) ? "s" : "");
286 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].ring
);
287 xhci_dbg(xhci
, "Ring cache full (%d rings), "
289 virt_dev
->num_rings_cached
);
291 virt_dev
->eps
[ep_index
].ring
= NULL
;
294 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
295 * pointers to the beginning of the ring.
297 static void xhci_reinit_cached_ring(struct xhci_hcd
*xhci
,
298 struct xhci_ring
*ring
, unsigned int cycle_state
,
299 enum xhci_ring_type type
)
301 struct xhci_segment
*seg
= ring
->first_seg
;
306 sizeof(union xhci_trb
)*TRBS_PER_SEGMENT
);
307 if (cycle_state
== 0) {
308 for (i
= 0; i
< TRBS_PER_SEGMENT
; i
++)
309 seg
->trbs
[i
].link
.control
|= TRB_CYCLE
;
311 /* All endpoint rings have link TRBs */
312 xhci_link_segments(xhci
, seg
, seg
->next
, type
);
314 } while (seg
!= ring
->first_seg
);
316 xhci_initialize_ring_info(ring
, cycle_state
);
317 /* td list should be empty since all URBs have been cancelled,
318 * but just in case...
320 INIT_LIST_HEAD(&ring
->td_list
);
324 * Expand an existing ring.
325 * Look for a cached ring or allocate a new ring which has same segment numbers
326 * and link the two rings.
328 int xhci_ring_expansion(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
329 unsigned int num_trbs
, gfp_t flags
)
331 struct xhci_segment
*first
;
332 struct xhci_segment
*last
;
333 unsigned int num_segs
;
334 unsigned int num_segs_needed
;
337 num_segs_needed
= (num_trbs
+ (TRBS_PER_SEGMENT
- 1) - 1) /
338 (TRBS_PER_SEGMENT
- 1);
340 /* Allocate number of segments we needed, or double the ring size */
341 num_segs
= ring
->num_segs
> num_segs_needed
?
342 ring
->num_segs
: num_segs_needed
;
344 ret
= xhci_alloc_segments_for_ring(xhci
, &first
, &last
,
345 num_segs
, ring
->cycle_state
, ring
->type
, flags
);
349 xhci_link_rings(xhci
, ring
, first
, last
, num_segs
);
350 xhci_dbg(xhci
, "ring expansion succeed, now has %d segments\n",
356 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
358 static struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
359 int type
, gfp_t flags
)
361 struct xhci_container_ctx
*ctx
;
363 if ((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
))
366 ctx
= kzalloc(sizeof(*ctx
), flags
);
371 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
372 if (type
== XHCI_CTX_TYPE_INPUT
)
373 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
375 ctx
->bytes
= dma_pool_alloc(xhci
->device_pool
, flags
, &ctx
->dma
);
380 memset(ctx
->bytes
, 0, ctx
->size
);
384 static void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
385 struct xhci_container_ctx
*ctx
)
389 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
393 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_hcd
*xhci
,
394 struct xhci_container_ctx
*ctx
)
396 if (ctx
->type
!= XHCI_CTX_TYPE_INPUT
)
399 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
402 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
403 struct xhci_container_ctx
*ctx
)
405 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
406 return (struct xhci_slot_ctx
*)ctx
->bytes
;
408 return (struct xhci_slot_ctx
*)
409 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
412 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
413 struct xhci_container_ctx
*ctx
,
414 unsigned int ep_index
)
416 /* increment ep index by offset of start of ep ctx array */
418 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
421 return (struct xhci_ep_ctx
*)
422 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
426 /***************** Streams structures manipulation *************************/
428 static void xhci_free_stream_ctx(struct xhci_hcd
*xhci
,
429 unsigned int num_stream_ctxs
,
430 struct xhci_stream_ctx
*stream_ctx
, dma_addr_t dma
)
432 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
434 if (num_stream_ctxs
> MEDIUM_STREAM_ARRAY_SIZE
)
435 dma_free_coherent(&pdev
->dev
,
436 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
,
438 else if (num_stream_ctxs
<= SMALL_STREAM_ARRAY_SIZE
)
439 return dma_pool_free(xhci
->small_streams_pool
,
442 return dma_pool_free(xhci
->medium_streams_pool
,
447 * The stream context array for each endpoint with bulk streams enabled can
448 * vary in size, based on:
449 * - how many streams the endpoint supports,
450 * - the maximum primary stream array size the host controller supports,
451 * - and how many streams the device driver asks for.
453 * The stream context array must be a power of 2, and can be as small as
454 * 64 bytes or as large as 1MB.
456 static struct xhci_stream_ctx
*xhci_alloc_stream_ctx(struct xhci_hcd
*xhci
,
457 unsigned int num_stream_ctxs
, dma_addr_t
*dma
,
460 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
462 if (num_stream_ctxs
> MEDIUM_STREAM_ARRAY_SIZE
)
463 return dma_alloc_coherent(&pdev
->dev
,
464 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
,
466 else if (num_stream_ctxs
<= SMALL_STREAM_ARRAY_SIZE
)
467 return dma_pool_alloc(xhci
->small_streams_pool
,
470 return dma_pool_alloc(xhci
->medium_streams_pool
,
474 struct xhci_ring
*xhci_dma_to_transfer_ring(
475 struct xhci_virt_ep
*ep
,
478 if (ep
->ep_state
& EP_HAS_STREAMS
)
479 return radix_tree_lookup(&ep
->stream_info
->trb_address_map
,
480 address
>> TRB_SEGMENT_SHIFT
);
484 struct xhci_ring
*xhci_stream_id_to_ring(
485 struct xhci_virt_device
*dev
,
486 unsigned int ep_index
,
487 unsigned int stream_id
)
489 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
493 if (!ep
->stream_info
)
496 if (stream_id
> ep
->stream_info
->num_streams
)
498 return ep
->stream_info
->stream_rings
[stream_id
];
502 * Change an endpoint's internal structure so it supports stream IDs. The
503 * number of requested streams includes stream 0, which cannot be used by device
506 * The number of stream contexts in the stream context array may be bigger than
507 * the number of streams the driver wants to use. This is because the number of
508 * stream context array entries must be a power of two.
510 * We need a radix tree for mapping physical addresses of TRBs to which stream
511 * ID they belong to. We need to do this because the host controller won't tell
512 * us which stream ring the TRB came from. We could store the stream ID in an
513 * event data TRB, but that doesn't help us for the cancellation case, since the
514 * endpoint may stop before it reaches that event data TRB.
516 * The radix tree maps the upper portion of the TRB DMA address to a ring
517 * segment that has the same upper portion of DMA addresses. For example, say I
518 * have segments of size 1KB, that are always 64-byte aligned. A segment may
519 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
520 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
521 * pass the radix tree a key to get the right stream ID:
523 * 0x10c90fff >> 10 = 0x43243
524 * 0x10c912c0 >> 10 = 0x43244
525 * 0x10c91400 >> 10 = 0x43245
527 * Obviously, only those TRBs with DMA addresses that are within the segment
528 * will make the radix tree return the stream ID for that ring.
530 * Caveats for the radix tree:
532 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
533 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
534 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
535 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
536 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
537 * extended systems (where the DMA address can be bigger than 32-bits),
538 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
540 struct xhci_stream_info
*xhci_alloc_stream_info(struct xhci_hcd
*xhci
,
541 unsigned int num_stream_ctxs
,
542 unsigned int num_streams
, gfp_t mem_flags
)
544 struct xhci_stream_info
*stream_info
;
546 struct xhci_ring
*cur_ring
;
551 xhci_dbg(xhci
, "Allocating %u streams and %u "
552 "stream context array entries.\n",
553 num_streams
, num_stream_ctxs
);
554 if (xhci
->cmd_ring_reserved_trbs
== MAX_RSVD_CMD_TRBS
) {
555 xhci_dbg(xhci
, "Command ring has no reserved TRBs available\n");
558 xhci
->cmd_ring_reserved_trbs
++;
560 stream_info
= kzalloc(sizeof(struct xhci_stream_info
), mem_flags
);
564 stream_info
->num_streams
= num_streams
;
565 stream_info
->num_stream_ctxs
= num_stream_ctxs
;
567 /* Initialize the array of virtual pointers to stream rings. */
568 stream_info
->stream_rings
= kzalloc(
569 sizeof(struct xhci_ring
*)*num_streams
,
571 if (!stream_info
->stream_rings
)
574 /* Initialize the array of DMA addresses for stream rings for the HW. */
575 stream_info
->stream_ctx_array
= xhci_alloc_stream_ctx(xhci
,
576 num_stream_ctxs
, &stream_info
->ctx_array_dma
,
578 if (!stream_info
->stream_ctx_array
)
580 memset(stream_info
->stream_ctx_array
, 0,
581 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
);
583 /* Allocate everything needed to free the stream rings later */
584 stream_info
->free_streams_command
=
585 xhci_alloc_command(xhci
, true, true, mem_flags
);
586 if (!stream_info
->free_streams_command
)
589 INIT_RADIX_TREE(&stream_info
->trb_address_map
, GFP_ATOMIC
);
591 /* Allocate rings for all the streams that the driver will use,
592 * and add their segment DMA addresses to the radix tree.
593 * Stream 0 is reserved.
595 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
596 stream_info
->stream_rings
[cur_stream
] =
597 xhci_ring_alloc(xhci
, 2, 1, TYPE_STREAM
, mem_flags
);
598 cur_ring
= stream_info
->stream_rings
[cur_stream
];
601 cur_ring
->stream_id
= cur_stream
;
602 /* Set deq ptr, cycle bit, and stream context type */
603 addr
= cur_ring
->first_seg
->dma
|
604 SCT_FOR_CTX(SCT_PRI_TR
) |
605 cur_ring
->cycle_state
;
606 stream_info
->stream_ctx_array
[cur_stream
].stream_ring
=
608 xhci_dbg(xhci
, "Setting stream %d ring ptr to 0x%08llx\n",
609 cur_stream
, (unsigned long long) addr
);
611 key
= (unsigned long)
612 (cur_ring
->first_seg
->dma
>> TRB_SEGMENT_SHIFT
);
613 ret
= radix_tree_insert(&stream_info
->trb_address_map
,
616 xhci_ring_free(xhci
, cur_ring
);
617 stream_info
->stream_rings
[cur_stream
] = NULL
;
621 /* Leave the other unused stream ring pointers in the stream context
622 * array initialized to zero. This will cause the xHC to give us an
623 * error if the device asks for a stream ID we don't have setup (if it
624 * was any other way, the host controller would assume the ring is
625 * "empty" and wait forever for data to be queued to that stream ID).
631 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
632 cur_ring
= stream_info
->stream_rings
[cur_stream
];
634 addr
= cur_ring
->first_seg
->dma
;
635 radix_tree_delete(&stream_info
->trb_address_map
,
636 addr
>> TRB_SEGMENT_SHIFT
);
637 xhci_ring_free(xhci
, cur_ring
);
638 stream_info
->stream_rings
[cur_stream
] = NULL
;
641 xhci_free_command(xhci
, stream_info
->free_streams_command
);
643 kfree(stream_info
->stream_rings
);
647 xhci
->cmd_ring_reserved_trbs
--;
651 * Sets the MaxPStreams field and the Linear Stream Array field.
652 * Sets the dequeue pointer to the stream context array.
654 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
655 struct xhci_ep_ctx
*ep_ctx
,
656 struct xhci_stream_info
*stream_info
)
658 u32 max_primary_streams
;
659 /* MaxPStreams is the number of stream context array entries, not the
660 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
661 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
663 max_primary_streams
= fls(stream_info
->num_stream_ctxs
) - 2;
664 xhci_dbg(xhci
, "Setting number of stream ctx array entries to %u\n",
665 1 << (max_primary_streams
+ 1));
666 ep_ctx
->ep_info
&= cpu_to_le32(~EP_MAXPSTREAMS_MASK
);
667 ep_ctx
->ep_info
|= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams
)
669 ep_ctx
->deq
= cpu_to_le64(stream_info
->ctx_array_dma
);
673 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
674 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
675 * not at the beginning of the ring).
677 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
678 struct xhci_ep_ctx
*ep_ctx
,
679 struct xhci_virt_ep
*ep
)
682 ep_ctx
->ep_info
&= cpu_to_le32(~(EP_MAXPSTREAMS_MASK
| EP_HAS_LSA
));
683 addr
= xhci_trb_virt_to_dma(ep
->ring
->deq_seg
, ep
->ring
->dequeue
);
684 ep_ctx
->deq
= cpu_to_le64(addr
| ep
->ring
->cycle_state
);
687 /* Frees all stream contexts associated with the endpoint,
689 * Caller should fix the endpoint context streams fields.
691 void xhci_free_stream_info(struct xhci_hcd
*xhci
,
692 struct xhci_stream_info
*stream_info
)
695 struct xhci_ring
*cur_ring
;
701 for (cur_stream
= 1; cur_stream
< stream_info
->num_streams
;
703 cur_ring
= stream_info
->stream_rings
[cur_stream
];
705 addr
= cur_ring
->first_seg
->dma
;
706 radix_tree_delete(&stream_info
->trb_address_map
,
707 addr
>> TRB_SEGMENT_SHIFT
);
708 xhci_ring_free(xhci
, cur_ring
);
709 stream_info
->stream_rings
[cur_stream
] = NULL
;
712 xhci_free_command(xhci
, stream_info
->free_streams_command
);
713 xhci
->cmd_ring_reserved_trbs
--;
714 if (stream_info
->stream_ctx_array
)
715 xhci_free_stream_ctx(xhci
,
716 stream_info
->num_stream_ctxs
,
717 stream_info
->stream_ctx_array
,
718 stream_info
->ctx_array_dma
);
721 kfree(stream_info
->stream_rings
);
726 /***************** Device context manipulation *************************/
728 static void xhci_init_endpoint_timer(struct xhci_hcd
*xhci
,
729 struct xhci_virt_ep
*ep
)
731 init_timer(&ep
->stop_cmd_timer
);
732 ep
->stop_cmd_timer
.data
= (unsigned long) ep
;
733 ep
->stop_cmd_timer
.function
= xhci_stop_endpoint_command_watchdog
;
737 static void xhci_free_tt_info(struct xhci_hcd
*xhci
,
738 struct xhci_virt_device
*virt_dev
,
741 struct list_head
*tt_list_head
;
742 struct xhci_tt_bw_info
*tt_info
, *next
;
743 bool slot_found
= false;
745 /* If the device never made it past the Set Address stage,
746 * it may not have the real_port set correctly.
748 if (virt_dev
->real_port
== 0 ||
749 virt_dev
->real_port
> HCS_MAX_PORTS(xhci
->hcs_params1
)) {
750 xhci_dbg(xhci
, "Bad real port.\n");
754 tt_list_head
= &(xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
755 list_for_each_entry_safe(tt_info
, next
, tt_list_head
, tt_list
) {
756 /* Multi-TT hubs will have more than one entry */
757 if (tt_info
->slot_id
== slot_id
) {
759 list_del(&tt_info
->tt_list
);
761 } else if (slot_found
) {
767 int xhci_alloc_tt_info(struct xhci_hcd
*xhci
,
768 struct xhci_virt_device
*virt_dev
,
769 struct usb_device
*hdev
,
770 struct usb_tt
*tt
, gfp_t mem_flags
)
772 struct xhci_tt_bw_info
*tt_info
;
773 unsigned int num_ports
;
779 num_ports
= hdev
->maxchild
;
781 for (i
= 0; i
< num_ports
; i
++, tt_info
++) {
782 struct xhci_interval_bw_table
*bw_table
;
784 tt_info
= kzalloc(sizeof(*tt_info
), mem_flags
);
787 INIT_LIST_HEAD(&tt_info
->tt_list
);
788 list_add(&tt_info
->tt_list
,
789 &xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
790 tt_info
->slot_id
= virt_dev
->udev
->slot_id
;
792 tt_info
->ttport
= i
+1;
793 bw_table
= &tt_info
->bw_table
;
794 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
795 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
800 xhci_free_tt_info(xhci
, virt_dev
, virt_dev
->udev
->slot_id
);
805 /* All the xhci_tds in the ring's TD list should be freed at this point.
806 * Should be called with xhci->lock held if there is any chance the TT lists
807 * will be manipulated by the configure endpoint, allocate device, or update
808 * hub functions while this function is removing the TT entries from the list.
810 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
812 struct xhci_virt_device
*dev
;
814 int old_active_eps
= 0;
816 /* Slot ID 0 is reserved */
817 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
820 dev
= xhci
->devs
[slot_id
];
821 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
826 old_active_eps
= dev
->tt_info
->active_eps
;
828 for (i
= 0; i
< 31; ++i
) {
829 if (dev
->eps
[i
].ring
)
830 xhci_ring_free(xhci
, dev
->eps
[i
].ring
);
831 if (dev
->eps
[i
].stream_info
)
832 xhci_free_stream_info(xhci
,
833 dev
->eps
[i
].stream_info
);
834 /* Endpoints on the TT/root port lists should have been removed
835 * when usb_disable_device() was called for the device.
836 * We can't drop them anyway, because the udev might have gone
837 * away by this point, and we can't tell what speed it was.
839 if (!list_empty(&dev
->eps
[i
].bw_endpoint_list
))
840 xhci_warn(xhci
, "Slot %u endpoint %u "
841 "not removed from BW list!\n",
844 /* If this is a hub, free the TT(s) from the TT list */
845 xhci_free_tt_info(xhci
, dev
, slot_id
);
846 /* If necessary, update the number of active TTs on this root port */
847 xhci_update_tt_active_eps(xhci
, dev
, old_active_eps
);
849 if (dev
->ring_cache
) {
850 for (i
= 0; i
< dev
->num_rings_cached
; i
++)
851 xhci_ring_free(xhci
, dev
->ring_cache
[i
]);
852 kfree(dev
->ring_cache
);
856 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
858 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
860 kfree(xhci
->devs
[slot_id
]);
861 xhci
->devs
[slot_id
] = NULL
;
864 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
865 struct usb_device
*udev
, gfp_t flags
)
867 struct xhci_virt_device
*dev
;
870 /* Slot ID 0 is reserved */
871 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
872 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
876 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
877 if (!xhci
->devs
[slot_id
])
879 dev
= xhci
->devs
[slot_id
];
881 /* Allocate the (output) device context that will be used in the HC. */
882 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
886 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
887 (unsigned long long)dev
->out_ctx
->dma
);
889 /* Allocate the (input) device context for address device command */
890 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
894 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
895 (unsigned long long)dev
->in_ctx
->dma
);
897 /* Initialize the cancellation list and watchdog timers for each ep */
898 for (i
= 0; i
< 31; i
++) {
899 xhci_init_endpoint_timer(xhci
, &dev
->eps
[i
]);
900 INIT_LIST_HEAD(&dev
->eps
[i
].cancelled_td_list
);
901 INIT_LIST_HEAD(&dev
->eps
[i
].bw_endpoint_list
);
904 /* Allocate endpoint 0 ring */
905 dev
->eps
[0].ring
= xhci_ring_alloc(xhci
, 2, 1, TYPE_CTRL
, flags
);
906 if (!dev
->eps
[0].ring
)
909 /* Allocate pointers to the ring cache */
910 dev
->ring_cache
= kzalloc(
911 sizeof(struct xhci_ring
*)*XHCI_MAX_RINGS_CACHED
,
913 if (!dev
->ring_cache
)
915 dev
->num_rings_cached
= 0;
917 init_completion(&dev
->cmd_completion
);
918 INIT_LIST_HEAD(&dev
->cmd_list
);
921 /* Point to output device context in dcbaa. */
922 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = cpu_to_le64(dev
->out_ctx
->dma
);
923 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
925 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
926 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[slot_id
]));
930 xhci_free_virt_device(xhci
, slot_id
);
934 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd
*xhci
,
935 struct usb_device
*udev
)
937 struct xhci_virt_device
*virt_dev
;
938 struct xhci_ep_ctx
*ep0_ctx
;
939 struct xhci_ring
*ep_ring
;
941 virt_dev
= xhci
->devs
[udev
->slot_id
];
942 ep0_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, 0);
943 ep_ring
= virt_dev
->eps
[0].ring
;
945 * FIXME we don't keep track of the dequeue pointer very well after a
946 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
947 * host to our enqueue pointer. This should only be called after a
948 * configured device has reset, so all control transfers should have
949 * been completed or cancelled before the reset.
951 ep0_ctx
->deq
= cpu_to_le64(xhci_trb_virt_to_dma(ep_ring
->enq_seg
,
953 | ep_ring
->cycle_state
);
957 * The xHCI roothub may have ports of differing speeds in any order in the port
958 * status registers. xhci->port_array provides an array of the port speed for
959 * each offset into the port status registers.
961 * The xHCI hardware wants to know the roothub port number that the USB device
962 * is attached to (or the roothub port its ancestor hub is attached to). All we
963 * know is the index of that port under either the USB 2.0 or the USB 3.0
964 * roothub, but that doesn't give us the real index into the HW port status
965 * registers. Call xhci_find_raw_port_number() to get real index.
967 static u32
xhci_find_real_port_number(struct xhci_hcd
*xhci
,
968 struct usb_device
*udev
)
970 struct usb_device
*top_dev
;
973 if (udev
->speed
== USB_SPEED_SUPER
)
974 hcd
= xhci
->shared_hcd
;
976 hcd
= xhci
->main_hcd
;
978 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
979 top_dev
= top_dev
->parent
)
980 /* Found device below root hub */;
982 return xhci_find_raw_port_number(hcd
, top_dev
->portnum
);
985 /* Setup an xHCI virtual device for a Set Address command */
986 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
988 struct xhci_virt_device
*dev
;
989 struct xhci_ep_ctx
*ep0_ctx
;
990 struct xhci_slot_ctx
*slot_ctx
;
993 struct usb_device
*top_dev
;
995 dev
= xhci
->devs
[udev
->slot_id
];
996 /* Slot ID 0 is reserved */
997 if (udev
->slot_id
== 0 || !dev
) {
998 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
1002 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
1003 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
1005 /* 3) Only the control endpoint is valid - one endpoint context */
1006 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1) | udev
->route
);
1007 switch (udev
->speed
) {
1008 case USB_SPEED_SUPER
:
1009 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_SS
);
1010 max_packets
= MAX_PACKET(512);
1012 case USB_SPEED_HIGH
:
1013 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_HS
);
1014 max_packets
= MAX_PACKET(64);
1016 /* USB core guesses at a 64-byte max packet first for FS devices */
1017 case USB_SPEED_FULL
:
1018 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_FS
);
1019 max_packets
= MAX_PACKET(64);
1022 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_LS
);
1023 max_packets
= MAX_PACKET(8);
1025 case USB_SPEED_WIRELESS
:
1026 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
1030 /* Speed was set earlier, this shouldn't happen. */
1033 /* Find the root hub port this device is under */
1034 port_num
= xhci_find_real_port_number(xhci
, udev
);
1037 slot_ctx
->dev_info2
|= cpu_to_le32(ROOT_HUB_PORT(port_num
));
1038 /* Set the port number in the virtual_device to the faked port number */
1039 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
1040 top_dev
= top_dev
->parent
)
1041 /* Found device below root hub */;
1042 dev
->fake_port
= top_dev
->portnum
;
1043 dev
->real_port
= port_num
;
1044 xhci_dbg(xhci
, "Set root hub portnum to %d\n", port_num
);
1045 xhci_dbg(xhci
, "Set fake root hub portnum to %d\n", dev
->fake_port
);
1047 /* Find the right bandwidth table that this device will be a part of.
1048 * If this is a full speed device attached directly to a root port (or a
1049 * decendent of one), it counts as a primary bandwidth domain, not a
1050 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1051 * will never be created for the HS root hub.
1053 if (!udev
->tt
|| !udev
->tt
->hub
->parent
) {
1054 dev
->bw_table
= &xhci
->rh_bw
[port_num
- 1].bw_table
;
1056 struct xhci_root_port_bw_info
*rh_bw
;
1057 struct xhci_tt_bw_info
*tt_bw
;
1059 rh_bw
= &xhci
->rh_bw
[port_num
- 1];
1060 /* Find the right TT. */
1061 list_for_each_entry(tt_bw
, &rh_bw
->tts
, tt_list
) {
1062 if (tt_bw
->slot_id
!= udev
->tt
->hub
->slot_id
)
1065 if (!dev
->udev
->tt
->multi
||
1067 tt_bw
->ttport
== dev
->udev
->ttport
)) {
1068 dev
->bw_table
= &tt_bw
->bw_table
;
1069 dev
->tt_info
= tt_bw
;
1074 xhci_warn(xhci
, "WARN: Didn't find a matching TT\n");
1077 /* Is this a LS/FS device under an external HS hub? */
1078 if (udev
->tt
&& udev
->tt
->hub
->parent
) {
1079 slot_ctx
->tt_info
= cpu_to_le32(udev
->tt
->hub
->slot_id
|
1080 (udev
->ttport
<< 8));
1081 if (udev
->tt
->multi
)
1082 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
1084 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
1085 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
1087 /* Step 4 - ring already allocated */
1089 ep0_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(CTRL_EP
));
1091 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1092 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1095 ep0_ctx
->deq
= cpu_to_le64(dev
->eps
[0].ring
->first_seg
->dma
|
1096 dev
->eps
[0].ring
->cycle_state
);
1098 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1104 * Convert interval expressed as 2^(bInterval - 1) == interval into
1105 * straight exponent value 2^n == interval.
1108 static unsigned int xhci_parse_exponent_interval(struct usb_device
*udev
,
1109 struct usb_host_endpoint
*ep
)
1111 unsigned int interval
;
1113 interval
= clamp_val(ep
->desc
.bInterval
, 1, 16) - 1;
1114 if (interval
!= ep
->desc
.bInterval
- 1)
1115 dev_warn(&udev
->dev
,
1116 "ep %#x - rounding interval to %d %sframes\n",
1117 ep
->desc
.bEndpointAddress
,
1119 udev
->speed
== USB_SPEED_FULL
? "" : "micro");
1121 if (udev
->speed
== USB_SPEED_FULL
) {
1123 * Full speed isoc endpoints specify interval in frames,
1124 * not microframes. We are using microframes everywhere,
1125 * so adjust accordingly.
1127 interval
+= 3; /* 1 frame = 2^3 uframes */
1134 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1135 * microframes, rounded down to nearest power of 2.
1137 static unsigned int xhci_microframes_to_exponent(struct usb_device
*udev
,
1138 struct usb_host_endpoint
*ep
, unsigned int desc_interval
,
1139 unsigned int min_exponent
, unsigned int max_exponent
)
1141 unsigned int interval
;
1143 interval
= fls(desc_interval
) - 1;
1144 interval
= clamp_val(interval
, min_exponent
, max_exponent
);
1145 if ((1 << interval
) != desc_interval
)
1146 dev_warn(&udev
->dev
,
1147 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1148 ep
->desc
.bEndpointAddress
,
1155 static unsigned int xhci_parse_microframe_interval(struct usb_device
*udev
,
1156 struct usb_host_endpoint
*ep
)
1158 if (ep
->desc
.bInterval
== 0)
1160 return xhci_microframes_to_exponent(udev
, ep
,
1161 ep
->desc
.bInterval
, 0, 15);
1165 static unsigned int xhci_parse_frame_interval(struct usb_device
*udev
,
1166 struct usb_host_endpoint
*ep
)
1168 return xhci_microframes_to_exponent(udev
, ep
,
1169 ep
->desc
.bInterval
* 8, 3, 10);
1172 /* Return the polling or NAK interval.
1174 * The polling interval is expressed in "microframes". If xHCI's Interval field
1175 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1177 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1180 static unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
1181 struct usb_host_endpoint
*ep
)
1183 unsigned int interval
= 0;
1185 switch (udev
->speed
) {
1186 case USB_SPEED_HIGH
:
1188 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1189 usb_endpoint_xfer_bulk(&ep
->desc
)) {
1190 interval
= xhci_parse_microframe_interval(udev
, ep
);
1193 /* Fall through - SS and HS isoc/int have same decoding */
1195 case USB_SPEED_SUPER
:
1196 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1197 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1198 interval
= xhci_parse_exponent_interval(udev
, ep
);
1202 case USB_SPEED_FULL
:
1203 if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1204 interval
= xhci_parse_exponent_interval(udev
, ep
);
1208 * Fall through for interrupt endpoint interval decoding
1209 * since it uses the same rules as low speed interrupt
1214 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1215 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1217 interval
= xhci_parse_frame_interval(udev
, ep
);
1224 return EP_INTERVAL(interval
);
1227 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1228 * High speed endpoint descriptors can define "the number of additional
1229 * transaction opportunities per microframe", but that goes in the Max Burst
1230 * endpoint context field.
1232 static u32
xhci_get_endpoint_mult(struct usb_device
*udev
,
1233 struct usb_host_endpoint
*ep
)
1235 if (udev
->speed
!= USB_SPEED_SUPER
||
1236 !usb_endpoint_xfer_isoc(&ep
->desc
))
1238 return ep
->ss_ep_comp
.bmAttributes
;
1241 static u32
xhci_get_endpoint_type(struct usb_device
*udev
,
1242 struct usb_host_endpoint
*ep
)
1247 in
= usb_endpoint_dir_in(&ep
->desc
);
1248 if (usb_endpoint_xfer_control(&ep
->desc
)) {
1249 type
= EP_TYPE(CTRL_EP
);
1250 } else if (usb_endpoint_xfer_bulk(&ep
->desc
)) {
1252 type
= EP_TYPE(BULK_IN_EP
);
1254 type
= EP_TYPE(BULK_OUT_EP
);
1255 } else if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1257 type
= EP_TYPE(ISOC_IN_EP
);
1259 type
= EP_TYPE(ISOC_OUT_EP
);
1260 } else if (usb_endpoint_xfer_int(&ep
->desc
)) {
1262 type
= EP_TYPE(INT_IN_EP
);
1264 type
= EP_TYPE(INT_OUT_EP
);
1271 /* Return the maximum endpoint service interval time (ESIT) payload.
1272 * Basically, this is the maxpacket size, multiplied by the burst size
1275 static u32
xhci_get_max_esit_payload(struct xhci_hcd
*xhci
,
1276 struct usb_device
*udev
,
1277 struct usb_host_endpoint
*ep
)
1282 /* Only applies for interrupt or isochronous endpoints */
1283 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1284 usb_endpoint_xfer_bulk(&ep
->desc
))
1287 if (udev
->speed
== USB_SPEED_SUPER
)
1288 return le16_to_cpu(ep
->ss_ep_comp
.wBytesPerInterval
);
1290 max_packet
= GET_MAX_PACKET(usb_endpoint_maxp(&ep
->desc
));
1291 max_burst
= (usb_endpoint_maxp(&ep
->desc
) & 0x1800) >> 11;
1292 /* A 0 in max burst means 1 transfer per ESIT */
1293 return max_packet
* (max_burst
+ 1);
1296 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1297 * Drivers will have to call usb_alloc_streams() to do that.
1299 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
1300 struct xhci_virt_device
*virt_dev
,
1301 struct usb_device
*udev
,
1302 struct usb_host_endpoint
*ep
,
1305 unsigned int ep_index
;
1306 struct xhci_ep_ctx
*ep_ctx
;
1307 struct xhci_ring
*ep_ring
;
1308 unsigned int max_packet
;
1309 unsigned int max_burst
;
1310 enum xhci_ring_type type
;
1311 u32 max_esit_payload
;
1314 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1315 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1317 endpoint_type
= xhci_get_endpoint_type(udev
, ep
);
1320 ep_ctx
->ep_info2
= cpu_to_le32(endpoint_type
);
1322 type
= usb_endpoint_type(&ep
->desc
);
1323 /* Set up the endpoint ring */
1324 virt_dev
->eps
[ep_index
].new_ring
=
1325 xhci_ring_alloc(xhci
, 2, 1, type
, mem_flags
);
1326 if (!virt_dev
->eps
[ep_index
].new_ring
) {
1327 /* Attempt to use the ring cache */
1328 if (virt_dev
->num_rings_cached
== 0)
1330 virt_dev
->eps
[ep_index
].new_ring
=
1331 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
];
1332 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
] = NULL
;
1333 virt_dev
->num_rings_cached
--;
1334 xhci_reinit_cached_ring(xhci
, virt_dev
->eps
[ep_index
].new_ring
,
1337 virt_dev
->eps
[ep_index
].skip
= false;
1338 ep_ring
= virt_dev
->eps
[ep_index
].new_ring
;
1339 ep_ctx
->deq
= cpu_to_le64(ep_ring
->first_seg
->dma
| ep_ring
->cycle_state
);
1341 ep_ctx
->ep_info
= cpu_to_le32(xhci_get_endpoint_interval(udev
, ep
)
1342 | EP_MULT(xhci_get_endpoint_mult(udev
, ep
)));
1344 /* FIXME dig Mult and streams info out of ep companion desc */
1346 /* Allow 3 retries for everything but isoc;
1347 * CErr shall be set to 0 for Isoch endpoints.
1349 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
1350 ep_ctx
->ep_info2
|= cpu_to_le32(ERROR_COUNT(3));
1352 ep_ctx
->ep_info2
|= cpu_to_le32(ERROR_COUNT(0));
1354 /* Set the max packet size and max burst */
1355 max_packet
= GET_MAX_PACKET(usb_endpoint_maxp(&ep
->desc
));
1357 switch (udev
->speed
) {
1358 case USB_SPEED_SUPER
:
1359 /* dig out max burst from ep companion desc */
1360 max_burst
= ep
->ss_ep_comp
.bMaxBurst
;
1362 case USB_SPEED_HIGH
:
1363 /* Some devices get this wrong */
1364 if (usb_endpoint_xfer_bulk(&ep
->desc
))
1366 /* bits 11:12 specify the number of additional transaction
1367 * opportunities per microframe (USB 2.0, section 9.6.6)
1369 if (usb_endpoint_xfer_isoc(&ep
->desc
) ||
1370 usb_endpoint_xfer_int(&ep
->desc
)) {
1371 max_burst
= (usb_endpoint_maxp(&ep
->desc
)
1375 case USB_SPEED_FULL
:
1381 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(max_packet
) |
1382 MAX_BURST(max_burst
));
1383 max_esit_payload
= xhci_get_max_esit_payload(xhci
, udev
, ep
);
1384 ep_ctx
->tx_info
= cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload
));
1387 * XXX no idea how to calculate the average TRB buffer length for bulk
1388 * endpoints, as the driver gives us no clue how big each scatter gather
1389 * list entry (or buffer) is going to be.
1391 * For isochronous and interrupt endpoints, we set it to the max
1392 * available, until we have new API in the USB core to allow drivers to
1393 * declare how much bandwidth they actually need.
1395 * Normally, it would be calculated by taking the total of the buffer
1396 * lengths in the TD and then dividing by the number of TRBs in a TD,
1397 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
1398 * use Event Data TRBs, and we don't chain in a link TRB on short
1399 * transfers, we're basically dividing by 1.
1401 * xHCI 1.0 specification indicates that the Average TRB Length should
1402 * be set to 8 for control endpoints.
1404 if (usb_endpoint_xfer_control(&ep
->desc
) && xhci
->hci_version
== 0x100)
1405 ep_ctx
->tx_info
|= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1408 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload
));
1410 /* FIXME Debug endpoint context */
1414 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
1415 struct xhci_virt_device
*virt_dev
,
1416 struct usb_host_endpoint
*ep
)
1418 unsigned int ep_index
;
1419 struct xhci_ep_ctx
*ep_ctx
;
1421 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1422 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1424 ep_ctx
->ep_info
= 0;
1425 ep_ctx
->ep_info2
= 0;
1427 ep_ctx
->tx_info
= 0;
1428 /* Don't free the endpoint ring until the set interface or configuration
1433 void xhci_clear_endpoint_bw_info(struct xhci_bw_info
*bw_info
)
1435 bw_info
->ep_interval
= 0;
1437 bw_info
->num_packets
= 0;
1438 bw_info
->max_packet_size
= 0;
1440 bw_info
->max_esit_payload
= 0;
1443 void xhci_update_bw_info(struct xhci_hcd
*xhci
,
1444 struct xhci_container_ctx
*in_ctx
,
1445 struct xhci_input_control_ctx
*ctrl_ctx
,
1446 struct xhci_virt_device
*virt_dev
)
1448 struct xhci_bw_info
*bw_info
;
1449 struct xhci_ep_ctx
*ep_ctx
;
1450 unsigned int ep_type
;
1453 for (i
= 1; i
< 31; ++i
) {
1454 bw_info
= &virt_dev
->eps
[i
].bw_info
;
1456 /* We can't tell what endpoint type is being dropped, but
1457 * unconditionally clearing the bandwidth info for non-periodic
1458 * endpoints should be harmless because the info will never be
1459 * set in the first place.
1461 if (!EP_IS_ADDED(ctrl_ctx
, i
) && EP_IS_DROPPED(ctrl_ctx
, i
)) {
1462 /* Dropped endpoint */
1463 xhci_clear_endpoint_bw_info(bw_info
);
1467 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
1468 ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, i
);
1469 ep_type
= CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx
->ep_info2
));
1471 /* Ignore non-periodic endpoints */
1472 if (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
1473 ep_type
!= ISOC_IN_EP
&&
1474 ep_type
!= INT_IN_EP
)
1477 /* Added or changed endpoint */
1478 bw_info
->ep_interval
= CTX_TO_EP_INTERVAL(
1479 le32_to_cpu(ep_ctx
->ep_info
));
1480 /* Number of packets and mult are zero-based in the
1481 * input context, but we want one-based for the
1484 bw_info
->mult
= CTX_TO_EP_MULT(
1485 le32_to_cpu(ep_ctx
->ep_info
)) + 1;
1486 bw_info
->num_packets
= CTX_TO_MAX_BURST(
1487 le32_to_cpu(ep_ctx
->ep_info2
)) + 1;
1488 bw_info
->max_packet_size
= MAX_PACKET_DECODED(
1489 le32_to_cpu(ep_ctx
->ep_info2
));
1490 bw_info
->type
= ep_type
;
1491 bw_info
->max_esit_payload
= CTX_TO_MAX_ESIT_PAYLOAD(
1492 le32_to_cpu(ep_ctx
->tx_info
));
1497 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1498 * Useful when you want to change one particular aspect of the endpoint and then
1499 * issue a configure endpoint command.
1501 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
1502 struct xhci_container_ctx
*in_ctx
,
1503 struct xhci_container_ctx
*out_ctx
,
1504 unsigned int ep_index
)
1506 struct xhci_ep_ctx
*out_ep_ctx
;
1507 struct xhci_ep_ctx
*in_ep_ctx
;
1509 out_ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1510 in_ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
1512 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
1513 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
1514 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
1515 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
1518 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1519 * Useful when you want to change one particular aspect of the endpoint and then
1520 * issue a configure endpoint command. Only the context entries field matters,
1521 * but we'll copy the whole thing anyway.
1523 void xhci_slot_copy(struct xhci_hcd
*xhci
,
1524 struct xhci_container_ctx
*in_ctx
,
1525 struct xhci_container_ctx
*out_ctx
)
1527 struct xhci_slot_ctx
*in_slot_ctx
;
1528 struct xhci_slot_ctx
*out_slot_ctx
;
1530 in_slot_ctx
= xhci_get_slot_ctx(xhci
, in_ctx
);
1531 out_slot_ctx
= xhci_get_slot_ctx(xhci
, out_ctx
);
1533 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
1534 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
1535 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
1536 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
1539 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1540 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
1543 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1544 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1546 xhci_dbg(xhci
, "Allocating %d scratchpad buffers\n", num_sp
);
1551 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
1552 if (!xhci
->scratchpad
)
1555 xhci
->scratchpad
->sp_array
= dma_alloc_coherent(dev
,
1556 num_sp
* sizeof(u64
),
1557 &xhci
->scratchpad
->sp_dma
, flags
);
1558 if (!xhci
->scratchpad
->sp_array
)
1561 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
1562 if (!xhci
->scratchpad
->sp_buffers
)
1565 xhci
->scratchpad
->sp_dma_buffers
=
1566 kzalloc(sizeof(dma_addr_t
) * num_sp
, flags
);
1568 if (!xhci
->scratchpad
->sp_dma_buffers
)
1571 xhci
->dcbaa
->dev_context_ptrs
[0] = cpu_to_le64(xhci
->scratchpad
->sp_dma
);
1572 for (i
= 0; i
< num_sp
; i
++) {
1574 void *buf
= dma_alloc_coherent(dev
, xhci
->page_size
, &dma
,
1579 xhci
->scratchpad
->sp_array
[i
] = dma
;
1580 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
1581 xhci
->scratchpad
->sp_dma_buffers
[i
] = dma
;
1587 for (i
= i
- 1; i
>= 0; i
--) {
1588 dma_free_coherent(dev
, xhci
->page_size
,
1589 xhci
->scratchpad
->sp_buffers
[i
],
1590 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1592 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1595 kfree(xhci
->scratchpad
->sp_buffers
);
1598 dma_free_coherent(dev
, num_sp
* sizeof(u64
),
1599 xhci
->scratchpad
->sp_array
,
1600 xhci
->scratchpad
->sp_dma
);
1603 kfree(xhci
->scratchpad
);
1604 xhci
->scratchpad
= NULL
;
1610 static void scratchpad_free(struct xhci_hcd
*xhci
)
1614 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
1616 if (!xhci
->scratchpad
)
1619 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1621 for (i
= 0; i
< num_sp
; i
++) {
1622 dma_free_coherent(&pdev
->dev
, xhci
->page_size
,
1623 xhci
->scratchpad
->sp_buffers
[i
],
1624 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1626 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1627 kfree(xhci
->scratchpad
->sp_buffers
);
1628 dma_free_coherent(&pdev
->dev
, num_sp
* sizeof(u64
),
1629 xhci
->scratchpad
->sp_array
,
1630 xhci
->scratchpad
->sp_dma
);
1631 kfree(xhci
->scratchpad
);
1632 xhci
->scratchpad
= NULL
;
1635 struct xhci_command
*xhci_alloc_command(struct xhci_hcd
*xhci
,
1636 bool allocate_in_ctx
, bool allocate_completion
,
1639 struct xhci_command
*command
;
1641 command
= kzalloc(sizeof(*command
), mem_flags
);
1645 if (allocate_in_ctx
) {
1647 xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
,
1649 if (!command
->in_ctx
) {
1655 if (allocate_completion
) {
1656 command
->completion
=
1657 kzalloc(sizeof(struct completion
), mem_flags
);
1658 if (!command
->completion
) {
1659 xhci_free_container_ctx(xhci
, command
->in_ctx
);
1663 init_completion(command
->completion
);
1666 command
->status
= 0;
1667 INIT_LIST_HEAD(&command
->cmd_list
);
1671 void xhci_urb_free_priv(struct xhci_hcd
*xhci
, struct urb_priv
*urb_priv
)
1674 kfree(urb_priv
->td
[0]);
1679 void xhci_free_command(struct xhci_hcd
*xhci
,
1680 struct xhci_command
*command
)
1682 xhci_free_container_ctx(xhci
,
1684 kfree(command
->completion
);
1688 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
1690 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
1691 struct dev_info
*dev_info
, *next
;
1692 struct xhci_cd
*cur_cd
, *next_cd
;
1693 unsigned long flags
;
1695 int i
, j
, num_ports
;
1697 /* Free the Event Ring Segment Table and the actual Event Ring */
1698 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
1699 if (xhci
->erst
.entries
)
1700 dma_free_coherent(&pdev
->dev
, size
,
1701 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
1702 xhci
->erst
.entries
= NULL
;
1703 xhci_dbg(xhci
, "Freed ERST\n");
1704 if (xhci
->event_ring
)
1705 xhci_ring_free(xhci
, xhci
->event_ring
);
1706 xhci
->event_ring
= NULL
;
1707 xhci_dbg(xhci
, "Freed event ring\n");
1709 if (xhci
->lpm_command
)
1710 xhci_free_command(xhci
, xhci
->lpm_command
);
1711 xhci
->cmd_ring_reserved_trbs
= 0;
1713 xhci_ring_free(xhci
, xhci
->cmd_ring
);
1714 xhci
->cmd_ring
= NULL
;
1715 xhci_dbg(xhci
, "Freed command ring\n");
1716 list_for_each_entry_safe(cur_cd
, next_cd
,
1717 &xhci
->cancel_cmd_list
, cancel_cmd_list
) {
1718 list_del(&cur_cd
->cancel_cmd_list
);
1722 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
1723 xhci_free_virt_device(xhci
, i
);
1725 if (xhci
->segment_pool
)
1726 dma_pool_destroy(xhci
->segment_pool
);
1727 xhci
->segment_pool
= NULL
;
1728 xhci_dbg(xhci
, "Freed segment pool\n");
1730 if (xhci
->device_pool
)
1731 dma_pool_destroy(xhci
->device_pool
);
1732 xhci
->device_pool
= NULL
;
1733 xhci_dbg(xhci
, "Freed device context pool\n");
1735 if (xhci
->small_streams_pool
)
1736 dma_pool_destroy(xhci
->small_streams_pool
);
1737 xhci
->small_streams_pool
= NULL
;
1738 xhci_dbg(xhci
, "Freed small stream array pool\n");
1740 if (xhci
->medium_streams_pool
)
1741 dma_pool_destroy(xhci
->medium_streams_pool
);
1742 xhci
->medium_streams_pool
= NULL
;
1743 xhci_dbg(xhci
, "Freed medium stream array pool\n");
1746 dma_free_coherent(&pdev
->dev
, sizeof(*xhci
->dcbaa
),
1747 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
1750 scratchpad_free(xhci
);
1752 spin_lock_irqsave(&xhci
->lock
, flags
);
1753 list_for_each_entry_safe(dev_info
, next
, &xhci
->lpm_failed_devs
, list
) {
1754 list_del(&dev_info
->list
);
1757 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1762 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1763 for (i
= 0; i
< num_ports
; i
++) {
1764 struct xhci_interval_bw_table
*bwt
= &xhci
->rh_bw
[i
].bw_table
;
1765 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++) {
1766 struct list_head
*ep
= &bwt
->interval_bw
[j
].endpoints
;
1767 while (!list_empty(ep
))
1768 list_del_init(ep
->next
);
1772 for (i
= 0; i
< num_ports
; i
++) {
1773 struct xhci_tt_bw_info
*tt
, *n
;
1774 list_for_each_entry_safe(tt
, n
, &xhci
->rh_bw
[i
].tts
, tt_list
) {
1775 list_del(&tt
->tt_list
);
1781 xhci
->num_usb2_ports
= 0;
1782 xhci
->num_usb3_ports
= 0;
1783 xhci
->num_active_eps
= 0;
1784 kfree(xhci
->usb2_ports
);
1785 kfree(xhci
->usb3_ports
);
1786 kfree(xhci
->port_array
);
1788 kfree(xhci
->ext_caps
);
1790 xhci
->page_size
= 0;
1791 xhci
->page_shift
= 0;
1792 xhci
->bus_state
[0].bus_suspended
= 0;
1793 xhci
->bus_state
[1].bus_suspended
= 0;
1796 static int xhci_test_trb_in_td(struct xhci_hcd
*xhci
,
1797 struct xhci_segment
*input_seg
,
1798 union xhci_trb
*start_trb
,
1799 union xhci_trb
*end_trb
,
1800 dma_addr_t input_dma
,
1801 struct xhci_segment
*result_seg
,
1802 char *test_name
, int test_number
)
1804 unsigned long long start_dma
;
1805 unsigned long long end_dma
;
1806 struct xhci_segment
*seg
;
1808 start_dma
= xhci_trb_virt_to_dma(input_seg
, start_trb
);
1809 end_dma
= xhci_trb_virt_to_dma(input_seg
, end_trb
);
1811 seg
= trb_in_td(input_seg
, start_trb
, end_trb
, input_dma
);
1812 if (seg
!= result_seg
) {
1813 xhci_warn(xhci
, "WARN: %s TRB math test %d failed!\n",
1814 test_name
, test_number
);
1815 xhci_warn(xhci
, "Tested TRB math w/ seg %p and "
1816 "input DMA 0x%llx\n",
1818 (unsigned long long) input_dma
);
1819 xhci_warn(xhci
, "starting TRB %p (0x%llx DMA), "
1820 "ending TRB %p (0x%llx DMA)\n",
1821 start_trb
, start_dma
,
1823 xhci_warn(xhci
, "Expected seg %p, got seg %p\n",
1830 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1831 static int xhci_check_trb_in_td_math(struct xhci_hcd
*xhci
, gfp_t mem_flags
)
1834 dma_addr_t input_dma
;
1835 struct xhci_segment
*result_seg
;
1836 } simple_test_vector
[] = {
1837 /* A zeroed DMA field should fail */
1839 /* One TRB before the ring start should fail */
1840 { xhci
->event_ring
->first_seg
->dma
- 16, NULL
},
1841 /* One byte before the ring start should fail */
1842 { xhci
->event_ring
->first_seg
->dma
- 1, NULL
},
1843 /* Starting TRB should succeed */
1844 { xhci
->event_ring
->first_seg
->dma
, xhci
->event_ring
->first_seg
},
1845 /* Ending TRB should succeed */
1846 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16,
1847 xhci
->event_ring
->first_seg
},
1848 /* One byte after the ring end should fail */
1849 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16 + 1, NULL
},
1850 /* One TRB after the ring end should fail */
1851 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
)*16, NULL
},
1852 /* An address of all ones should fail */
1853 { (dma_addr_t
) (~0), NULL
},
1856 struct xhci_segment
*input_seg
;
1857 union xhci_trb
*start_trb
;
1858 union xhci_trb
*end_trb
;
1859 dma_addr_t input_dma
;
1860 struct xhci_segment
*result_seg
;
1861 } complex_test_vector
[] = {
1862 /* Test feeding a valid DMA address from a different ring */
1863 { .input_seg
= xhci
->event_ring
->first_seg
,
1864 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1865 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1866 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1869 /* Test feeding a valid end TRB from a different ring */
1870 { .input_seg
= xhci
->event_ring
->first_seg
,
1871 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1872 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1873 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1876 /* Test feeding a valid start and end TRB from a different ring */
1877 { .input_seg
= xhci
->event_ring
->first_seg
,
1878 .start_trb
= xhci
->cmd_ring
->first_seg
->trbs
,
1879 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1880 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1883 /* TRB in this ring, but after this TD */
1884 { .input_seg
= xhci
->event_ring
->first_seg
,
1885 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[0],
1886 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1887 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 4*16,
1890 /* TRB in this ring, but before this TD */
1891 { .input_seg
= xhci
->event_ring
->first_seg
,
1892 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1893 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[6],
1894 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1897 /* TRB in this ring, but after this wrapped TD */
1898 { .input_seg
= xhci
->event_ring
->first_seg
,
1899 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1900 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1901 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1904 /* TRB in this ring, but before this wrapped TD */
1905 { .input_seg
= xhci
->event_ring
->first_seg
,
1906 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1907 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1908 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 4)*16,
1911 /* TRB not in this ring, and we have a wrapped TD */
1912 { .input_seg
= xhci
->event_ring
->first_seg
,
1913 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1914 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1915 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
+ 2*16,
1920 unsigned int num_tests
;
1923 num_tests
= ARRAY_SIZE(simple_test_vector
);
1924 for (i
= 0; i
< num_tests
; i
++) {
1925 ret
= xhci_test_trb_in_td(xhci
,
1926 xhci
->event_ring
->first_seg
,
1927 xhci
->event_ring
->first_seg
->trbs
,
1928 &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1929 simple_test_vector
[i
].input_dma
,
1930 simple_test_vector
[i
].result_seg
,
1936 num_tests
= ARRAY_SIZE(complex_test_vector
);
1937 for (i
= 0; i
< num_tests
; i
++) {
1938 ret
= xhci_test_trb_in_td(xhci
,
1939 complex_test_vector
[i
].input_seg
,
1940 complex_test_vector
[i
].start_trb
,
1941 complex_test_vector
[i
].end_trb
,
1942 complex_test_vector
[i
].input_dma
,
1943 complex_test_vector
[i
].result_seg
,
1948 xhci_dbg(xhci
, "TRB math tests passed.\n");
1952 static void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
1957 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
1958 xhci
->event_ring
->dequeue
);
1959 if (deq
== 0 && !in_interrupt())
1960 xhci_warn(xhci
, "WARN something wrong with SW event ring "
1962 /* Update HC event ring dequeue pointer */
1963 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
1964 temp
&= ERST_PTR_MASK
;
1965 /* Don't clear the EHB bit (which is RW1C) because
1966 * there might be more events to service.
1969 xhci_dbg(xhci
, "// Write event ring dequeue pointer, "
1970 "preserving EHB bit\n");
1971 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
1972 &xhci
->ir_set
->erst_dequeue
);
1975 static void xhci_add_in_port(struct xhci_hcd
*xhci
, unsigned int num_ports
,
1976 __le32 __iomem
*addr
, u8 major_revision
, int max_caps
)
1978 u32 temp
, port_offset
, port_count
;
1981 if (major_revision
> 0x03) {
1982 xhci_warn(xhci
, "Ignoring unknown port speed, "
1983 "Ext Cap %p, revision = 0x%x\n",
1984 addr
, major_revision
);
1985 /* Ignoring port protocol we can't understand. FIXME */
1989 /* Port offset and count in the third dword, see section 7.2 */
1990 temp
= xhci_readl(xhci
, addr
+ 2);
1991 port_offset
= XHCI_EXT_PORT_OFF(temp
);
1992 port_count
= XHCI_EXT_PORT_COUNT(temp
);
1993 xhci_dbg(xhci
, "Ext Cap %p, port offset = %u, "
1994 "count = %u, revision = 0x%x\n",
1995 addr
, port_offset
, port_count
, major_revision
);
1996 /* Port count includes the current port offset */
1997 if (port_offset
== 0 || (port_offset
+ port_count
- 1) > num_ports
)
1998 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2001 /* cache usb2 port capabilities */
2002 if (major_revision
< 0x03 && xhci
->num_ext_caps
< max_caps
)
2003 xhci
->ext_caps
[xhci
->num_ext_caps
++] = temp
;
2005 /* Check the host's USB2 LPM capability */
2006 if ((xhci
->hci_version
== 0x96) && (major_revision
!= 0x03) &&
2007 (temp
& XHCI_L1C
)) {
2008 xhci_dbg(xhci
, "xHCI 0.96: support USB2 software lpm\n");
2009 xhci
->sw_lpm_support
= 1;
2012 if ((xhci
->hci_version
>= 0x100) && (major_revision
!= 0x03)) {
2013 xhci_dbg(xhci
, "xHCI 1.0: support USB2 software lpm\n");
2014 xhci
->sw_lpm_support
= 1;
2015 if (temp
& XHCI_HLC
) {
2016 xhci_dbg(xhci
, "xHCI 1.0: support USB2 hardware lpm\n");
2017 xhci
->hw_lpm_support
= 1;
2022 for (i
= port_offset
; i
< (port_offset
+ port_count
); i
++) {
2023 /* Duplicate entry. Ignore the port if the revisions differ. */
2024 if (xhci
->port_array
[i
] != 0) {
2025 xhci_warn(xhci
, "Duplicate port entry, Ext Cap %p,"
2026 " port %u\n", addr
, i
);
2027 xhci_warn(xhci
, "Port was marked as USB %u, "
2028 "duplicated as USB %u\n",
2029 xhci
->port_array
[i
], major_revision
);
2030 /* Only adjust the roothub port counts if we haven't
2031 * found a similar duplicate.
2033 if (xhci
->port_array
[i
] != major_revision
&&
2034 xhci
->port_array
[i
] != DUPLICATE_ENTRY
) {
2035 if (xhci
->port_array
[i
] == 0x03)
2036 xhci
->num_usb3_ports
--;
2038 xhci
->num_usb2_ports
--;
2039 xhci
->port_array
[i
] = DUPLICATE_ENTRY
;
2041 /* FIXME: Should we disable the port? */
2044 xhci
->port_array
[i
] = major_revision
;
2045 if (major_revision
== 0x03)
2046 xhci
->num_usb3_ports
++;
2048 xhci
->num_usb2_ports
++;
2050 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2054 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2055 * specify what speeds each port is supposed to be. We can't count on the port
2056 * speed bits in the PORTSC register being correct until a device is connected,
2057 * but we need to set up the two fake roothubs with the correct number of USB
2058 * 3.0 and USB 2.0 ports at host controller initialization time.
2060 static int xhci_setup_port_arrays(struct xhci_hcd
*xhci
, gfp_t flags
)
2062 __le32 __iomem
*addr
, *tmp_addr
;
2063 u32 offset
, tmp_offset
;
2064 unsigned int num_ports
;
2065 int i
, j
, port_index
;
2068 addr
= &xhci
->cap_regs
->hcc_params
;
2069 offset
= XHCI_HCC_EXT_CAPS(xhci_readl(xhci
, addr
));
2071 xhci_err(xhci
, "No Extended Capability registers, "
2072 "unable to set up roothub.\n");
2076 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
2077 xhci
->port_array
= kzalloc(sizeof(*xhci
->port_array
)*num_ports
, flags
);
2078 if (!xhci
->port_array
)
2081 xhci
->rh_bw
= kzalloc(sizeof(*xhci
->rh_bw
)*num_ports
, flags
);
2084 for (i
= 0; i
< num_ports
; i
++) {
2085 struct xhci_interval_bw_table
*bw_table
;
2087 INIT_LIST_HEAD(&xhci
->rh_bw
[i
].tts
);
2088 bw_table
= &xhci
->rh_bw
[i
].bw_table
;
2089 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
2090 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
2094 * For whatever reason, the first capability offset is from the
2095 * capability register base, not from the HCCPARAMS register.
2096 * See section 5.3.6 for offset calculation.
2098 addr
= &xhci
->cap_regs
->hc_capbase
+ offset
;
2101 tmp_offset
= offset
;
2103 /* count extended protocol capability entries for later caching */
2106 cap_id
= xhci_readl(xhci
, tmp_addr
);
2107 if (XHCI_EXT_CAPS_ID(cap_id
) == XHCI_EXT_CAPS_PROTOCOL
)
2109 tmp_offset
= XHCI_EXT_CAPS_NEXT(cap_id
);
2110 tmp_addr
+= tmp_offset
;
2111 } while (tmp_offset
);
2113 xhci
->ext_caps
= kzalloc(sizeof(*xhci
->ext_caps
) * cap_count
, flags
);
2114 if (!xhci
->ext_caps
)
2120 cap_id
= xhci_readl(xhci
, addr
);
2121 if (XHCI_EXT_CAPS_ID(cap_id
) == XHCI_EXT_CAPS_PROTOCOL
)
2122 xhci_add_in_port(xhci
, num_ports
, addr
,
2123 (u8
) XHCI_EXT_PORT_MAJOR(cap_id
),
2125 offset
= XHCI_EXT_CAPS_NEXT(cap_id
);
2126 if (!offset
|| (xhci
->num_usb2_ports
+ xhci
->num_usb3_ports
)
2130 * Once you're into the Extended Capabilities, the offset is
2131 * always relative to the register holding the offset.
2136 if (xhci
->num_usb2_ports
== 0 && xhci
->num_usb3_ports
== 0) {
2137 xhci_warn(xhci
, "No ports on the roothubs?\n");
2140 xhci_dbg(xhci
, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2141 xhci
->num_usb2_ports
, xhci
->num_usb3_ports
);
2143 /* Place limits on the number of roothub ports so that the hub
2144 * descriptors aren't longer than the USB core will allocate.
2146 if (xhci
->num_usb3_ports
> 15) {
2147 xhci_dbg(xhci
, "Limiting USB 3.0 roothub ports to 15.\n");
2148 xhci
->num_usb3_ports
= 15;
2150 if (xhci
->num_usb2_ports
> USB_MAXCHILDREN
) {
2151 xhci_dbg(xhci
, "Limiting USB 2.0 roothub ports to %u.\n",
2153 xhci
->num_usb2_ports
= USB_MAXCHILDREN
;
2157 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2158 * Not sure how the USB core will handle a hub with no ports...
2160 if (xhci
->num_usb2_ports
) {
2161 xhci
->usb2_ports
= kmalloc(sizeof(*xhci
->usb2_ports
)*
2162 xhci
->num_usb2_ports
, flags
);
2163 if (!xhci
->usb2_ports
)
2167 for (i
= 0; i
< num_ports
; i
++) {
2168 if (xhci
->port_array
[i
] == 0x03 ||
2169 xhci
->port_array
[i
] == 0 ||
2170 xhci
->port_array
[i
] == DUPLICATE_ENTRY
)
2173 xhci
->usb2_ports
[port_index
] =
2174 &xhci
->op_regs
->port_status_base
+
2176 xhci_dbg(xhci
, "USB 2.0 port at index %u, "
2178 xhci
->usb2_ports
[port_index
]);
2180 if (port_index
== xhci
->num_usb2_ports
)
2184 if (xhci
->num_usb3_ports
) {
2185 xhci
->usb3_ports
= kmalloc(sizeof(*xhci
->usb3_ports
)*
2186 xhci
->num_usb3_ports
, flags
);
2187 if (!xhci
->usb3_ports
)
2191 for (i
= 0; i
< num_ports
; i
++)
2192 if (xhci
->port_array
[i
] == 0x03) {
2193 xhci
->usb3_ports
[port_index
] =
2194 &xhci
->op_regs
->port_status_base
+
2196 xhci_dbg(xhci
, "USB 3.0 port at index %u, "
2198 xhci
->usb3_ports
[port_index
]);
2200 if (port_index
== xhci
->num_usb3_ports
)
2207 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
2210 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
2211 unsigned int val
, val2
;
2213 struct xhci_segment
*seg
;
2214 u32 page_size
, temp
;
2217 INIT_LIST_HEAD(&xhci
->lpm_failed_devs
);
2218 INIT_LIST_HEAD(&xhci
->cancel_cmd_list
);
2220 page_size
= xhci_readl(xhci
, &xhci
->op_regs
->page_size
);
2221 xhci_dbg(xhci
, "Supported page size register = 0x%x\n", page_size
);
2222 for (i
= 0; i
< 16; i
++) {
2223 if ((0x1 & page_size
) != 0)
2225 page_size
= page_size
>> 1;
2228 xhci_dbg(xhci
, "Supported page size of %iK\n", (1 << (i
+12)) / 1024);
2230 xhci_warn(xhci
, "WARN: no supported page size\n");
2231 /* Use 4K pages, since that's common and the minimum the HC supports */
2232 xhci
->page_shift
= 12;
2233 xhci
->page_size
= 1 << xhci
->page_shift
;
2234 xhci_dbg(xhci
, "HCD page size set to %iK\n", xhci
->page_size
/ 1024);
2237 * Program the Number of Device Slots Enabled field in the CONFIG
2238 * register with the max value of slots the HC can handle.
2240 val
= HCS_MAX_SLOTS(xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params1
));
2241 xhci_dbg(xhci
, "// xHC can handle at most %d device slots.\n",
2242 (unsigned int) val
);
2243 val2
= xhci_readl(xhci
, &xhci
->op_regs
->config_reg
);
2244 val
|= (val2
& ~HCS_SLOTS_MASK
);
2245 xhci_dbg(xhci
, "// Setting Max device slots reg = 0x%x.\n",
2246 (unsigned int) val
);
2247 xhci_writel(xhci
, val
, &xhci
->op_regs
->config_reg
);
2250 * Section 5.4.8 - doorbell array must be
2251 * "physically contiguous and 64-byte (cache line) aligned".
2253 xhci
->dcbaa
= dma_alloc_coherent(dev
, sizeof(*xhci
->dcbaa
), &dma
,
2257 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
2258 xhci
->dcbaa
->dma
= dma
;
2259 xhci_dbg(xhci
, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2260 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
2261 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
2264 * Initialize the ring segment pool. The ring must be a contiguous
2265 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2266 * however, the command ring segment needs 64-byte aligned segments,
2267 * so we pick the greater alignment need.
2269 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
2270 TRB_SEGMENT_SIZE
, 64, xhci
->page_size
);
2272 /* See Table 46 and Note on Figure 55 */
2273 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
2274 2112, 64, xhci
->page_size
);
2275 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
2278 /* Linear stream context arrays don't have any boundary restrictions,
2279 * and only need to be 16-byte aligned.
2281 xhci
->small_streams_pool
=
2282 dma_pool_create("xHCI 256 byte stream ctx arrays",
2283 dev
, SMALL_STREAM_ARRAY_SIZE
, 16, 0);
2284 xhci
->medium_streams_pool
=
2285 dma_pool_create("xHCI 1KB stream ctx arrays",
2286 dev
, MEDIUM_STREAM_ARRAY_SIZE
, 16, 0);
2287 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2288 * will be allocated with dma_alloc_coherent()
2291 if (!xhci
->small_streams_pool
|| !xhci
->medium_streams_pool
)
2294 /* Set up the command ring to have one segments for now. */
2295 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, 1, TYPE_COMMAND
, flags
);
2296 if (!xhci
->cmd_ring
)
2298 xhci_dbg(xhci
, "Allocated command ring at %p\n", xhci
->cmd_ring
);
2299 xhci_dbg(xhci
, "First segment DMA is 0x%llx\n",
2300 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
2302 /* Set the address in the Command Ring Control register */
2303 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
2304 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
2305 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
2306 xhci
->cmd_ring
->cycle_state
;
2307 xhci_dbg(xhci
, "// Setting command ring address to 0x%x\n", val
);
2308 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
2309 xhci_dbg_cmd_ptrs(xhci
);
2311 xhci
->lpm_command
= xhci_alloc_command(xhci
, true, true, flags
);
2312 if (!xhci
->lpm_command
)
2315 /* Reserve one command ring TRB for disabling LPM.
2316 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2317 * disabling LPM, we only need to reserve one TRB for all devices.
2319 xhci
->cmd_ring_reserved_trbs
++;
2321 val
= xhci_readl(xhci
, &xhci
->cap_regs
->db_off
);
2323 xhci_dbg(xhci
, "// Doorbell array is located at offset 0x%x"
2324 " from cap regs base addr\n", val
);
2325 xhci
->dba
= (void __iomem
*) xhci
->cap_regs
+ val
;
2326 xhci_dbg_regs(xhci
);
2327 xhci_print_run_regs(xhci
);
2328 /* Set ir_set to interrupt register set 0 */
2329 xhci
->ir_set
= &xhci
->run_regs
->ir_set
[0];
2332 * Event ring setup: Allocate a normal ring, but also setup
2333 * the event ring segment table (ERST). Section 4.9.3.
2335 xhci_dbg(xhci
, "// Allocating event ring\n");
2336 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, 1, TYPE_EVENT
,
2338 if (!xhci
->event_ring
)
2340 if (xhci_check_trb_in_td_math(xhci
, flags
) < 0)
2343 xhci
->erst
.entries
= dma_alloc_coherent(dev
,
2344 sizeof(struct xhci_erst_entry
) * ERST_NUM_SEGS
, &dma
,
2346 if (!xhci
->erst
.entries
)
2348 xhci_dbg(xhci
, "// Allocated event ring segment table at 0x%llx\n",
2349 (unsigned long long)dma
);
2351 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
2352 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
2353 xhci
->erst
.erst_dma_addr
= dma
;
2354 xhci_dbg(xhci
, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2355 xhci
->erst
.num_entries
,
2357 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2359 /* set ring base address and size for each segment table entry */
2360 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
2361 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
2362 entry
->seg_addr
= cpu_to_le64(seg
->dma
);
2363 entry
->seg_size
= cpu_to_le32(TRBS_PER_SEGMENT
);
2368 /* set ERST count with the number of entries in the segment table */
2369 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_size
);
2370 val
&= ERST_SIZE_MASK
;
2371 val
|= ERST_NUM_SEGS
;
2372 xhci_dbg(xhci
, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2374 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_size
);
2376 xhci_dbg(xhci
, "// Set ERST entries to point to event ring.\n");
2377 /* set the segment table base address */
2378 xhci_dbg(xhci
, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2379 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2380 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
2381 val_64
&= ERST_PTR_MASK
;
2382 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
2383 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
2385 /* Set the event ring dequeue address */
2386 xhci_set_hc_event_deq(xhci
);
2387 xhci_dbg(xhci
, "Wrote ERST address to ir_set 0.\n");
2388 xhci_print_ir_set(xhci
, 0);
2391 * XXX: Might need to set the Interrupter Moderation Register to
2392 * something other than the default (~1ms minimum between interrupts).
2393 * See section 5.5.1.2.
2395 init_completion(&xhci
->addr_dev
);
2396 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
2397 xhci
->devs
[i
] = NULL
;
2398 for (i
= 0; i
< USB_MAXCHILDREN
; ++i
) {
2399 xhci
->bus_state
[0].resume_done
[i
] = 0;
2400 xhci
->bus_state
[1].resume_done
[i
] = 0;
2403 if (scratchpad_alloc(xhci
, flags
))
2405 if (xhci_setup_port_arrays(xhci
, flags
))
2408 /* Enable USB 3.0 device notifications for function remote wake, which
2409 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2410 * U3 (device suspend).
2412 temp
= xhci_readl(xhci
, &xhci
->op_regs
->dev_notification
);
2413 temp
&= ~DEV_NOTE_MASK
;
2414 temp
|= DEV_NOTE_FWAKE
;
2415 xhci_writel(xhci
, temp
, &xhci
->op_regs
->dev_notification
);
2420 xhci_warn(xhci
, "Couldn't initialize memory\n");
2423 xhci_mem_cleanup(xhci
);