drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25
  26 #include "xhci.h"
  27
  28 /*
  29  * Allocates a generic ring segment from the ring pool, sets the dma address,
  30  * initializes the segment to zero, and sets the private next pointer to NULL.
  31  *
  32  * Section 4.11.1.1:
  33  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  34  */
  35 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  36 {
  37         struct xhci_segment *seg;
  38         dma_addr_t      dma;
  39
  40         seg = kzalloc(sizeof *seg, flags);
  41         if (!seg)
  42                 return 0;
  43         xhci_dbg(xhci, "Allocating priv segment structure at 0x%x\n",
  44                         (unsigned int) seg);
  45
  46         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  47         if (!seg->trbs) {
  48                 kfree(seg);
  49                 return 0;
  50         }
  51         xhci_dbg(xhci, "// Allocating segment at 0x%x (virtual) 0x%x (DMA)\n",
  52                         (unsigned int) seg->trbs, (u32) dma);
  53
  54         memset(seg->trbs, 0, SEGMENT_SIZE);
  55         seg->dma = dma;
  56         seg->next = NULL;
  57
  58         return seg;
  59 }
  60
  61 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  62 {
  63         if (!seg)
  64                 return;
  65         if (seg->trbs) {
  66                 xhci_dbg(xhci, "Freeing DMA segment at 0x%x"
  67                                 " (virtual) 0x%x (DMA)\n",
  68                                 (unsigned int) seg->trbs, (u32) seg->dma);
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         xhci_dbg(xhci, "Freeing priv segment structure at 0x%x\n",
  73                         (unsigned int) seg);
  74         kfree(seg);
  75 }
  76
  77 /*
  78  * Make the prev segment point to the next segment.
  79  *
  80  * Change the last TRB in the prev segment to be a Link TRB which points to the
  81  * DMA address of the next segment.  The caller needs to set any Link TRB
  82  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  83  */
  84 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  85                 struct xhci_segment *next, bool link_trbs)
  86 {
  87         u32 val;
  88
  89         if (!prev || !next)
  90                 return;
  91         prev->next = next;
  92         if (link_trbs) {
  93                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr[0] = next->dma;
  94
  95                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  96                 val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
  97                 val &= ~TRB_TYPE_BITMASK;
  98                 val |= TRB_TYPE(TRB_LINK);
  99                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
 100         }
 101         xhci_dbg(xhci, "Linking segment 0x%x to segment 0x%x (DMA)\n",
 102                         prev->dma, next->dma);
 103 }
 104
 105 /* XXX: Do we need the hcd structure in all these functions? */
 106 static void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 107 {
 108         struct xhci_segment *seg;
 109         struct xhci_segment *first_seg;
 110
 111         if (!ring || !ring->first_seg)
 112                 return;
 113         first_seg = ring->first_seg;
 114         seg = first_seg->next;
 115         xhci_dbg(xhci, "Freeing ring at 0x%x\n", (unsigned int) ring);
 116         while (seg != first_seg) {
 117                 struct xhci_segment *next = seg->next;
 118                 xhci_segment_free(xhci, seg);
 119                 seg = next;
 120         }
 121         xhci_segment_free(xhci, first_seg);
 122         ring->first_seg = NULL;
 123         kfree(ring);
 124 }
 125
 126 /**
 127  * Create a new ring with zero or more segments.
 128  *
 129  * Link each segment together into a ring.
 130  * Set the end flag and the cycle toggle bit on the last segment.
 131  * See section 4.9.1 and figures 15 and 16.
 132  */
 133 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 134                 unsigned int num_segs, bool link_trbs, gfp_t flags)
 135 {
 136         struct xhci_ring        *ring;
 137         struct xhci_segment     *prev;
 138
 139         ring = kzalloc(sizeof *(ring), flags);
 140         xhci_dbg(xhci, "Allocating ring at 0x%x\n", (unsigned int) ring);
 141         if (!ring)
 142                 return 0;
 143
 144         if (num_segs == 0)
 145                 return ring;
 146
 147         ring->first_seg = xhci_segment_alloc(xhci, flags);
 148         if (!ring->first_seg)
 149                 goto fail;
 150         num_segs--;
 151
 152         prev = ring->first_seg;
 153         while (num_segs > 0) {
 154                 struct xhci_segment     *next;
 155
 156                 next = xhci_segment_alloc(xhci, flags);
 157                 if (!next)
 158                         goto fail;
 159                 xhci_link_segments(xhci, prev, next, link_trbs);
 160
 161                 prev = next;
 162                 num_segs--;
 163         }
 164         xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
 165
 166         if (link_trbs) {
 167                 /* See section 4.9.2.1 and 6.4.4.1 */
 168                 prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
 169                 xhci_dbg(xhci, "Wrote link toggle flag to"
 170                                 " segment 0x%x (virtual), 0x%x (DMA)\n",
 171                                 (unsigned int) prev, (u32) prev->dma);
 172         }
 173         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 174         ring->enqueue = ring->first_seg->trbs;
 175         ring->enq_seg = ring->first_seg;
 176         ring->dequeue = ring->enqueue;
 177         ring->deq_seg = ring->first_seg;
 178         /* The ring is initialized to 0. The producer must write 1 to the cycle
 179          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 180          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 181          */
 182         ring->cycle_state = 1;
 183
 184         return ring;
 185
 186 fail:
 187         xhci_ring_free(xhci, ring);
 188         return 0;
 189 }
 190
 191 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 192 {
 193         struct xhci_virt_device *dev;
 194         int i;
 195
 196         /* Slot ID 0 is reserved */
 197         if (slot_id == 0 || !xhci->devs[slot_id])
 198                 return;
 199
 200         dev = xhci->devs[slot_id];
 201         xhci->dcbaa->dev_context_ptrs[2*slot_id] = 0;
 202         xhci->dcbaa->dev_context_ptrs[2*slot_id + 1] = 0;
 203         if (!dev)
 204                 return;
 205
 206         for (i = 0; i < 31; ++i)
 207                 if (dev->ep_rings[i])
 208                         xhci_ring_free(xhci, dev->ep_rings[i]);
 209
 210         if (dev->in_ctx)
 211                 dma_pool_free(xhci->device_pool,
 212                                 dev->in_ctx, dev->in_ctx_dma);
 213         if (dev->out_ctx)
 214                 dma_pool_free(xhci->device_pool,
 215                                 dev->out_ctx, dev->out_ctx_dma);
 216         kfree(xhci->devs[slot_id]);
 217         xhci->devs[slot_id] = 0;
 218 }
 219
 220 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 221                 struct usb_device *udev, gfp_t flags)
 222 {
 223         dma_addr_t      dma;
 224         struct xhci_virt_device *dev;
 225
 226         /* Slot ID 0 is reserved */
 227         if (slot_id == 0 || xhci->devs[slot_id]) {
 228                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 229                 return 0;
 230         }
 231
 232         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 233         if (!xhci->devs[slot_id])
 234                 return 0;
 235         dev = xhci->devs[slot_id];
 236
 237         /* Allocate the (output) device context that will be used in the HC */
 238         dev->out_ctx = dma_pool_alloc(xhci->device_pool, flags, &dma);
 239         if (!dev->out_ctx)
 240                 goto fail;
 241         dev->out_ctx_dma = dma;
 242         xhci_dbg(xhci, "Slot %d output ctx = 0x%x (dma)\n", slot_id, dma);
 243         memset(dev->out_ctx, 0, sizeof(*dev->out_ctx));
 244
 245         /* Allocate the (input) device context for address device command */
 246         dev->in_ctx = dma_pool_alloc(xhci->device_pool, flags, &dma);
 247         if (!dev->in_ctx)
 248                 goto fail;
 249         dev->in_ctx_dma = dma;
 250         xhci_dbg(xhci, "Slot %d input ctx = 0x%x (dma)\n", slot_id, dma);
 251         memset(dev->in_ctx, 0, sizeof(*dev->in_ctx));
 252
 253         /* Allocate endpoint 0 ring */
 254         dev->ep_rings[0] = xhci_ring_alloc(xhci, 1, true, flags);
 255         if (!dev->ep_rings[0])
 256                 goto fail;
 257
 258         /*
 259          * Point to output device context in dcbaa; skip the output control
 260          * context, which is eight 32 bit fields (or 32 bytes long)
 261          */
 262         xhci->dcbaa->dev_context_ptrs[2*slot_id] =
 263                 (u32) dev->out_ctx_dma + (32);
 264         xhci_dbg(xhci, "Set slot id %d dcbaa entry 0x%x to 0x%x\n",
 265                         slot_id,
 266                         (unsigned int) &xhci->dcbaa->dev_context_ptrs[2*slot_id],
 267                         dev->out_ctx_dma);
 268         xhci->dcbaa->dev_context_ptrs[2*slot_id + 1] = 0;
 269
 270         return 1;
 271 fail:
 272         xhci_free_virt_device(xhci, slot_id);
 273         return 0;
 274 }
 275
 276 /* Setup an xHCI virtual device for a Set Address command */
 277 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
 278 {
 279         struct xhci_virt_device *dev;
 280         struct xhci_ep_ctx      *ep0_ctx;
 281         struct usb_device       *top_dev;
 282
 283         dev = xhci->devs[udev->slot_id];
 284         /* Slot ID 0 is reserved */
 285         if (udev->slot_id == 0 || !dev) {
 286                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
 287                                 udev->slot_id);
 288                 return -EINVAL;
 289         }
 290         ep0_ctx = &dev->in_ctx->ep[0];
 291
 292         /* 2) New slot context and endpoint 0 context are valid*/
 293         dev->in_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
 294
 295         /* 3) Only the control endpoint is valid - one endpoint context */
 296         dev->in_ctx->slot.dev_info |= LAST_CTX(1);
 297
 298         switch (udev->speed) {
 299         case USB_SPEED_SUPER:
 300                 dev->in_ctx->slot.dev_info |= (u32) udev->route;
 301                 dev->in_ctx->slot.dev_info |= (u32) SLOT_SPEED_SS;
 302                 break;
 303         case USB_SPEED_HIGH:
 304                 dev->in_ctx->slot.dev_info |= (u32) SLOT_SPEED_HS;
 305                 break;
 306         case USB_SPEED_FULL:
 307                 dev->in_ctx->slot.dev_info |= (u32) SLOT_SPEED_FS;
 308                 break;
 309         case USB_SPEED_LOW:
 310                 dev->in_ctx->slot.dev_info |= (u32) SLOT_SPEED_LS;
 311                 break;
 312         case USB_SPEED_VARIABLE:
 313                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
 314                 return -EINVAL;
 315                 break;
 316         default:
 317                 /* Speed was set earlier, this shouldn't happen. */
 318                 BUG();
 319         }
 320         /* Find the root hub port this device is under */
 321         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 322                         top_dev = top_dev->parent)
 323                 /* Found device below root hub */;
 324         dev->in_ctx->slot.dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
 325         xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum);
 326
 327         /* Is this a LS/FS device under a HS hub? */
 328         /*
 329          * FIXME: I don't think this is right, where does the TT info for the
 330          * roothub or parent hub come from?
 331          */
 332         if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&
 333                         udev->tt) {
 334                 dev->in_ctx->slot.tt_info = udev->tt->hub->slot_id;
 335                 dev->in_ctx->slot.tt_info |= udev->ttport << 8;
 336         }
 337         xhci_dbg(xhci, "udev->tt = 0x%x\n", (unsigned int) udev->tt);
 338         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
 339
 340         /* Step 4 - ring already allocated */
 341         /* Step 5 */
 342         ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
 343         /*
 344          * See section 4.3 bullet 6:
 345          * The default Max Packet size for ep0 is "8 bytes for a USB2
 346          * LS/FS/HS device or 512 bytes for a USB3 SS device"
 347          * XXX: Not sure about wireless USB devices.
 348          */
 349         if (udev->speed == USB_SPEED_SUPER)
 350                 ep0_ctx->ep_info2 |= MAX_PACKET(512);
 351         else
 352                 ep0_ctx->ep_info2 |= MAX_PACKET(8);
 353         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
 354         ep0_ctx->ep_info2 |= MAX_BURST(0);
 355         ep0_ctx->ep_info2 |= ERROR_COUNT(3);
 356
 357         ep0_ctx->deq[0] =
 358                 dev->ep_rings[0]->first_seg->dma;
 359         ep0_ctx->deq[0] |= dev->ep_rings[0]->cycle_state;
 360         ep0_ctx->deq[1] = 0;
 361
 362         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
 363
 364         return 0;
 365 }
 366
 367 void xhci_mem_cleanup(struct xhci_hcd *xhci)
 368 {
 369         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 370         int size;
 371         int i;
 372
 373         /* Free the Event Ring Segment Table and the actual Event Ring */
 374         xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
 375         xhci_writel(xhci, 0, &xhci->ir_set->erst_base[1]);
 376         xhci_writel(xhci, 0, &xhci->ir_set->erst_base[0]);
 377         xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[1]);
 378         xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[0]);
 379         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
 380         if (xhci->erst.entries)
 381                 pci_free_consistent(pdev, size,
 382                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
 383         xhci->erst.entries = NULL;
 384         xhci_dbg(xhci, "Freed ERST\n");
 385         if (xhci->event_ring)
 386                 xhci_ring_free(xhci, xhci->event_ring);
 387         xhci->event_ring = NULL;
 388         xhci_dbg(xhci, "Freed event ring\n");
 389
 390         xhci_writel(xhci, 0, &xhci->op_regs->cmd_ring[1]);
 391         xhci_writel(xhci, 0, &xhci->op_regs->cmd_ring[0]);
 392         if (xhci->cmd_ring)
 393                 xhci_ring_free(xhci, xhci->cmd_ring);
 394         xhci->cmd_ring = NULL;
 395         xhci_dbg(xhci, "Freed command ring\n");
 396
 397         for (i = 1; i < MAX_HC_SLOTS; ++i)
 398                 xhci_free_virt_device(xhci, i);
 399
 400         if (xhci->segment_pool)
 401                 dma_pool_destroy(xhci->segment_pool);
 402         xhci->segment_pool = NULL;
 403         xhci_dbg(xhci, "Freed segment pool\n");
 404
 405         if (xhci->device_pool)
 406                 dma_pool_destroy(xhci->device_pool);
 407         xhci->device_pool = NULL;
 408         xhci_dbg(xhci, "Freed device context pool\n");
 409
 410         xhci_writel(xhci, 0, &xhci->op_regs->dcbaa_ptr[1]);
 411         xhci_writel(xhci, 0, &xhci->op_regs->dcbaa_ptr[0]);
 412         if (xhci->dcbaa)
 413                 pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
 414                                 xhci->dcbaa, xhci->dcbaa->dma);
 415         xhci->dcbaa = NULL;
 416
 417         xhci->page_size = 0;
 418         xhci->page_shift = 0;
 419 }
 420
 421 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
 422 {
 423         dma_addr_t      dma;
 424         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
 425         unsigned int    val, val2;
 426         struct xhci_segment     *seg;
 427         u32 page_size;
 428         int i;
 429
 430         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
 431         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
 432         for (i = 0; i < 16; i++) {
 433                 if ((0x1 & page_size) != 0)
 434                         break;
 435                 page_size = page_size >> 1;
 436         }
 437         if (i < 16)
 438                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
 439         else
 440                 xhci_warn(xhci, "WARN: no supported page size\n");
 441         /* Use 4K pages, since that's common and the minimum the HC supports */
 442         xhci->page_shift = 12;
 443         xhci->page_size = 1 << xhci->page_shift;
 444         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
 445
 446         /*
 447          * Program the Number of Device Slots Enabled field in the CONFIG
 448          * register with the max value of slots the HC can handle.
 449          */
 450         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
 451         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
 452                         (unsigned int) val);
 453         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
 454         val |= (val2 & ~HCS_SLOTS_MASK);
 455         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
 456                         (unsigned int) val);
 457         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
 458
 459         /*
 460          * Section 5.4.8 - doorbell array must be
 461          * "physically contiguous and 64-byte (cache line) aligned".
 462          */
 463         xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
 464                         sizeof(*xhci->dcbaa), &dma);
 465         if (!xhci->dcbaa)
 466                 goto fail;
 467         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
 468         xhci->dcbaa->dma = dma;
 469         xhci_dbg(xhci, "// Device context base array address = 0x%x (DMA), 0x%x (virt)\n",
 470                         xhci->dcbaa->dma, (unsigned int) xhci->dcbaa);
 471         xhci_writel(xhci, (u32) 0, &xhci->op_regs->dcbaa_ptr[1]);
 472         xhci_writel(xhci, dma, &xhci->op_regs->dcbaa_ptr[0]);
 473
 474         /*
 475          * Initialize the ring segment pool.  The ring must be a contiguous
 476          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
 477          * however, the command ring segment needs 64-byte aligned segments,
 478          * so we pick the greater alignment need.
 479          */
 480         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
 481                         SEGMENT_SIZE, 64, xhci->page_size);
 482         /* See Table 46 and Note on Figure 55 */
 483         /* FIXME support 64-byte contexts */
 484         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
 485                         sizeof(struct xhci_device_control),
 486                         64, xhci->page_size);
 487         if (!xhci->segment_pool || !xhci->device_pool)
 488                 goto fail;
 489
 490         /* Set up the command ring to have one segments for now. */
 491         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
 492         if (!xhci->cmd_ring)
 493                 goto fail;
 494         xhci_dbg(xhci, "Allocated command ring at 0x%x\n", (unsigned int) xhci->cmd_ring);
 495         xhci_dbg(xhci, "First segment DMA is 0x%x\n", (unsigned int) xhci->cmd_ring->first_seg->dma);
 496
 497         /* Set the address in the Command Ring Control register */
 498         val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]);
 499         val = (val & ~CMD_RING_ADDR_MASK) |
 500                 (xhci->cmd_ring->first_seg->dma & CMD_RING_ADDR_MASK) |
 501                 xhci->cmd_ring->cycle_state;
 502         xhci_dbg(xhci, "// Setting command ring address high bits to 0x0\n");
 503         xhci_writel(xhci, (u32) 0, &xhci->op_regs->cmd_ring[1]);
 504         xhci_dbg(xhci, "// Setting command ring address low bits to 0x%x\n", val);
 505         xhci_writel(xhci, val, &xhci->op_regs->cmd_ring[0]);
 506         xhci_dbg_cmd_ptrs(xhci);
 507
 508         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
 509         val &= DBOFF_MASK;
 510         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
 511                         " from cap regs base addr\n", val);
 512         xhci->dba = (void *) xhci->cap_regs + val;
 513         xhci_dbg_regs(xhci);
 514         xhci_print_run_regs(xhci);
 515         /* Set ir_set to interrupt register set 0 */
 516         xhci->ir_set = (void *) xhci->run_regs->ir_set;
 517
 518         /*
 519          * Event ring setup: Allocate a normal ring, but also setup
 520          * the event ring segment table (ERST).  Section 4.9.3.
 521          */
 522         xhci_dbg(xhci, "// Allocating event ring\n");
 523         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
 524         if (!xhci->event_ring)
 525                 goto fail;
 526
 527         xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
 528                         sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
 529         if (!xhci->erst.entries)
 530                 goto fail;
 531         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%x\n", dma);
 532
 533         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
 534         xhci->erst.num_entries = ERST_NUM_SEGS;
 535         xhci->erst.erst_dma_addr = dma;
 536         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = 0x%x, dma addr = 0x%x\n",
 537                         xhci->erst.num_entries,
 538                         (unsigned int) xhci->erst.entries,
 539                         xhci->erst.erst_dma_addr);
 540
 541         /* set ring base address and size for each segment table entry */
 542         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
 543                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
 544                 entry->seg_addr[1] = 0;
 545                 entry->seg_addr[0] = seg->dma;
 546                 entry->seg_size = TRBS_PER_SEGMENT;
 547                 entry->rsvd = 0;
 548                 seg = seg->next;
 549         }
 550
 551         /* set ERST count with the number of entries in the segment table */
 552         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
 553         val &= ERST_SIZE_MASK;
 554         val |= ERST_NUM_SEGS;
 555         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
 556                         val);
 557         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
 558
 559         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
 560         /* set the segment table base address */
 561         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%x\n",
 562                         xhci->erst.erst_dma_addr);
 563         xhci_writel(xhci, 0, &xhci->ir_set->erst_base[1]);
 564         val = xhci_readl(xhci, &xhci->ir_set->erst_base[0]);
 565         val &= ERST_PTR_MASK;
 566         val |= (xhci->erst.erst_dma_addr & ~ERST_PTR_MASK);
 567         xhci_writel(xhci, val, &xhci->ir_set->erst_base[0]);
 568
 569         /* Set the event ring dequeue address */
 570         set_hc_event_deq(xhci);
 571         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
 572         xhci_print_ir_set(xhci, xhci->ir_set, 0);
 573
 574         /*
 575          * XXX: Might need to set the Interrupter Moderation Register to
 576          * something other than the default (~1ms minimum between interrupts).
 577          * See section 5.5.1.2.
 578          */
 579         init_completion(&xhci->addr_dev);
 580         for (i = 0; i < MAX_HC_SLOTS; ++i)
 581                 xhci->devs[i] = 0;
 582
 583         return 0;
 584 fail:
 585         xhci_warn(xhci, "Couldn't initialize memory\n");
 586         xhci_mem_cleanup(xhci);
 587         return -ENOMEM;
 588 }