2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
27 #include <linux/dma-mapping.h>
30 #include "xhci-trace.h"
33 * Allocates a generic ring segment from the ring pool, sets the dma address,
34 * initializes the segment to zero, and sets the private next pointer to NULL.
37 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
39 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
,
40 unsigned int cycle_state
, gfp_t flags
)
42 struct xhci_segment
*seg
;
46 seg
= kzalloc(sizeof *seg
, flags
);
50 seg
->trbs
= dma_pool_alloc(xhci
->segment_pool
, flags
, &dma
);
56 memset(seg
->trbs
, 0, TRB_SEGMENT_SIZE
);
57 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
58 if (cycle_state
== 0) {
59 for (i
= 0; i
< TRBS_PER_SEGMENT
; i
++)
60 seg
->trbs
[i
].link
.control
|= cpu_to_le32(TRB_CYCLE
);
68 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
71 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
77 static void xhci_free_segments_for_ring(struct xhci_hcd
*xhci
,
78 struct xhci_segment
*first
)
80 struct xhci_segment
*seg
;
83 while (seg
!= first
) {
84 struct xhci_segment
*next
= seg
->next
;
85 xhci_segment_free(xhci
, seg
);
88 xhci_segment_free(xhci
, first
);
92 * Make the prev segment point to the next segment.
94 * Change the last TRB in the prev segment to be a Link TRB which points to the
95 * DMA address of the next segment. The caller needs to set any Link TRB
96 * related flags, such as End TRB, Toggle Cycle, and no snoop.
98 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
99 struct xhci_segment
*next
, enum xhci_ring_type type
)
106 if (type
!= TYPE_EVENT
) {
107 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
=
108 cpu_to_le64(next
->dma
);
110 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
111 val
= le32_to_cpu(prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
);
112 val
&= ~TRB_TYPE_BITMASK
;
113 val
|= TRB_TYPE(TRB_LINK
);
114 /* Always set the chain bit with 0.95 hardware */
115 /* Set chain bit for isoc rings on AMD 0.96 host */
116 if (xhci_link_trb_quirk(xhci
) ||
117 (type
== TYPE_ISOC
&&
118 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
120 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= cpu_to_le32(val
);
125 * Link the ring to the new segments.
126 * Set Toggle Cycle for the new ring if needed.
128 static void xhci_link_rings(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
129 struct xhci_segment
*first
, struct xhci_segment
*last
,
130 unsigned int num_segs
)
132 struct xhci_segment
*next
;
134 if (!ring
|| !first
|| !last
)
137 next
= ring
->enq_seg
->next
;
138 xhci_link_segments(xhci
, ring
->enq_seg
, first
, ring
->type
);
139 xhci_link_segments(xhci
, last
, next
, ring
->type
);
140 ring
->num_segs
+= num_segs
;
141 ring
->num_trbs_free
+= (TRBS_PER_SEGMENT
- 1) * num_segs
;
143 if (ring
->type
!= TYPE_EVENT
&& ring
->enq_seg
== ring
->last_seg
) {
144 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
145 &= ~cpu_to_le32(LINK_TOGGLE
);
146 last
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
147 |= cpu_to_le32(LINK_TOGGLE
);
148 ring
->last_seg
= last
;
152 /* XXX: Do we need the hcd structure in all these functions? */
153 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
159 xhci_free_segments_for_ring(xhci
, ring
->first_seg
);
164 static void xhci_initialize_ring_info(struct xhci_ring
*ring
,
165 unsigned int cycle_state
)
167 /* The ring is empty, so the enqueue pointer == dequeue pointer */
168 ring
->enqueue
= ring
->first_seg
->trbs
;
169 ring
->enq_seg
= ring
->first_seg
;
170 ring
->dequeue
= ring
->enqueue
;
171 ring
->deq_seg
= ring
->first_seg
;
172 /* The ring is initialized to 0. The producer must write 1 to the cycle
173 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
174 * compare CCS to the cycle bit to check ownership, so CCS = 1.
176 * New rings are initialized with cycle state equal to 1; if we are
177 * handling ring expansion, set the cycle state equal to the old ring.
179 ring
->cycle_state
= cycle_state
;
180 /* Not necessary for new rings, but needed for re-initialized rings */
181 ring
->enq_updates
= 0;
182 ring
->deq_updates
= 0;
185 * Each segment has a link TRB, and leave an extra TRB for SW
188 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
191 /* Allocate segments and link them for a ring */
192 static int xhci_alloc_segments_for_ring(struct xhci_hcd
*xhci
,
193 struct xhci_segment
**first
, struct xhci_segment
**last
,
194 unsigned int num_segs
, unsigned int cycle_state
,
195 enum xhci_ring_type type
, gfp_t flags
)
197 struct xhci_segment
*prev
;
199 prev
= xhci_segment_alloc(xhci
, cycle_state
, flags
);
205 while (num_segs
> 0) {
206 struct xhci_segment
*next
;
208 next
= xhci_segment_alloc(xhci
, cycle_state
, flags
);
213 xhci_segment_free(xhci
, prev
);
218 xhci_link_segments(xhci
, prev
, next
, type
);
223 xhci_link_segments(xhci
, prev
, *first
, type
);
230 * Create a new ring with zero or more segments.
232 * Link each segment together into a ring.
233 * Set the end flag and the cycle toggle bit on the last segment.
234 * See section 4.9.1 and figures 15 and 16.
236 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
237 unsigned int num_segs
, unsigned int cycle_state
,
238 enum xhci_ring_type type
, gfp_t flags
)
240 struct xhci_ring
*ring
;
243 ring
= kzalloc(sizeof *(ring
), flags
);
247 ring
->num_segs
= num_segs
;
248 INIT_LIST_HEAD(&ring
->td_list
);
253 ret
= xhci_alloc_segments_for_ring(xhci
, &ring
->first_seg
,
254 &ring
->last_seg
, num_segs
, cycle_state
, type
, flags
);
258 /* Only event ring does not use link TRB */
259 if (type
!= TYPE_EVENT
) {
260 /* See section 4.9.2.1 and 6.4.4.1 */
261 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
|=
262 cpu_to_le32(LINK_TOGGLE
);
264 xhci_initialize_ring_info(ring
, cycle_state
);
272 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd
*xhci
,
273 struct xhci_virt_device
*virt_dev
,
274 unsigned int ep_index
)
278 rings_cached
= virt_dev
->num_rings_cached
;
279 if (rings_cached
< XHCI_MAX_RINGS_CACHED
) {
280 virt_dev
->ring_cache
[rings_cached
] =
281 virt_dev
->eps
[ep_index
].ring
;
282 virt_dev
->num_rings_cached
++;
283 xhci_dbg(xhci
, "Cached old ring, "
284 "%d ring%s cached\n",
285 virt_dev
->num_rings_cached
,
286 (virt_dev
->num_rings_cached
> 1) ? "s" : "");
288 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].ring
);
289 xhci_dbg(xhci
, "Ring cache full (%d rings), "
291 virt_dev
->num_rings_cached
);
293 virt_dev
->eps
[ep_index
].ring
= NULL
;
296 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
297 * pointers to the beginning of the ring.
299 static void xhci_reinit_cached_ring(struct xhci_hcd
*xhci
,
300 struct xhci_ring
*ring
, unsigned int cycle_state
,
301 enum xhci_ring_type type
)
303 struct xhci_segment
*seg
= ring
->first_seg
;
308 sizeof(union xhci_trb
)*TRBS_PER_SEGMENT
);
309 if (cycle_state
== 0) {
310 for (i
= 0; i
< TRBS_PER_SEGMENT
; i
++)
311 seg
->trbs
[i
].link
.control
|=
312 cpu_to_le32(TRB_CYCLE
);
314 /* All endpoint rings have link TRBs */
315 xhci_link_segments(xhci
, seg
, seg
->next
, type
);
317 } while (seg
!= ring
->first_seg
);
319 xhci_initialize_ring_info(ring
, cycle_state
);
320 /* td list should be empty since all URBs have been cancelled,
321 * but just in case...
323 INIT_LIST_HEAD(&ring
->td_list
);
327 * Expand an existing ring.
328 * Look for a cached ring or allocate a new ring which has same segment numbers
329 * and link the two rings.
331 int xhci_ring_expansion(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
332 unsigned int num_trbs
, gfp_t flags
)
334 struct xhci_segment
*first
;
335 struct xhci_segment
*last
;
336 unsigned int num_segs
;
337 unsigned int num_segs_needed
;
340 num_segs_needed
= (num_trbs
+ (TRBS_PER_SEGMENT
- 1) - 1) /
341 (TRBS_PER_SEGMENT
- 1);
343 /* Allocate number of segments we needed, or double the ring size */
344 num_segs
= ring
->num_segs
> num_segs_needed
?
345 ring
->num_segs
: num_segs_needed
;
347 ret
= xhci_alloc_segments_for_ring(xhci
, &first
, &last
,
348 num_segs
, ring
->cycle_state
, ring
->type
, flags
);
352 xhci_link_rings(xhci
, ring
, first
, last
, num_segs
);
353 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
354 "ring expansion succeed, now has %d segments",
360 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
362 static struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
363 int type
, gfp_t flags
)
365 struct xhci_container_ctx
*ctx
;
367 if ((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
))
370 ctx
= kzalloc(sizeof(*ctx
), flags
);
375 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
376 if (type
== XHCI_CTX_TYPE_INPUT
)
377 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
379 ctx
->bytes
= dma_pool_alloc(xhci
->device_pool
, flags
, &ctx
->dma
);
384 memset(ctx
->bytes
, 0, ctx
->size
);
388 static void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
389 struct xhci_container_ctx
*ctx
)
393 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
397 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_hcd
*xhci
,
398 struct xhci_container_ctx
*ctx
)
400 if (ctx
->type
!= XHCI_CTX_TYPE_INPUT
)
403 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
406 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
407 struct xhci_container_ctx
*ctx
)
409 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
410 return (struct xhci_slot_ctx
*)ctx
->bytes
;
412 return (struct xhci_slot_ctx
*)
413 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
416 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
417 struct xhci_container_ctx
*ctx
,
418 unsigned int ep_index
)
420 /* increment ep index by offset of start of ep ctx array */
422 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
425 return (struct xhci_ep_ctx
*)
426 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
430 /***************** Streams structures manipulation *************************/
432 static void xhci_free_stream_ctx(struct xhci_hcd
*xhci
,
433 unsigned int num_stream_ctxs
,
434 struct xhci_stream_ctx
*stream_ctx
, dma_addr_t dma
)
436 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
438 if (num_stream_ctxs
> MEDIUM_STREAM_ARRAY_SIZE
)
439 dma_free_coherent(&pdev
->dev
,
440 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
,
442 else if (num_stream_ctxs
<= SMALL_STREAM_ARRAY_SIZE
)
443 return dma_pool_free(xhci
->small_streams_pool
,
446 return dma_pool_free(xhci
->medium_streams_pool
,
451 * The stream context array for each endpoint with bulk streams enabled can
452 * vary in size, based on:
453 * - how many streams the endpoint supports,
454 * - the maximum primary stream array size the host controller supports,
455 * - and how many streams the device driver asks for.
457 * The stream context array must be a power of 2, and can be as small as
458 * 64 bytes or as large as 1MB.
460 static struct xhci_stream_ctx
*xhci_alloc_stream_ctx(struct xhci_hcd
*xhci
,
461 unsigned int num_stream_ctxs
, dma_addr_t
*dma
,
464 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
466 if (num_stream_ctxs
> MEDIUM_STREAM_ARRAY_SIZE
)
467 return dma_alloc_coherent(&pdev
->dev
,
468 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
,
470 else if (num_stream_ctxs
<= SMALL_STREAM_ARRAY_SIZE
)
471 return dma_pool_alloc(xhci
->small_streams_pool
,
474 return dma_pool_alloc(xhci
->medium_streams_pool
,
478 struct xhci_ring
*xhci_dma_to_transfer_ring(
479 struct xhci_virt_ep
*ep
,
482 if (ep
->ep_state
& EP_HAS_STREAMS
)
483 return radix_tree_lookup(&ep
->stream_info
->trb_address_map
,
484 address
>> TRB_SEGMENT_SHIFT
);
488 struct xhci_ring
*xhci_stream_id_to_ring(
489 struct xhci_virt_device
*dev
,
490 unsigned int ep_index
,
491 unsigned int stream_id
)
493 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
497 if (!ep
->stream_info
)
500 if (stream_id
> ep
->stream_info
->num_streams
)
502 return ep
->stream_info
->stream_rings
[stream_id
];
506 * Change an endpoint's internal structure so it supports stream IDs. The
507 * number of requested streams includes stream 0, which cannot be used by device
510 * The number of stream contexts in the stream context array may be bigger than
511 * the number of streams the driver wants to use. This is because the number of
512 * stream context array entries must be a power of two.
514 * We need a radix tree for mapping physical addresses of TRBs to which stream
515 * ID they belong to. We need to do this because the host controller won't tell
516 * us which stream ring the TRB came from. We could store the stream ID in an
517 * event data TRB, but that doesn't help us for the cancellation case, since the
518 * endpoint may stop before it reaches that event data TRB.
520 * The radix tree maps the upper portion of the TRB DMA address to a ring
521 * segment that has the same upper portion of DMA addresses. For example, say I
522 * have segments of size 1KB, that are always 64-byte aligned. A segment may
523 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
524 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
525 * pass the radix tree a key to get the right stream ID:
527 * 0x10c90fff >> 10 = 0x43243
528 * 0x10c912c0 >> 10 = 0x43244
529 * 0x10c91400 >> 10 = 0x43245
531 * Obviously, only those TRBs with DMA addresses that are within the segment
532 * will make the radix tree return the stream ID for that ring.
534 * Caveats for the radix tree:
536 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
537 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
538 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
539 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
540 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
541 * extended systems (where the DMA address can be bigger than 32-bits),
542 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
544 struct xhci_stream_info
*xhci_alloc_stream_info(struct xhci_hcd
*xhci
,
545 unsigned int num_stream_ctxs
,
546 unsigned int num_streams
, gfp_t mem_flags
)
548 struct xhci_stream_info
*stream_info
;
550 struct xhci_ring
*cur_ring
;
555 xhci_dbg(xhci
, "Allocating %u streams and %u "
556 "stream context array entries.\n",
557 num_streams
, num_stream_ctxs
);
558 if (xhci
->cmd_ring_reserved_trbs
== MAX_RSVD_CMD_TRBS
) {
559 xhci_dbg(xhci
, "Command ring has no reserved TRBs available\n");
562 xhci
->cmd_ring_reserved_trbs
++;
564 stream_info
= kzalloc(sizeof(struct xhci_stream_info
), mem_flags
);
568 stream_info
->num_streams
= num_streams
;
569 stream_info
->num_stream_ctxs
= num_stream_ctxs
;
571 /* Initialize the array of virtual pointers to stream rings. */
572 stream_info
->stream_rings
= kzalloc(
573 sizeof(struct xhci_ring
*)*num_streams
,
575 if (!stream_info
->stream_rings
)
578 /* Initialize the array of DMA addresses for stream rings for the HW. */
579 stream_info
->stream_ctx_array
= xhci_alloc_stream_ctx(xhci
,
580 num_stream_ctxs
, &stream_info
->ctx_array_dma
,
582 if (!stream_info
->stream_ctx_array
)
584 memset(stream_info
->stream_ctx_array
, 0,
585 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
);
587 /* Allocate everything needed to free the stream rings later */
588 stream_info
->free_streams_command
=
589 xhci_alloc_command(xhci
, true, true, mem_flags
);
590 if (!stream_info
->free_streams_command
)
593 INIT_RADIX_TREE(&stream_info
->trb_address_map
, GFP_ATOMIC
);
595 /* Allocate rings for all the streams that the driver will use,
596 * and add their segment DMA addresses to the radix tree.
597 * Stream 0 is reserved.
599 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
600 stream_info
->stream_rings
[cur_stream
] =
601 xhci_ring_alloc(xhci
, 2, 1, TYPE_STREAM
, mem_flags
);
602 cur_ring
= stream_info
->stream_rings
[cur_stream
];
605 cur_ring
->stream_id
= cur_stream
;
606 /* Set deq ptr, cycle bit, and stream context type */
607 addr
= cur_ring
->first_seg
->dma
|
608 SCT_FOR_CTX(SCT_PRI_TR
) |
609 cur_ring
->cycle_state
;
610 stream_info
->stream_ctx_array
[cur_stream
].stream_ring
=
612 xhci_dbg(xhci
, "Setting stream %d ring ptr to 0x%08llx\n",
613 cur_stream
, (unsigned long long) addr
);
615 key
= (unsigned long)
616 (cur_ring
->first_seg
->dma
>> TRB_SEGMENT_SHIFT
);
617 ret
= radix_tree_insert(&stream_info
->trb_address_map
,
620 xhci_ring_free(xhci
, cur_ring
);
621 stream_info
->stream_rings
[cur_stream
] = NULL
;
625 /* Leave the other unused stream ring pointers in the stream context
626 * array initialized to zero. This will cause the xHC to give us an
627 * error if the device asks for a stream ID we don't have setup (if it
628 * was any other way, the host controller would assume the ring is
629 * "empty" and wait forever for data to be queued to that stream ID).
635 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
636 cur_ring
= stream_info
->stream_rings
[cur_stream
];
638 addr
= cur_ring
->first_seg
->dma
;
639 radix_tree_delete(&stream_info
->trb_address_map
,
640 addr
>> TRB_SEGMENT_SHIFT
);
641 xhci_ring_free(xhci
, cur_ring
);
642 stream_info
->stream_rings
[cur_stream
] = NULL
;
645 xhci_free_command(xhci
, stream_info
->free_streams_command
);
647 kfree(stream_info
->stream_rings
);
651 xhci
->cmd_ring_reserved_trbs
--;
655 * Sets the MaxPStreams field and the Linear Stream Array field.
656 * Sets the dequeue pointer to the stream context array.
658 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
659 struct xhci_ep_ctx
*ep_ctx
,
660 struct xhci_stream_info
*stream_info
)
662 u32 max_primary_streams
;
663 /* MaxPStreams is the number of stream context array entries, not the
664 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
665 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
667 max_primary_streams
= fls(stream_info
->num_stream_ctxs
) - 2;
668 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
669 "Setting number of stream ctx array entries to %u",
670 1 << (max_primary_streams
+ 1));
671 ep_ctx
->ep_info
&= cpu_to_le32(~EP_MAXPSTREAMS_MASK
);
672 ep_ctx
->ep_info
|= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams
)
674 ep_ctx
->deq
= cpu_to_le64(stream_info
->ctx_array_dma
);
678 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
679 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
680 * not at the beginning of the ring).
682 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
683 struct xhci_ep_ctx
*ep_ctx
,
684 struct xhci_virt_ep
*ep
)
687 ep_ctx
->ep_info
&= cpu_to_le32(~(EP_MAXPSTREAMS_MASK
| EP_HAS_LSA
));
688 addr
= xhci_trb_virt_to_dma(ep
->ring
->deq_seg
, ep
->ring
->dequeue
);
689 ep_ctx
->deq
= cpu_to_le64(addr
| ep
->ring
->cycle_state
);
692 /* Frees all stream contexts associated with the endpoint,
694 * Caller should fix the endpoint context streams fields.
696 void xhci_free_stream_info(struct xhci_hcd
*xhci
,
697 struct xhci_stream_info
*stream_info
)
700 struct xhci_ring
*cur_ring
;
706 for (cur_stream
= 1; cur_stream
< stream_info
->num_streams
;
708 cur_ring
= stream_info
->stream_rings
[cur_stream
];
710 addr
= cur_ring
->first_seg
->dma
;
711 radix_tree_delete(&stream_info
->trb_address_map
,
712 addr
>> TRB_SEGMENT_SHIFT
);
713 xhci_ring_free(xhci
, cur_ring
);
714 stream_info
->stream_rings
[cur_stream
] = NULL
;
717 xhci_free_command(xhci
, stream_info
->free_streams_command
);
718 xhci
->cmd_ring_reserved_trbs
--;
719 if (stream_info
->stream_ctx_array
)
720 xhci_free_stream_ctx(xhci
,
721 stream_info
->num_stream_ctxs
,
722 stream_info
->stream_ctx_array
,
723 stream_info
->ctx_array_dma
);
726 kfree(stream_info
->stream_rings
);
731 /***************** Device context manipulation *************************/
733 static void xhci_init_endpoint_timer(struct xhci_hcd
*xhci
,
734 struct xhci_virt_ep
*ep
)
736 init_timer(&ep
->stop_cmd_timer
);
737 ep
->stop_cmd_timer
.data
= (unsigned long) ep
;
738 ep
->stop_cmd_timer
.function
= xhci_stop_endpoint_command_watchdog
;
742 static void xhci_free_tt_info(struct xhci_hcd
*xhci
,
743 struct xhci_virt_device
*virt_dev
,
746 struct list_head
*tt_list_head
;
747 struct xhci_tt_bw_info
*tt_info
, *next
;
748 bool slot_found
= false;
750 /* If the device never made it past the Set Address stage,
751 * it may not have the real_port set correctly.
753 if (virt_dev
->real_port
== 0 ||
754 virt_dev
->real_port
> HCS_MAX_PORTS(xhci
->hcs_params1
)) {
755 xhci_dbg(xhci
, "Bad real port.\n");
759 tt_list_head
= &(xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
760 list_for_each_entry_safe(tt_info
, next
, tt_list_head
, tt_list
) {
761 /* Multi-TT hubs will have more than one entry */
762 if (tt_info
->slot_id
== slot_id
) {
764 list_del(&tt_info
->tt_list
);
766 } else if (slot_found
) {
772 int xhci_alloc_tt_info(struct xhci_hcd
*xhci
,
773 struct xhci_virt_device
*virt_dev
,
774 struct usb_device
*hdev
,
775 struct usb_tt
*tt
, gfp_t mem_flags
)
777 struct xhci_tt_bw_info
*tt_info
;
778 unsigned int num_ports
;
784 num_ports
= hdev
->maxchild
;
786 for (i
= 0; i
< num_ports
; i
++, tt_info
++) {
787 struct xhci_interval_bw_table
*bw_table
;
789 tt_info
= kzalloc(sizeof(*tt_info
), mem_flags
);
792 INIT_LIST_HEAD(&tt_info
->tt_list
);
793 list_add(&tt_info
->tt_list
,
794 &xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
795 tt_info
->slot_id
= virt_dev
->udev
->slot_id
;
797 tt_info
->ttport
= i
+1;
798 bw_table
= &tt_info
->bw_table
;
799 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
800 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
805 xhci_free_tt_info(xhci
, virt_dev
, virt_dev
->udev
->slot_id
);
810 /* All the xhci_tds in the ring's TD list should be freed at this point.
811 * Should be called with xhci->lock held if there is any chance the TT lists
812 * will be manipulated by the configure endpoint, allocate device, or update
813 * hub functions while this function is removing the TT entries from the list.
815 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
817 struct xhci_virt_device
*dev
;
819 int old_active_eps
= 0;
821 /* Slot ID 0 is reserved */
822 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
825 dev
= xhci
->devs
[slot_id
];
826 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
831 old_active_eps
= dev
->tt_info
->active_eps
;
833 for (i
= 0; i
< 31; ++i
) {
834 if (dev
->eps
[i
].ring
)
835 xhci_ring_free(xhci
, dev
->eps
[i
].ring
);
836 if (dev
->eps
[i
].stream_info
)
837 xhci_free_stream_info(xhci
,
838 dev
->eps
[i
].stream_info
);
839 /* Endpoints on the TT/root port lists should have been removed
840 * when usb_disable_device() was called for the device.
841 * We can't drop them anyway, because the udev might have gone
842 * away by this point, and we can't tell what speed it was.
844 if (!list_empty(&dev
->eps
[i
].bw_endpoint_list
))
845 xhci_warn(xhci
, "Slot %u endpoint %u "
846 "not removed from BW list!\n",
849 /* If this is a hub, free the TT(s) from the TT list */
850 xhci_free_tt_info(xhci
, dev
, slot_id
);
851 /* If necessary, update the number of active TTs on this root port */
852 xhci_update_tt_active_eps(xhci
, dev
, old_active_eps
);
854 if (dev
->ring_cache
) {
855 for (i
= 0; i
< dev
->num_rings_cached
; i
++)
856 xhci_ring_free(xhci
, dev
->ring_cache
[i
]);
857 kfree(dev
->ring_cache
);
861 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
863 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
865 kfree(xhci
->devs
[slot_id
]);
866 xhci
->devs
[slot_id
] = NULL
;
869 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
870 struct usb_device
*udev
, gfp_t flags
)
872 struct xhci_virt_device
*dev
;
875 /* Slot ID 0 is reserved */
876 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
877 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
881 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
882 if (!xhci
->devs
[slot_id
])
884 dev
= xhci
->devs
[slot_id
];
886 /* Allocate the (output) device context that will be used in the HC. */
887 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
891 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
892 (unsigned long long)dev
->out_ctx
->dma
);
894 /* Allocate the (input) device context for address device command */
895 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
899 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
900 (unsigned long long)dev
->in_ctx
->dma
);
902 /* Initialize the cancellation list and watchdog timers for each ep */
903 for (i
= 0; i
< 31; i
++) {
904 xhci_init_endpoint_timer(xhci
, &dev
->eps
[i
]);
905 INIT_LIST_HEAD(&dev
->eps
[i
].cancelled_td_list
);
906 INIT_LIST_HEAD(&dev
->eps
[i
].bw_endpoint_list
);
909 /* Allocate endpoint 0 ring */
910 dev
->eps
[0].ring
= xhci_ring_alloc(xhci
, 2, 1, TYPE_CTRL
, flags
);
911 if (!dev
->eps
[0].ring
)
914 /* Allocate pointers to the ring cache */
915 dev
->ring_cache
= kzalloc(
916 sizeof(struct xhci_ring
*)*XHCI_MAX_RINGS_CACHED
,
918 if (!dev
->ring_cache
)
920 dev
->num_rings_cached
= 0;
922 init_completion(&dev
->cmd_completion
);
923 INIT_LIST_HEAD(&dev
->cmd_list
);
926 /* Point to output device context in dcbaa. */
927 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = cpu_to_le64(dev
->out_ctx
->dma
);
928 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
930 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
931 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[slot_id
]));
935 xhci_free_virt_device(xhci
, slot_id
);
939 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd
*xhci
,
940 struct usb_device
*udev
)
942 struct xhci_virt_device
*virt_dev
;
943 struct xhci_ep_ctx
*ep0_ctx
;
944 struct xhci_ring
*ep_ring
;
946 virt_dev
= xhci
->devs
[udev
->slot_id
];
947 ep0_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, 0);
948 ep_ring
= virt_dev
->eps
[0].ring
;
950 * FIXME we don't keep track of the dequeue pointer very well after a
951 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
952 * host to our enqueue pointer. This should only be called after a
953 * configured device has reset, so all control transfers should have
954 * been completed or cancelled before the reset.
956 ep0_ctx
->deq
= cpu_to_le64(xhci_trb_virt_to_dma(ep_ring
->enq_seg
,
958 | ep_ring
->cycle_state
);
962 * The xHCI roothub may have ports of differing speeds in any order in the port
963 * status registers. xhci->port_array provides an array of the port speed for
964 * each offset into the port status registers.
966 * The xHCI hardware wants to know the roothub port number that the USB device
967 * is attached to (or the roothub port its ancestor hub is attached to). All we
968 * know is the index of that port under either the USB 2.0 or the USB 3.0
969 * roothub, but that doesn't give us the real index into the HW port status
970 * registers. Call xhci_find_raw_port_number() to get real index.
972 static u32
xhci_find_real_port_number(struct xhci_hcd
*xhci
,
973 struct usb_device
*udev
)
975 struct usb_device
*top_dev
;
978 if (udev
->speed
== USB_SPEED_SUPER
)
979 hcd
= xhci
->shared_hcd
;
981 hcd
= xhci
->main_hcd
;
983 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
984 top_dev
= top_dev
->parent
)
985 /* Found device below root hub */;
987 return xhci_find_raw_port_number(hcd
, top_dev
->portnum
);
990 /* Setup an xHCI virtual device for a Set Address command */
991 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
993 struct xhci_virt_device
*dev
;
994 struct xhci_ep_ctx
*ep0_ctx
;
995 struct xhci_slot_ctx
*slot_ctx
;
998 struct usb_device
*top_dev
;
1000 dev
= xhci
->devs
[udev
->slot_id
];
1001 /* Slot ID 0 is reserved */
1002 if (udev
->slot_id
== 0 || !dev
) {
1003 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
1007 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
1008 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
1010 /* 3) Only the control endpoint is valid - one endpoint context */
1011 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1) | udev
->route
);
1012 switch (udev
->speed
) {
1013 case USB_SPEED_SUPER
:
1014 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_SS
);
1015 max_packets
= MAX_PACKET(512);
1017 case USB_SPEED_HIGH
:
1018 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_HS
);
1019 max_packets
= MAX_PACKET(64);
1021 /* USB core guesses at a 64-byte max packet first for FS devices */
1022 case USB_SPEED_FULL
:
1023 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_FS
);
1024 max_packets
= MAX_PACKET(64);
1027 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_LS
);
1028 max_packets
= MAX_PACKET(8);
1030 case USB_SPEED_WIRELESS
:
1031 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
1035 /* Speed was set earlier, this shouldn't happen. */
1038 /* Find the root hub port this device is under */
1039 port_num
= xhci_find_real_port_number(xhci
, udev
);
1042 slot_ctx
->dev_info2
|= cpu_to_le32(ROOT_HUB_PORT(port_num
));
1043 /* Set the port number in the virtual_device to the faked port number */
1044 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
1045 top_dev
= top_dev
->parent
)
1046 /* Found device below root hub */;
1047 dev
->fake_port
= top_dev
->portnum
;
1048 dev
->real_port
= port_num
;
1049 xhci_dbg(xhci
, "Set root hub portnum to %d\n", port_num
);
1050 xhci_dbg(xhci
, "Set fake root hub portnum to %d\n", dev
->fake_port
);
1052 /* Find the right bandwidth table that this device will be a part of.
1053 * If this is a full speed device attached directly to a root port (or a
1054 * decendent of one), it counts as a primary bandwidth domain, not a
1055 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1056 * will never be created for the HS root hub.
1058 if (!udev
->tt
|| !udev
->tt
->hub
->parent
) {
1059 dev
->bw_table
= &xhci
->rh_bw
[port_num
- 1].bw_table
;
1061 struct xhci_root_port_bw_info
*rh_bw
;
1062 struct xhci_tt_bw_info
*tt_bw
;
1064 rh_bw
= &xhci
->rh_bw
[port_num
- 1];
1065 /* Find the right TT. */
1066 list_for_each_entry(tt_bw
, &rh_bw
->tts
, tt_list
) {
1067 if (tt_bw
->slot_id
!= udev
->tt
->hub
->slot_id
)
1070 if (!dev
->udev
->tt
->multi
||
1072 tt_bw
->ttport
== dev
->udev
->ttport
)) {
1073 dev
->bw_table
= &tt_bw
->bw_table
;
1074 dev
->tt_info
= tt_bw
;
1079 xhci_warn(xhci
, "WARN: Didn't find a matching TT\n");
1082 /* Is this a LS/FS device under an external HS hub? */
1083 if (udev
->tt
&& udev
->tt
->hub
->parent
) {
1084 slot_ctx
->tt_info
= cpu_to_le32(udev
->tt
->hub
->slot_id
|
1085 (udev
->ttport
<< 8));
1086 if (udev
->tt
->multi
)
1087 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
1089 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
1090 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
1092 /* Step 4 - ring already allocated */
1094 ep0_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(CTRL_EP
));
1096 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1097 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1100 ep0_ctx
->deq
= cpu_to_le64(dev
->eps
[0].ring
->first_seg
->dma
|
1101 dev
->eps
[0].ring
->cycle_state
);
1103 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1109 * Convert interval expressed as 2^(bInterval - 1) == interval into
1110 * straight exponent value 2^n == interval.
1113 static unsigned int xhci_parse_exponent_interval(struct usb_device
*udev
,
1114 struct usb_host_endpoint
*ep
)
1116 unsigned int interval
;
1118 interval
= clamp_val(ep
->desc
.bInterval
, 1, 16) - 1;
1119 if (interval
!= ep
->desc
.bInterval
- 1)
1120 dev_warn(&udev
->dev
,
1121 "ep %#x - rounding interval to %d %sframes\n",
1122 ep
->desc
.bEndpointAddress
,
1124 udev
->speed
== USB_SPEED_FULL
? "" : "micro");
1126 if (udev
->speed
== USB_SPEED_FULL
) {
1128 * Full speed isoc endpoints specify interval in frames,
1129 * not microframes. We are using microframes everywhere,
1130 * so adjust accordingly.
1132 interval
+= 3; /* 1 frame = 2^3 uframes */
1139 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1140 * microframes, rounded down to nearest power of 2.
1142 static unsigned int xhci_microframes_to_exponent(struct usb_device
*udev
,
1143 struct usb_host_endpoint
*ep
, unsigned int desc_interval
,
1144 unsigned int min_exponent
, unsigned int max_exponent
)
1146 unsigned int interval
;
1148 interval
= fls(desc_interval
) - 1;
1149 interval
= clamp_val(interval
, min_exponent
, max_exponent
);
1150 if ((1 << interval
) != desc_interval
)
1151 dev_warn(&udev
->dev
,
1152 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1153 ep
->desc
.bEndpointAddress
,
1160 static unsigned int xhci_parse_microframe_interval(struct usb_device
*udev
,
1161 struct usb_host_endpoint
*ep
)
1163 if (ep
->desc
.bInterval
== 0)
1165 return xhci_microframes_to_exponent(udev
, ep
,
1166 ep
->desc
.bInterval
, 0, 15);
1170 static unsigned int xhci_parse_frame_interval(struct usb_device
*udev
,
1171 struct usb_host_endpoint
*ep
)
1173 return xhci_microframes_to_exponent(udev
, ep
,
1174 ep
->desc
.bInterval
* 8, 3, 10);
1177 /* Return the polling or NAK interval.
1179 * The polling interval is expressed in "microframes". If xHCI's Interval field
1180 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1182 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1185 static unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
1186 struct usb_host_endpoint
*ep
)
1188 unsigned int interval
= 0;
1190 switch (udev
->speed
) {
1191 case USB_SPEED_HIGH
:
1193 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1194 usb_endpoint_xfer_bulk(&ep
->desc
)) {
1195 interval
= xhci_parse_microframe_interval(udev
, ep
);
1198 /* Fall through - SS and HS isoc/int have same decoding */
1200 case USB_SPEED_SUPER
:
1201 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1202 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1203 interval
= xhci_parse_exponent_interval(udev
, ep
);
1207 case USB_SPEED_FULL
:
1208 if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1209 interval
= xhci_parse_exponent_interval(udev
, ep
);
1213 * Fall through for interrupt endpoint interval decoding
1214 * since it uses the same rules as low speed interrupt
1219 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1220 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1222 interval
= xhci_parse_frame_interval(udev
, ep
);
1229 return EP_INTERVAL(interval
);
1232 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1233 * High speed endpoint descriptors can define "the number of additional
1234 * transaction opportunities per microframe", but that goes in the Max Burst
1235 * endpoint context field.
1237 static u32
xhci_get_endpoint_mult(struct usb_device
*udev
,
1238 struct usb_host_endpoint
*ep
)
1240 if (udev
->speed
!= USB_SPEED_SUPER
||
1241 !usb_endpoint_xfer_isoc(&ep
->desc
))
1243 return ep
->ss_ep_comp
.bmAttributes
;
1246 static u32
xhci_get_endpoint_type(struct usb_device
*udev
,
1247 struct usb_host_endpoint
*ep
)
1252 in
= usb_endpoint_dir_in(&ep
->desc
);
1253 if (usb_endpoint_xfer_control(&ep
->desc
)) {
1254 type
= EP_TYPE(CTRL_EP
);
1255 } else if (usb_endpoint_xfer_bulk(&ep
->desc
)) {
1257 type
= EP_TYPE(BULK_IN_EP
);
1259 type
= EP_TYPE(BULK_OUT_EP
);
1260 } else if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1262 type
= EP_TYPE(ISOC_IN_EP
);
1264 type
= EP_TYPE(ISOC_OUT_EP
);
1265 } else if (usb_endpoint_xfer_int(&ep
->desc
)) {
1267 type
= EP_TYPE(INT_IN_EP
);
1269 type
= EP_TYPE(INT_OUT_EP
);
1276 /* Return the maximum endpoint service interval time (ESIT) payload.
1277 * Basically, this is the maxpacket size, multiplied by the burst size
1280 static u32
xhci_get_max_esit_payload(struct xhci_hcd
*xhci
,
1281 struct usb_device
*udev
,
1282 struct usb_host_endpoint
*ep
)
1287 /* Only applies for interrupt or isochronous endpoints */
1288 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1289 usb_endpoint_xfer_bulk(&ep
->desc
))
1292 if (udev
->speed
== USB_SPEED_SUPER
)
1293 return le16_to_cpu(ep
->ss_ep_comp
.wBytesPerInterval
);
1295 max_packet
= GET_MAX_PACKET(usb_endpoint_maxp(&ep
->desc
));
1296 max_burst
= (usb_endpoint_maxp(&ep
->desc
) & 0x1800) >> 11;
1297 /* A 0 in max burst means 1 transfer per ESIT */
1298 return max_packet
* (max_burst
+ 1);
1301 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1302 * Drivers will have to call usb_alloc_streams() to do that.
1304 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
1305 struct xhci_virt_device
*virt_dev
,
1306 struct usb_device
*udev
,
1307 struct usb_host_endpoint
*ep
,
1310 unsigned int ep_index
;
1311 struct xhci_ep_ctx
*ep_ctx
;
1312 struct xhci_ring
*ep_ring
;
1313 unsigned int max_packet
;
1314 unsigned int max_burst
;
1315 enum xhci_ring_type type
;
1316 u32 max_esit_payload
;
1319 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1320 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1322 endpoint_type
= xhci_get_endpoint_type(udev
, ep
);
1325 ep_ctx
->ep_info2
= cpu_to_le32(endpoint_type
);
1327 type
= usb_endpoint_type(&ep
->desc
);
1328 /* Set up the endpoint ring */
1329 virt_dev
->eps
[ep_index
].new_ring
=
1330 xhci_ring_alloc(xhci
, 2, 1, type
, mem_flags
);
1331 if (!virt_dev
->eps
[ep_index
].new_ring
) {
1332 /* Attempt to use the ring cache */
1333 if (virt_dev
->num_rings_cached
== 0)
1335 virt_dev
->eps
[ep_index
].new_ring
=
1336 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
];
1337 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
] = NULL
;
1338 virt_dev
->num_rings_cached
--;
1339 xhci_reinit_cached_ring(xhci
, virt_dev
->eps
[ep_index
].new_ring
,
1342 virt_dev
->eps
[ep_index
].skip
= false;
1343 ep_ring
= virt_dev
->eps
[ep_index
].new_ring
;
1344 ep_ctx
->deq
= cpu_to_le64(ep_ring
->first_seg
->dma
| ep_ring
->cycle_state
);
1346 ep_ctx
->ep_info
= cpu_to_le32(xhci_get_endpoint_interval(udev
, ep
)
1347 | EP_MULT(xhci_get_endpoint_mult(udev
, ep
)));
1349 /* FIXME dig Mult and streams info out of ep companion desc */
1351 /* Allow 3 retries for everything but isoc;
1352 * CErr shall be set to 0 for Isoch endpoints.
1354 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
1355 ep_ctx
->ep_info2
|= cpu_to_le32(ERROR_COUNT(3));
1357 ep_ctx
->ep_info2
|= cpu_to_le32(ERROR_COUNT(0));
1359 /* Set the max packet size and max burst */
1360 max_packet
= GET_MAX_PACKET(usb_endpoint_maxp(&ep
->desc
));
1362 switch (udev
->speed
) {
1363 case USB_SPEED_SUPER
:
1364 /* dig out max burst from ep companion desc */
1365 max_burst
= ep
->ss_ep_comp
.bMaxBurst
;
1367 case USB_SPEED_HIGH
:
1368 /* Some devices get this wrong */
1369 if (usb_endpoint_xfer_bulk(&ep
->desc
))
1371 /* bits 11:12 specify the number of additional transaction
1372 * opportunities per microframe (USB 2.0, section 9.6.6)
1374 if (usb_endpoint_xfer_isoc(&ep
->desc
) ||
1375 usb_endpoint_xfer_int(&ep
->desc
)) {
1376 max_burst
= (usb_endpoint_maxp(&ep
->desc
)
1380 case USB_SPEED_FULL
:
1386 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(max_packet
) |
1387 MAX_BURST(max_burst
));
1388 max_esit_payload
= xhci_get_max_esit_payload(xhci
, udev
, ep
);
1389 ep_ctx
->tx_info
= cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload
));
1392 * XXX no idea how to calculate the average TRB buffer length for bulk
1393 * endpoints, as the driver gives us no clue how big each scatter gather
1394 * list entry (or buffer) is going to be.
1396 * For isochronous and interrupt endpoints, we set it to the max
1397 * available, until we have new API in the USB core to allow drivers to
1398 * declare how much bandwidth they actually need.
1400 * Normally, it would be calculated by taking the total of the buffer
1401 * lengths in the TD and then dividing by the number of TRBs in a TD,
1402 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
1403 * use Event Data TRBs, and we don't chain in a link TRB on short
1404 * transfers, we're basically dividing by 1.
1406 * xHCI 1.0 specification indicates that the Average TRB Length should
1407 * be set to 8 for control endpoints.
1409 if (usb_endpoint_xfer_control(&ep
->desc
) && xhci
->hci_version
== 0x100)
1410 ep_ctx
->tx_info
|= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1413 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload
));
1415 /* FIXME Debug endpoint context */
1419 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
1420 struct xhci_virt_device
*virt_dev
,
1421 struct usb_host_endpoint
*ep
)
1423 unsigned int ep_index
;
1424 struct xhci_ep_ctx
*ep_ctx
;
1426 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1427 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1429 ep_ctx
->ep_info
= 0;
1430 ep_ctx
->ep_info2
= 0;
1432 ep_ctx
->tx_info
= 0;
1433 /* Don't free the endpoint ring until the set interface or configuration
1438 void xhci_clear_endpoint_bw_info(struct xhci_bw_info
*bw_info
)
1440 bw_info
->ep_interval
= 0;
1442 bw_info
->num_packets
= 0;
1443 bw_info
->max_packet_size
= 0;
1445 bw_info
->max_esit_payload
= 0;
1448 void xhci_update_bw_info(struct xhci_hcd
*xhci
,
1449 struct xhci_container_ctx
*in_ctx
,
1450 struct xhci_input_control_ctx
*ctrl_ctx
,
1451 struct xhci_virt_device
*virt_dev
)
1453 struct xhci_bw_info
*bw_info
;
1454 struct xhci_ep_ctx
*ep_ctx
;
1455 unsigned int ep_type
;
1458 for (i
= 1; i
< 31; ++i
) {
1459 bw_info
= &virt_dev
->eps
[i
].bw_info
;
1461 /* We can't tell what endpoint type is being dropped, but
1462 * unconditionally clearing the bandwidth info for non-periodic
1463 * endpoints should be harmless because the info will never be
1464 * set in the first place.
1466 if (!EP_IS_ADDED(ctrl_ctx
, i
) && EP_IS_DROPPED(ctrl_ctx
, i
)) {
1467 /* Dropped endpoint */
1468 xhci_clear_endpoint_bw_info(bw_info
);
1472 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
1473 ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, i
);
1474 ep_type
= CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx
->ep_info2
));
1476 /* Ignore non-periodic endpoints */
1477 if (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
1478 ep_type
!= ISOC_IN_EP
&&
1479 ep_type
!= INT_IN_EP
)
1482 /* Added or changed endpoint */
1483 bw_info
->ep_interval
= CTX_TO_EP_INTERVAL(
1484 le32_to_cpu(ep_ctx
->ep_info
));
1485 /* Number of packets and mult are zero-based in the
1486 * input context, but we want one-based for the
1489 bw_info
->mult
= CTX_TO_EP_MULT(
1490 le32_to_cpu(ep_ctx
->ep_info
)) + 1;
1491 bw_info
->num_packets
= CTX_TO_MAX_BURST(
1492 le32_to_cpu(ep_ctx
->ep_info2
)) + 1;
1493 bw_info
->max_packet_size
= MAX_PACKET_DECODED(
1494 le32_to_cpu(ep_ctx
->ep_info2
));
1495 bw_info
->type
= ep_type
;
1496 bw_info
->max_esit_payload
= CTX_TO_MAX_ESIT_PAYLOAD(
1497 le32_to_cpu(ep_ctx
->tx_info
));
1502 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1503 * Useful when you want to change one particular aspect of the endpoint and then
1504 * issue a configure endpoint command.
1506 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
1507 struct xhci_container_ctx
*in_ctx
,
1508 struct xhci_container_ctx
*out_ctx
,
1509 unsigned int ep_index
)
1511 struct xhci_ep_ctx
*out_ep_ctx
;
1512 struct xhci_ep_ctx
*in_ep_ctx
;
1514 out_ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1515 in_ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
1517 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
1518 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
1519 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
1520 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
1523 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1524 * Useful when you want to change one particular aspect of the endpoint and then
1525 * issue a configure endpoint command. Only the context entries field matters,
1526 * but we'll copy the whole thing anyway.
1528 void xhci_slot_copy(struct xhci_hcd
*xhci
,
1529 struct xhci_container_ctx
*in_ctx
,
1530 struct xhci_container_ctx
*out_ctx
)
1532 struct xhci_slot_ctx
*in_slot_ctx
;
1533 struct xhci_slot_ctx
*out_slot_ctx
;
1535 in_slot_ctx
= xhci_get_slot_ctx(xhci
, in_ctx
);
1536 out_slot_ctx
= xhci_get_slot_ctx(xhci
, out_ctx
);
1538 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
1539 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
1540 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
1541 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
1544 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1545 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
1548 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1549 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1551 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1552 "Allocating %d scratchpad buffers", num_sp
);
1557 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
1558 if (!xhci
->scratchpad
)
1561 xhci
->scratchpad
->sp_array
= dma_alloc_coherent(dev
,
1562 num_sp
* sizeof(u64
),
1563 &xhci
->scratchpad
->sp_dma
, flags
);
1564 if (!xhci
->scratchpad
->sp_array
)
1567 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
1568 if (!xhci
->scratchpad
->sp_buffers
)
1571 xhci
->scratchpad
->sp_dma_buffers
=
1572 kzalloc(sizeof(dma_addr_t
) * num_sp
, flags
);
1574 if (!xhci
->scratchpad
->sp_dma_buffers
)
1577 xhci
->dcbaa
->dev_context_ptrs
[0] = cpu_to_le64(xhci
->scratchpad
->sp_dma
);
1578 for (i
= 0; i
< num_sp
; i
++) {
1580 void *buf
= dma_alloc_coherent(dev
, xhci
->page_size
, &dma
,
1585 xhci
->scratchpad
->sp_array
[i
] = dma
;
1586 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
1587 xhci
->scratchpad
->sp_dma_buffers
[i
] = dma
;
1593 for (i
= i
- 1; i
>= 0; i
--) {
1594 dma_free_coherent(dev
, xhci
->page_size
,
1595 xhci
->scratchpad
->sp_buffers
[i
],
1596 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1598 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1601 kfree(xhci
->scratchpad
->sp_buffers
);
1604 dma_free_coherent(dev
, num_sp
* sizeof(u64
),
1605 xhci
->scratchpad
->sp_array
,
1606 xhci
->scratchpad
->sp_dma
);
1609 kfree(xhci
->scratchpad
);
1610 xhci
->scratchpad
= NULL
;
1616 static void scratchpad_free(struct xhci_hcd
*xhci
)
1620 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
1622 if (!xhci
->scratchpad
)
1625 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1627 for (i
= 0; i
< num_sp
; i
++) {
1628 dma_free_coherent(&pdev
->dev
, xhci
->page_size
,
1629 xhci
->scratchpad
->sp_buffers
[i
],
1630 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1632 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1633 kfree(xhci
->scratchpad
->sp_buffers
);
1634 dma_free_coherent(&pdev
->dev
, num_sp
* sizeof(u64
),
1635 xhci
->scratchpad
->sp_array
,
1636 xhci
->scratchpad
->sp_dma
);
1637 kfree(xhci
->scratchpad
);
1638 xhci
->scratchpad
= NULL
;
1641 struct xhci_command
*xhci_alloc_command(struct xhci_hcd
*xhci
,
1642 bool allocate_in_ctx
, bool allocate_completion
,
1645 struct xhci_command
*command
;
1647 command
= kzalloc(sizeof(*command
), mem_flags
);
1651 if (allocate_in_ctx
) {
1653 xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
,
1655 if (!command
->in_ctx
) {
1661 if (allocate_completion
) {
1662 command
->completion
=
1663 kzalloc(sizeof(struct completion
), mem_flags
);
1664 if (!command
->completion
) {
1665 xhci_free_container_ctx(xhci
, command
->in_ctx
);
1669 init_completion(command
->completion
);
1672 command
->status
= 0;
1673 INIT_LIST_HEAD(&command
->cmd_list
);
1677 void xhci_urb_free_priv(struct xhci_hcd
*xhci
, struct urb_priv
*urb_priv
)
1680 kfree(urb_priv
->td
[0]);
1685 void xhci_free_command(struct xhci_hcd
*xhci
,
1686 struct xhci_command
*command
)
1688 xhci_free_container_ctx(xhci
,
1690 kfree(command
->completion
);
1694 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
1696 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
1697 struct xhci_cd
*cur_cd
, *next_cd
;
1699 int i
, j
, num_ports
;
1701 /* Free the Event Ring Segment Table and the actual Event Ring */
1702 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
1703 if (xhci
->erst
.entries
)
1704 dma_free_coherent(&pdev
->dev
, size
,
1705 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
1706 xhci
->erst
.entries
= NULL
;
1707 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed ERST");
1708 if (xhci
->event_ring
)
1709 xhci_ring_free(xhci
, xhci
->event_ring
);
1710 xhci
->event_ring
= NULL
;
1711 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed event ring");
1713 if (xhci
->lpm_command
)
1714 xhci_free_command(xhci
, xhci
->lpm_command
);
1715 xhci
->cmd_ring_reserved_trbs
= 0;
1717 xhci_ring_free(xhci
, xhci
->cmd_ring
);
1718 xhci
->cmd_ring
= NULL
;
1719 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed command ring");
1720 list_for_each_entry_safe(cur_cd
, next_cd
,
1721 &xhci
->cancel_cmd_list
, cancel_cmd_list
) {
1722 list_del(&cur_cd
->cancel_cmd_list
);
1726 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
1727 xhci_free_virt_device(xhci
, i
);
1729 if (xhci
->segment_pool
)
1730 dma_pool_destroy(xhci
->segment_pool
);
1731 xhci
->segment_pool
= NULL
;
1732 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed segment pool");
1734 if (xhci
->device_pool
)
1735 dma_pool_destroy(xhci
->device_pool
);
1736 xhci
->device_pool
= NULL
;
1737 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed device context pool");
1739 if (xhci
->small_streams_pool
)
1740 dma_pool_destroy(xhci
->small_streams_pool
);
1741 xhci
->small_streams_pool
= NULL
;
1742 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1743 "Freed small stream array pool");
1745 if (xhci
->medium_streams_pool
)
1746 dma_pool_destroy(xhci
->medium_streams_pool
);
1747 xhci
->medium_streams_pool
= NULL
;
1748 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1749 "Freed medium stream array pool");
1752 dma_free_coherent(&pdev
->dev
, sizeof(*xhci
->dcbaa
),
1753 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
1756 scratchpad_free(xhci
);
1761 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1762 for (i
= 0; i
< num_ports
; i
++) {
1763 struct xhci_interval_bw_table
*bwt
= &xhci
->rh_bw
[i
].bw_table
;
1764 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++) {
1765 struct list_head
*ep
= &bwt
->interval_bw
[j
].endpoints
;
1766 while (!list_empty(ep
))
1767 list_del_init(ep
->next
);
1771 for (i
= 0; i
< num_ports
; i
++) {
1772 struct xhci_tt_bw_info
*tt
, *n
;
1773 list_for_each_entry_safe(tt
, n
, &xhci
->rh_bw
[i
].tts
, tt_list
) {
1774 list_del(&tt
->tt_list
);
1780 xhci
->num_usb2_ports
= 0;
1781 xhci
->num_usb3_ports
= 0;
1782 xhci
->num_active_eps
= 0;
1783 kfree(xhci
->usb2_ports
);
1784 kfree(xhci
->usb3_ports
);
1785 kfree(xhci
->port_array
);
1787 kfree(xhci
->ext_caps
);
1789 xhci
->page_size
= 0;
1790 xhci
->page_shift
= 0;
1791 xhci
->bus_state
[0].bus_suspended
= 0;
1792 xhci
->bus_state
[1].bus_suspended
= 0;
1795 static int xhci_test_trb_in_td(struct xhci_hcd
*xhci
,
1796 struct xhci_segment
*input_seg
,
1797 union xhci_trb
*start_trb
,
1798 union xhci_trb
*end_trb
,
1799 dma_addr_t input_dma
,
1800 struct xhci_segment
*result_seg
,
1801 char *test_name
, int test_number
)
1803 unsigned long long start_dma
;
1804 unsigned long long end_dma
;
1805 struct xhci_segment
*seg
;
1807 start_dma
= xhci_trb_virt_to_dma(input_seg
, start_trb
);
1808 end_dma
= xhci_trb_virt_to_dma(input_seg
, end_trb
);
1810 seg
= trb_in_td(input_seg
, start_trb
, end_trb
, input_dma
);
1811 if (seg
!= result_seg
) {
1812 xhci_warn(xhci
, "WARN: %s TRB math test %d failed!\n",
1813 test_name
, test_number
);
1814 xhci_warn(xhci
, "Tested TRB math w/ seg %p and "
1815 "input DMA 0x%llx\n",
1817 (unsigned long long) input_dma
);
1818 xhci_warn(xhci
, "starting TRB %p (0x%llx DMA), "
1819 "ending TRB %p (0x%llx DMA)\n",
1820 start_trb
, start_dma
,
1822 xhci_warn(xhci
, "Expected seg %p, got seg %p\n",
1829 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1830 static int xhci_check_trb_in_td_math(struct xhci_hcd
*xhci
, gfp_t mem_flags
)
1833 dma_addr_t input_dma
;
1834 struct xhci_segment
*result_seg
;
1835 } simple_test_vector
[] = {
1836 /* A zeroed DMA field should fail */
1838 /* One TRB before the ring start should fail */
1839 { xhci
->event_ring
->first_seg
->dma
- 16, NULL
},
1840 /* One byte before the ring start should fail */
1841 { xhci
->event_ring
->first_seg
->dma
- 1, NULL
},
1842 /* Starting TRB should succeed */
1843 { xhci
->event_ring
->first_seg
->dma
, xhci
->event_ring
->first_seg
},
1844 /* Ending TRB should succeed */
1845 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16,
1846 xhci
->event_ring
->first_seg
},
1847 /* One byte after the ring end should fail */
1848 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16 + 1, NULL
},
1849 /* One TRB after the ring end should fail */
1850 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
)*16, NULL
},
1851 /* An address of all ones should fail */
1852 { (dma_addr_t
) (~0), NULL
},
1855 struct xhci_segment
*input_seg
;
1856 union xhci_trb
*start_trb
;
1857 union xhci_trb
*end_trb
;
1858 dma_addr_t input_dma
;
1859 struct xhci_segment
*result_seg
;
1860 } complex_test_vector
[] = {
1861 /* Test feeding a valid DMA address from a different ring */
1862 { .input_seg
= xhci
->event_ring
->first_seg
,
1863 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1864 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1865 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1868 /* Test feeding a valid end TRB from a different ring */
1869 { .input_seg
= xhci
->event_ring
->first_seg
,
1870 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1871 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1872 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1875 /* Test feeding a valid start and end TRB from a different ring */
1876 { .input_seg
= xhci
->event_ring
->first_seg
,
1877 .start_trb
= xhci
->cmd_ring
->first_seg
->trbs
,
1878 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1879 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1882 /* TRB in this ring, but after this TD */
1883 { .input_seg
= xhci
->event_ring
->first_seg
,
1884 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[0],
1885 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1886 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 4*16,
1889 /* TRB in this ring, but before this TD */
1890 { .input_seg
= xhci
->event_ring
->first_seg
,
1891 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1892 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[6],
1893 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1896 /* TRB in this ring, but after this wrapped TD */
1897 { .input_seg
= xhci
->event_ring
->first_seg
,
1898 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1899 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1900 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1903 /* TRB in this ring, but before this wrapped TD */
1904 { .input_seg
= xhci
->event_ring
->first_seg
,
1905 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1906 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1907 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 4)*16,
1910 /* TRB not in this ring, and we have a wrapped TD */
1911 { .input_seg
= xhci
->event_ring
->first_seg
,
1912 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1913 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1914 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
+ 2*16,
1919 unsigned int num_tests
;
1922 num_tests
= ARRAY_SIZE(simple_test_vector
);
1923 for (i
= 0; i
< num_tests
; i
++) {
1924 ret
= xhci_test_trb_in_td(xhci
,
1925 xhci
->event_ring
->first_seg
,
1926 xhci
->event_ring
->first_seg
->trbs
,
1927 &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1928 simple_test_vector
[i
].input_dma
,
1929 simple_test_vector
[i
].result_seg
,
1935 num_tests
= ARRAY_SIZE(complex_test_vector
);
1936 for (i
= 0; i
< num_tests
; i
++) {
1937 ret
= xhci_test_trb_in_td(xhci
,
1938 complex_test_vector
[i
].input_seg
,
1939 complex_test_vector
[i
].start_trb
,
1940 complex_test_vector
[i
].end_trb
,
1941 complex_test_vector
[i
].input_dma
,
1942 complex_test_vector
[i
].result_seg
,
1947 xhci_dbg(xhci
, "TRB math tests passed.\n");
1951 static void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
1956 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
1957 xhci
->event_ring
->dequeue
);
1958 if (deq
== 0 && !in_interrupt())
1959 xhci_warn(xhci
, "WARN something wrong with SW event ring "
1961 /* Update HC event ring dequeue pointer */
1962 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
1963 temp
&= ERST_PTR_MASK
;
1964 /* Don't clear the EHB bit (which is RW1C) because
1965 * there might be more events to service.
1968 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1969 "// Write event ring dequeue pointer, "
1970 "preserving EHB bit");
1971 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
1972 &xhci
->ir_set
->erst_dequeue
);
1975 static void xhci_add_in_port(struct xhci_hcd
*xhci
, unsigned int num_ports
,
1976 __le32 __iomem
*addr
, u8 major_revision
, int max_caps
)
1978 u32 temp
, port_offset
, port_count
;
1981 if (major_revision
> 0x03) {
1982 xhci_warn(xhci
, "Ignoring unknown port speed, "
1983 "Ext Cap %p, revision = 0x%x\n",
1984 addr
, major_revision
);
1985 /* Ignoring port protocol we can't understand. FIXME */
1989 /* Port offset and count in the third dword, see section 7.2 */
1990 temp
= xhci_readl(xhci
, addr
+ 2);
1991 port_offset
= XHCI_EXT_PORT_OFF(temp
);
1992 port_count
= XHCI_EXT_PORT_COUNT(temp
);
1993 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1994 "Ext Cap %p, port offset = %u, "
1995 "count = %u, revision = 0x%x",
1996 addr
, port_offset
, port_count
, major_revision
);
1997 /* Port count includes the current port offset */
1998 if (port_offset
== 0 || (port_offset
+ port_count
- 1) > num_ports
)
1999 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2002 /* cache usb2 port capabilities */
2003 if (major_revision
< 0x03 && xhci
->num_ext_caps
< max_caps
)
2004 xhci
->ext_caps
[xhci
->num_ext_caps
++] = temp
;
2006 /* Check the host's USB2 LPM capability */
2007 if ((xhci
->hci_version
== 0x96) && (major_revision
!= 0x03) &&
2008 (temp
& XHCI_L1C
)) {
2009 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2010 "xHCI 0.96: support USB2 software lpm");
2011 xhci
->sw_lpm_support
= 1;
2014 if ((xhci
->hci_version
>= 0x100) && (major_revision
!= 0x03)) {
2015 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2016 "xHCI 1.0: support USB2 software lpm");
2017 xhci
->sw_lpm_support
= 1;
2018 if (temp
& XHCI_HLC
) {
2019 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2020 "xHCI 1.0: support USB2 hardware lpm");
2021 xhci
->hw_lpm_support
= 1;
2026 for (i
= port_offset
; i
< (port_offset
+ port_count
); i
++) {
2027 /* Duplicate entry. Ignore the port if the revisions differ. */
2028 if (xhci
->port_array
[i
] != 0) {
2029 xhci_warn(xhci
, "Duplicate port entry, Ext Cap %p,"
2030 " port %u\n", addr
, i
);
2031 xhci_warn(xhci
, "Port was marked as USB %u, "
2032 "duplicated as USB %u\n",
2033 xhci
->port_array
[i
], major_revision
);
2034 /* Only adjust the roothub port counts if we haven't
2035 * found a similar duplicate.
2037 if (xhci
->port_array
[i
] != major_revision
&&
2038 xhci
->port_array
[i
] != DUPLICATE_ENTRY
) {
2039 if (xhci
->port_array
[i
] == 0x03)
2040 xhci
->num_usb3_ports
--;
2042 xhci
->num_usb2_ports
--;
2043 xhci
->port_array
[i
] = DUPLICATE_ENTRY
;
2045 /* FIXME: Should we disable the port? */
2048 xhci
->port_array
[i
] = major_revision
;
2049 if (major_revision
== 0x03)
2050 xhci
->num_usb3_ports
++;
2052 xhci
->num_usb2_ports
++;
2054 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2058 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2059 * specify what speeds each port is supposed to be. We can't count on the port
2060 * speed bits in the PORTSC register being correct until a device is connected,
2061 * but we need to set up the two fake roothubs with the correct number of USB
2062 * 3.0 and USB 2.0 ports at host controller initialization time.
2064 static int xhci_setup_port_arrays(struct xhci_hcd
*xhci
, gfp_t flags
)
2066 __le32 __iomem
*addr
, *tmp_addr
;
2067 u32 offset
, tmp_offset
;
2068 unsigned int num_ports
;
2069 int i
, j
, port_index
;
2072 addr
= &xhci
->cap_regs
->hcc_params
;
2073 offset
= XHCI_HCC_EXT_CAPS(xhci_readl(xhci
, addr
));
2075 xhci_err(xhci
, "No Extended Capability registers, "
2076 "unable to set up roothub.\n");
2080 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
2081 xhci
->port_array
= kzalloc(sizeof(*xhci
->port_array
)*num_ports
, flags
);
2082 if (!xhci
->port_array
)
2085 xhci
->rh_bw
= kzalloc(sizeof(*xhci
->rh_bw
)*num_ports
, flags
);
2088 for (i
= 0; i
< num_ports
; i
++) {
2089 struct xhci_interval_bw_table
*bw_table
;
2091 INIT_LIST_HEAD(&xhci
->rh_bw
[i
].tts
);
2092 bw_table
= &xhci
->rh_bw
[i
].bw_table
;
2093 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
2094 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
2098 * For whatever reason, the first capability offset is from the
2099 * capability register base, not from the HCCPARAMS register.
2100 * See section 5.3.6 for offset calculation.
2102 addr
= &xhci
->cap_regs
->hc_capbase
+ offset
;
2105 tmp_offset
= offset
;
2107 /* count extended protocol capability entries for later caching */
2110 cap_id
= xhci_readl(xhci
, tmp_addr
);
2111 if (XHCI_EXT_CAPS_ID(cap_id
) == XHCI_EXT_CAPS_PROTOCOL
)
2113 tmp_offset
= XHCI_EXT_CAPS_NEXT(cap_id
);
2114 tmp_addr
+= tmp_offset
;
2115 } while (tmp_offset
);
2117 xhci
->ext_caps
= kzalloc(sizeof(*xhci
->ext_caps
) * cap_count
, flags
);
2118 if (!xhci
->ext_caps
)
2124 cap_id
= xhci_readl(xhci
, addr
);
2125 if (XHCI_EXT_CAPS_ID(cap_id
) == XHCI_EXT_CAPS_PROTOCOL
)
2126 xhci_add_in_port(xhci
, num_ports
, addr
,
2127 (u8
) XHCI_EXT_PORT_MAJOR(cap_id
),
2129 offset
= XHCI_EXT_CAPS_NEXT(cap_id
);
2130 if (!offset
|| (xhci
->num_usb2_ports
+ xhci
->num_usb3_ports
)
2134 * Once you're into the Extended Capabilities, the offset is
2135 * always relative to the register holding the offset.
2140 if (xhci
->num_usb2_ports
== 0 && xhci
->num_usb3_ports
== 0) {
2141 xhci_warn(xhci
, "No ports on the roothubs?\n");
2144 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2145 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2146 xhci
->num_usb2_ports
, xhci
->num_usb3_ports
);
2148 /* Place limits on the number of roothub ports so that the hub
2149 * descriptors aren't longer than the USB core will allocate.
2151 if (xhci
->num_usb3_ports
> 15) {
2152 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2153 "Limiting USB 3.0 roothub ports to 15.");
2154 xhci
->num_usb3_ports
= 15;
2156 if (xhci
->num_usb2_ports
> USB_MAXCHILDREN
) {
2157 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2158 "Limiting USB 2.0 roothub ports to %u.",
2160 xhci
->num_usb2_ports
= USB_MAXCHILDREN
;
2164 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2165 * Not sure how the USB core will handle a hub with no ports...
2167 if (xhci
->num_usb2_ports
) {
2168 xhci
->usb2_ports
= kmalloc(sizeof(*xhci
->usb2_ports
)*
2169 xhci
->num_usb2_ports
, flags
);
2170 if (!xhci
->usb2_ports
)
2174 for (i
= 0; i
< num_ports
; i
++) {
2175 if (xhci
->port_array
[i
] == 0x03 ||
2176 xhci
->port_array
[i
] == 0 ||
2177 xhci
->port_array
[i
] == DUPLICATE_ENTRY
)
2180 xhci
->usb2_ports
[port_index
] =
2181 &xhci
->op_regs
->port_status_base
+
2183 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2184 "USB 2.0 port at index %u, "
2186 xhci
->usb2_ports
[port_index
]);
2188 if (port_index
== xhci
->num_usb2_ports
)
2192 if (xhci
->num_usb3_ports
) {
2193 xhci
->usb3_ports
= kmalloc(sizeof(*xhci
->usb3_ports
)*
2194 xhci
->num_usb3_ports
, flags
);
2195 if (!xhci
->usb3_ports
)
2199 for (i
= 0; i
< num_ports
; i
++)
2200 if (xhci
->port_array
[i
] == 0x03) {
2201 xhci
->usb3_ports
[port_index
] =
2202 &xhci
->op_regs
->port_status_base
+
2204 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2205 "USB 3.0 port at index %u, "
2207 xhci
->usb3_ports
[port_index
]);
2209 if (port_index
== xhci
->num_usb3_ports
)
2216 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
2219 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
2220 unsigned int val
, val2
;
2222 struct xhci_segment
*seg
;
2223 u32 page_size
, temp
;
2226 INIT_LIST_HEAD(&xhci
->cancel_cmd_list
);
2228 page_size
= xhci_readl(xhci
, &xhci
->op_regs
->page_size
);
2229 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2230 "Supported page size register = 0x%x", page_size
);
2231 for (i
= 0; i
< 16; i
++) {
2232 if ((0x1 & page_size
) != 0)
2234 page_size
= page_size
>> 1;
2237 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2238 "Supported page size of %iK", (1 << (i
+12)) / 1024);
2240 xhci_warn(xhci
, "WARN: no supported page size\n");
2241 /* Use 4K pages, since that's common and the minimum the HC supports */
2242 xhci
->page_shift
= 12;
2243 xhci
->page_size
= 1 << xhci
->page_shift
;
2244 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2245 "HCD page size set to %iK", xhci
->page_size
/ 1024);
2248 * Program the Number of Device Slots Enabled field in the CONFIG
2249 * register with the max value of slots the HC can handle.
2251 val
= HCS_MAX_SLOTS(xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params1
));
2252 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2253 "// xHC can handle at most %d device slots.", val
);
2254 val2
= xhci_readl(xhci
, &xhci
->op_regs
->config_reg
);
2255 val
|= (val2
& ~HCS_SLOTS_MASK
);
2256 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2257 "// Setting Max device slots reg = 0x%x.", val
);
2258 xhci_writel(xhci
, val
, &xhci
->op_regs
->config_reg
);
2261 * Section 5.4.8 - doorbell array must be
2262 * "physically contiguous and 64-byte (cache line) aligned".
2264 xhci
->dcbaa
= dma_alloc_coherent(dev
, sizeof(*xhci
->dcbaa
), &dma
,
2268 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
2269 xhci
->dcbaa
->dma
= dma
;
2270 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2271 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2272 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
2273 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
2276 * Initialize the ring segment pool. The ring must be a contiguous
2277 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2278 * however, the command ring segment needs 64-byte aligned segments,
2279 * so we pick the greater alignment need.
2281 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
2282 TRB_SEGMENT_SIZE
, 64, xhci
->page_size
);
2284 /* See Table 46 and Note on Figure 55 */
2285 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
2286 2112, 64, xhci
->page_size
);
2287 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
2290 /* Linear stream context arrays don't have any boundary restrictions,
2291 * and only need to be 16-byte aligned.
2293 xhci
->small_streams_pool
=
2294 dma_pool_create("xHCI 256 byte stream ctx arrays",
2295 dev
, SMALL_STREAM_ARRAY_SIZE
, 16, 0);
2296 xhci
->medium_streams_pool
=
2297 dma_pool_create("xHCI 1KB stream ctx arrays",
2298 dev
, MEDIUM_STREAM_ARRAY_SIZE
, 16, 0);
2299 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2300 * will be allocated with dma_alloc_coherent()
2303 if (!xhci
->small_streams_pool
|| !xhci
->medium_streams_pool
)
2306 /* Set up the command ring to have one segments for now. */
2307 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, 1, TYPE_COMMAND
, flags
);
2308 if (!xhci
->cmd_ring
)
2310 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2311 "Allocated command ring at %p", xhci
->cmd_ring
);
2312 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "First segment DMA is 0x%llx",
2313 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
2315 /* Set the address in the Command Ring Control register */
2316 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
2317 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
2318 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
2319 xhci
->cmd_ring
->cycle_state
;
2320 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2321 "// Setting command ring address to 0x%x", val
);
2322 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
2323 xhci_dbg_cmd_ptrs(xhci
);
2325 xhci
->lpm_command
= xhci_alloc_command(xhci
, true, true, flags
);
2326 if (!xhci
->lpm_command
)
2329 /* Reserve one command ring TRB for disabling LPM.
2330 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2331 * disabling LPM, we only need to reserve one TRB for all devices.
2333 xhci
->cmd_ring_reserved_trbs
++;
2335 val
= xhci_readl(xhci
, &xhci
->cap_regs
->db_off
);
2337 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2338 "// Doorbell array is located at offset 0x%x"
2339 " from cap regs base addr", val
);
2340 xhci
->dba
= (void __iomem
*) xhci
->cap_regs
+ val
;
2341 xhci_dbg_regs(xhci
);
2342 xhci_print_run_regs(xhci
);
2343 /* Set ir_set to interrupt register set 0 */
2344 xhci
->ir_set
= &xhci
->run_regs
->ir_set
[0];
2347 * Event ring setup: Allocate a normal ring, but also setup
2348 * the event ring segment table (ERST). Section 4.9.3.
2350 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Allocating event ring");
2351 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, 1, TYPE_EVENT
,
2353 if (!xhci
->event_ring
)
2355 if (xhci_check_trb_in_td_math(xhci
, flags
) < 0)
2358 xhci
->erst
.entries
= dma_alloc_coherent(dev
,
2359 sizeof(struct xhci_erst_entry
) * ERST_NUM_SEGS
, &dma
,
2361 if (!xhci
->erst
.entries
)
2363 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2364 "// Allocated event ring segment table at 0x%llx",
2365 (unsigned long long)dma
);
2367 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
2368 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
2369 xhci
->erst
.erst_dma_addr
= dma
;
2370 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2371 "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx",
2372 xhci
->erst
.num_entries
,
2374 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2376 /* set ring base address and size for each segment table entry */
2377 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
2378 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
2379 entry
->seg_addr
= cpu_to_le64(seg
->dma
);
2380 entry
->seg_size
= cpu_to_le32(TRBS_PER_SEGMENT
);
2385 /* set ERST count with the number of entries in the segment table */
2386 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_size
);
2387 val
&= ERST_SIZE_MASK
;
2388 val
|= ERST_NUM_SEGS
;
2389 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2390 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2392 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_size
);
2394 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2395 "// Set ERST entries to point to event ring.");
2396 /* set the segment table base address */
2397 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2398 "// Set ERST base address for ir_set 0 = 0x%llx",
2399 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2400 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
2401 val_64
&= ERST_PTR_MASK
;
2402 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
2403 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
2405 /* Set the event ring dequeue address */
2406 xhci_set_hc_event_deq(xhci
);
2407 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2408 "Wrote ERST address to ir_set 0.");
2409 xhci_print_ir_set(xhci
, 0);
2412 * XXX: Might need to set the Interrupter Moderation Register to
2413 * something other than the default (~1ms minimum between interrupts).
2414 * See section 5.5.1.2.
2416 init_completion(&xhci
->addr_dev
);
2417 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
2418 xhci
->devs
[i
] = NULL
;
2419 for (i
= 0; i
< USB_MAXCHILDREN
; ++i
) {
2420 xhci
->bus_state
[0].resume_done
[i
] = 0;
2421 xhci
->bus_state
[1].resume_done
[i
] = 0;
2422 /* Only the USB 2.0 completions will ever be used. */
2423 init_completion(&xhci
->bus_state
[1].rexit_done
[i
]);
2426 if (scratchpad_alloc(xhci
, flags
))
2428 if (xhci_setup_port_arrays(xhci
, flags
))
2431 /* Enable USB 3.0 device notifications for function remote wake, which
2432 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2433 * U3 (device suspend).
2435 temp
= xhci_readl(xhci
, &xhci
->op_regs
->dev_notification
);
2436 temp
&= ~DEV_NOTE_MASK
;
2437 temp
|= DEV_NOTE_FWAKE
;
2438 xhci_writel(xhci
, temp
, &xhci
->op_regs
->dev_notification
);
2443 xhci_warn(xhci
, "Couldn't initialize memory\n");
2446 xhci_mem_cleanup(xhci
);