2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
74 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
80 unsigned long segment_offset
;
82 if (!seg
|| !trb
|| trb
< seg
->trbs
)
85 segment_offset
= trb
- seg
->trbs
;
86 if (segment_offset
>= TRBS_PER_SEGMENT
)
88 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
91 /* Does this link TRB point to the first segment in a ring,
92 * or was the previous TRB the last TRB on the last segment in the ERST?
94 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
95 struct xhci_segment
*seg
, union xhci_trb
*trb
)
97 if (ring
== xhci
->event_ring
)
98 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
99 (seg
->next
== xhci
->event_ring
->first_seg
);
101 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
104 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
105 * segment? I.e. would the updated event TRB pointer step off the end of the
108 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
109 struct xhci_segment
*seg
, union xhci_trb
*trb
)
111 if (ring
== xhci
->event_ring
)
112 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
114 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
117 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
119 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
120 return TRB_TYPE_LINK_LE32(link
->control
);
123 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
124 * TRB is in a new segment. This does not skip over link TRBs, and it does not
125 * effect the ring dequeue or enqueue pointers.
127 static void next_trb(struct xhci_hcd
*xhci
,
128 struct xhci_ring
*ring
,
129 struct xhci_segment
**seg
,
130 union xhci_trb
**trb
)
132 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
134 *trb
= ((*seg
)->trbs
);
141 * See Cycle bit rules. SW is the consumer for the event ring only.
142 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
144 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
149 * If this is not event ring, and the dequeue pointer
150 * is not on a link TRB, there is one more usable TRB
152 if (ring
->type
!= TYPE_EVENT
&&
153 !last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
))
154 ring
->num_trbs_free
++;
158 * Update the dequeue pointer further if that was a link TRB or
159 * we're at the end of an event ring segment (which doesn't have
162 if (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
)) {
163 if (ring
->type
== TYPE_EVENT
&&
164 last_trb_on_last_seg(xhci
, ring
,
165 ring
->deq_seg
, ring
->dequeue
)) {
166 ring
->cycle_state
^= 1;
168 ring
->deq_seg
= ring
->deq_seg
->next
;
169 ring
->dequeue
= ring
->deq_seg
->trbs
;
173 } while (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
));
177 * See Cycle bit rules. SW is the consumer for the event ring only.
178 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
180 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
181 * chain bit is set), then set the chain bit in all the following link TRBs.
182 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
183 * have their chain bit cleared (so that each Link TRB is a separate TD).
185 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
186 * set, but other sections talk about dealing with the chain bit set. This was
187 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
188 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
190 * @more_trbs_coming: Will you enqueue more TRBs before calling
191 * prepare_transfer()?
193 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
194 bool more_trbs_coming
)
197 union xhci_trb
*next
;
199 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
200 /* If this is not event ring, there is one less usable TRB */
201 if (ring
->type
!= TYPE_EVENT
&&
202 !last_trb(xhci
, ring
, ring
->enq_seg
, ring
->enqueue
))
203 ring
->num_trbs_free
--;
204 next
= ++(ring
->enqueue
);
207 /* Update the dequeue pointer further if that was a link TRB or we're at
208 * the end of an event ring segment (which doesn't have link TRBS)
210 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
211 if (ring
->type
!= TYPE_EVENT
) {
213 * If the caller doesn't plan on enqueueing more
214 * TDs before ringing the doorbell, then we
215 * don't want to give the link TRB to the
216 * hardware just yet. We'll give the link TRB
217 * back in prepare_ring() just before we enqueue
218 * the TD at the top of the ring.
220 if (!chain
&& !more_trbs_coming
)
223 /* If we're not dealing with 0.95 hardware or
224 * isoc rings on AMD 0.96 host,
225 * carry over the chain bit of the previous TRB
226 * (which may mean the chain bit is cleared).
228 if (!(ring
->type
== TYPE_ISOC
&&
229 (xhci
->quirks
& XHCI_AMD_0x96_HOST
))
230 && !xhci_link_trb_quirk(xhci
)) {
231 next
->link
.control
&=
232 cpu_to_le32(~TRB_CHAIN
);
233 next
->link
.control
|=
236 /* Give this link TRB to the hardware */
238 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
240 /* Toggle the cycle bit after the last ring segment. */
241 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
242 ring
->cycle_state
^= 1;
245 ring
->enq_seg
= ring
->enq_seg
->next
;
246 ring
->enqueue
= ring
->enq_seg
->trbs
;
247 next
= ring
->enqueue
;
252 * Check to see if there's room to enqueue num_trbs on the ring and make sure
253 * enqueue pointer will not advance into dequeue segment. See rules above.
255 static inline int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
256 unsigned int num_trbs
)
258 int num_trbs_in_deq_seg
;
260 if (ring
->num_trbs_free
< num_trbs
)
263 if (ring
->type
!= TYPE_COMMAND
&& ring
->type
!= TYPE_EVENT
) {
264 num_trbs_in_deq_seg
= ring
->dequeue
- ring
->deq_seg
->trbs
;
265 if (ring
->num_trbs_free
< num_trbs
+ num_trbs_in_deq_seg
)
272 /* Ring the host controller doorbell after placing a command on the ring */
273 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
275 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
))
278 xhci_dbg(xhci
, "// Ding dong!\n");
279 writel(DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
280 /* Flush PCI posted writes */
281 readl(&xhci
->dba
->doorbell
[0]);
284 static int xhci_abort_cmd_ring(struct xhci_hcd
*xhci
)
289 xhci_dbg(xhci
, "Abort command ring\n");
291 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
292 xhci
->cmd_ring_state
= CMD_RING_STATE_ABORTED
;
293 xhci_write_64(xhci
, temp_64
| CMD_RING_ABORT
,
294 &xhci
->op_regs
->cmd_ring
);
296 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
297 * time the completion od all xHCI commands, including
298 * the Command Abort operation. If software doesn't see
299 * CRR negated in a timely manner (e.g. longer than 5
300 * seconds), then it should assume that the there are
301 * larger problems with the xHC and assert HCRST.
303 ret
= xhci_handshake(&xhci
->op_regs
->cmd_ring
,
304 CMD_RING_RUNNING
, 0, 5 * 1000 * 1000);
306 /* we are about to kill xhci, give it one more chance */
307 xhci_write_64(xhci
, temp_64
| CMD_RING_ABORT
,
308 &xhci
->op_regs
->cmd_ring
);
310 ret
= xhci_handshake(&xhci
->op_regs
->cmd_ring
,
311 CMD_RING_RUNNING
, 0, 3 * 1000 * 1000);
315 xhci_err(xhci
, "Stopped the command ring failed, "
316 "maybe the host is dead\n");
317 xhci
->xhc_state
|= XHCI_STATE_DYING
;
326 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
327 unsigned int slot_id
,
328 unsigned int ep_index
,
329 unsigned int stream_id
)
331 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
332 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
333 unsigned int ep_state
= ep
->ep_state
;
335 /* Don't ring the doorbell for this endpoint if there are pending
336 * cancellations because we don't want to interrupt processing.
337 * We don't want to restart any stream rings if there's a set dequeue
338 * pointer command pending because the device can choose to start any
339 * stream once the endpoint is on the HW schedule.
341 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
342 (ep_state
& EP_HALTED
))
344 writel(DB_VALUE(ep_index
, stream_id
), db_addr
);
345 /* The CPU has better things to do at this point than wait for a
346 * write-posting flush. It'll get there soon enough.
350 /* Ring the doorbell for any rings with pending URBs */
351 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
352 unsigned int slot_id
,
353 unsigned int ep_index
)
355 unsigned int stream_id
;
356 struct xhci_virt_ep
*ep
;
358 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
360 /* A ring has pending URBs if its TD list is not empty */
361 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
362 if (ep
->ring
&& !(list_empty(&ep
->ring
->td_list
)))
363 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
367 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
369 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
370 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
371 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
376 /* Get the right ring for the given slot_id, ep_index and stream_id.
377 * If the endpoint supports streams, boundary check the URB's stream ID.
378 * If the endpoint doesn't support streams, return the singular endpoint ring.
380 struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
381 unsigned int slot_id
, unsigned int ep_index
,
382 unsigned int stream_id
)
384 struct xhci_virt_ep
*ep
;
386 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
387 /* Common case: no streams */
388 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
391 if (stream_id
== 0) {
393 "WARN: Slot ID %u, ep index %u has streams, "
394 "but URB has no stream ID.\n",
399 if (stream_id
< ep
->stream_info
->num_streams
)
400 return ep
->stream_info
->stream_rings
[stream_id
];
403 "WARN: Slot ID %u, ep index %u has "
404 "stream IDs 1 to %u allocated, "
405 "but stream ID %u is requested.\n",
407 ep
->stream_info
->num_streams
- 1,
413 * Move the xHC's endpoint ring dequeue pointer past cur_td.
414 * Record the new state of the xHC's endpoint ring dequeue segment,
415 * dequeue pointer, and new consumer cycle state in state.
416 * Update our internal representation of the ring's dequeue pointer.
418 * We do this in three jumps:
419 * - First we update our new ring state to be the same as when the xHC stopped.
420 * - Then we traverse the ring to find the segment that contains
421 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
422 * any link TRBs with the toggle cycle bit set.
423 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
424 * if we've moved it past a link TRB with the toggle cycle bit set.
426 * Some of the uses of xhci_generic_trb are grotty, but if they're done
427 * with correct __le32 accesses they should work fine. Only users of this are
430 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
431 unsigned int slot_id
, unsigned int ep_index
,
432 unsigned int stream_id
, struct xhci_td
*cur_td
,
433 struct xhci_dequeue_state
*state
)
435 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
436 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
437 struct xhci_ring
*ep_ring
;
438 struct xhci_segment
*new_seg
;
439 union xhci_trb
*new_deq
;
442 bool cycle_found
= false;
443 bool td_last_trb_found
= false;
445 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
446 ep_index
, stream_id
);
448 xhci_warn(xhci
, "WARN can't find new dequeue state "
449 "for invalid stream ID %u.\n",
454 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
455 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
456 "Finding endpoint context");
457 /* 4.6.9 the css flag is written to the stream context for streams */
458 if (ep
->ep_state
& EP_HAS_STREAMS
) {
459 struct xhci_stream_ctx
*ctx
=
460 &ep
->stream_info
->stream_ctx_array
[stream_id
];
461 hw_dequeue
= le64_to_cpu(ctx
->stream_ring
);
463 struct xhci_ep_ctx
*ep_ctx
464 = xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
465 hw_dequeue
= le64_to_cpu(ep_ctx
->deq
);
468 new_seg
= ep_ring
->deq_seg
;
469 new_deq
= ep_ring
->dequeue
;
470 state
->new_cycle_state
= hw_dequeue
& 0x1;
473 * We want to find the pointer, segment and cycle state of the new trb
474 * (the one after current TD's last_trb). We know the cycle state at
475 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
479 if (!cycle_found
&& xhci_trb_virt_to_dma(new_seg
, new_deq
)
480 == (dma_addr_t
)(hw_dequeue
& ~0xf)) {
482 if (td_last_trb_found
)
485 if (new_deq
== cur_td
->last_trb
)
486 td_last_trb_found
= true;
489 TRB_TYPE_LINK_LE32(new_deq
->generic
.field
[3]) &&
490 new_deq
->generic
.field
[3] & cpu_to_le32(LINK_TOGGLE
))
491 state
->new_cycle_state
^= 0x1;
493 next_trb(xhci
, ep_ring
, &new_seg
, &new_deq
);
495 /* Search wrapped around, bail out */
496 if (new_deq
== ep
->ring
->dequeue
) {
497 xhci_err(xhci
, "Error: Failed finding new dequeue state\n");
498 state
->new_deq_seg
= NULL
;
499 state
->new_deq_ptr
= NULL
;
503 } while (!cycle_found
|| !td_last_trb_found
);
505 state
->new_deq_seg
= new_seg
;
506 state
->new_deq_ptr
= new_deq
;
508 /* Don't update the ring cycle state for the producer (us). */
509 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
510 "Cycle state = 0x%x", state
->new_cycle_state
);
512 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
513 "New dequeue segment = %p (virtual)",
515 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
516 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
517 "New dequeue pointer = 0x%llx (DMA)",
518 (unsigned long long) addr
);
521 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
522 * (The last TRB actually points to the ring enqueue pointer, which is not part
523 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
525 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
526 struct xhci_td
*cur_td
, bool flip_cycle
)
528 struct xhci_segment
*cur_seg
;
529 union xhci_trb
*cur_trb
;
531 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
533 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
534 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
535 /* Unchain any chained Link TRBs, but
536 * leave the pointers intact.
538 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
539 /* Flip the cycle bit (link TRBs can't be the first
543 cur_trb
->generic
.field
[3] ^=
544 cpu_to_le32(TRB_CYCLE
);
545 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
546 "Cancel (unchain) link TRB");
547 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
548 "Address = %p (0x%llx dma); "
549 "in seg %p (0x%llx dma)",
551 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
553 (unsigned long long)cur_seg
->dma
);
555 cur_trb
->generic
.field
[0] = 0;
556 cur_trb
->generic
.field
[1] = 0;
557 cur_trb
->generic
.field
[2] = 0;
558 /* Preserve only the cycle bit of this TRB */
559 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
560 /* Flip the cycle bit except on the first or last TRB */
561 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
562 cur_trb
!= cur_td
->last_trb
)
563 cur_trb
->generic
.field
[3] ^=
564 cpu_to_le32(TRB_CYCLE
);
565 cur_trb
->generic
.field
[3] |= cpu_to_le32(
566 TRB_TYPE(TRB_TR_NOOP
));
567 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
568 "TRB to noop at offset 0x%llx",
570 xhci_trb_virt_to_dma(cur_seg
, cur_trb
));
572 if (cur_trb
== cur_td
->last_trb
)
577 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
578 struct xhci_virt_ep
*ep
)
580 ep
->ep_state
&= ~EP_HALT_PENDING
;
581 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
582 * timer is running on another CPU, we don't decrement stop_cmds_pending
583 * (since we didn't successfully stop the watchdog timer).
585 if (del_timer(&ep
->stop_cmd_timer
))
586 ep
->stop_cmds_pending
--;
589 /* Must be called with xhci->lock held in interrupt context */
590 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
591 struct xhci_td
*cur_td
, int status
)
595 struct urb_priv
*urb_priv
;
598 urb_priv
= urb
->hcpriv
;
600 hcd
= bus_to_hcd(urb
->dev
->bus
);
602 /* Only giveback urb when this is the last td in urb */
603 if (urb_priv
->td_cnt
== urb_priv
->length
) {
604 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
605 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
606 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
607 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
608 usb_amd_quirk_pll_enable();
611 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
613 spin_unlock(&xhci
->lock
);
614 usb_hcd_giveback_urb(hcd
, urb
, status
);
615 xhci_urb_free_priv(urb_priv
);
616 spin_lock(&xhci
->lock
);
621 * When we get a command completion for a Stop Endpoint Command, we need to
622 * unlink any cancelled TDs from the ring. There are two ways to do that:
624 * 1. If the HW was in the middle of processing the TD that needs to be
625 * cancelled, then we must move the ring's dequeue pointer past the last TRB
626 * in the TD with a Set Dequeue Pointer Command.
627 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
628 * bit cleared) so that the HW will skip over them.
630 static void xhci_handle_cmd_stop_ep(struct xhci_hcd
*xhci
, int slot_id
,
631 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
633 unsigned int ep_index
;
634 struct xhci_ring
*ep_ring
;
635 struct xhci_virt_ep
*ep
;
636 struct list_head
*entry
;
637 struct xhci_td
*cur_td
= NULL
;
638 struct xhci_td
*last_unlinked_td
;
640 struct xhci_dequeue_state deq_state
;
642 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb
->generic
.field
[3])))) {
643 if (!xhci
->devs
[slot_id
])
644 xhci_warn(xhci
, "Stop endpoint command "
645 "completion for disabled slot %u\n",
650 memset(&deq_state
, 0, sizeof(deq_state
));
651 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
652 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
654 if (list_empty(&ep
->cancelled_td_list
)) {
655 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
656 ep
->stopped_td
= NULL
;
657 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
661 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
662 * We have the xHCI lock, so nothing can modify this list until we drop
663 * it. We're also in the event handler, so we can't get re-interrupted
664 * if another Stop Endpoint command completes
666 list_for_each(entry
, &ep
->cancelled_td_list
) {
667 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
668 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
669 "Removing canceled TD starting at 0x%llx (dma).",
670 (unsigned long long)xhci_trb_virt_to_dma(
671 cur_td
->start_seg
, cur_td
->first_trb
));
672 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
674 /* This shouldn't happen unless a driver is mucking
675 * with the stream ID after submission. This will
676 * leave the TD on the hardware ring, and the hardware
677 * will try to execute it, and may access a buffer
678 * that has already been freed. In the best case, the
679 * hardware will execute it, and the event handler will
680 * ignore the completion event for that TD, since it was
681 * removed from the td_list for that endpoint. In
682 * short, don't muck with the stream ID after
685 xhci_warn(xhci
, "WARN Cancelled URB %p "
686 "has invalid stream ID %u.\n",
688 cur_td
->urb
->stream_id
);
689 goto remove_finished_td
;
692 * If we stopped on the TD we need to cancel, then we have to
693 * move the xHC endpoint ring dequeue pointer past this TD.
695 if (cur_td
== ep
->stopped_td
)
696 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
697 cur_td
->urb
->stream_id
,
700 td_to_noop(xhci
, ep_ring
, cur_td
, false);
703 * The event handler won't see a completion for this TD anymore,
704 * so remove it from the endpoint ring's TD list. Keep it in
705 * the cancelled TD list for URB completion later.
707 list_del_init(&cur_td
->td_list
);
709 last_unlinked_td
= cur_td
;
710 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
712 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
713 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
714 xhci_queue_new_dequeue_state(xhci
, slot_id
, ep_index
,
715 ep
->stopped_td
->urb
->stream_id
, &deq_state
);
716 xhci_ring_cmd_db(xhci
);
718 /* Otherwise ring the doorbell(s) to restart queued transfers */
719 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
722 ep
->stopped_td
= NULL
;
725 * Drop the lock and complete the URBs in the cancelled TD list.
726 * New TDs to be cancelled might be added to the end of the list before
727 * we can complete all the URBs for the TDs we already unlinked.
728 * So stop when we've completed the URB for the last TD we unlinked.
731 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
732 struct xhci_td
, cancelled_td_list
);
733 list_del_init(&cur_td
->cancelled_td_list
);
735 /* Clean up the cancelled URB */
736 /* Doesn't matter what we pass for status, since the core will
737 * just overwrite it (because the URB has been unlinked).
739 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0);
741 /* Stop processing the cancelled list if the watchdog timer is
744 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
746 } while (cur_td
!= last_unlinked_td
);
748 /* Return to the event handler with xhci->lock re-acquired */
751 static void xhci_kill_ring_urbs(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
753 struct xhci_td
*cur_td
;
755 while (!list_empty(&ring
->td_list
)) {
756 cur_td
= list_first_entry(&ring
->td_list
,
757 struct xhci_td
, td_list
);
758 list_del_init(&cur_td
->td_list
);
759 if (!list_empty(&cur_td
->cancelled_td_list
))
760 list_del_init(&cur_td
->cancelled_td_list
);
761 xhci_giveback_urb_in_irq(xhci
, cur_td
, -ESHUTDOWN
);
765 static void xhci_kill_endpoint_urbs(struct xhci_hcd
*xhci
,
766 int slot_id
, int ep_index
)
768 struct xhci_td
*cur_td
;
769 struct xhci_virt_ep
*ep
;
770 struct xhci_ring
*ring
;
772 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
773 if ((ep
->ep_state
& EP_HAS_STREAMS
) ||
774 (ep
->ep_state
& EP_GETTING_NO_STREAMS
)) {
777 for (stream_id
= 0; stream_id
< ep
->stream_info
->num_streams
;
779 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
780 "Killing URBs for slot ID %u, ep index %u, stream %u",
781 slot_id
, ep_index
, stream_id
+ 1);
782 xhci_kill_ring_urbs(xhci
,
783 ep
->stream_info
->stream_rings
[stream_id
]);
789 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
790 "Killing URBs for slot ID %u, ep index %u",
792 xhci_kill_ring_urbs(xhci
, ring
);
794 while (!list_empty(&ep
->cancelled_td_list
)) {
795 cur_td
= list_first_entry(&ep
->cancelled_td_list
,
796 struct xhci_td
, cancelled_td_list
);
797 list_del_init(&cur_td
->cancelled_td_list
);
798 xhci_giveback_urb_in_irq(xhci
, cur_td
, -ESHUTDOWN
);
802 /* Watchdog timer function for when a stop endpoint command fails to complete.
803 * In this case, we assume the host controller is broken or dying or dead. The
804 * host may still be completing some other events, so we have to be careful to
805 * let the event ring handler and the URB dequeueing/enqueueing functions know
806 * through xhci->state.
808 * The timer may also fire if the host takes a very long time to respond to the
809 * command, and the stop endpoint command completion handler cannot delete the
810 * timer before the timer function is called. Another endpoint cancellation may
811 * sneak in before the timer function can grab the lock, and that may queue
812 * another stop endpoint command and add the timer back. So we cannot use a
813 * simple flag to say whether there is a pending stop endpoint command for a
814 * particular endpoint.
816 * Instead we use a combination of that flag and a counter for the number of
817 * pending stop endpoint commands. If the timer is the tail end of the last
818 * stop endpoint command, and the endpoint's command is still pending, we assume
821 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
823 struct xhci_hcd
*xhci
;
824 struct xhci_virt_ep
*ep
;
828 ep
= (struct xhci_virt_ep
*) arg
;
831 spin_lock_irqsave(&xhci
->lock
, flags
);
833 ep
->stop_cmds_pending
--;
834 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
835 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
836 "Stop EP timer ran, but another timer marked "
837 "xHCI as DYING, exiting.");
838 spin_unlock_irqrestore(&xhci
->lock
, flags
);
841 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
842 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
843 "Stop EP timer ran, but no command pending, "
845 spin_unlock_irqrestore(&xhci
->lock
, flags
);
849 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
850 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
851 /* Oops, HC is dead or dying or at least not responding to the stop
854 xhci
->xhc_state
|= XHCI_STATE_DYING
;
855 /* Disable interrupts from the host controller and start halting it */
857 spin_unlock_irqrestore(&xhci
->lock
, flags
);
859 ret
= xhci_halt(xhci
);
861 spin_lock_irqsave(&xhci
->lock
, flags
);
863 /* This is bad; the host is not responding to commands and it's
864 * not allowing itself to be halted. At least interrupts are
865 * disabled. If we call usb_hc_died(), it will attempt to
866 * disconnect all device drivers under this host. Those
867 * disconnect() methods will wait for all URBs to be unlinked,
868 * so we must complete them.
870 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
871 xhci_warn(xhci
, "Completing active URBs anyway.\n");
872 /* We could turn all TDs on the rings to no-ops. This won't
873 * help if the host has cached part of the ring, and is slow if
874 * we want to preserve the cycle bit. Skip it and hope the host
875 * doesn't touch the memory.
878 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
881 for (j
= 0; j
< 31; j
++)
882 xhci_kill_endpoint_urbs(xhci
, i
, j
);
884 spin_unlock_irqrestore(&xhci
->lock
, flags
);
885 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
886 "Calling usb_hc_died()");
887 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
888 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
889 "xHCI host controller is dead.");
893 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
894 struct xhci_virt_device
*dev
,
895 struct xhci_ring
*ep_ring
,
896 unsigned int ep_index
)
898 union xhci_trb
*dequeue_temp
;
899 int num_trbs_free_temp
;
902 num_trbs_free_temp
= ep_ring
->num_trbs_free
;
903 dequeue_temp
= ep_ring
->dequeue
;
905 /* If we get two back-to-back stalls, and the first stalled transfer
906 * ends just before a link TRB, the dequeue pointer will be left on
907 * the link TRB by the code in the while loop. So we have to update
908 * the dequeue pointer one segment further, or we'll jump off
909 * the segment into la-la-land.
911 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
, ep_ring
->dequeue
)) {
912 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
913 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
916 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
917 /* We have more usable TRBs */
918 ep_ring
->num_trbs_free
++;
920 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
,
922 if (ep_ring
->dequeue
==
923 dev
->eps
[ep_index
].queued_deq_ptr
)
925 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
926 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
928 if (ep_ring
->dequeue
== dequeue_temp
) {
935 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
936 ep_ring
->num_trbs_free
= num_trbs_free_temp
;
941 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
942 * we need to clear the set deq pending flag in the endpoint ring state, so that
943 * the TD queueing code can ring the doorbell again. We also need to ring the
944 * endpoint doorbell to restart the ring, but only if there aren't more
945 * cancellations pending.
947 static void xhci_handle_cmd_set_deq(struct xhci_hcd
*xhci
, int slot_id
,
948 union xhci_trb
*trb
, u32 cmd_comp_code
)
950 unsigned int ep_index
;
951 unsigned int stream_id
;
952 struct xhci_ring
*ep_ring
;
953 struct xhci_virt_device
*dev
;
954 struct xhci_virt_ep
*ep
;
955 struct xhci_ep_ctx
*ep_ctx
;
956 struct xhci_slot_ctx
*slot_ctx
;
958 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
959 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
960 dev
= xhci
->devs
[slot_id
];
961 ep
= &dev
->eps
[ep_index
];
963 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
965 xhci_warn(xhci
, "WARN Set TR deq ptr command for freed stream ID %u\n",
967 /* XXX: Harmless??? */
971 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
972 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
974 if (cmd_comp_code
!= COMP_SUCCESS
) {
975 unsigned int ep_state
;
976 unsigned int slot_state
;
978 switch (cmd_comp_code
) {
980 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
983 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
984 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
985 ep_state
&= EP_STATE_MASK
;
986 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
987 slot_state
= GET_SLOT_STATE(slot_state
);
988 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
989 "Slot state = %u, EP state = %u",
990 slot_state
, ep_state
);
993 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
997 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1001 /* OK what do we do now? The endpoint state is hosed, and we
1002 * should never get to this point if the synchronization between
1003 * queueing, and endpoint state are correct. This might happen
1004 * if the device gets disconnected after we've finished
1005 * cancelling URBs, which might not be an error...
1009 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1010 if (ep
->ep_state
& EP_HAS_STREAMS
) {
1011 struct xhci_stream_ctx
*ctx
=
1012 &ep
->stream_info
->stream_ctx_array
[stream_id
];
1013 deq
= le64_to_cpu(ctx
->stream_ring
) & SCTX_DEQ_MASK
;
1015 deq
= le64_to_cpu(ep_ctx
->deq
) & ~EP_CTX_CYCLE_MASK
;
1017 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1018 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq
);
1019 if (xhci_trb_virt_to_dma(ep
->queued_deq_seg
,
1020 ep
->queued_deq_ptr
) == deq
) {
1021 /* Update the ring's dequeue segment and dequeue pointer
1022 * to reflect the new position.
1024 update_ring_for_set_deq_completion(xhci
, dev
,
1027 xhci_warn(xhci
, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1028 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1029 ep
->queued_deq_seg
, ep
->queued_deq_ptr
);
1034 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1035 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
1036 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
1037 /* Restart any rings with pending URBs */
1038 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1041 static void xhci_handle_cmd_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1042 union xhci_trb
*trb
, u32 cmd_comp_code
)
1044 unsigned int ep_index
;
1046 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1047 /* This command will only fail if the endpoint wasn't halted,
1048 * but we don't care.
1050 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
1051 "Ignoring reset ep completion code of %u", cmd_comp_code
);
1053 /* HW with the reset endpoint quirk needs to have a configure endpoint
1054 * command complete before the endpoint can be used. Queue that here
1055 * because the HW can't handle two commands being queued in a row.
1057 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1058 struct xhci_command
*command
;
1059 command
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
1061 xhci_warn(xhci
, "WARN Cannot submit cfg ep: ENOMEM\n");
1064 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1065 "Queueing configure endpoint command");
1066 xhci_queue_configure_endpoint(xhci
, command
,
1067 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1069 xhci_ring_cmd_db(xhci
);
1071 /* Clear our internal halted state */
1072 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1076 static void xhci_handle_cmd_enable_slot(struct xhci_hcd
*xhci
, int slot_id
,
1079 if (cmd_comp_code
== COMP_SUCCESS
)
1080 xhci
->slot_id
= slot_id
;
1085 static void xhci_handle_cmd_disable_slot(struct xhci_hcd
*xhci
, int slot_id
)
1087 struct xhci_virt_device
*virt_dev
;
1089 virt_dev
= xhci
->devs
[slot_id
];
1092 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1093 /* Delete default control endpoint resources */
1094 xhci_free_device_endpoint_resources(xhci
, virt_dev
, true);
1095 xhci_free_virt_device(xhci
, slot_id
);
1098 static void xhci_handle_cmd_config_ep(struct xhci_hcd
*xhci
, int slot_id
,
1099 struct xhci_event_cmd
*event
, u32 cmd_comp_code
)
1101 struct xhci_virt_device
*virt_dev
;
1102 struct xhci_input_control_ctx
*ctrl_ctx
;
1103 unsigned int ep_index
;
1104 unsigned int ep_state
;
1105 u32 add_flags
, drop_flags
;
1108 * Configure endpoint commands can come from the USB core
1109 * configuration or alt setting changes, or because the HW
1110 * needed an extra configure endpoint command after a reset
1111 * endpoint command or streams were being configured.
1112 * If the command was for a halted endpoint, the xHCI driver
1113 * is not waiting on the configure endpoint command.
1115 virt_dev
= xhci
->devs
[slot_id
];
1116 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
1118 xhci_warn(xhci
, "Could not get input context, bad type.\n");
1122 add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1123 drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1124 /* Input ctx add_flags are the endpoint index plus one */
1125 ep_index
= xhci_last_valid_endpoint(add_flags
) - 1;
1127 /* A usb_set_interface() call directly after clearing a halted
1128 * condition may race on this quirky hardware. Not worth
1129 * worrying about, since this is prototype hardware. Not sure
1130 * if this will work for streams, but streams support was
1131 * untested on this prototype.
1133 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1134 ep_index
!= (unsigned int) -1 &&
1135 add_flags
- SLOT_FLAG
== drop_flags
) {
1136 ep_state
= virt_dev
->eps
[ep_index
].ep_state
;
1137 if (!(ep_state
& EP_HALTED
))
1139 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1140 "Completed config ep cmd - "
1141 "last ep index = %d, state = %d",
1142 ep_index
, ep_state
);
1143 /* Clear internal halted state and restart ring(s) */
1144 virt_dev
->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1145 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1151 static void xhci_handle_cmd_reset_dev(struct xhci_hcd
*xhci
, int slot_id
,
1152 struct xhci_event_cmd
*event
)
1154 xhci_dbg(xhci
, "Completed reset device command.\n");
1155 if (!xhci
->devs
[slot_id
])
1156 xhci_warn(xhci
, "Reset device command completion "
1157 "for disabled slot %u\n", slot_id
);
1160 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd
*xhci
,
1161 struct xhci_event_cmd
*event
)
1163 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1164 xhci
->error_bitmask
|= 1 << 6;
1167 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1168 "NEC firmware version %2x.%02x",
1169 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1170 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1173 static void xhci_complete_del_and_free_cmd(struct xhci_command
*cmd
, u32 status
)
1175 list_del(&cmd
->cmd_list
);
1177 if (cmd
->completion
) {
1178 cmd
->status
= status
;
1179 complete(cmd
->completion
);
1185 void xhci_cleanup_command_queue(struct xhci_hcd
*xhci
)
1187 struct xhci_command
*cur_cmd
, *tmp_cmd
;
1188 list_for_each_entry_safe(cur_cmd
, tmp_cmd
, &xhci
->cmd_list
, cmd_list
)
1189 xhci_complete_del_and_free_cmd(cur_cmd
, COMP_CMD_ABORT
);
1193 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1194 * If there are other commands waiting then restart the ring and kick the timer.
1195 * This must be called with command ring stopped and xhci->lock held.
1197 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd
*xhci
,
1198 struct xhci_command
*cur_cmd
)
1200 struct xhci_command
*i_cmd
, *tmp_cmd
;
1203 /* Turn all aborted commands in list to no-ops, then restart */
1204 list_for_each_entry_safe(i_cmd
, tmp_cmd
, &xhci
->cmd_list
,
1207 if (i_cmd
->status
!= COMP_CMD_ABORT
)
1210 i_cmd
->status
= COMP_CMD_STOP
;
1212 xhci_dbg(xhci
, "Turn aborted command %p to no-op\n",
1213 i_cmd
->command_trb
);
1214 /* get cycle state from the original cmd trb */
1215 cycle_state
= le32_to_cpu(
1216 i_cmd
->command_trb
->generic
.field
[3]) & TRB_CYCLE
;
1217 /* modify the command trb to no-op command */
1218 i_cmd
->command_trb
->generic
.field
[0] = 0;
1219 i_cmd
->command_trb
->generic
.field
[1] = 0;
1220 i_cmd
->command_trb
->generic
.field
[2] = 0;
1221 i_cmd
->command_trb
->generic
.field
[3] = cpu_to_le32(
1222 TRB_TYPE(TRB_CMD_NOOP
) | cycle_state
);
1225 * caller waiting for completion is called when command
1226 * completion event is received for these no-op commands
1230 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
1232 /* ring command ring doorbell to restart the command ring */
1233 if ((xhci
->cmd_ring
->dequeue
!= xhci
->cmd_ring
->enqueue
) &&
1234 !(xhci
->xhc_state
& XHCI_STATE_DYING
)) {
1235 xhci
->current_cmd
= cur_cmd
;
1236 mod_timer(&xhci
->cmd_timer
, jiffies
+ XHCI_CMD_DEFAULT_TIMEOUT
);
1237 xhci_ring_cmd_db(xhci
);
1243 void xhci_handle_command_timeout(unsigned long data
)
1245 struct xhci_hcd
*xhci
;
1247 unsigned long flags
;
1249 struct xhci_command
*cur_cmd
= NULL
;
1250 xhci
= (struct xhci_hcd
*) data
;
1252 /* mark this command to be cancelled */
1253 spin_lock_irqsave(&xhci
->lock
, flags
);
1254 if (xhci
->current_cmd
) {
1255 cur_cmd
= xhci
->current_cmd
;
1256 cur_cmd
->status
= COMP_CMD_ABORT
;
1260 /* Make sure command ring is running before aborting it */
1261 hw_ring_state
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
1262 if ((xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
) &&
1263 (hw_ring_state
& CMD_RING_RUNNING
)) {
1265 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1266 xhci_dbg(xhci
, "Command timeout\n");
1267 ret
= xhci_abort_cmd_ring(xhci
);
1268 if (unlikely(ret
== -ESHUTDOWN
)) {
1269 xhci_err(xhci
, "Abort command ring failed\n");
1270 xhci_cleanup_command_queue(xhci
);
1271 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
1272 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
1276 /* command timeout on stopped ring, ring can't be aborted */
1277 xhci_dbg(xhci
, "Command timeout on stopped ring\n");
1278 xhci_handle_stopped_cmd_ring(xhci
, xhci
->current_cmd
);
1279 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1283 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1284 struct xhci_event_cmd
*event
)
1286 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1288 dma_addr_t cmd_dequeue_dma
;
1290 union xhci_trb
*cmd_trb
;
1291 struct xhci_command
*cmd
;
1294 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1295 cmd_trb
= xhci
->cmd_ring
->dequeue
;
1296 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1298 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1299 if (cmd_dequeue_dma
== 0) {
1300 xhci
->error_bitmask
|= 1 << 4;
1303 /* Does the DMA address match our internal dequeue pointer address? */
1304 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1305 xhci
->error_bitmask
|= 1 << 5;
1309 cmd
= list_entry(xhci
->cmd_list
.next
, struct xhci_command
, cmd_list
);
1311 if (cmd
->command_trb
!= xhci
->cmd_ring
->dequeue
) {
1313 "Command completion event does not match command\n");
1317 del_timer(&xhci
->cmd_timer
);
1319 trace_xhci_cmd_completion(cmd_trb
, (struct xhci_generic_trb
*) event
);
1321 cmd_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1323 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1324 if (cmd_comp_code
== COMP_CMD_STOP
) {
1325 xhci_handle_stopped_cmd_ring(xhci
, cmd
);
1329 * Host aborted the command ring, check if the current command was
1330 * supposed to be aborted, otherwise continue normally.
1331 * The command ring is stopped now, but the xHC will issue a Command
1332 * Ring Stopped event which will cause us to restart it.
1334 if (cmd_comp_code
== COMP_CMD_ABORT
) {
1335 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
1336 if (cmd
->status
== COMP_CMD_ABORT
)
1340 cmd_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb
->generic
.field
[3]));
1342 case TRB_ENABLE_SLOT
:
1343 xhci_handle_cmd_enable_slot(xhci
, slot_id
, cmd_comp_code
);
1345 case TRB_DISABLE_SLOT
:
1346 xhci_handle_cmd_disable_slot(xhci
, slot_id
);
1349 if (!cmd
->completion
)
1350 xhci_handle_cmd_config_ep(xhci
, slot_id
, event
,
1353 case TRB_EVAL_CONTEXT
:
1358 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1359 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1360 xhci_handle_cmd_stop_ep(xhci
, slot_id
, cmd_trb
, event
);
1363 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1364 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1365 xhci_handle_cmd_set_deq(xhci
, slot_id
, cmd_trb
, cmd_comp_code
);
1368 /* Is this an aborted command turned to NO-OP? */
1369 if (cmd
->status
== COMP_CMD_STOP
)
1370 cmd_comp_code
= COMP_CMD_STOP
;
1373 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1374 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1375 xhci_handle_cmd_reset_ep(xhci
, slot_id
, cmd_trb
, cmd_comp_code
);
1378 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1379 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1381 slot_id
= TRB_TO_SLOT_ID(
1382 le32_to_cpu(cmd_trb
->generic
.field
[3]));
1383 xhci_handle_cmd_reset_dev(xhci
, slot_id
, event
);
1385 case TRB_NEC_GET_FW
:
1386 xhci_handle_cmd_nec_get_fw(xhci
, event
);
1389 /* Skip over unknown commands on the event ring */
1390 xhci
->error_bitmask
|= 1 << 6;
1394 /* restart timer if this wasn't the last command */
1395 if (cmd
->cmd_list
.next
!= &xhci
->cmd_list
) {
1396 xhci
->current_cmd
= list_entry(cmd
->cmd_list
.next
,
1397 struct xhci_command
, cmd_list
);
1398 mod_timer(&xhci
->cmd_timer
, jiffies
+ XHCI_CMD_DEFAULT_TIMEOUT
);
1402 xhci_complete_del_and_free_cmd(cmd
, cmd_comp_code
);
1404 inc_deq(xhci
, xhci
->cmd_ring
);
1407 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1408 union xhci_trb
*event
)
1412 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1413 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1414 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1415 handle_cmd_completion(xhci
, &event
->event_cmd
);
1418 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1419 * port registers -- USB 3.0 and USB 2.0).
1421 * Returns a zero-based port number, which is suitable for indexing into each of
1422 * the split roothubs' port arrays and bus state arrays.
1423 * Add one to it in order to call xhci_find_slot_id_by_port.
1425 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1426 struct xhci_hcd
*xhci
, u32 port_id
)
1429 unsigned int num_similar_speed_ports
= 0;
1431 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1432 * and usb2_ports are 0-based indexes. Count the number of similar
1433 * speed ports, up to 1 port before this port.
1435 for (i
= 0; i
< (port_id
- 1); i
++) {
1436 u8 port_speed
= xhci
->port_array
[i
];
1439 * Skip ports that don't have known speeds, or have duplicate
1440 * Extended Capabilities port speed entries.
1442 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1446 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1447 * 1.1 ports are under the USB 2.0 hub. If the port speed
1448 * matches the device speed, it's a similar speed port.
1450 if ((port_speed
== 0x03) == (hcd
->speed
>= HCD_USB3
))
1451 num_similar_speed_ports
++;
1453 return num_similar_speed_ports
;
1456 static void handle_device_notification(struct xhci_hcd
*xhci
,
1457 union xhci_trb
*event
)
1460 struct usb_device
*udev
;
1462 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->generic
.field
[3]));
1463 if (!xhci
->devs
[slot_id
]) {
1464 xhci_warn(xhci
, "Device Notification event for "
1465 "unused slot %u\n", slot_id
);
1469 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1471 udev
= xhci
->devs
[slot_id
]->udev
;
1472 if (udev
&& udev
->parent
)
1473 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1476 static void handle_port_status(struct xhci_hcd
*xhci
,
1477 union xhci_trb
*event
)
1479 struct usb_hcd
*hcd
;
1484 unsigned int faked_port_index
;
1486 struct xhci_bus_state
*bus_state
;
1487 __le32 __iomem
**port_array
;
1488 bool bogus_port_status
= false;
1490 /* Port status change events always have a successful completion code */
1491 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1492 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1493 xhci
->error_bitmask
|= 1 << 8;
1495 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1496 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1498 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1499 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1500 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1501 inc_deq(xhci
, xhci
->event_ring
);
1505 /* Figure out which usb_hcd this port is attached to:
1506 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1508 major_revision
= xhci
->port_array
[port_id
- 1];
1510 /* Find the right roothub. */
1511 hcd
= xhci_to_hcd(xhci
);
1512 if ((major_revision
== 0x03) != (hcd
->speed
>= HCD_USB3
))
1513 hcd
= xhci
->shared_hcd
;
1515 if (major_revision
== 0) {
1516 xhci_warn(xhci
, "Event for port %u not in "
1517 "Extended Capabilities, ignoring.\n",
1519 bogus_port_status
= true;
1522 if (major_revision
== DUPLICATE_ENTRY
) {
1523 xhci_warn(xhci
, "Event for port %u duplicated in"
1524 "Extended Capabilities, ignoring.\n",
1526 bogus_port_status
= true;
1531 * Hardware port IDs reported by a Port Status Change Event include USB
1532 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1533 * resume event, but we first need to translate the hardware port ID
1534 * into the index into the ports on the correct split roothub, and the
1535 * correct bus_state structure.
1537 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1538 if (hcd
->speed
>= HCD_USB3
)
1539 port_array
= xhci
->usb3_ports
;
1541 port_array
= xhci
->usb2_ports
;
1542 /* Find the faked port hub number */
1543 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1546 temp
= readl(port_array
[faked_port_index
]);
1547 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1548 xhci_dbg(xhci
, "resume root hub\n");
1549 usb_hcd_resume_root_hub(hcd
);
1552 if (hcd
->speed
>= HCD_USB3
&& (temp
& PORT_PLS_MASK
) == XDEV_INACTIVE
)
1553 bus_state
->port_remote_wakeup
&= ~(1 << faked_port_index
);
1555 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1556 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1558 temp1
= readl(&xhci
->op_regs
->command
);
1559 if (!(temp1
& CMD_RUN
)) {
1560 xhci_warn(xhci
, "xHC is not running.\n");
1564 if (DEV_SUPERSPEED_ANY(temp
)) {
1565 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1566 /* Set a flag to say the port signaled remote wakeup,
1567 * so we can tell the difference between the end of
1568 * device and host initiated resume.
1570 bus_state
->port_remote_wakeup
|= 1 << faked_port_index
;
1571 xhci_test_and_clear_bit(xhci
, port_array
,
1572 faked_port_index
, PORT_PLC
);
1573 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1575 /* Need to wait until the next link state change
1576 * indicates the device is actually in U0.
1578 bogus_port_status
= true;
1580 } else if (!test_bit(faked_port_index
,
1581 &bus_state
->resuming_ports
)) {
1582 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1583 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1584 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
1585 set_bit(faked_port_index
, &bus_state
->resuming_ports
);
1586 mod_timer(&hcd
->rh_timer
,
1587 bus_state
->resume_done
[faked_port_index
]);
1588 /* Do the rest in GetPortStatus */
1592 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_U0
&&
1593 DEV_SUPERSPEED_ANY(temp
)) {
1594 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1595 /* We've just brought the device into U0 through either the
1596 * Resume state after a device remote wakeup, or through the
1597 * U3Exit state after a host-initiated resume. If it's a device
1598 * initiated remote wake, don't pass up the link state change,
1599 * so the roothub behavior is consistent with external
1600 * USB 3.0 hub behavior.
1602 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1603 faked_port_index
+ 1);
1604 if (slot_id
&& xhci
->devs
[slot_id
])
1605 xhci_ring_device(xhci
, slot_id
);
1606 if (bus_state
->port_remote_wakeup
& (1 << faked_port_index
)) {
1607 bus_state
->port_remote_wakeup
&=
1608 ~(1 << faked_port_index
);
1609 xhci_test_and_clear_bit(xhci
, port_array
,
1610 faked_port_index
, PORT_PLC
);
1611 usb_wakeup_notification(hcd
->self
.root_hub
,
1612 faked_port_index
+ 1);
1613 bogus_port_status
= true;
1619 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1620 * RExit to a disconnect state). If so, let the the driver know it's
1621 * out of the RExit state.
1623 if (!DEV_SUPERSPEED_ANY(temp
) &&
1624 test_and_clear_bit(faked_port_index
,
1625 &bus_state
->rexit_ports
)) {
1626 complete(&bus_state
->rexit_done
[faked_port_index
]);
1627 bogus_port_status
= true;
1631 if (hcd
->speed
< HCD_USB3
)
1632 xhci_test_and_clear_bit(xhci
, port_array
, faked_port_index
,
1636 /* Update event ring dequeue pointer before dropping the lock */
1637 inc_deq(xhci
, xhci
->event_ring
);
1639 /* Don't make the USB core poll the roothub if we got a bad port status
1640 * change event. Besides, at that point we can't tell which roothub
1641 * (USB 2.0 or USB 3.0) to kick.
1643 if (bogus_port_status
)
1647 * xHCI port-status-change events occur when the "or" of all the
1648 * status-change bits in the portsc register changes from 0 to 1.
1649 * New status changes won't cause an event if any other change
1650 * bits are still set. When an event occurs, switch over to
1651 * polling to avoid losing status changes.
1653 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
1654 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1655 spin_unlock(&xhci
->lock
);
1656 /* Pass this up to the core */
1657 usb_hcd_poll_rh_status(hcd
);
1658 spin_lock(&xhci
->lock
);
1662 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1663 * at end_trb, which may be in another segment. If the suspect DMA address is a
1664 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1667 struct xhci_segment
*trb_in_td(struct xhci_hcd
*xhci
,
1668 struct xhci_segment
*start_seg
,
1669 union xhci_trb
*start_trb
,
1670 union xhci_trb
*end_trb
,
1671 dma_addr_t suspect_dma
,
1674 dma_addr_t start_dma
;
1675 dma_addr_t end_seg_dma
;
1676 dma_addr_t end_trb_dma
;
1677 struct xhci_segment
*cur_seg
;
1679 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1680 cur_seg
= start_seg
;
1685 /* We may get an event for a Link TRB in the middle of a TD */
1686 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1687 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1688 /* If the end TRB isn't in this segment, this is set to 0 */
1689 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1693 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1694 (unsigned long long)suspect_dma
,
1695 (unsigned long long)start_dma
,
1696 (unsigned long long)end_trb_dma
,
1697 (unsigned long long)cur_seg
->dma
,
1698 (unsigned long long)end_seg_dma
);
1700 if (end_trb_dma
> 0) {
1701 /* The end TRB is in this segment, so suspect should be here */
1702 if (start_dma
<= end_trb_dma
) {
1703 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1706 /* Case for one segment with
1707 * a TD wrapped around to the top
1709 if ((suspect_dma
>= start_dma
&&
1710 suspect_dma
<= end_seg_dma
) ||
1711 (suspect_dma
>= cur_seg
->dma
&&
1712 suspect_dma
<= end_trb_dma
))
1717 /* Might still be somewhere in this segment */
1718 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1721 cur_seg
= cur_seg
->next
;
1722 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1723 } while (cur_seg
!= start_seg
);
1728 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1729 unsigned int slot_id
, unsigned int ep_index
,
1730 unsigned int stream_id
,
1731 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1733 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1734 struct xhci_command
*command
;
1735 command
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
1739 ep
->ep_state
|= EP_HALTED
;
1740 ep
->stopped_stream
= stream_id
;
1742 xhci_queue_reset_ep(xhci
, command
, slot_id
, ep_index
);
1743 xhci_cleanup_stalled_ring(xhci
, ep_index
, td
);
1745 ep
->stopped_stream
= 0;
1747 xhci_ring_cmd_db(xhci
);
1750 /* Check if an error has halted the endpoint ring. The class driver will
1751 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1752 * However, a babble and other errors also halt the endpoint ring, and the class
1753 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1754 * Ring Dequeue Pointer command manually.
1756 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1757 struct xhci_ep_ctx
*ep_ctx
,
1758 unsigned int trb_comp_code
)
1760 /* TRB completion codes that may require a manual halt cleanup */
1761 if (trb_comp_code
== COMP_TX_ERR
||
1762 trb_comp_code
== COMP_BABBLE
||
1763 trb_comp_code
== COMP_SPLIT_ERR
)
1764 /* The 0.95 spec says a babbling control endpoint
1765 * is not halted. The 0.96 spec says it is. Some HW
1766 * claims to be 0.95 compliant, but it halts the control
1767 * endpoint anyway. Check if a babble halted the
1770 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1771 cpu_to_le32(EP_STATE_HALTED
))
1777 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1779 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1780 /* Vendor defined "informational" completion code,
1781 * treat as not-an-error.
1783 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1785 xhci_dbg(xhci
, "Treating code as success.\n");
1792 * Finish the td processing, remove the td from td list;
1793 * Return 1 if the urb can be given back.
1795 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1796 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1797 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1799 struct xhci_virt_device
*xdev
;
1800 struct xhci_ring
*ep_ring
;
1801 unsigned int slot_id
;
1803 struct urb
*urb
= NULL
;
1804 struct xhci_ep_ctx
*ep_ctx
;
1806 struct urb_priv
*urb_priv
;
1809 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1810 xdev
= xhci
->devs
[slot_id
];
1811 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1812 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1813 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1814 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1819 if (trb_comp_code
== COMP_STOP_INVAL
||
1820 trb_comp_code
== COMP_STOP
||
1821 trb_comp_code
== COMP_STOP_SHORT
) {
1822 /* The Endpoint Stop Command completion will take care of any
1823 * stopped TDs. A stopped TD may be restarted, so don't update
1824 * the ring dequeue pointer or take this TD off any lists yet.
1826 ep
->stopped_td
= td
;
1829 if (trb_comp_code
== COMP_STALL
||
1830 xhci_requires_manual_halt_cleanup(xhci
, ep_ctx
,
1832 /* Issue a reset endpoint command to clear the host side
1833 * halt, followed by a set dequeue command to move the
1834 * dequeue pointer past the TD.
1835 * The class driver clears the device side halt later.
1837 xhci_cleanup_halted_endpoint(xhci
, slot_id
, ep_index
,
1838 ep_ring
->stream_id
, td
, event_trb
);
1840 /* Update ring dequeue pointer */
1841 while (ep_ring
->dequeue
!= td
->last_trb
)
1842 inc_deq(xhci
, ep_ring
);
1843 inc_deq(xhci
, ep_ring
);
1847 /* Clean up the endpoint's TD list */
1849 urb_priv
= urb
->hcpriv
;
1851 /* Do one last check of the actual transfer length.
1852 * If the host controller said we transferred more data than the buffer
1853 * length, urb->actual_length will be a very big number (since it's
1854 * unsigned). Play it safe and say we didn't transfer anything.
1856 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1857 xhci_warn(xhci
, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1858 urb
->transfer_buffer_length
,
1859 urb
->actual_length
);
1860 urb
->actual_length
= 0;
1861 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1862 *status
= -EREMOTEIO
;
1866 list_del_init(&td
->td_list
);
1867 /* Was this TD slated to be cancelled but completed anyway? */
1868 if (!list_empty(&td
->cancelled_td_list
))
1869 list_del_init(&td
->cancelled_td_list
);
1872 /* Giveback the urb when all the tds are completed */
1873 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1875 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1876 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1877 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
1878 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1879 usb_amd_quirk_pll_enable();
1888 * Process control tds, update urb status and actual_length.
1890 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1891 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1892 struct xhci_virt_ep
*ep
, int *status
)
1894 struct xhci_virt_device
*xdev
;
1895 struct xhci_ring
*ep_ring
;
1896 unsigned int slot_id
;
1898 struct xhci_ep_ctx
*ep_ctx
;
1901 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1902 xdev
= xhci
->devs
[slot_id
];
1903 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1904 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1905 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1906 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1908 switch (trb_comp_code
) {
1910 if (event_trb
== ep_ring
->dequeue
) {
1911 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1912 "without IOC set??\n");
1913 *status
= -ESHUTDOWN
;
1914 } else if (event_trb
!= td
->last_trb
) {
1915 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1916 "without IOC set??\n");
1917 *status
= -ESHUTDOWN
;
1923 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1924 *status
= -EREMOTEIO
;
1928 case COMP_STOP_SHORT
:
1929 if (event_trb
== ep_ring
->dequeue
|| event_trb
== td
->last_trb
)
1930 xhci_warn(xhci
, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1932 td
->urb
->actual_length
=
1933 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
1935 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1937 /* Did we stop at data stage? */
1938 if (event_trb
!= ep_ring
->dequeue
&& event_trb
!= td
->last_trb
)
1939 td
->urb
->actual_length
=
1940 td
->urb
->transfer_buffer_length
-
1941 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
1943 case COMP_STOP_INVAL
:
1944 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1946 if (!xhci_requires_manual_halt_cleanup(xhci
,
1947 ep_ctx
, trb_comp_code
))
1949 xhci_dbg(xhci
, "TRB error code %u, "
1950 "halted endpoint index = %u\n",
1951 trb_comp_code
, ep_index
);
1952 /* else fall through */
1954 /* Did we transfer part of the data (middle) phase? */
1955 if (event_trb
!= ep_ring
->dequeue
&&
1956 event_trb
!= td
->last_trb
)
1957 td
->urb
->actual_length
=
1958 td
->urb
->transfer_buffer_length
-
1959 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
1960 else if (!td
->urb_length_set
)
1961 td
->urb
->actual_length
= 0;
1963 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1966 * Did we transfer any data, despite the errors that might have
1967 * happened? I.e. did we get past the setup stage?
1969 if (event_trb
!= ep_ring
->dequeue
) {
1970 /* The event was for the status stage */
1971 if (event_trb
== td
->last_trb
) {
1972 if (td
->urb_length_set
) {
1973 /* Don't overwrite a previously set error code
1975 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
1976 (td
->urb
->transfer_flags
1977 & URB_SHORT_NOT_OK
))
1978 /* Did we already see a short data
1980 *status
= -EREMOTEIO
;
1982 td
->urb
->actual_length
=
1983 td
->urb
->transfer_buffer_length
;
1987 * Maybe the event was for the data stage? If so, update
1988 * already the actual_length of the URB and flag it as
1989 * set, so that it is not overwritten in the event for
1992 td
->urb_length_set
= true;
1993 td
->urb
->actual_length
=
1994 td
->urb
->transfer_buffer_length
-
1995 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
1996 xhci_dbg(xhci
, "Waiting for status "
2002 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2006 * Process isochronous tds, update urb packet status and actual_length.
2008 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2009 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2010 struct xhci_virt_ep
*ep
, int *status
)
2012 struct xhci_ring
*ep_ring
;
2013 struct urb_priv
*urb_priv
;
2016 union xhci_trb
*cur_trb
;
2017 struct xhci_segment
*cur_seg
;
2018 struct usb_iso_packet_descriptor
*frame
;
2020 bool skip_td
= false;
2022 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2023 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2024 urb_priv
= td
->urb
->hcpriv
;
2025 idx
= urb_priv
->td_cnt
;
2026 frame
= &td
->urb
->iso_frame_desc
[idx
];
2028 /* handle completion code */
2029 switch (trb_comp_code
) {
2031 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0) {
2035 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2036 trb_comp_code
= COMP_SHORT_TX
;
2038 case COMP_STOP_SHORT
:
2040 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
2044 frame
->status
= -ECOMM
;
2047 case COMP_BUFF_OVER
:
2049 frame
->status
= -EOVERFLOW
;
2054 frame
->status
= -EPROTO
;
2058 frame
->status
= -EPROTO
;
2059 if (event_trb
!= td
->last_trb
)
2064 case COMP_STOP_INVAL
:
2071 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
2072 frame
->actual_length
= frame
->length
;
2073 td
->urb
->actual_length
+= frame
->length
;
2074 } else if (trb_comp_code
== COMP_STOP_SHORT
) {
2075 frame
->actual_length
=
2076 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2077 td
->urb
->actual_length
+= frame
->actual_length
;
2079 for (cur_trb
= ep_ring
->dequeue
,
2080 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
2081 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2082 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2083 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2084 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2086 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2087 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2089 if (trb_comp_code
!= COMP_STOP_INVAL
) {
2090 frame
->actual_length
= len
;
2091 td
->urb
->actual_length
+= len
;
2095 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2098 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2099 struct xhci_transfer_event
*event
,
2100 struct xhci_virt_ep
*ep
, int *status
)
2102 struct xhci_ring
*ep_ring
;
2103 struct urb_priv
*urb_priv
;
2104 struct usb_iso_packet_descriptor
*frame
;
2107 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2108 urb_priv
= td
->urb
->hcpriv
;
2109 idx
= urb_priv
->td_cnt
;
2110 frame
= &td
->urb
->iso_frame_desc
[idx
];
2112 /* The transfer is partly done. */
2113 frame
->status
= -EXDEV
;
2115 /* calc actual length */
2116 frame
->actual_length
= 0;
2118 /* Update ring dequeue pointer */
2119 while (ep_ring
->dequeue
!= td
->last_trb
)
2120 inc_deq(xhci
, ep_ring
);
2121 inc_deq(xhci
, ep_ring
);
2123 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
2127 * Process bulk and interrupt tds, update urb status and actual_length.
2129 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2130 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2131 struct xhci_virt_ep
*ep
, int *status
)
2133 struct xhci_ring
*ep_ring
;
2134 union xhci_trb
*cur_trb
;
2135 struct xhci_segment
*cur_seg
;
2138 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2139 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2141 switch (trb_comp_code
) {
2143 /* Double check that the HW transferred everything. */
2144 if (event_trb
!= td
->last_trb
||
2145 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2146 xhci_warn(xhci
, "WARN Successful completion "
2148 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2149 *status
= -EREMOTEIO
;
2152 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2153 trb_comp_code
= COMP_SHORT_TX
;
2158 case COMP_STOP_SHORT
:
2160 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2161 *status
= -EREMOTEIO
;
2166 /* Others already handled above */
2169 if (trb_comp_code
== COMP_SHORT_TX
)
2170 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
2171 "%d bytes untransferred\n",
2172 td
->urb
->ep
->desc
.bEndpointAddress
,
2173 td
->urb
->transfer_buffer_length
,
2174 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2175 /* Stopped - short packet completion */
2176 if (trb_comp_code
== COMP_STOP_SHORT
) {
2177 td
->urb
->actual_length
=
2178 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2180 if (td
->urb
->transfer_buffer_length
<
2181 td
->urb
->actual_length
) {
2182 xhci_warn(xhci
, "HC gave bad length of %d bytes txed\n",
2183 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2184 td
->urb
->actual_length
= 0;
2185 /* status will be set by usb core for canceled urbs */
2187 /* Fast path - was this the last TRB in the TD for this URB? */
2188 } else if (event_trb
== td
->last_trb
) {
2189 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2190 td
->urb
->actual_length
=
2191 td
->urb
->transfer_buffer_length
-
2192 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2193 if (td
->urb
->transfer_buffer_length
<
2194 td
->urb
->actual_length
) {
2195 xhci_warn(xhci
, "HC gave bad length "
2196 "of %d bytes left\n",
2197 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2198 td
->urb
->actual_length
= 0;
2199 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2200 *status
= -EREMOTEIO
;
2204 /* Don't overwrite a previously set error code */
2205 if (*status
== -EINPROGRESS
) {
2206 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2207 *status
= -EREMOTEIO
;
2212 td
->urb
->actual_length
=
2213 td
->urb
->transfer_buffer_length
;
2214 /* Ignore a short packet completion if the
2215 * untransferred length was zero.
2217 if (*status
== -EREMOTEIO
)
2221 /* Slow path - walk the list, starting from the dequeue
2222 * pointer, to get the actual length transferred.
2224 td
->urb
->actual_length
= 0;
2225 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
2226 cur_trb
!= event_trb
;
2227 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2228 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2229 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2230 td
->urb
->actual_length
+=
2231 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2233 /* If the ring didn't stop on a Link or No-op TRB, add
2234 * in the actual bytes transferred from the Normal TRB
2236 if (trb_comp_code
!= COMP_STOP_INVAL
)
2237 td
->urb
->actual_length
+=
2238 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2239 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2242 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2246 * If this function returns an error condition, it means it got a Transfer
2247 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2248 * At this point, the host controller is probably hosed and should be reset.
2250 static int handle_tx_event(struct xhci_hcd
*xhci
,
2251 struct xhci_transfer_event
*event
)
2252 __releases(&xhci
->lock
)
2253 __acquires(&xhci
->lock
)
2255 struct xhci_virt_device
*xdev
;
2256 struct xhci_virt_ep
*ep
;
2257 struct xhci_ring
*ep_ring
;
2258 unsigned int slot_id
;
2260 struct xhci_td
*td
= NULL
;
2261 dma_addr_t event_dma
;
2262 struct xhci_segment
*event_seg
;
2263 union xhci_trb
*event_trb
;
2264 struct urb
*urb
= NULL
;
2265 int status
= -EINPROGRESS
;
2266 struct urb_priv
*urb_priv
;
2267 struct xhci_ep_ctx
*ep_ctx
;
2268 struct list_head
*tmp
;
2272 bool handling_skipped_tds
= false;
2274 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2275 xdev
= xhci
->devs
[slot_id
];
2277 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
2278 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2279 (unsigned long long) xhci_trb_virt_to_dma(
2280 xhci
->event_ring
->deq_seg
,
2281 xhci
->event_ring
->dequeue
),
2282 lower_32_bits(le64_to_cpu(event
->buffer
)),
2283 upper_32_bits(le64_to_cpu(event
->buffer
)),
2284 le32_to_cpu(event
->transfer_len
),
2285 le32_to_cpu(event
->flags
));
2286 xhci_dbg(xhci
, "Event ring:\n");
2287 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2291 /* Endpoint ID is 1 based, our index is zero based */
2292 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2293 ep
= &xdev
->eps
[ep_index
];
2294 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2295 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2297 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
2298 EP_STATE_DISABLED
) {
2299 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
2300 "or incorrect stream ring\n");
2301 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2302 (unsigned long long) xhci_trb_virt_to_dma(
2303 xhci
->event_ring
->deq_seg
,
2304 xhci
->event_ring
->dequeue
),
2305 lower_32_bits(le64_to_cpu(event
->buffer
)),
2306 upper_32_bits(le64_to_cpu(event
->buffer
)),
2307 le32_to_cpu(event
->transfer_len
),
2308 le32_to_cpu(event
->flags
));
2309 xhci_dbg(xhci
, "Event ring:\n");
2310 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2314 /* Count current td numbers if ep->skip is set */
2316 list_for_each(tmp
, &ep_ring
->td_list
)
2320 event_dma
= le64_to_cpu(event
->buffer
);
2321 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2322 /* Look for common error cases */
2323 switch (trb_comp_code
) {
2324 /* Skip codes that require special handling depending on
2328 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2330 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2331 trb_comp_code
= COMP_SHORT_TX
;
2333 xhci_warn_ratelimited(xhci
,
2334 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2338 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
2340 case COMP_STOP_INVAL
:
2341 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
2343 case COMP_STOP_SHORT
:
2344 xhci_dbg(xhci
, "Stopped with short packet transfer detected\n");
2347 xhci_dbg(xhci
, "Stalled endpoint\n");
2348 ep
->ep_state
|= EP_HALTED
;
2352 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
2355 case COMP_SPLIT_ERR
:
2357 xhci_dbg(xhci
, "Transfer error on endpoint\n");
2361 xhci_dbg(xhci
, "Babble error on endpoint\n");
2362 status
= -EOVERFLOW
;
2365 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2369 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2371 case COMP_BUFF_OVER
:
2372 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2376 * When the Isoch ring is empty, the xHC will generate
2377 * a Ring Overrun Event for IN Isoch endpoint or Ring
2378 * Underrun Event for OUT Isoch endpoint.
2380 xhci_dbg(xhci
, "underrun event on endpoint\n");
2381 if (!list_empty(&ep_ring
->td_list
))
2382 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2383 "still with TDs queued?\n",
2384 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2388 xhci_dbg(xhci
, "overrun event on endpoint\n");
2389 if (!list_empty(&ep_ring
->td_list
))
2390 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2391 "still with TDs queued?\n",
2392 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2396 xhci_warn(xhci
, "WARN: detect an incompatible device");
2399 case COMP_MISSED_INT
:
2401 * When encounter missed service error, one or more isoc tds
2402 * may be missed by xHC.
2403 * Set skip flag of the ep_ring; Complete the missed tds as
2404 * short transfer when process the ep_ring next time.
2407 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2411 xhci_dbg(xhci
, "No Ping response error, Skip one Isoc TD\n");
2414 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2418 xhci_warn(xhci
, "ERROR Unknown event condition %u, HC probably busted\n",
2424 /* This TRB should be in the TD at the head of this ring's
2427 if (list_empty(&ep_ring
->td_list
)) {
2429 * A stopped endpoint may generate an extra completion
2430 * event if the device was suspended. Don't print
2433 if (!(trb_comp_code
== COMP_STOP
||
2434 trb_comp_code
== COMP_STOP_INVAL
)) {
2435 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2436 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2438 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2439 (le32_to_cpu(event
->flags
) &
2440 TRB_TYPE_BITMASK
)>>10);
2441 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2445 xhci_dbg(xhci
, "td_list is empty while skip "
2446 "flag set. Clear skip flag.\n");
2452 /* We've skipped all the TDs on the ep ring when ep->skip set */
2453 if (ep
->skip
&& td_num
== 0) {
2455 xhci_dbg(xhci
, "All tds on the ep_ring skipped. "
2456 "Clear skip flag.\n");
2461 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2465 /* Is this a TRB in the currently executing TD? */
2466 event_seg
= trb_in_td(xhci
, ep_ring
->deq_seg
, ep_ring
->dequeue
,
2467 td
->last_trb
, event_dma
, false);
2470 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2471 * is not in the current TD pointed by ep_ring->dequeue because
2472 * that the hardware dequeue pointer still at the previous TRB
2473 * of the current TD. The previous TRB maybe a Link TD or the
2474 * last TRB of the previous TD. The command completion handle
2475 * will take care the rest.
2477 if (!event_seg
&& (trb_comp_code
== COMP_STOP
||
2478 trb_comp_code
== COMP_STOP_INVAL
)) {
2485 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2486 /* Some host controllers give a spurious
2487 * successful event after a short transfer.
2490 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2491 ep_ring
->last_td_was_short
) {
2492 ep_ring
->last_td_was_short
= false;
2496 /* HC is busted, give up! */
2498 "ERROR Transfer event TRB DMA ptr not "
2499 "part of current TD ep_index %d "
2500 "comp_code %u\n", ep_index
,
2502 trb_in_td(xhci
, ep_ring
->deq_seg
,
2503 ep_ring
->dequeue
, td
->last_trb
,
2508 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2511 if (trb_comp_code
== COMP_SHORT_TX
)
2512 ep_ring
->last_td_was_short
= true;
2514 ep_ring
->last_td_was_short
= false;
2517 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2521 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2522 sizeof(*event_trb
)];
2524 * No-op TRB should not trigger interrupts.
2525 * If event_trb is a no-op TRB, it means the
2526 * corresponding TD has been cancelled. Just ignore
2529 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2531 "event_trb is a no-op TRB. Skip it\n");
2535 /* Now update the urb's actual_length and give back to
2538 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2539 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2541 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2542 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2545 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2551 handling_skipped_tds
= ep
->skip
&&
2552 trb_comp_code
!= COMP_MISSED_INT
&&
2553 trb_comp_code
!= COMP_PING_ERR
;
2556 * Do not update event ring dequeue pointer if we're in a loop
2557 * processing missed tds.
2559 if (!handling_skipped_tds
)
2560 inc_deq(xhci
, xhci
->event_ring
);
2564 urb_priv
= urb
->hcpriv
;
2566 xhci_urb_free_priv(urb_priv
);
2568 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2569 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2570 (urb
->transfer_flags
&
2571 URB_SHORT_NOT_OK
)) ||
2573 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2574 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2575 "expected = %d, status = %d\n",
2576 urb
, urb
->actual_length
,
2577 urb
->transfer_buffer_length
,
2579 spin_unlock(&xhci
->lock
);
2580 /* EHCI, UHCI, and OHCI always unconditionally set the
2581 * urb->status of an isochronous endpoint to 0.
2583 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2585 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2586 spin_lock(&xhci
->lock
);
2590 * If ep->skip is set, it means there are missed tds on the
2591 * endpoint ring need to take care of.
2592 * Process them as short transfer until reach the td pointed by
2595 } while (handling_skipped_tds
);
2601 * This function handles all OS-owned events on the event ring. It may drop
2602 * xhci->lock between event processing (e.g. to pass up port status changes).
2603 * Returns >0 for "possibly more events to process" (caller should call again),
2604 * otherwise 0 if done. In future, <0 returns should indicate error code.
2606 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2608 union xhci_trb
*event
;
2609 int update_ptrs
= 1;
2612 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2613 xhci
->error_bitmask
|= 1 << 1;
2617 event
= xhci
->event_ring
->dequeue
;
2618 /* Does the HC or OS own the TRB? */
2619 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2620 xhci
->event_ring
->cycle_state
) {
2621 xhci
->error_bitmask
|= 1 << 2;
2626 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2627 * speculative reads of the event's flags/data below.
2630 /* FIXME: Handle more event types. */
2631 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2632 case TRB_TYPE(TRB_COMPLETION
):
2633 handle_cmd_completion(xhci
, &event
->event_cmd
);
2635 case TRB_TYPE(TRB_PORT_STATUS
):
2636 handle_port_status(xhci
, event
);
2639 case TRB_TYPE(TRB_TRANSFER
):
2640 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2642 xhci
->error_bitmask
|= 1 << 9;
2646 case TRB_TYPE(TRB_DEV_NOTE
):
2647 handle_device_notification(xhci
, event
);
2650 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2652 handle_vendor_event(xhci
, event
);
2654 xhci
->error_bitmask
|= 1 << 3;
2656 /* Any of the above functions may drop and re-acquire the lock, so check
2657 * to make sure a watchdog timer didn't mark the host as non-responsive.
2659 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2660 xhci_dbg(xhci
, "xHCI host dying, returning from "
2661 "event handler.\n");
2666 /* Update SW event ring dequeue pointer */
2667 inc_deq(xhci
, xhci
->event_ring
);
2669 /* Are there more items on the event ring? Caller will call us again to
2676 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2677 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2678 * indicators of an event TRB error, but we check the status *first* to be safe.
2680 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2682 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2685 union xhci_trb
*event_ring_deq
;
2688 spin_lock(&xhci
->lock
);
2689 /* Check if the xHC generated the interrupt, or the irq is shared */
2690 status
= readl(&xhci
->op_regs
->status
);
2691 if (status
== 0xffffffff)
2694 if (!(status
& STS_EINT
)) {
2695 spin_unlock(&xhci
->lock
);
2698 if (status
& STS_FATAL
) {
2699 xhci_warn(xhci
, "WARNING: Host System Error\n");
2702 spin_unlock(&xhci
->lock
);
2707 * Clear the op reg interrupt status first,
2708 * so we can receive interrupts from other MSI-X interrupters.
2709 * Write 1 to clear the interrupt status.
2712 writel(status
, &xhci
->op_regs
->status
);
2713 /* FIXME when MSI-X is supported and there are multiple vectors */
2714 /* Clear the MSI-X event interrupt status */
2718 /* Acknowledge the PCI interrupt */
2719 irq_pending
= readl(&xhci
->ir_set
->irq_pending
);
2720 irq_pending
|= IMAN_IP
;
2721 writel(irq_pending
, &xhci
->ir_set
->irq_pending
);
2724 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2725 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2726 "Shouldn't IRQs be disabled?\n");
2727 /* Clear the event handler busy flag (RW1C);
2728 * the event ring should be empty.
2730 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2731 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2732 &xhci
->ir_set
->erst_dequeue
);
2733 spin_unlock(&xhci
->lock
);
2738 event_ring_deq
= xhci
->event_ring
->dequeue
;
2739 /* FIXME this should be a delayed service routine
2740 * that clears the EHB.
2742 while (xhci_handle_event(xhci
) > 0) {}
2744 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2745 /* If necessary, update the HW's version of the event ring deq ptr. */
2746 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2747 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2748 xhci
->event_ring
->dequeue
);
2750 xhci_warn(xhci
, "WARN something wrong with SW event "
2751 "ring dequeue ptr.\n");
2752 /* Update HC event ring dequeue pointer */
2753 temp_64
&= ERST_PTR_MASK
;
2754 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2757 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2758 temp_64
|= ERST_EHB
;
2759 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2761 spin_unlock(&xhci
->lock
);
2766 irqreturn_t
xhci_msi_irq(int irq
, void *hcd
)
2768 return xhci_irq(hcd
);
2771 /**** Endpoint Ring Operations ****/
2774 * Generic function for queueing a TRB on a ring.
2775 * The caller must have checked to make sure there's room on the ring.
2777 * @more_trbs_coming: Will you enqueue more TRBs before calling
2778 * prepare_transfer()?
2780 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2781 bool more_trbs_coming
,
2782 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2784 struct xhci_generic_trb
*trb
;
2786 trb
= &ring
->enqueue
->generic
;
2787 trb
->field
[0] = cpu_to_le32(field1
);
2788 trb
->field
[1] = cpu_to_le32(field2
);
2789 trb
->field
[2] = cpu_to_le32(field3
);
2790 trb
->field
[3] = cpu_to_le32(field4
);
2791 inc_enq(xhci
, ring
, more_trbs_coming
);
2795 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2796 * FIXME allocate segments if the ring is full.
2798 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2799 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2801 unsigned int num_trbs_needed
;
2803 /* Make sure the endpoint has been added to xHC schedule */
2805 case EP_STATE_DISABLED
:
2807 * USB core changed config/interfaces without notifying us,
2808 * or hardware is reporting the wrong state.
2810 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2812 case EP_STATE_ERROR
:
2813 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2814 /* FIXME event handling code for error needs to clear it */
2815 /* XXX not sure if this should be -ENOENT or not */
2817 case EP_STATE_HALTED
:
2818 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2819 case EP_STATE_STOPPED
:
2820 case EP_STATE_RUNNING
:
2823 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2825 * FIXME issue Configure Endpoint command to try to get the HC
2826 * back into a known state.
2832 if (room_on_ring(xhci
, ep_ring
, num_trbs
))
2835 if (ep_ring
== xhci
->cmd_ring
) {
2836 xhci_err(xhci
, "Do not support expand command ring\n");
2840 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
2841 "ERROR no room on ep ring, try ring expansion");
2842 num_trbs_needed
= num_trbs
- ep_ring
->num_trbs_free
;
2843 if (xhci_ring_expansion(xhci
, ep_ring
, num_trbs_needed
,
2845 xhci_err(xhci
, "Ring expansion failed\n");
2850 if (enqueue_is_link_trb(ep_ring
)) {
2851 struct xhci_ring
*ring
= ep_ring
;
2852 union xhci_trb
*next
;
2854 next
= ring
->enqueue
;
2856 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2857 /* If we're not dealing with 0.95 hardware or isoc rings
2858 * on AMD 0.96 host, clear the chain bit.
2860 if (!xhci_link_trb_quirk(xhci
) &&
2861 !(ring
->type
== TYPE_ISOC
&&
2862 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
2863 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2865 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2868 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2870 /* Toggle the cycle bit after the last ring segment. */
2871 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2872 ring
->cycle_state
^= 1;
2874 ring
->enq_seg
= ring
->enq_seg
->next
;
2875 ring
->enqueue
= ring
->enq_seg
->trbs
;
2876 next
= ring
->enqueue
;
2883 static int prepare_transfer(struct xhci_hcd
*xhci
,
2884 struct xhci_virt_device
*xdev
,
2885 unsigned int ep_index
,
2886 unsigned int stream_id
,
2887 unsigned int num_trbs
,
2889 unsigned int td_index
,
2893 struct urb_priv
*urb_priv
;
2895 struct xhci_ring
*ep_ring
;
2896 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2898 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2900 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2905 ret
= prepare_ring(xhci
, ep_ring
,
2906 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2907 num_trbs
, mem_flags
);
2911 urb_priv
= urb
->hcpriv
;
2912 td
= urb_priv
->td
[td_index
];
2914 INIT_LIST_HEAD(&td
->td_list
);
2915 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2917 if (td_index
== 0) {
2918 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2924 /* Add this TD to the tail of the endpoint ring's TD list */
2925 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2926 td
->start_seg
= ep_ring
->enq_seg
;
2927 td
->first_trb
= ep_ring
->enqueue
;
2929 urb_priv
->td
[td_index
] = td
;
2934 static unsigned int count_trbs(u64 addr
, u64 len
)
2936 unsigned int num_trbs
;
2938 num_trbs
= DIV_ROUND_UP(len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
2946 static inline unsigned int count_trbs_needed(struct urb
*urb
)
2948 return count_trbs(urb
->transfer_dma
, urb
->transfer_buffer_length
);
2951 static unsigned int count_sg_trbs_needed(struct urb
*urb
)
2953 struct scatterlist
*sg
;
2954 unsigned int i
, len
, full_len
, num_trbs
= 0;
2956 full_len
= urb
->transfer_buffer_length
;
2958 for_each_sg(urb
->sg
, sg
, urb
->num_mapped_sgs
, i
) {
2959 len
= sg_dma_len(sg
);
2960 num_trbs
+= count_trbs(sg_dma_address(sg
), len
);
2961 len
= min_t(unsigned int, len
, full_len
);
2970 static unsigned int count_isoc_trbs_needed(struct urb
*urb
, int i
)
2974 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
2975 len
= urb
->iso_frame_desc
[i
].length
;
2977 return count_trbs(addr
, len
);
2980 static void check_trb_math(struct urb
*urb
, int running_total
)
2982 if (unlikely(running_total
!= urb
->transfer_buffer_length
))
2983 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
2984 "queued %#x (%d), asked for %#x (%d)\n",
2986 urb
->ep
->desc
.bEndpointAddress
,
2987 running_total
, running_total
,
2988 urb
->transfer_buffer_length
,
2989 urb
->transfer_buffer_length
);
2992 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
2993 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
2994 struct xhci_generic_trb
*start_trb
)
2997 * Pass all the TRBs to the hardware at once and make sure this write
3002 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
3004 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
3005 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
3008 static void check_interval(struct xhci_hcd
*xhci
, struct urb
*urb
,
3009 struct xhci_ep_ctx
*ep_ctx
)
3014 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3015 ep_interval
= urb
->interval
;
3017 /* Convert to microframes */
3018 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3019 urb
->dev
->speed
== USB_SPEED_FULL
)
3022 /* FIXME change this to a warning and a suggestion to use the new API
3023 * to set the polling interval (once the API is added).
3025 if (xhci_interval
!= ep_interval
) {
3026 dev_dbg_ratelimited(&urb
->dev
->dev
,
3027 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3028 ep_interval
, ep_interval
== 1 ? "" : "s",
3029 xhci_interval
, xhci_interval
== 1 ? "" : "s");
3030 urb
->interval
= xhci_interval
;
3031 /* Convert back to frames for LS/FS devices */
3032 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3033 urb
->dev
->speed
== USB_SPEED_FULL
)
3039 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3040 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3041 * (comprised of sg list entries) can take several service intervals to
3044 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3045 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3047 struct xhci_ep_ctx
*ep_ctx
;
3049 ep_ctx
= xhci_get_ep_ctx(xhci
, xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
3050 check_interval(xhci
, urb
, ep_ctx
);
3052 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3056 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3057 * packets remaining in the TD (*not* including this TRB).
3059 * Total TD packet count = total_packet_count =
3060 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3062 * Packets transferred up to and including this TRB = packets_transferred =
3063 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3065 * TD size = total_packet_count - packets_transferred
3067 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3068 * including this TRB, right shifted by 10
3070 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3071 * This is taken care of in the TRB_TD_SIZE() macro
3073 * The last TRB in a TD must have the TD size set to zero.
3075 static u32
xhci_td_remainder(struct xhci_hcd
*xhci
, int transferred
,
3076 int trb_buff_len
, unsigned int td_total_len
,
3077 struct urb
*urb
, unsigned int num_trbs_left
)
3079 u32 maxp
, total_packet_count
;
3081 /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */
3082 if (xhci
->hci_version
< 0x100 && !(xhci
->quirks
& XHCI_MTK_HOST
))
3083 return ((td_total_len
- transferred
) >> 10);
3085 /* One TRB with a zero-length data packet. */
3086 if (num_trbs_left
== 0 || (transferred
== 0 && trb_buff_len
== 0) ||
3087 trb_buff_len
== td_total_len
)
3090 /* for MTK xHCI, TD size doesn't include this TRB */
3091 if (xhci
->quirks
& XHCI_MTK_HOST
)
3094 maxp
= GET_MAX_PACKET(usb_endpoint_maxp(&urb
->ep
->desc
));
3095 total_packet_count
= DIV_ROUND_UP(td_total_len
, maxp
);
3097 /* Queueing functions don't count the current TRB into transferred */
3098 return (total_packet_count
- ((transferred
+ trb_buff_len
) / maxp
));
3101 /* This is very similar to what ehci-q.c qtd_fill() does */
3102 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3103 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3105 struct xhci_ring
*ep_ring
;
3106 struct urb_priv
*urb_priv
;
3108 struct xhci_generic_trb
*start_trb
;
3109 struct scatterlist
*sg
= NULL
;
3110 bool more_trbs_coming
;
3111 bool zero_length_needed
;
3112 unsigned int num_trbs
, last_trb_num
, i
;
3113 unsigned int start_cycle
, num_sgs
= 0;
3114 unsigned int running_total
, block_len
, trb_buff_len
;
3115 unsigned int full_len
;
3117 u32 field
, length_field
, remainder
;
3120 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3124 /* If we have scatter/gather list, we use it. */
3126 num_sgs
= urb
->num_mapped_sgs
;
3128 num_trbs
= count_sg_trbs_needed(urb
);
3130 num_trbs
= count_trbs_needed(urb
);
3132 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3133 ep_index
, urb
->stream_id
,
3134 num_trbs
, urb
, 0, mem_flags
);
3135 if (unlikely(ret
< 0))
3138 urb_priv
= urb
->hcpriv
;
3140 last_trb_num
= num_trbs
- 1;
3142 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3143 zero_length_needed
= urb
->transfer_flags
& URB_ZERO_PACKET
&&
3144 urb_priv
->length
== 2;
3145 if (zero_length_needed
) {
3147 xhci_dbg(xhci
, "Creating zero length td.\n");
3148 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3149 ep_index
, urb
->stream_id
,
3150 1, urb
, 1, mem_flags
);
3151 if (unlikely(ret
< 0))
3155 td
= urb_priv
->td
[0];
3158 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3159 * until we've finished creating all the other TRBs. The ring's cycle
3160 * state may change as we enqueue the other TRBs, so save it too.
3162 start_trb
= &ep_ring
->enqueue
->generic
;
3163 start_cycle
= ep_ring
->cycle_state
;
3165 full_len
= urb
->transfer_buffer_length
;
3169 /* Queue the TRBs, even if they are zero-length */
3170 for (i
= 0; i
< num_trbs
; i
++) {
3171 field
= TRB_TYPE(TRB_NORMAL
);
3173 if (block_len
== 0) {
3174 /* A new contiguous block. */
3176 addr
= (u64
) sg_dma_address(sg
);
3177 block_len
= sg_dma_len(sg
);
3179 addr
= (u64
) urb
->transfer_dma
;
3180 block_len
= full_len
;
3182 /* TRB buffer should not cross 64KB boundaries */
3183 trb_buff_len
= TRB_BUFF_LEN_UP_TO_BOUNDARY(addr
);
3184 trb_buff_len
= min_t(unsigned int,
3188 /* Further through the contiguous block. */
3189 trb_buff_len
= block_len
;
3190 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
3191 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
3194 if (running_total
+ trb_buff_len
> full_len
)
3195 trb_buff_len
= full_len
- running_total
;
3197 /* Don't change the cycle bit of the first TRB until later */
3199 if (start_cycle
== 0)
3202 field
|= ep_ring
->cycle_state
;
3204 /* Chain all the TRBs together; clear the chain bit in the last
3205 * TRB to indicate it's the last TRB in the chain.
3207 if (i
< last_trb_num
) {
3211 if (i
== last_trb_num
)
3212 td
->last_trb
= ep_ring
->enqueue
;
3213 else if (zero_length_needed
) {
3215 urb_priv
->td
[1]->last_trb
= ep_ring
->enqueue
;
3219 /* Only set interrupt on short packet for IN endpoints */
3220 if (usb_urb_dir_in(urb
))
3223 /* Set the TRB length, TD size, and interrupter fields. */
3224 remainder
= xhci_td_remainder(xhci
, running_total
,
3225 trb_buff_len
, full_len
,
3226 urb
, num_trbs
- i
- 1);
3228 length_field
= TRB_LEN(trb_buff_len
) |
3229 TRB_TD_SIZE(remainder
) |
3232 if (i
< num_trbs
- 1)
3233 more_trbs_coming
= true;
3235 more_trbs_coming
= false;
3236 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3237 lower_32_bits(addr
),
3238 upper_32_bits(addr
),
3242 running_total
+= trb_buff_len
;
3243 addr
+= trb_buff_len
;
3244 block_len
-= trb_buff_len
;
3247 if (block_len
== 0) {
3257 check_trb_math(urb
, running_total
);
3258 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3259 start_cycle
, start_trb
);
3263 /* Caller must have locked xhci->lock */
3264 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3265 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3267 struct xhci_ring
*ep_ring
;
3270 struct usb_ctrlrequest
*setup
;
3271 struct xhci_generic_trb
*start_trb
;
3273 u32 field
, length_field
, remainder
;
3274 struct urb_priv
*urb_priv
;
3277 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3282 * Need to copy setup packet into setup TRB, so we can't use the setup
3285 if (!urb
->setup_packet
)
3288 /* 1 TRB for setup, 1 for status */
3291 * Don't need to check if we need additional event data and normal TRBs,
3292 * since data in control transfers will never get bigger than 16MB
3293 * XXX: can we get a buffer that crosses 64KB boundaries?
3295 if (urb
->transfer_buffer_length
> 0)
3297 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3298 ep_index
, urb
->stream_id
,
3299 num_trbs
, urb
, 0, mem_flags
);
3303 urb_priv
= urb
->hcpriv
;
3304 td
= urb_priv
->td
[0];
3307 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3308 * until we've finished creating all the other TRBs. The ring's cycle
3309 * state may change as we enqueue the other TRBs, so save it too.
3311 start_trb
= &ep_ring
->enqueue
->generic
;
3312 start_cycle
= ep_ring
->cycle_state
;
3314 /* Queue setup TRB - see section 6.4.1.2.1 */
3315 /* FIXME better way to translate setup_packet into two u32 fields? */
3316 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3318 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3319 if (start_cycle
== 0)
3322 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3323 if ((xhci
->hci_version
>= 0x100) || (xhci
->quirks
& XHCI_MTK_HOST
)) {
3324 if (urb
->transfer_buffer_length
> 0) {
3325 if (setup
->bRequestType
& USB_DIR_IN
)
3326 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3328 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3332 queue_trb(xhci
, ep_ring
, true,
3333 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3334 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3335 TRB_LEN(8) | TRB_INTR_TARGET(0),
3336 /* Immediate data in pointer */
3339 /* If there's data, queue data TRBs */
3340 /* Only set interrupt on short packet for IN endpoints */
3341 if (usb_urb_dir_in(urb
))
3342 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3344 field
= TRB_TYPE(TRB_DATA
);
3346 remainder
= xhci_td_remainder(xhci
, 0,
3347 urb
->transfer_buffer_length
,
3348 urb
->transfer_buffer_length
,
3351 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3352 TRB_TD_SIZE(remainder
) |
3355 if (urb
->transfer_buffer_length
> 0) {
3356 if (setup
->bRequestType
& USB_DIR_IN
)
3357 field
|= TRB_DIR_IN
;
3358 queue_trb(xhci
, ep_ring
, true,
3359 lower_32_bits(urb
->transfer_dma
),
3360 upper_32_bits(urb
->transfer_dma
),
3362 field
| ep_ring
->cycle_state
);
3365 /* Save the DMA address of the last TRB in the TD */
3366 td
->last_trb
= ep_ring
->enqueue
;
3368 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3369 /* If the device sent data, the status stage is an OUT transfer */
3370 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3374 queue_trb(xhci
, ep_ring
, false,
3378 /* Event on completion */
3379 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3381 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3382 start_cycle
, start_trb
);
3387 * The transfer burst count field of the isochronous TRB defines the number of
3388 * bursts that are required to move all packets in this TD. Only SuperSpeed
3389 * devices can burst up to bMaxBurst number of packets per service interval.
3390 * This field is zero based, meaning a value of zero in the field means one
3391 * burst. Basically, for everything but SuperSpeed devices, this field will be
3392 * zero. Only xHCI 1.0 host controllers support this field.
3394 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3395 struct urb
*urb
, unsigned int total_packet_count
)
3397 unsigned int max_burst
;
3399 if (xhci
->hci_version
< 0x100 || urb
->dev
->speed
< USB_SPEED_SUPER
)
3402 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3403 return DIV_ROUND_UP(total_packet_count
, max_burst
+ 1) - 1;
3407 * Returns the number of packets in the last "burst" of packets. This field is
3408 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3409 * the last burst packet count is equal to the total number of packets in the
3410 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3411 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3412 * contain 1 to (bMaxBurst + 1) packets.
3414 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3415 struct urb
*urb
, unsigned int total_packet_count
)
3417 unsigned int max_burst
;
3418 unsigned int residue
;
3420 if (xhci
->hci_version
< 0x100)
3423 if (urb
->dev
->speed
>= USB_SPEED_SUPER
) {
3424 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3425 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3426 residue
= total_packet_count
% (max_burst
+ 1);
3427 /* If residue is zero, the last burst contains (max_burst + 1)
3428 * number of packets, but the TLBPC field is zero-based.
3434 if (total_packet_count
== 0)
3436 return total_packet_count
- 1;
3440 * Calculates Frame ID field of the isochronous TRB identifies the
3441 * target frame that the Interval associated with this Isochronous
3442 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3444 * Returns actual frame id on success, negative value on error.
3446 static int xhci_get_isoc_frame_id(struct xhci_hcd
*xhci
,
3447 struct urb
*urb
, int index
)
3449 int start_frame
, ist
, ret
= 0;
3450 int start_frame_id
, end_frame_id
, current_frame_id
;
3452 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3453 urb
->dev
->speed
== USB_SPEED_FULL
)
3454 start_frame
= urb
->start_frame
+ index
* urb
->interval
;
3456 start_frame
= (urb
->start_frame
+ index
* urb
->interval
) >> 3;
3458 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3460 * If bit [3] of IST is cleared to '0', software can add a TRB no
3461 * later than IST[2:0] Microframes before that TRB is scheduled to
3463 * If bit [3] of IST is set to '1', software can add a TRB no later
3464 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3466 ist
= HCS_IST(xhci
->hcs_params2
) & 0x7;
3467 if (HCS_IST(xhci
->hcs_params2
) & (1 << 3))
3470 /* Software shall not schedule an Isoch TD with a Frame ID value that
3471 * is less than the Start Frame ID or greater than the End Frame ID,
3474 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3475 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3477 * Both the End Frame ID and Start Frame ID values are calculated
3478 * in microframes. When software determines the valid Frame ID value;
3479 * The End Frame ID value should be rounded down to the nearest Frame
3480 * boundary, and the Start Frame ID value should be rounded up to the
3481 * nearest Frame boundary.
3483 current_frame_id
= readl(&xhci
->run_regs
->microframe_index
);
3484 start_frame_id
= roundup(current_frame_id
+ ist
+ 1, 8);
3485 end_frame_id
= rounddown(current_frame_id
+ 895 * 8, 8);
3487 start_frame
&= 0x7ff;
3488 start_frame_id
= (start_frame_id
>> 3) & 0x7ff;
3489 end_frame_id
= (end_frame_id
>> 3) & 0x7ff;
3491 xhci_dbg(xhci
, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3492 __func__
, index
, readl(&xhci
->run_regs
->microframe_index
),
3493 start_frame_id
, end_frame_id
, start_frame
);
3495 if (start_frame_id
< end_frame_id
) {
3496 if (start_frame
> end_frame_id
||
3497 start_frame
< start_frame_id
)
3499 } else if (start_frame_id
> end_frame_id
) {
3500 if ((start_frame
> end_frame_id
&&
3501 start_frame
< start_frame_id
))
3508 if (ret
== -EINVAL
|| start_frame
== start_frame_id
) {
3509 start_frame
= start_frame_id
+ 1;
3510 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3511 urb
->dev
->speed
== USB_SPEED_FULL
)
3512 urb
->start_frame
= start_frame
;
3514 urb
->start_frame
= start_frame
<< 3;
3520 xhci_warn(xhci
, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3521 start_frame
, current_frame_id
, index
,
3522 start_frame_id
, end_frame_id
);
3523 xhci_warn(xhci
, "Ignore frame ID field, use SIA bit instead\n");
3530 /* This is for isoc transfer */
3531 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3532 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3534 struct xhci_ring
*ep_ring
;
3535 struct urb_priv
*urb_priv
;
3537 int num_tds
, trbs_per_td
;
3538 struct xhci_generic_trb
*start_trb
;
3541 u32 field
, length_field
;
3542 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3543 u64 start_addr
, addr
;
3545 bool more_trbs_coming
;
3546 struct xhci_virt_ep
*xep
;
3549 xep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3550 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3552 num_tds
= urb
->number_of_packets
;
3554 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3557 start_addr
= (u64
) urb
->transfer_dma
;
3558 start_trb
= &ep_ring
->enqueue
->generic
;
3559 start_cycle
= ep_ring
->cycle_state
;
3561 urb_priv
= urb
->hcpriv
;
3562 /* Queue the TRBs for each TD, even if they are zero-length */
3563 for (i
= 0; i
< num_tds
; i
++) {
3564 unsigned int total_pkt_count
, max_pkt
;
3565 unsigned int burst_count
, last_burst_pkt_count
;
3570 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3571 td_len
= urb
->iso_frame_desc
[i
].length
;
3572 td_remain_len
= td_len
;
3573 max_pkt
= GET_MAX_PACKET(usb_endpoint_maxp(&urb
->ep
->desc
));
3574 total_pkt_count
= DIV_ROUND_UP(td_len
, max_pkt
);
3576 /* A zero-length transfer still involves at least one packet. */
3577 if (total_pkt_count
== 0)
3579 burst_count
= xhci_get_burst_count(xhci
, urb
, total_pkt_count
);
3580 last_burst_pkt_count
= xhci_get_last_burst_packet_count(xhci
,
3581 urb
, total_pkt_count
);
3583 trbs_per_td
= count_isoc_trbs_needed(urb
, i
);
3585 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3586 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3592 td
= urb_priv
->td
[i
];
3594 /* use SIA as default, if frame id is used overwrite it */
3595 sia_frame_id
= TRB_SIA
;
3596 if (!(urb
->transfer_flags
& URB_ISO_ASAP
) &&
3597 HCC_CFC(xhci
->hcc_params
)) {
3598 frame_id
= xhci_get_isoc_frame_id(xhci
, urb
, i
);
3600 sia_frame_id
= TRB_FRAME_ID(frame_id
);
3603 * Set isoc specific data for the first TRB in a TD.
3604 * Prevent HW from getting the TRBs by keeping the cycle state
3605 * inverted in the first TDs isoc TRB.
3607 field
= TRB_TYPE(TRB_ISOC
) |
3608 TRB_TLBPC(last_burst_pkt_count
) |
3610 (i
? ep_ring
->cycle_state
: !start_cycle
);
3612 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3613 if (!xep
->use_extended_tbc
)
3614 field
|= TRB_TBC(burst_count
);
3616 /* fill the rest of the TRB fields, and remaining normal TRBs */
3617 for (j
= 0; j
< trbs_per_td
; j
++) {
3620 /* only first TRB is isoc, overwrite otherwise */
3622 field
= TRB_TYPE(TRB_NORMAL
) |
3623 ep_ring
->cycle_state
;
3625 /* Only set interrupt on short packet for IN EPs */
3626 if (usb_urb_dir_in(urb
))
3629 /* Set the chain bit for all except the last TRB */
3630 if (j
< trbs_per_td
- 1) {
3631 more_trbs_coming
= true;
3634 more_trbs_coming
= false;
3635 td
->last_trb
= ep_ring
->enqueue
;
3637 /* set BEI, except for the last TD */
3638 if (xhci
->hci_version
>= 0x100 &&
3639 !(xhci
->quirks
& XHCI_AVOID_BEI
) &&
3643 /* Calculate TRB length */
3644 trb_buff_len
= TRB_BUFF_LEN_UP_TO_BOUNDARY(addr
);
3645 if (trb_buff_len
> td_remain_len
)
3646 trb_buff_len
= td_remain_len
;
3648 /* Set the TRB length, TD size, & interrupter fields. */
3649 remainder
= xhci_td_remainder(xhci
, running_total
,
3650 trb_buff_len
, td_len
,
3651 urb
, trbs_per_td
- j
- 1);
3653 length_field
= TRB_LEN(trb_buff_len
) |
3656 /* xhci 1.1 with ETE uses TD Size field for TBC */
3657 if (first_trb
&& xep
->use_extended_tbc
)
3658 length_field
|= TRB_TD_SIZE_TBC(burst_count
);
3660 length_field
|= TRB_TD_SIZE(remainder
);
3663 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3664 lower_32_bits(addr
),
3665 upper_32_bits(addr
),
3668 running_total
+= trb_buff_len
;
3670 addr
+= trb_buff_len
;
3671 td_remain_len
-= trb_buff_len
;
3674 /* Check TD length */
3675 if (running_total
!= td_len
) {
3676 xhci_err(xhci
, "ISOC TD length unmatch\n");
3682 /* store the next frame id */
3683 if (HCC_CFC(xhci
->hcc_params
))
3684 xep
->next_frame_id
= urb
->start_frame
+ num_tds
* urb
->interval
;
3686 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3687 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3688 usb_amd_quirk_pll_disable();
3690 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3692 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3693 start_cycle
, start_trb
);
3696 /* Clean up a partially enqueued isoc transfer. */
3698 for (i
--; i
>= 0; i
--)
3699 list_del_init(&urb_priv
->td
[i
]->td_list
);
3701 /* Use the first TD as a temporary variable to turn the TDs we've queued
3702 * into No-ops with a software-owned cycle bit. That way the hardware
3703 * won't accidentally start executing bogus TDs when we partially
3704 * overwrite them. td->first_trb and td->start_seg are already set.
3706 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3707 /* Every TRB except the first & last will have its cycle bit flipped. */
3708 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3710 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3711 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3712 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3713 ep_ring
->cycle_state
= start_cycle
;
3714 ep_ring
->num_trbs_free
= ep_ring
->num_trbs_free_temp
;
3715 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3720 * Check transfer ring to guarantee there is enough room for the urb.
3721 * Update ISO URB start_frame and interval.
3722 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3723 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3724 * Contiguous Frame ID is not supported by HC.
3726 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3727 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3729 struct xhci_virt_device
*xdev
;
3730 struct xhci_ring
*ep_ring
;
3731 struct xhci_ep_ctx
*ep_ctx
;
3733 int num_tds
, num_trbs
, i
;
3735 struct xhci_virt_ep
*xep
;
3738 xdev
= xhci
->devs
[slot_id
];
3739 xep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3740 ep_ring
= xdev
->eps
[ep_index
].ring
;
3741 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3744 num_tds
= urb
->number_of_packets
;
3745 for (i
= 0; i
< num_tds
; i
++)
3746 num_trbs
+= count_isoc_trbs_needed(urb
, i
);
3748 /* Check the ring to guarantee there is enough room for the whole urb.
3749 * Do not insert any td of the urb to the ring if the check failed.
3751 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3752 num_trbs
, mem_flags
);
3757 * Check interval value. This should be done before we start to
3758 * calculate the start frame value.
3760 check_interval(xhci
, urb
, ep_ctx
);
3762 /* Calculate the start frame and put it in urb->start_frame. */
3763 if (HCC_CFC(xhci
->hcc_params
) && !list_empty(&ep_ring
->td_list
)) {
3764 if ((le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
3766 urb
->start_frame
= xep
->next_frame_id
;
3767 goto skip_start_over
;
3771 start_frame
= readl(&xhci
->run_regs
->microframe_index
);
3772 start_frame
&= 0x3fff;
3774 * Round up to the next frame and consider the time before trb really
3775 * gets scheduled by hardare.
3777 ist
= HCS_IST(xhci
->hcs_params2
) & 0x7;
3778 if (HCS_IST(xhci
->hcs_params2
) & (1 << 3))
3780 start_frame
+= ist
+ XHCI_CFC_DELAY
;
3781 start_frame
= roundup(start_frame
, 8);
3784 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3785 * is greate than 8 microframes.
3787 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3788 urb
->dev
->speed
== USB_SPEED_FULL
) {
3789 start_frame
= roundup(start_frame
, urb
->interval
<< 3);
3790 urb
->start_frame
= start_frame
>> 3;
3792 start_frame
= roundup(start_frame
, urb
->interval
);
3793 urb
->start_frame
= start_frame
;
3797 ep_ring
->num_trbs_free_temp
= ep_ring
->num_trbs_free
;
3799 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3802 /**** Command Ring Operations ****/
3804 /* Generic function for queueing a command TRB on the command ring.
3805 * Check to make sure there's room on the command ring for one command TRB.
3806 * Also check that there's room reserved for commands that must not fail.
3807 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3808 * then only check for the number of reserved spots.
3809 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3810 * because the command event handler may want to resubmit a failed command.
3812 static int queue_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3813 u32 field1
, u32 field2
,
3814 u32 field3
, u32 field4
, bool command_must_succeed
)
3816 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3819 if ((xhci
->xhc_state
& XHCI_STATE_DYING
) ||
3820 (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
3821 xhci_dbg(xhci
, "xHCI dying or halted, can't queue_command\n");
3825 if (!command_must_succeed
)
3828 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3829 reserved_trbs
, GFP_ATOMIC
);
3831 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3832 if (command_must_succeed
)
3833 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3834 "unfailable commands failed.\n");
3838 cmd
->command_trb
= xhci
->cmd_ring
->enqueue
;
3839 list_add_tail(&cmd
->cmd_list
, &xhci
->cmd_list
);
3841 /* if there are no other commands queued we start the timeout timer */
3842 if (xhci
->cmd_list
.next
== &cmd
->cmd_list
&&
3843 !timer_pending(&xhci
->cmd_timer
)) {
3844 xhci
->current_cmd
= cmd
;
3845 mod_timer(&xhci
->cmd_timer
, jiffies
+ XHCI_CMD_DEFAULT_TIMEOUT
);
3848 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
3849 field4
| xhci
->cmd_ring
->cycle_state
);
3853 /* Queue a slot enable or disable request on the command ring */
3854 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3855 u32 trb_type
, u32 slot_id
)
3857 return queue_command(xhci
, cmd
, 0, 0, 0,
3858 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3861 /* Queue an address device command TRB */
3862 int xhci_queue_address_device(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3863 dma_addr_t in_ctx_ptr
, u32 slot_id
, enum xhci_setup_dev setup
)
3865 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
3866 upper_32_bits(in_ctx_ptr
), 0,
3867 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
)
3868 | (setup
== SETUP_CONTEXT_ONLY
? TRB_BSR
: 0), false);
3871 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3872 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3874 return queue_command(xhci
, cmd
, field1
, field2
, field3
, field4
, false);
3877 /* Queue a reset device command TRB */
3878 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3881 return queue_command(xhci
, cmd
, 0, 0, 0,
3882 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3886 /* Queue a configure endpoint command TRB */
3887 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
,
3888 struct xhci_command
*cmd
, dma_addr_t in_ctx_ptr
,
3889 u32 slot_id
, bool command_must_succeed
)
3891 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
3892 upper_32_bits(in_ctx_ptr
), 0,
3893 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3894 command_must_succeed
);
3897 /* Queue an evaluate context command TRB */
3898 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3899 dma_addr_t in_ctx_ptr
, u32 slot_id
, bool command_must_succeed
)
3901 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
3902 upper_32_bits(in_ctx_ptr
), 0,
3903 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3904 command_must_succeed
);
3908 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3909 * activity on an endpoint that is about to be suspended.
3911 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3912 int slot_id
, unsigned int ep_index
, int suspend
)
3914 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3915 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3916 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3917 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3919 return queue_command(xhci
, cmd
, 0, 0, 0,
3920 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3923 /* Set Transfer Ring Dequeue Pointer command */
3924 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
3925 unsigned int slot_id
, unsigned int ep_index
,
3926 unsigned int stream_id
,
3927 struct xhci_dequeue_state
*deq_state
)
3930 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3931 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3932 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
3934 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
3935 struct xhci_virt_ep
*ep
;
3936 struct xhci_command
*cmd
;
3939 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
3940 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
3941 deq_state
->new_deq_seg
,
3942 (unsigned long long)deq_state
->new_deq_seg
->dma
,
3943 deq_state
->new_deq_ptr
,
3944 (unsigned long long)xhci_trb_virt_to_dma(
3945 deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
3946 deq_state
->new_cycle_state
);
3948 addr
= xhci_trb_virt_to_dma(deq_state
->new_deq_seg
,
3949 deq_state
->new_deq_ptr
);
3951 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3952 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
3953 deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
);
3956 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3957 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
3958 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3959 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
3963 /* This function gets called from contexts where it cannot sleep */
3964 cmd
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
3966 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
3970 ep
->queued_deq_seg
= deq_state
->new_deq_seg
;
3971 ep
->queued_deq_ptr
= deq_state
->new_deq_ptr
;
3973 trb_sct
= SCT_FOR_TRB(SCT_PRI_TR
);
3974 ret
= queue_command(xhci
, cmd
,
3975 lower_32_bits(addr
) | trb_sct
| deq_state
->new_cycle_state
,
3976 upper_32_bits(addr
), trb_stream_id
,
3977 trb_slot_id
| trb_ep_index
| type
, false);
3979 xhci_free_command(xhci
, cmd
);
3983 /* Stop the TD queueing code from ringing the doorbell until
3984 * this command completes. The HC won't set the dequeue pointer
3985 * if the ring is running, and ringing the doorbell starts the
3988 ep
->ep_state
|= SET_DEQ_PENDING
;
3991 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3992 int slot_id
, unsigned int ep_index
)
3994 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3995 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3996 u32 type
= TRB_TYPE(TRB_RESET_EP
);
3998 return queue_command(xhci
, cmd
, 0, 0, 0,
3999 trb_slot_id
| trb_ep_index
| type
, false);