2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
72 struct xhci_virt_device
*virt_dev
,
73 struct xhci_event_cmd
*event
);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
82 unsigned long segment_offset
;
84 if (!seg
|| !trb
|| trb
< seg
->trbs
)
87 segment_offset
= trb
- seg
->trbs
;
88 if (segment_offset
> TRBS_PER_SEGMENT
)
90 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
97 struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 if (ring
== xhci
->event_ring
)
100 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
101 (seg
->next
== xhci
->event_ring
->first_seg
);
103 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
111 struct xhci_segment
*seg
, union xhci_trb
*trb
)
113 if (ring
== xhci
->event_ring
)
114 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
116 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
119 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
121 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
122 return TRB_TYPE_LINK_LE32(link
->control
);
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd
*xhci
,
130 struct xhci_ring
*ring
,
131 struct xhci_segment
**seg
,
132 union xhci_trb
**trb
)
134 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
136 *trb
= ((*seg
)->trbs
);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
148 union xhci_trb
*next
;
149 unsigned long long addr
;
153 /* If this is not event ring, there is one more usable TRB */
154 if (ring
->type
!= TYPE_EVENT
&&
155 !last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
))
156 ring
->num_trbs_free
++;
157 next
= ++(ring
->dequeue
);
159 /* Update the dequeue pointer further if that was a link TRB or we're at
160 * the end of an event ring segment (which doesn't have link TRBS)
162 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
163 if (ring
->type
== TYPE_EVENT
&& last_trb_on_last_seg(xhci
,
164 ring
, ring
->deq_seg
, next
)) {
165 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
167 ring
->deq_seg
= ring
->deq_seg
->next
;
168 ring
->dequeue
= ring
->deq_seg
->trbs
;
169 next
= ring
->dequeue
;
171 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
175 * See Cycle bit rules. SW is the consumer for the event ring only.
176 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
178 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
179 * chain bit is set), then set the chain bit in all the following link TRBs.
180 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
181 * have their chain bit cleared (so that each Link TRB is a separate TD).
183 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
184 * set, but other sections talk about dealing with the chain bit set. This was
185 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
186 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
188 * @more_trbs_coming: Will you enqueue more TRBs before calling
189 * prepare_transfer()?
191 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
192 bool more_trbs_coming
)
195 union xhci_trb
*next
;
196 unsigned long long addr
;
198 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring
->type
!= TYPE_EVENT
&&
201 !last_trb(xhci
, ring
, ring
->enq_seg
, ring
->enqueue
))
202 ring
->num_trbs_free
--;
203 next
= ++(ring
->enqueue
);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
210 if (ring
->type
!= TYPE_EVENT
) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain
&& !more_trbs_coming
)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring
->type
== TYPE_ISOC
&&
228 (xhci
->quirks
& XHCI_AMD_0x96_HOST
))
229 && !xhci_link_trb_quirk(xhci
)) {
230 next
->link
.control
&=
231 cpu_to_le32(~TRB_CHAIN
);
232 next
->link
.control
|=
235 /* Give this link TRB to the hardware */
237 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
241 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
244 ring
->enq_seg
= ring
->enq_seg
->next
;
245 ring
->enqueue
= ring
->enq_seg
->trbs
;
246 next
= ring
->enqueue
;
248 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
252 * Check to see if there's room to enqueue num_trbs on the ring and make sure
253 * enqueue pointer will not advance into dequeue segment. See rules above.
255 static inline int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
256 unsigned int num_trbs
)
258 int num_trbs_in_deq_seg
;
260 if (ring
->num_trbs_free
< num_trbs
)
263 if (ring
->type
!= TYPE_COMMAND
&& ring
->type
!= TYPE_EVENT
) {
264 num_trbs_in_deq_seg
= ring
->dequeue
- ring
->deq_seg
->trbs
;
265 if (ring
->num_trbs_free
< num_trbs
+ num_trbs_in_deq_seg
)
272 /* Ring the host controller doorbell after placing a command on the ring */
273 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
275 xhci_dbg(xhci
, "// Ding dong!\n");
276 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
277 /* Flush PCI posted writes */
278 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
281 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
282 unsigned int slot_id
,
283 unsigned int ep_index
,
284 unsigned int stream_id
)
286 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
287 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
288 unsigned int ep_state
= ep
->ep_state
;
290 /* Don't ring the doorbell for this endpoint if there are pending
291 * cancellations because we don't want to interrupt processing.
292 * We don't want to restart any stream rings if there's a set dequeue
293 * pointer command pending because the device can choose to start any
294 * stream once the endpoint is on the HW schedule.
295 * FIXME - check all the stream rings for pending cancellations.
297 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
298 (ep_state
& EP_HALTED
))
300 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
301 /* The CPU has better things to do at this point than wait for a
302 * write-posting flush. It'll get there soon enough.
306 /* Ring the doorbell for any rings with pending URBs */
307 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
308 unsigned int slot_id
,
309 unsigned int ep_index
)
311 unsigned int stream_id
;
312 struct xhci_virt_ep
*ep
;
314 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
316 /* A ring has pending URBs if its TD list is not empty */
317 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
318 if (!(list_empty(&ep
->ring
->td_list
)))
319 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
323 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
325 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
326 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
327 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
333 * Find the segment that trb is in. Start searching in start_seg.
334 * If we must move past a segment that has a link TRB with a toggle cycle state
335 * bit set, then we will toggle the value pointed at by cycle_state.
337 static struct xhci_segment
*find_trb_seg(
338 struct xhci_segment
*start_seg
,
339 union xhci_trb
*trb
, int *cycle_state
)
341 struct xhci_segment
*cur_seg
= start_seg
;
342 struct xhci_generic_trb
*generic_trb
;
344 while (cur_seg
->trbs
> trb
||
345 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
346 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
347 if (generic_trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
))
349 cur_seg
= cur_seg
->next
;
350 if (cur_seg
== start_seg
)
351 /* Looped over the entire list. Oops! */
358 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
359 unsigned int slot_id
, unsigned int ep_index
,
360 unsigned int stream_id
)
362 struct xhci_virt_ep
*ep
;
364 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
365 /* Common case: no streams */
366 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
369 if (stream_id
== 0) {
371 "WARN: Slot ID %u, ep index %u has streams, "
372 "but URB has no stream ID.\n",
377 if (stream_id
< ep
->stream_info
->num_streams
)
378 return ep
->stream_info
->stream_rings
[stream_id
];
381 "WARN: Slot ID %u, ep index %u has "
382 "stream IDs 1 to %u allocated, "
383 "but stream ID %u is requested.\n",
385 ep
->stream_info
->num_streams
- 1,
390 /* Get the right ring for the given URB.
391 * If the endpoint supports streams, boundary check the URB's stream ID.
392 * If the endpoint doesn't support streams, return the singular endpoint ring.
394 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
397 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
398 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
402 * Move the xHC's endpoint ring dequeue pointer past cur_td.
403 * Record the new state of the xHC's endpoint ring dequeue segment,
404 * dequeue pointer, and new consumer cycle state in state.
405 * Update our internal representation of the ring's dequeue pointer.
407 * We do this in three jumps:
408 * - First we update our new ring state to be the same as when the xHC stopped.
409 * - Then we traverse the ring to find the segment that contains
410 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
411 * any link TRBs with the toggle cycle bit set.
412 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
413 * if we've moved it past a link TRB with the toggle cycle bit set.
415 * Some of the uses of xhci_generic_trb are grotty, but if they're done
416 * with correct __le32 accesses they should work fine. Only users of this are
419 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
420 unsigned int slot_id
, unsigned int ep_index
,
421 unsigned int stream_id
, struct xhci_td
*cur_td
,
422 struct xhci_dequeue_state
*state
)
424 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
425 struct xhci_ring
*ep_ring
;
426 struct xhci_generic_trb
*trb
;
427 struct xhci_ep_ctx
*ep_ctx
;
430 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
431 ep_index
, stream_id
);
433 xhci_warn(xhci
, "WARN can't find new dequeue state "
434 "for invalid stream ID %u.\n",
438 state
->new_cycle_state
= 0;
439 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
440 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
441 dev
->eps
[ep_index
].stopped_trb
,
442 &state
->new_cycle_state
);
443 if (!state
->new_deq_seg
) {
448 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
449 xhci_dbg(xhci
, "Finding endpoint context\n");
450 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
451 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
453 state
->new_deq_ptr
= cur_td
->last_trb
;
454 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
455 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
457 &state
->new_cycle_state
);
458 if (!state
->new_deq_seg
) {
463 trb
= &state
->new_deq_ptr
->generic
;
464 if (TRB_TYPE_LINK_LE32(trb
->field
[3]) &&
465 (trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
)))
466 state
->new_cycle_state
^= 0x1;
467 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
470 * If there is only one segment in a ring, find_trb_seg()'s while loop
471 * will not run, and it will return before it has a chance to see if it
472 * needs to toggle the cycle bit. It can't tell if the stalled transfer
473 * ended just before the link TRB on a one-segment ring, or if the TD
474 * wrapped around the top of the ring, because it doesn't have the TD in
475 * question. Look for the one-segment case where stalled TRB's address
476 * is greater than the new dequeue pointer address.
478 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
479 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
480 state
->new_cycle_state
^= 0x1;
481 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
483 /* Don't update the ring cycle state for the producer (us). */
484 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
486 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
487 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
488 (unsigned long long) addr
);
491 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
492 * (The last TRB actually points to the ring enqueue pointer, which is not part
493 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
495 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
496 struct xhci_td
*cur_td
, bool flip_cycle
)
498 struct xhci_segment
*cur_seg
;
499 union xhci_trb
*cur_trb
;
501 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
503 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
504 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
505 /* Unchain any chained Link TRBs, but
506 * leave the pointers intact.
508 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
509 /* Flip the cycle bit (link TRBs can't be the first
513 cur_trb
->generic
.field
[3] ^=
514 cpu_to_le32(TRB_CYCLE
);
515 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
516 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
517 "in seg %p (0x%llx dma)\n",
519 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
521 (unsigned long long)cur_seg
->dma
);
523 cur_trb
->generic
.field
[0] = 0;
524 cur_trb
->generic
.field
[1] = 0;
525 cur_trb
->generic
.field
[2] = 0;
526 /* Preserve only the cycle bit of this TRB */
527 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
528 /* Flip the cycle bit except on the first or last TRB */
529 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
530 cur_trb
!= cur_td
->last_trb
)
531 cur_trb
->generic
.field
[3] ^=
532 cpu_to_le32(TRB_CYCLE
);
533 cur_trb
->generic
.field
[3] |= cpu_to_le32(
534 TRB_TYPE(TRB_TR_NOOP
));
535 xhci_dbg(xhci
, "TRB to noop at offset 0x%llx\n",
537 xhci_trb_virt_to_dma(cur_seg
, cur_trb
));
539 if (cur_trb
== cur_td
->last_trb
)
544 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
545 unsigned int ep_index
, unsigned int stream_id
,
546 struct xhci_segment
*deq_seg
,
547 union xhci_trb
*deq_ptr
, u32 cycle_state
);
549 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
550 unsigned int slot_id
, unsigned int ep_index
,
551 unsigned int stream_id
,
552 struct xhci_dequeue_state
*deq_state
)
554 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
556 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
557 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
558 deq_state
->new_deq_seg
,
559 (unsigned long long)deq_state
->new_deq_seg
->dma
,
560 deq_state
->new_deq_ptr
,
561 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
562 deq_state
->new_cycle_state
);
563 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
564 deq_state
->new_deq_seg
,
565 deq_state
->new_deq_ptr
,
566 (u32
) deq_state
->new_cycle_state
);
567 /* Stop the TD queueing code from ringing the doorbell until
568 * this command completes. The HC won't set the dequeue pointer
569 * if the ring is running, and ringing the doorbell starts the
572 ep
->ep_state
|= SET_DEQ_PENDING
;
575 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
576 struct xhci_virt_ep
*ep
)
578 ep
->ep_state
&= ~EP_HALT_PENDING
;
579 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
580 * timer is running on another CPU, we don't decrement stop_cmds_pending
581 * (since we didn't successfully stop the watchdog timer).
583 if (del_timer(&ep
->stop_cmd_timer
))
584 ep
->stop_cmds_pending
--;
587 /* Must be called with xhci->lock held in interrupt context */
588 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
589 struct xhci_td
*cur_td
, int status
, char *adjective
)
593 struct urb_priv
*urb_priv
;
596 urb_priv
= urb
->hcpriv
;
598 hcd
= bus_to_hcd(urb
->dev
->bus
);
600 /* Only giveback urb when this is the last td in urb */
601 if (urb_priv
->td_cnt
== urb_priv
->length
) {
602 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
603 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
604 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
605 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
606 usb_amd_quirk_pll_enable();
609 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
611 spin_unlock(&xhci
->lock
);
612 usb_hcd_giveback_urb(hcd
, urb
, status
);
613 xhci_urb_free_priv(xhci
, urb_priv
);
614 spin_lock(&xhci
->lock
);
619 * When we get a command completion for a Stop Endpoint Command, we need to
620 * unlink any cancelled TDs from the ring. There are two ways to do that:
622 * 1. If the HW was in the middle of processing the TD that needs to be
623 * cancelled, then we must move the ring's dequeue pointer past the last TRB
624 * in the TD with a Set Dequeue Pointer Command.
625 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
626 * bit cleared) so that the HW will skip over them.
628 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
629 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
631 unsigned int slot_id
;
632 unsigned int ep_index
;
633 struct xhci_virt_device
*virt_dev
;
634 struct xhci_ring
*ep_ring
;
635 struct xhci_virt_ep
*ep
;
636 struct list_head
*entry
;
637 struct xhci_td
*cur_td
= NULL
;
638 struct xhci_td
*last_unlinked_td
;
640 struct xhci_dequeue_state deq_state
;
642 if (unlikely(TRB_TO_SUSPEND_PORT(
643 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
644 slot_id
= TRB_TO_SLOT_ID(
645 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
646 virt_dev
= xhci
->devs
[slot_id
];
648 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
651 xhci_warn(xhci
, "Stop endpoint command "
652 "completion for disabled slot %u\n",
657 memset(&deq_state
, 0, sizeof(deq_state
));
658 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
659 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
660 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
662 if (list_empty(&ep
->cancelled_td_list
)) {
663 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
664 ep
->stopped_td
= NULL
;
665 ep
->stopped_trb
= NULL
;
666 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
670 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
671 * We have the xHCI lock, so nothing can modify this list until we drop
672 * it. We're also in the event handler, so we can't get re-interrupted
673 * if another Stop Endpoint command completes
675 list_for_each(entry
, &ep
->cancelled_td_list
) {
676 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
677 xhci_dbg(xhci
, "Removing canceled TD starting at 0x%llx (dma).\n",
678 (unsigned long long)xhci_trb_virt_to_dma(
679 cur_td
->start_seg
, cur_td
->first_trb
));
680 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
682 /* This shouldn't happen unless a driver is mucking
683 * with the stream ID after submission. This will
684 * leave the TD on the hardware ring, and the hardware
685 * will try to execute it, and may access a buffer
686 * that has already been freed. In the best case, the
687 * hardware will execute it, and the event handler will
688 * ignore the completion event for that TD, since it was
689 * removed from the td_list for that endpoint. In
690 * short, don't muck with the stream ID after
693 xhci_warn(xhci
, "WARN Cancelled URB %p "
694 "has invalid stream ID %u.\n",
696 cur_td
->urb
->stream_id
);
697 goto remove_finished_td
;
700 * If we stopped on the TD we need to cancel, then we have to
701 * move the xHC endpoint ring dequeue pointer past this TD.
703 if (cur_td
== ep
->stopped_td
)
704 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
705 cur_td
->urb
->stream_id
,
708 td_to_noop(xhci
, ep_ring
, cur_td
, false);
711 * The event handler won't see a completion for this TD anymore,
712 * so remove it from the endpoint ring's TD list. Keep it in
713 * the cancelled TD list for URB completion later.
715 list_del_init(&cur_td
->td_list
);
717 last_unlinked_td
= cur_td
;
718 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
720 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
721 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
722 xhci_queue_new_dequeue_state(xhci
,
724 ep
->stopped_td
->urb
->stream_id
,
726 xhci_ring_cmd_db(xhci
);
728 /* Otherwise ring the doorbell(s) to restart queued transfers */
729 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
731 ep
->stopped_td
= NULL
;
732 ep
->stopped_trb
= NULL
;
735 * Drop the lock and complete the URBs in the cancelled TD list.
736 * New TDs to be cancelled might be added to the end of the list before
737 * we can complete all the URBs for the TDs we already unlinked.
738 * So stop when we've completed the URB for the last TD we unlinked.
741 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
742 struct xhci_td
, cancelled_td_list
);
743 list_del_init(&cur_td
->cancelled_td_list
);
745 /* Clean up the cancelled URB */
746 /* Doesn't matter what we pass for status, since the core will
747 * just overwrite it (because the URB has been unlinked).
749 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
751 /* Stop processing the cancelled list if the watchdog timer is
754 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
756 } while (cur_td
!= last_unlinked_td
);
758 /* Return to the event handler with xhci->lock re-acquired */
761 /* Watchdog timer function for when a stop endpoint command fails to complete.
762 * In this case, we assume the host controller is broken or dying or dead. The
763 * host may still be completing some other events, so we have to be careful to
764 * let the event ring handler and the URB dequeueing/enqueueing functions know
765 * through xhci->state.
767 * The timer may also fire if the host takes a very long time to respond to the
768 * command, and the stop endpoint command completion handler cannot delete the
769 * timer before the timer function is called. Another endpoint cancellation may
770 * sneak in before the timer function can grab the lock, and that may queue
771 * another stop endpoint command and add the timer back. So we cannot use a
772 * simple flag to say whether there is a pending stop endpoint command for a
773 * particular endpoint.
775 * Instead we use a combination of that flag and a counter for the number of
776 * pending stop endpoint commands. If the timer is the tail end of the last
777 * stop endpoint command, and the endpoint's command is still pending, we assume
780 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
782 struct xhci_hcd
*xhci
;
783 struct xhci_virt_ep
*ep
;
784 struct xhci_virt_ep
*temp_ep
;
785 struct xhci_ring
*ring
;
786 struct xhci_td
*cur_td
;
790 ep
= (struct xhci_virt_ep
*) arg
;
793 spin_lock_irqsave(&xhci
->lock
, flags
);
795 ep
->stop_cmds_pending
--;
796 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
797 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
798 "xHCI as DYING, exiting.\n");
799 spin_unlock_irqrestore(&xhci
->lock
, flags
);
802 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
803 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
805 spin_unlock_irqrestore(&xhci
->lock
, flags
);
809 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
810 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
811 /* Oops, HC is dead or dying or at least not responding to the stop
814 xhci
->xhc_state
|= XHCI_STATE_DYING
;
815 /* Disable interrupts from the host controller and start halting it */
817 spin_unlock_irqrestore(&xhci
->lock
, flags
);
819 ret
= xhci_halt(xhci
);
821 spin_lock_irqsave(&xhci
->lock
, flags
);
823 /* This is bad; the host is not responding to commands and it's
824 * not allowing itself to be halted. At least interrupts are
825 * disabled. If we call usb_hc_died(), it will attempt to
826 * disconnect all device drivers under this host. Those
827 * disconnect() methods will wait for all URBs to be unlinked,
828 * so we must complete them.
830 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
831 xhci_warn(xhci
, "Completing active URBs anyway.\n");
832 /* We could turn all TDs on the rings to no-ops. This won't
833 * help if the host has cached part of the ring, and is slow if
834 * we want to preserve the cycle bit. Skip it and hope the host
835 * doesn't touch the memory.
838 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
841 for (j
= 0; j
< 31; j
++) {
842 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
843 ring
= temp_ep
->ring
;
846 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
847 "ep index %u\n", i
, j
);
848 while (!list_empty(&ring
->td_list
)) {
849 cur_td
= list_first_entry(&ring
->td_list
,
852 list_del_init(&cur_td
->td_list
);
853 if (!list_empty(&cur_td
->cancelled_td_list
))
854 list_del_init(&cur_td
->cancelled_td_list
);
855 xhci_giveback_urb_in_irq(xhci
, cur_td
,
856 -ESHUTDOWN
, "killed");
858 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
859 cur_td
= list_first_entry(
860 &temp_ep
->cancelled_td_list
,
863 list_del_init(&cur_td
->cancelled_td_list
);
864 xhci_giveback_urb_in_irq(xhci
, cur_td
,
865 -ESHUTDOWN
, "killed");
869 spin_unlock_irqrestore(&xhci
->lock
, flags
);
870 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
871 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
872 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
876 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
877 struct xhci_virt_device
*dev
,
878 struct xhci_ring
*ep_ring
,
879 unsigned int ep_index
)
881 union xhci_trb
*dequeue_temp
;
882 int num_trbs_free_temp
;
885 num_trbs_free_temp
= ep_ring
->num_trbs_free
;
886 dequeue_temp
= ep_ring
->dequeue
;
888 /* If we get two back-to-back stalls, and the first stalled transfer
889 * ends just before a link TRB, the dequeue pointer will be left on
890 * the link TRB by the code in the while loop. So we have to update
891 * the dequeue pointer one segment further, or we'll jump off
892 * the segment into la-la-land.
894 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
, ep_ring
->dequeue
)) {
895 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
896 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
899 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
900 /* We have more usable TRBs */
901 ep_ring
->num_trbs_free
++;
903 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
,
905 if (ep_ring
->dequeue
==
906 dev
->eps
[ep_index
].queued_deq_ptr
)
908 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
909 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
911 if (ep_ring
->dequeue
== dequeue_temp
) {
918 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
919 ep_ring
->num_trbs_free
= num_trbs_free_temp
;
924 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
925 * we need to clear the set deq pending flag in the endpoint ring state, so that
926 * the TD queueing code can ring the doorbell again. We also need to ring the
927 * endpoint doorbell to restart the ring, but only if there aren't more
928 * cancellations pending.
930 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
931 struct xhci_event_cmd
*event
,
934 unsigned int slot_id
;
935 unsigned int ep_index
;
936 unsigned int stream_id
;
937 struct xhci_ring
*ep_ring
;
938 struct xhci_virt_device
*dev
;
939 struct xhci_ep_ctx
*ep_ctx
;
940 struct xhci_slot_ctx
*slot_ctx
;
942 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
943 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
944 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
945 dev
= xhci
->devs
[slot_id
];
947 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
949 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
950 "freed stream ID %u\n",
952 /* XXX: Harmless??? */
953 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
957 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
958 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
960 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
961 unsigned int ep_state
;
962 unsigned int slot_state
;
964 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
966 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
967 "of stream ID configuration\n");
970 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
971 "to incorrect slot or ep state.\n");
972 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
973 ep_state
&= EP_STATE_MASK
;
974 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
975 slot_state
= GET_SLOT_STATE(slot_state
);
976 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
977 slot_state
, ep_state
);
980 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
981 "slot %u was not enabled.\n", slot_id
);
984 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
985 "completion code of %u.\n",
986 GET_COMP_CODE(le32_to_cpu(event
->status
)));
989 /* OK what do we do now? The endpoint state is hosed, and we
990 * should never get to this point if the synchronization between
991 * queueing, and endpoint state are correct. This might happen
992 * if the device gets disconnected after we've finished
993 * cancelling URBs, which might not be an error...
996 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
997 le64_to_cpu(ep_ctx
->deq
));
998 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
999 dev
->eps
[ep_index
].queued_deq_ptr
) ==
1000 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
1001 /* Update the ring's dequeue segment and dequeue pointer
1002 * to reflect the new position.
1004 update_ring_for_set_deq_completion(xhci
, dev
,
1007 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
1008 "Ptr command & xHCI internal state.\n");
1009 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1010 dev
->eps
[ep_index
].queued_deq_seg
,
1011 dev
->eps
[ep_index
].queued_deq_ptr
);
1015 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1016 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
1017 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
1018 /* Restart any rings with pending URBs */
1019 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1022 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
1023 struct xhci_event_cmd
*event
,
1024 union xhci_trb
*trb
)
1027 unsigned int ep_index
;
1029 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1030 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1031 /* This command will only fail if the endpoint wasn't halted,
1032 * but we don't care.
1034 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
1035 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1037 /* HW with the reset endpoint quirk needs to have a configure endpoint
1038 * command complete before the endpoint can be used. Queue that here
1039 * because the HW can't handle two commands being queued in a row.
1041 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1042 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
1043 xhci_queue_configure_endpoint(xhci
,
1044 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1046 xhci_ring_cmd_db(xhci
);
1048 /* Clear our internal halted state and restart the ring(s) */
1049 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1050 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1054 /* Check to see if a command in the device's command queue matches this one.
1055 * Signal the completion or free the command, and return 1. Return 0 if the
1056 * completed command isn't at the head of the command list.
1058 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1059 struct xhci_virt_device
*virt_dev
,
1060 struct xhci_event_cmd
*event
)
1062 struct xhci_command
*command
;
1064 if (list_empty(&virt_dev
->cmd_list
))
1067 command
= list_entry(virt_dev
->cmd_list
.next
,
1068 struct xhci_command
, cmd_list
);
1069 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1072 command
->status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1073 list_del(&command
->cmd_list
);
1074 if (command
->completion
)
1075 complete(command
->completion
);
1077 xhci_free_command(xhci
, command
);
1081 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1082 struct xhci_event_cmd
*event
)
1084 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1086 dma_addr_t cmd_dequeue_dma
;
1087 struct xhci_input_control_ctx
*ctrl_ctx
;
1088 struct xhci_virt_device
*virt_dev
;
1089 unsigned int ep_index
;
1090 struct xhci_ring
*ep_ring
;
1091 unsigned int ep_state
;
1093 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1094 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1095 xhci
->cmd_ring
->dequeue
);
1096 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1097 if (cmd_dequeue_dma
== 0) {
1098 xhci
->error_bitmask
|= 1 << 4;
1101 /* Does the DMA address match our internal dequeue pointer address? */
1102 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1103 xhci
->error_bitmask
|= 1 << 5;
1106 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1107 & TRB_TYPE_BITMASK
) {
1108 case TRB_TYPE(TRB_ENABLE_SLOT
):
1109 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1110 xhci
->slot_id
= slot_id
;
1113 complete(&xhci
->addr_dev
);
1115 case TRB_TYPE(TRB_DISABLE_SLOT
):
1116 if (xhci
->devs
[slot_id
]) {
1117 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1118 /* Delete default control endpoint resources */
1119 xhci_free_device_endpoint_resources(xhci
,
1120 xhci
->devs
[slot_id
], true);
1121 xhci_free_virt_device(xhci
, slot_id
);
1124 case TRB_TYPE(TRB_CONFIG_EP
):
1125 virt_dev
= xhci
->devs
[slot_id
];
1126 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1129 * Configure endpoint commands can come from the USB core
1130 * configuration or alt setting changes, or because the HW
1131 * needed an extra configure endpoint command after a reset
1132 * endpoint command or streams were being configured.
1133 * If the command was for a halted endpoint, the xHCI driver
1134 * is not waiting on the configure endpoint command.
1136 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1138 /* Input ctx add_flags are the endpoint index plus one */
1139 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1140 /* A usb_set_interface() call directly after clearing a halted
1141 * condition may race on this quirky hardware. Not worth
1142 * worrying about, since this is prototype hardware. Not sure
1143 * if this will work for streams, but streams support was
1144 * untested on this prototype.
1146 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1147 ep_index
!= (unsigned int) -1 &&
1148 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1149 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1150 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1151 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1152 if (!(ep_state
& EP_HALTED
))
1153 goto bandwidth_change
;
1154 xhci_dbg(xhci
, "Completed config ep cmd - "
1155 "last ep index = %d, state = %d\n",
1156 ep_index
, ep_state
);
1157 /* Clear internal halted state and restart ring(s) */
1158 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1160 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1164 xhci_dbg(xhci
, "Completed config ep cmd\n");
1165 xhci
->devs
[slot_id
]->cmd_status
=
1166 GET_COMP_CODE(le32_to_cpu(event
->status
));
1167 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1169 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1170 virt_dev
= xhci
->devs
[slot_id
];
1171 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1173 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1174 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1176 case TRB_TYPE(TRB_ADDR_DEV
):
1177 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1178 complete(&xhci
->addr_dev
);
1180 case TRB_TYPE(TRB_STOP_RING
):
1181 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1183 case TRB_TYPE(TRB_SET_DEQ
):
1184 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1186 case TRB_TYPE(TRB_CMD_NOOP
):
1188 case TRB_TYPE(TRB_RESET_EP
):
1189 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1191 case TRB_TYPE(TRB_RESET_DEV
):
1192 xhci_dbg(xhci
, "Completed reset device command.\n");
1193 slot_id
= TRB_TO_SLOT_ID(
1194 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1195 virt_dev
= xhci
->devs
[slot_id
];
1197 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1199 xhci_warn(xhci
, "Reset device command completion "
1200 "for disabled slot %u\n", slot_id
);
1202 case TRB_TYPE(TRB_NEC_GET_FW
):
1203 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1204 xhci
->error_bitmask
|= 1 << 6;
1207 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1208 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1209 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1212 /* Skip over unknown commands on the event ring */
1213 xhci
->error_bitmask
|= 1 << 6;
1216 inc_deq(xhci
, xhci
->cmd_ring
);
1219 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1220 union xhci_trb
*event
)
1224 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1225 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1226 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1227 handle_cmd_completion(xhci
, &event
->event_cmd
);
1230 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1231 * port registers -- USB 3.0 and USB 2.0).
1233 * Returns a zero-based port number, which is suitable for indexing into each of
1234 * the split roothubs' port arrays and bus state arrays.
1235 * Add one to it in order to call xhci_find_slot_id_by_port.
1237 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1238 struct xhci_hcd
*xhci
, u32 port_id
)
1241 unsigned int num_similar_speed_ports
= 0;
1243 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1244 * and usb2_ports are 0-based indexes. Count the number of similar
1245 * speed ports, up to 1 port before this port.
1247 for (i
= 0; i
< (port_id
- 1); i
++) {
1248 u8 port_speed
= xhci
->port_array
[i
];
1251 * Skip ports that don't have known speeds, or have duplicate
1252 * Extended Capabilities port speed entries.
1254 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1258 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1259 * 1.1 ports are under the USB 2.0 hub. If the port speed
1260 * matches the device speed, it's a similar speed port.
1262 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1263 num_similar_speed_ports
++;
1265 return num_similar_speed_ports
;
1268 static void handle_device_notification(struct xhci_hcd
*xhci
,
1269 union xhci_trb
*event
)
1272 struct usb_device
*udev
;
1274 slot_id
= TRB_TO_SLOT_ID(event
->generic
.field
[3]);
1275 if (!xhci
->devs
[slot_id
]) {
1276 xhci_warn(xhci
, "Device Notification event for "
1277 "unused slot %u\n", slot_id
);
1281 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1283 udev
= xhci
->devs
[slot_id
]->udev
;
1284 if (udev
&& udev
->parent
)
1285 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1288 static void handle_port_status(struct xhci_hcd
*xhci
,
1289 union xhci_trb
*event
)
1291 struct usb_hcd
*hcd
;
1296 unsigned int faked_port_index
;
1298 struct xhci_bus_state
*bus_state
;
1299 __le32 __iomem
**port_array
;
1300 bool bogus_port_status
= false;
1302 /* Port status change events always have a successful completion code */
1303 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1304 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1305 xhci
->error_bitmask
|= 1 << 8;
1307 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1308 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1310 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1311 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1312 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1313 bogus_port_status
= true;
1317 /* Figure out which usb_hcd this port is attached to:
1318 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1320 major_revision
= xhci
->port_array
[port_id
- 1];
1321 if (major_revision
== 0) {
1322 xhci_warn(xhci
, "Event for port %u not in "
1323 "Extended Capabilities, ignoring.\n",
1325 bogus_port_status
= true;
1328 if (major_revision
== DUPLICATE_ENTRY
) {
1329 xhci_warn(xhci
, "Event for port %u duplicated in"
1330 "Extended Capabilities, ignoring.\n",
1332 bogus_port_status
= true;
1337 * Hardware port IDs reported by a Port Status Change Event include USB
1338 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1339 * resume event, but we first need to translate the hardware port ID
1340 * into the index into the ports on the correct split roothub, and the
1341 * correct bus_state structure.
1343 /* Find the right roothub. */
1344 hcd
= xhci_to_hcd(xhci
);
1345 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1346 hcd
= xhci
->shared_hcd
;
1347 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1348 if (hcd
->speed
== HCD_USB3
)
1349 port_array
= xhci
->usb3_ports
;
1351 port_array
= xhci
->usb2_ports
;
1352 /* Find the faked port hub number */
1353 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1356 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1357 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1358 xhci_dbg(xhci
, "resume root hub\n");
1359 usb_hcd_resume_root_hub(hcd
);
1362 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1363 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1365 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1366 if (!(temp1
& CMD_RUN
)) {
1367 xhci_warn(xhci
, "xHC is not running.\n");
1371 if (DEV_SUPERSPEED(temp
)) {
1372 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1373 /* Set a flag to say the port signaled remote wakeup,
1374 * so we can tell the difference between the end of
1375 * device and host initiated resume.
1377 bus_state
->port_remote_wakeup
|= 1 << faked_port_index
;
1378 xhci_test_and_clear_bit(xhci
, port_array
,
1379 faked_port_index
, PORT_PLC
);
1380 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1382 /* Need to wait until the next link state change
1383 * indicates the device is actually in U0.
1385 bogus_port_status
= true;
1388 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1389 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1390 msecs_to_jiffies(20);
1391 set_bit(faked_port_index
, &bus_state
->resuming_ports
);
1392 mod_timer(&hcd
->rh_timer
,
1393 bus_state
->resume_done
[faked_port_index
]);
1394 /* Do the rest in GetPortStatus */
1398 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_U0
&&
1399 DEV_SUPERSPEED(temp
)) {
1400 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1401 /* We've just brought the device into U0 through either the
1402 * Resume state after a device remote wakeup, or through the
1403 * U3Exit state after a host-initiated resume. If it's a device
1404 * initiated remote wake, don't pass up the link state change,
1405 * so the roothub behavior is consistent with external
1406 * USB 3.0 hub behavior.
1408 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1409 faked_port_index
+ 1);
1410 if (slot_id
&& xhci
->devs
[slot_id
])
1411 xhci_ring_device(xhci
, slot_id
);
1412 if (bus_state
->port_remote_wakeup
&& (1 << faked_port_index
)) {
1413 bus_state
->port_remote_wakeup
&=
1414 ~(1 << faked_port_index
);
1415 xhci_test_and_clear_bit(xhci
, port_array
,
1416 faked_port_index
, PORT_PLC
);
1417 usb_wakeup_notification(hcd
->self
.root_hub
,
1418 faked_port_index
+ 1);
1419 bogus_port_status
= true;
1424 if (hcd
->speed
!= HCD_USB3
)
1425 xhci_test_and_clear_bit(xhci
, port_array
, faked_port_index
,
1429 /* Update event ring dequeue pointer before dropping the lock */
1430 inc_deq(xhci
, xhci
->event_ring
);
1432 /* Don't make the USB core poll the roothub if we got a bad port status
1433 * change event. Besides, at that point we can't tell which roothub
1434 * (USB 2.0 or USB 3.0) to kick.
1436 if (bogus_port_status
)
1439 spin_unlock(&xhci
->lock
);
1440 /* Pass this up to the core */
1441 usb_hcd_poll_rh_status(hcd
);
1442 spin_lock(&xhci
->lock
);
1446 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1447 * at end_trb, which may be in another segment. If the suspect DMA address is a
1448 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1451 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1452 union xhci_trb
*start_trb
,
1453 union xhci_trb
*end_trb
,
1454 dma_addr_t suspect_dma
)
1456 dma_addr_t start_dma
;
1457 dma_addr_t end_seg_dma
;
1458 dma_addr_t end_trb_dma
;
1459 struct xhci_segment
*cur_seg
;
1461 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1462 cur_seg
= start_seg
;
1467 /* We may get an event for a Link TRB in the middle of a TD */
1468 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1469 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1470 /* If the end TRB isn't in this segment, this is set to 0 */
1471 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1473 if (end_trb_dma
> 0) {
1474 /* The end TRB is in this segment, so suspect should be here */
1475 if (start_dma
<= end_trb_dma
) {
1476 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1479 /* Case for one segment with
1480 * a TD wrapped around to the top
1482 if ((suspect_dma
>= start_dma
&&
1483 suspect_dma
<= end_seg_dma
) ||
1484 (suspect_dma
>= cur_seg
->dma
&&
1485 suspect_dma
<= end_trb_dma
))
1490 /* Might still be somewhere in this segment */
1491 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1494 cur_seg
= cur_seg
->next
;
1495 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1496 } while (cur_seg
!= start_seg
);
1501 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1502 unsigned int slot_id
, unsigned int ep_index
,
1503 unsigned int stream_id
,
1504 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1506 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1507 ep
->ep_state
|= EP_HALTED
;
1508 ep
->stopped_td
= td
;
1509 ep
->stopped_trb
= event_trb
;
1510 ep
->stopped_stream
= stream_id
;
1512 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1513 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1515 ep
->stopped_td
= NULL
;
1516 ep
->stopped_trb
= NULL
;
1517 ep
->stopped_stream
= 0;
1519 xhci_ring_cmd_db(xhci
);
1522 /* Check if an error has halted the endpoint ring. The class driver will
1523 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1524 * However, a babble and other errors also halt the endpoint ring, and the class
1525 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1526 * Ring Dequeue Pointer command manually.
1528 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1529 struct xhci_ep_ctx
*ep_ctx
,
1530 unsigned int trb_comp_code
)
1532 /* TRB completion codes that may require a manual halt cleanup */
1533 if (trb_comp_code
== COMP_TX_ERR
||
1534 trb_comp_code
== COMP_BABBLE
||
1535 trb_comp_code
== COMP_SPLIT_ERR
)
1536 /* The 0.96 spec says a babbling control endpoint
1537 * is not halted. The 0.96 spec says it is. Some HW
1538 * claims to be 0.95 compliant, but it halts the control
1539 * endpoint anyway. Check if a babble halted the
1542 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1543 cpu_to_le32(EP_STATE_HALTED
))
1549 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1551 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1552 /* Vendor defined "informational" completion code,
1553 * treat as not-an-error.
1555 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1557 xhci_dbg(xhci
, "Treating code as success.\n");
1564 * Finish the td processing, remove the td from td list;
1565 * Return 1 if the urb can be given back.
1567 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1568 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1569 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1571 struct xhci_virt_device
*xdev
;
1572 struct xhci_ring
*ep_ring
;
1573 unsigned int slot_id
;
1575 struct urb
*urb
= NULL
;
1576 struct xhci_ep_ctx
*ep_ctx
;
1578 struct urb_priv
*urb_priv
;
1581 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1582 xdev
= xhci
->devs
[slot_id
];
1583 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1584 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1585 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1586 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1591 if (trb_comp_code
== COMP_STOP_INVAL
||
1592 trb_comp_code
== COMP_STOP
) {
1593 /* The Endpoint Stop Command completion will take care of any
1594 * stopped TDs. A stopped TD may be restarted, so don't update
1595 * the ring dequeue pointer or take this TD off any lists yet.
1597 ep
->stopped_td
= td
;
1598 ep
->stopped_trb
= event_trb
;
1601 if (trb_comp_code
== COMP_STALL
) {
1602 /* The transfer is completed from the driver's
1603 * perspective, but we need to issue a set dequeue
1604 * command for this stalled endpoint to move the dequeue
1605 * pointer past the TD. We can't do that here because
1606 * the halt condition must be cleared first. Let the
1607 * USB class driver clear the stall later.
1609 ep
->stopped_td
= td
;
1610 ep
->stopped_trb
= event_trb
;
1611 ep
->stopped_stream
= ep_ring
->stream_id
;
1612 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1613 ep_ctx
, trb_comp_code
)) {
1614 /* Other types of errors halt the endpoint, but the
1615 * class driver doesn't call usb_reset_endpoint() unless
1616 * the error is -EPIPE. Clear the halted status in the
1617 * xHCI hardware manually.
1619 xhci_cleanup_halted_endpoint(xhci
,
1620 slot_id
, ep_index
, ep_ring
->stream_id
,
1623 /* Update ring dequeue pointer */
1624 while (ep_ring
->dequeue
!= td
->last_trb
)
1625 inc_deq(xhci
, ep_ring
);
1626 inc_deq(xhci
, ep_ring
);
1630 /* Clean up the endpoint's TD list */
1632 urb_priv
= urb
->hcpriv
;
1634 /* Do one last check of the actual transfer length.
1635 * If the host controller said we transferred more data than
1636 * the buffer length, urb->actual_length will be a very big
1637 * number (since it's unsigned). Play it safe and say we didn't
1638 * transfer anything.
1640 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1641 xhci_warn(xhci
, "URB transfer length is wrong, "
1642 "xHC issue? req. len = %u, "
1644 urb
->transfer_buffer_length
,
1645 urb
->actual_length
);
1646 urb
->actual_length
= 0;
1647 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1648 *status
= -EREMOTEIO
;
1652 list_del_init(&td
->td_list
);
1653 /* Was this TD slated to be cancelled but completed anyway? */
1654 if (!list_empty(&td
->cancelled_td_list
))
1655 list_del_init(&td
->cancelled_td_list
);
1658 /* Giveback the urb when all the tds are completed */
1659 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1661 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1662 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1663 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
1665 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1666 usb_amd_quirk_pll_enable();
1676 * Process control tds, update urb status and actual_length.
1678 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1679 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1680 struct xhci_virt_ep
*ep
, int *status
)
1682 struct xhci_virt_device
*xdev
;
1683 struct xhci_ring
*ep_ring
;
1684 unsigned int slot_id
;
1686 struct xhci_ep_ctx
*ep_ctx
;
1689 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1690 xdev
= xhci
->devs
[slot_id
];
1691 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1692 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1693 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1694 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1696 switch (trb_comp_code
) {
1698 if (event_trb
== ep_ring
->dequeue
) {
1699 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1700 "without IOC set??\n");
1701 *status
= -ESHUTDOWN
;
1702 } else if (event_trb
!= td
->last_trb
) {
1703 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1704 "without IOC set??\n");
1705 *status
= -ESHUTDOWN
;
1711 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1712 *status
= -EREMOTEIO
;
1716 case COMP_STOP_INVAL
:
1718 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1720 if (!xhci_requires_manual_halt_cleanup(xhci
,
1721 ep_ctx
, trb_comp_code
))
1723 xhci_dbg(xhci
, "TRB error code %u, "
1724 "halted endpoint index = %u\n",
1725 trb_comp_code
, ep_index
);
1726 /* else fall through */
1728 /* Did we transfer part of the data (middle) phase? */
1729 if (event_trb
!= ep_ring
->dequeue
&&
1730 event_trb
!= td
->last_trb
)
1731 td
->urb
->actual_length
=
1732 td
->urb
->transfer_buffer_length
1733 - TRB_LEN(le32_to_cpu(event
->transfer_len
));
1735 td
->urb
->actual_length
= 0;
1737 xhci_cleanup_halted_endpoint(xhci
,
1738 slot_id
, ep_index
, 0, td
, event_trb
);
1739 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
1742 * Did we transfer any data, despite the errors that might have
1743 * happened? I.e. did we get past the setup stage?
1745 if (event_trb
!= ep_ring
->dequeue
) {
1746 /* The event was for the status stage */
1747 if (event_trb
== td
->last_trb
) {
1748 if (td
->urb
->actual_length
!= 0) {
1749 /* Don't overwrite a previously set error code
1751 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
1752 (td
->urb
->transfer_flags
1753 & URB_SHORT_NOT_OK
))
1754 /* Did we already see a short data
1756 *status
= -EREMOTEIO
;
1758 td
->urb
->actual_length
=
1759 td
->urb
->transfer_buffer_length
;
1762 /* Maybe the event was for the data stage? */
1763 td
->urb
->actual_length
=
1764 td
->urb
->transfer_buffer_length
-
1765 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1766 xhci_dbg(xhci
, "Waiting for status "
1772 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1776 * Process isochronous tds, update urb packet status and actual_length.
1778 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1779 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1780 struct xhci_virt_ep
*ep
, int *status
)
1782 struct xhci_ring
*ep_ring
;
1783 struct urb_priv
*urb_priv
;
1786 union xhci_trb
*cur_trb
;
1787 struct xhci_segment
*cur_seg
;
1788 struct usb_iso_packet_descriptor
*frame
;
1790 bool skip_td
= false;
1792 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1793 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1794 urb_priv
= td
->urb
->hcpriv
;
1795 idx
= urb_priv
->td_cnt
;
1796 frame
= &td
->urb
->iso_frame_desc
[idx
];
1798 /* handle completion code */
1799 switch (trb_comp_code
) {
1801 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0) {
1805 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
1806 trb_comp_code
= COMP_SHORT_TX
;
1808 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
1812 frame
->status
= -ECOMM
;
1815 case COMP_BUFF_OVER
:
1817 frame
->status
= -EOVERFLOW
;
1823 frame
->status
= -EPROTO
;
1827 case COMP_STOP_INVAL
:
1834 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
1835 frame
->actual_length
= frame
->length
;
1836 td
->urb
->actual_length
+= frame
->length
;
1838 for (cur_trb
= ep_ring
->dequeue
,
1839 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
1840 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1841 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
1842 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
1843 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1845 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1846 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1848 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1849 frame
->actual_length
= len
;
1850 td
->urb
->actual_length
+= len
;
1854 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1857 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1858 struct xhci_transfer_event
*event
,
1859 struct xhci_virt_ep
*ep
, int *status
)
1861 struct xhci_ring
*ep_ring
;
1862 struct urb_priv
*urb_priv
;
1863 struct usb_iso_packet_descriptor
*frame
;
1866 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1867 urb_priv
= td
->urb
->hcpriv
;
1868 idx
= urb_priv
->td_cnt
;
1869 frame
= &td
->urb
->iso_frame_desc
[idx
];
1871 /* The transfer is partly done. */
1872 frame
->status
= -EXDEV
;
1874 /* calc actual length */
1875 frame
->actual_length
= 0;
1877 /* Update ring dequeue pointer */
1878 while (ep_ring
->dequeue
!= td
->last_trb
)
1879 inc_deq(xhci
, ep_ring
);
1880 inc_deq(xhci
, ep_ring
);
1882 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
1886 * Process bulk and interrupt tds, update urb status and actual_length.
1888 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1889 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1890 struct xhci_virt_ep
*ep
, int *status
)
1892 struct xhci_ring
*ep_ring
;
1893 union xhci_trb
*cur_trb
;
1894 struct xhci_segment
*cur_seg
;
1897 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1898 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1900 switch (trb_comp_code
) {
1902 /* Double check that the HW transferred everything. */
1903 if (event_trb
!= td
->last_trb
||
1904 TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
1905 xhci_warn(xhci
, "WARN Successful completion "
1907 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1908 *status
= -EREMOTEIO
;
1911 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
1912 trb_comp_code
= COMP_SHORT_TX
;
1918 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1919 *status
= -EREMOTEIO
;
1924 /* Others already handled above */
1927 if (trb_comp_code
== COMP_SHORT_TX
)
1928 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
1929 "%d bytes untransferred\n",
1930 td
->urb
->ep
->desc
.bEndpointAddress
,
1931 td
->urb
->transfer_buffer_length
,
1932 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1933 /* Fast path - was this the last TRB in the TD for this URB? */
1934 if (event_trb
== td
->last_trb
) {
1935 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
1936 td
->urb
->actual_length
=
1937 td
->urb
->transfer_buffer_length
-
1938 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1939 if (td
->urb
->transfer_buffer_length
<
1940 td
->urb
->actual_length
) {
1941 xhci_warn(xhci
, "HC gave bad length "
1942 "of %d bytes left\n",
1943 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1944 td
->urb
->actual_length
= 0;
1945 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1946 *status
= -EREMOTEIO
;
1950 /* Don't overwrite a previously set error code */
1951 if (*status
== -EINPROGRESS
) {
1952 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1953 *status
= -EREMOTEIO
;
1958 td
->urb
->actual_length
=
1959 td
->urb
->transfer_buffer_length
;
1960 /* Ignore a short packet completion if the
1961 * untransferred length was zero.
1963 if (*status
== -EREMOTEIO
)
1967 /* Slow path - walk the list, starting from the dequeue
1968 * pointer, to get the actual length transferred.
1970 td
->urb
->actual_length
= 0;
1971 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1972 cur_trb
!= event_trb
;
1973 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1974 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
1975 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
1976 td
->urb
->actual_length
+=
1977 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1979 /* If the ring didn't stop on a Link or No-op TRB, add
1980 * in the actual bytes transferred from the Normal TRB
1982 if (trb_comp_code
!= COMP_STOP_INVAL
)
1983 td
->urb
->actual_length
+=
1984 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1985 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1988 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1992 * If this function returns an error condition, it means it got a Transfer
1993 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1994 * At this point, the host controller is probably hosed and should be reset.
1996 static int handle_tx_event(struct xhci_hcd
*xhci
,
1997 struct xhci_transfer_event
*event
)
1999 struct xhci_virt_device
*xdev
;
2000 struct xhci_virt_ep
*ep
;
2001 struct xhci_ring
*ep_ring
;
2002 unsigned int slot_id
;
2004 struct xhci_td
*td
= NULL
;
2005 dma_addr_t event_dma
;
2006 struct xhci_segment
*event_seg
;
2007 union xhci_trb
*event_trb
;
2008 struct urb
*urb
= NULL
;
2009 int status
= -EINPROGRESS
;
2010 struct urb_priv
*urb_priv
;
2011 struct xhci_ep_ctx
*ep_ctx
;
2012 struct list_head
*tmp
;
2017 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2018 xdev
= xhci
->devs
[slot_id
];
2020 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
2021 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2022 (unsigned long long) xhci_trb_virt_to_dma(
2023 xhci
->event_ring
->deq_seg
,
2024 xhci
->event_ring
->dequeue
),
2025 lower_32_bits(le64_to_cpu(event
->buffer
)),
2026 upper_32_bits(le64_to_cpu(event
->buffer
)),
2027 le32_to_cpu(event
->transfer_len
),
2028 le32_to_cpu(event
->flags
));
2029 xhci_dbg(xhci
, "Event ring:\n");
2030 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2034 /* Endpoint ID is 1 based, our index is zero based */
2035 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2036 ep
= &xdev
->eps
[ep_index
];
2037 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2038 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2040 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
2041 EP_STATE_DISABLED
) {
2042 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
2043 "or incorrect stream ring\n");
2044 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2045 (unsigned long long) xhci_trb_virt_to_dma(
2046 xhci
->event_ring
->deq_seg
,
2047 xhci
->event_ring
->dequeue
),
2048 lower_32_bits(le64_to_cpu(event
->buffer
)),
2049 upper_32_bits(le64_to_cpu(event
->buffer
)),
2050 le32_to_cpu(event
->transfer_len
),
2051 le32_to_cpu(event
->flags
));
2052 xhci_dbg(xhci
, "Event ring:\n");
2053 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2057 /* Count current td numbers if ep->skip is set */
2059 list_for_each(tmp
, &ep_ring
->td_list
)
2063 event_dma
= le64_to_cpu(event
->buffer
);
2064 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2065 /* Look for common error cases */
2066 switch (trb_comp_code
) {
2067 /* Skip codes that require special handling depending on
2071 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2073 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2074 trb_comp_code
= COMP_SHORT_TX
;
2076 xhci_warn(xhci
, "WARN Successful completion on short TX: "
2077 "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2081 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
2083 case COMP_STOP_INVAL
:
2084 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
2087 xhci_dbg(xhci
, "Stalled endpoint\n");
2088 ep
->ep_state
|= EP_HALTED
;
2092 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
2095 case COMP_SPLIT_ERR
:
2097 xhci_dbg(xhci
, "Transfer error on endpoint\n");
2101 xhci_dbg(xhci
, "Babble error on endpoint\n");
2102 status
= -EOVERFLOW
;
2105 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2109 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2111 case COMP_BUFF_OVER
:
2112 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2116 * When the Isoch ring is empty, the xHC will generate
2117 * a Ring Overrun Event for IN Isoch endpoint or Ring
2118 * Underrun Event for OUT Isoch endpoint.
2120 xhci_dbg(xhci
, "underrun event on endpoint\n");
2121 if (!list_empty(&ep_ring
->td_list
))
2122 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2123 "still with TDs queued?\n",
2124 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2128 xhci_dbg(xhci
, "overrun event on endpoint\n");
2129 if (!list_empty(&ep_ring
->td_list
))
2130 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2131 "still with TDs queued?\n",
2132 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2136 xhci_warn(xhci
, "WARN: detect an incompatible device");
2139 case COMP_MISSED_INT
:
2141 * When encounter missed service error, one or more isoc tds
2142 * may be missed by xHC.
2143 * Set skip flag of the ep_ring; Complete the missed tds as
2144 * short transfer when process the ep_ring next time.
2147 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2150 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2154 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2160 /* This TRB should be in the TD at the head of this ring's
2163 if (list_empty(&ep_ring
->td_list
)) {
2164 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d "
2165 "with no TDs queued?\n",
2166 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2168 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2169 (le32_to_cpu(event
->flags
) &
2170 TRB_TYPE_BITMASK
)>>10);
2171 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2174 xhci_dbg(xhci
, "td_list is empty while skip "
2175 "flag set. Clear skip flag.\n");
2181 /* We've skipped all the TDs on the ep ring when ep->skip set */
2182 if (ep
->skip
&& td_num
== 0) {
2184 xhci_dbg(xhci
, "All tds on the ep_ring skipped. "
2185 "Clear skip flag.\n");
2190 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2194 /* Is this a TRB in the currently executing TD? */
2195 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2196 td
->last_trb
, event_dma
);
2199 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2200 * is not in the current TD pointed by ep_ring->dequeue because
2201 * that the hardware dequeue pointer still at the previous TRB
2202 * of the current TD. The previous TRB maybe a Link TD or the
2203 * last TRB of the previous TD. The command completion handle
2204 * will take care the rest.
2206 if (!event_seg
&& trb_comp_code
== COMP_STOP_INVAL
) {
2213 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2214 /* Some host controllers give a spurious
2215 * successful event after a short transfer.
2218 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2219 ep_ring
->last_td_was_short
) {
2220 ep_ring
->last_td_was_short
= false;
2224 /* HC is busted, give up! */
2226 "ERROR Transfer event TRB DMA ptr not "
2227 "part of current TD\n");
2231 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2234 if (trb_comp_code
== COMP_SHORT_TX
)
2235 ep_ring
->last_td_was_short
= true;
2237 ep_ring
->last_td_was_short
= false;
2240 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2244 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2245 sizeof(*event_trb
)];
2247 * No-op TRB should not trigger interrupts.
2248 * If event_trb is a no-op TRB, it means the
2249 * corresponding TD has been cancelled. Just ignore
2252 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2254 "event_trb is a no-op TRB. Skip it\n");
2258 /* Now update the urb's actual_length and give back to
2261 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2262 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2264 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2265 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2268 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2273 * Do not update event ring dequeue pointer if ep->skip is set.
2274 * Will roll back to continue process missed tds.
2276 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2277 inc_deq(xhci
, xhci
->event_ring
);
2282 urb_priv
= urb
->hcpriv
;
2283 /* Leave the TD around for the reset endpoint function
2284 * to use(but only if it's not a control endpoint,
2285 * since we already queued the Set TR dequeue pointer
2286 * command for stalled control endpoints).
2288 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2289 (trb_comp_code
!= COMP_STALL
&&
2290 trb_comp_code
!= COMP_BABBLE
))
2291 xhci_urb_free_priv(xhci
, urb_priv
);
2293 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2294 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2295 (urb
->transfer_flags
&
2296 URB_SHORT_NOT_OK
)) ||
2298 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2299 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2300 "expected = %d, status = %d\n",
2301 urb
, urb
->actual_length
,
2302 urb
->transfer_buffer_length
,
2304 spin_unlock(&xhci
->lock
);
2305 /* EHCI, UHCI, and OHCI always unconditionally set the
2306 * urb->status of an isochronous endpoint to 0.
2308 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2310 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2311 spin_lock(&xhci
->lock
);
2315 * If ep->skip is set, it means there are missed tds on the
2316 * endpoint ring need to take care of.
2317 * Process them as short transfer until reach the td pointed by
2320 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2326 * This function handles all OS-owned events on the event ring. It may drop
2327 * xhci->lock between event processing (e.g. to pass up port status changes).
2328 * Returns >0 for "possibly more events to process" (caller should call again),
2329 * otherwise 0 if done. In future, <0 returns should indicate error code.
2331 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2333 union xhci_trb
*event
;
2334 int update_ptrs
= 1;
2337 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2338 xhci
->error_bitmask
|= 1 << 1;
2342 event
= xhci
->event_ring
->dequeue
;
2343 /* Does the HC or OS own the TRB? */
2344 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2345 xhci
->event_ring
->cycle_state
) {
2346 xhci
->error_bitmask
|= 1 << 2;
2351 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2352 * speculative reads of the event's flags/data below.
2355 /* FIXME: Handle more event types. */
2356 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2357 case TRB_TYPE(TRB_COMPLETION
):
2358 handle_cmd_completion(xhci
, &event
->event_cmd
);
2360 case TRB_TYPE(TRB_PORT_STATUS
):
2361 handle_port_status(xhci
, event
);
2364 case TRB_TYPE(TRB_TRANSFER
):
2365 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2367 xhci
->error_bitmask
|= 1 << 9;
2371 case TRB_TYPE(TRB_DEV_NOTE
):
2372 handle_device_notification(xhci
, event
);
2375 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2377 handle_vendor_event(xhci
, event
);
2379 xhci
->error_bitmask
|= 1 << 3;
2381 /* Any of the above functions may drop and re-acquire the lock, so check
2382 * to make sure a watchdog timer didn't mark the host as non-responsive.
2384 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2385 xhci_dbg(xhci
, "xHCI host dying, returning from "
2386 "event handler.\n");
2391 /* Update SW event ring dequeue pointer */
2392 inc_deq(xhci
, xhci
->event_ring
);
2394 /* Are there more items on the event ring? Caller will call us again to
2401 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2402 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2403 * indicators of an event TRB error, but we check the status *first* to be safe.
2405 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2407 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2409 union xhci_trb
*trb
;
2411 union xhci_trb
*event_ring_deq
;
2414 spin_lock(&xhci
->lock
);
2415 trb
= xhci
->event_ring
->dequeue
;
2416 /* Check if the xHC generated the interrupt, or the irq is shared */
2417 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2418 if (status
== 0xffffffff)
2421 if (!(status
& STS_EINT
)) {
2422 spin_unlock(&xhci
->lock
);
2425 if (status
& STS_FATAL
) {
2426 xhci_warn(xhci
, "WARNING: Host System Error\n");
2429 spin_unlock(&xhci
->lock
);
2434 * Clear the op reg interrupt status first,
2435 * so we can receive interrupts from other MSI-X interrupters.
2436 * Write 1 to clear the interrupt status.
2439 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2440 /* FIXME when MSI-X is supported and there are multiple vectors */
2441 /* Clear the MSI-X event interrupt status */
2445 /* Acknowledge the PCI interrupt */
2446 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2447 irq_pending
|= IMAN_IP
;
2448 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2451 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2452 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2453 "Shouldn't IRQs be disabled?\n");
2454 /* Clear the event handler busy flag (RW1C);
2455 * the event ring should be empty.
2457 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2458 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2459 &xhci
->ir_set
->erst_dequeue
);
2460 spin_unlock(&xhci
->lock
);
2465 event_ring_deq
= xhci
->event_ring
->dequeue
;
2466 /* FIXME this should be a delayed service routine
2467 * that clears the EHB.
2469 while (xhci_handle_event(xhci
) > 0) {}
2471 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2472 /* If necessary, update the HW's version of the event ring deq ptr. */
2473 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2474 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2475 xhci
->event_ring
->dequeue
);
2477 xhci_warn(xhci
, "WARN something wrong with SW event "
2478 "ring dequeue ptr.\n");
2479 /* Update HC event ring dequeue pointer */
2480 temp_64
&= ERST_PTR_MASK
;
2481 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2484 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2485 temp_64
|= ERST_EHB
;
2486 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2488 spin_unlock(&xhci
->lock
);
2493 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2495 return xhci_irq(hcd
);
2498 /**** Endpoint Ring Operations ****/
2501 * Generic function for queueing a TRB on a ring.
2502 * The caller must have checked to make sure there's room on the ring.
2504 * @more_trbs_coming: Will you enqueue more TRBs before calling
2505 * prepare_transfer()?
2507 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2508 bool more_trbs_coming
,
2509 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2511 struct xhci_generic_trb
*trb
;
2513 trb
= &ring
->enqueue
->generic
;
2514 trb
->field
[0] = cpu_to_le32(field1
);
2515 trb
->field
[1] = cpu_to_le32(field2
);
2516 trb
->field
[2] = cpu_to_le32(field3
);
2517 trb
->field
[3] = cpu_to_le32(field4
);
2518 inc_enq(xhci
, ring
, more_trbs_coming
);
2522 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2523 * FIXME allocate segments if the ring is full.
2525 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2526 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2528 unsigned int num_trbs_needed
;
2530 /* Make sure the endpoint has been added to xHC schedule */
2532 case EP_STATE_DISABLED
:
2534 * USB core changed config/interfaces without notifying us,
2535 * or hardware is reporting the wrong state.
2537 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2539 case EP_STATE_ERROR
:
2540 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2541 /* FIXME event handling code for error needs to clear it */
2542 /* XXX not sure if this should be -ENOENT or not */
2544 case EP_STATE_HALTED
:
2545 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2546 case EP_STATE_STOPPED
:
2547 case EP_STATE_RUNNING
:
2550 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2552 * FIXME issue Configure Endpoint command to try to get the HC
2553 * back into a known state.
2559 if (room_on_ring(xhci
, ep_ring
, num_trbs
))
2562 if (ep_ring
== xhci
->cmd_ring
) {
2563 xhci_err(xhci
, "Do not support expand command ring\n");
2567 xhci_dbg(xhci
, "ERROR no room on ep ring, "
2568 "try ring expansion\n");
2569 num_trbs_needed
= num_trbs
- ep_ring
->num_trbs_free
;
2570 if (xhci_ring_expansion(xhci
, ep_ring
, num_trbs_needed
,
2572 xhci_err(xhci
, "Ring expansion failed\n");
2577 if (enqueue_is_link_trb(ep_ring
)) {
2578 struct xhci_ring
*ring
= ep_ring
;
2579 union xhci_trb
*next
;
2581 next
= ring
->enqueue
;
2583 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2584 /* If we're not dealing with 0.95 hardware or isoc rings
2585 * on AMD 0.96 host, clear the chain bit.
2587 if (!xhci_link_trb_quirk(xhci
) &&
2588 !(ring
->type
== TYPE_ISOC
&&
2589 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
2590 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2592 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2595 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2597 /* Toggle the cycle bit after the last ring segment. */
2598 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2599 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2601 ring
->enq_seg
= ring
->enq_seg
->next
;
2602 ring
->enqueue
= ring
->enq_seg
->trbs
;
2603 next
= ring
->enqueue
;
2610 static int prepare_transfer(struct xhci_hcd
*xhci
,
2611 struct xhci_virt_device
*xdev
,
2612 unsigned int ep_index
,
2613 unsigned int stream_id
,
2614 unsigned int num_trbs
,
2616 unsigned int td_index
,
2620 struct urb_priv
*urb_priv
;
2622 struct xhci_ring
*ep_ring
;
2623 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2625 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2627 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2632 ret
= prepare_ring(xhci
, ep_ring
,
2633 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2634 num_trbs
, mem_flags
);
2638 urb_priv
= urb
->hcpriv
;
2639 td
= urb_priv
->td
[td_index
];
2641 INIT_LIST_HEAD(&td
->td_list
);
2642 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2644 if (td_index
== 0) {
2645 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2651 /* Add this TD to the tail of the endpoint ring's TD list */
2652 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2653 td
->start_seg
= ep_ring
->enq_seg
;
2654 td
->first_trb
= ep_ring
->enqueue
;
2656 urb_priv
->td
[td_index
] = td
;
2661 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
2663 int num_sgs
, num_trbs
, running_total
, temp
, i
;
2664 struct scatterlist
*sg
;
2667 num_sgs
= urb
->num_mapped_sgs
;
2668 temp
= urb
->transfer_buffer_length
;
2671 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
2672 unsigned int len
= sg_dma_len(sg
);
2674 /* Scatter gather list entries may cross 64KB boundaries */
2675 running_total
= TRB_MAX_BUFF_SIZE
-
2676 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
2677 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2678 if (running_total
!= 0)
2681 /* How many more 64KB chunks to transfer, how many more TRBs? */
2682 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
2684 running_total
+= TRB_MAX_BUFF_SIZE
;
2686 len
= min_t(int, len
, temp
);
2694 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
2697 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
2698 "TRBs, %d left\n", __func__
,
2699 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
2700 if (running_total
!= urb
->transfer_buffer_length
)
2701 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
2702 "queued %#x (%d), asked for %#x (%d)\n",
2704 urb
->ep
->desc
.bEndpointAddress
,
2705 running_total
, running_total
,
2706 urb
->transfer_buffer_length
,
2707 urb
->transfer_buffer_length
);
2710 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
2711 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
2712 struct xhci_generic_trb
*start_trb
)
2715 * Pass all the TRBs to the hardware at once and make sure this write
2720 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
2722 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
2723 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
2727 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2728 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2729 * (comprised of sg list entries) can take several service intervals to
2732 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2733 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2735 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
2736 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2740 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
2741 ep_interval
= urb
->interval
;
2742 /* Convert to microframes */
2743 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2744 urb
->dev
->speed
== USB_SPEED_FULL
)
2746 /* FIXME change this to a warning and a suggestion to use the new API
2747 * to set the polling interval (once the API is added).
2749 if (xhci_interval
!= ep_interval
) {
2750 if (printk_ratelimit())
2751 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
2752 " (%d microframe%s) than xHCI "
2753 "(%d microframe%s)\n",
2755 ep_interval
== 1 ? "" : "s",
2757 xhci_interval
== 1 ? "" : "s");
2758 urb
->interval
= xhci_interval
;
2759 /* Convert back to frames for LS/FS devices */
2760 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2761 urb
->dev
->speed
== USB_SPEED_FULL
)
2764 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2768 * The TD size is the number of bytes remaining in the TD (including this TRB),
2769 * right shifted by 10.
2770 * It must fit in bits 21:17, so it can't be bigger than 31.
2772 static u32
xhci_td_remainder(unsigned int remainder
)
2774 u32 max
= (1 << (21 - 17 + 1)) - 1;
2776 if ((remainder
>> 10) >= max
)
2779 return (remainder
>> 10) << 17;
2783 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2784 * the TD (*not* including this TRB).
2786 * Total TD packet count = total_packet_count =
2787 * roundup(TD size in bytes / wMaxPacketSize)
2789 * Packets transferred up to and including this TRB = packets_transferred =
2790 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2792 * TD size = total_packet_count - packets_transferred
2794 * It must fit in bits 21:17, so it can't be bigger than 31.
2797 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
2798 unsigned int total_packet_count
, struct urb
*urb
)
2800 int packets_transferred
;
2802 /* One TRB with a zero-length data packet. */
2803 if (running_total
== 0 && trb_buff_len
== 0)
2806 /* All the TRB queueing functions don't count the current TRB in
2809 packets_transferred
= (running_total
+ trb_buff_len
) /
2810 usb_endpoint_maxp(&urb
->ep
->desc
);
2812 return xhci_td_remainder(total_packet_count
- packets_transferred
);
2815 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2816 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2818 struct xhci_ring
*ep_ring
;
2819 unsigned int num_trbs
;
2820 struct urb_priv
*urb_priv
;
2822 struct scatterlist
*sg
;
2824 int trb_buff_len
, this_sg_len
, running_total
;
2825 unsigned int total_packet_count
;
2828 bool more_trbs_coming
;
2830 struct xhci_generic_trb
*start_trb
;
2833 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2837 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
2838 num_sgs
= urb
->num_mapped_sgs
;
2839 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2840 usb_endpoint_maxp(&urb
->ep
->desc
));
2842 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2843 ep_index
, urb
->stream_id
,
2844 num_trbs
, urb
, 0, mem_flags
);
2845 if (trb_buff_len
< 0)
2846 return trb_buff_len
;
2848 urb_priv
= urb
->hcpriv
;
2849 td
= urb_priv
->td
[0];
2852 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2853 * until we've finished creating all the other TRBs. The ring's cycle
2854 * state may change as we enqueue the other TRBs, so save it too.
2856 start_trb
= &ep_ring
->enqueue
->generic
;
2857 start_cycle
= ep_ring
->cycle_state
;
2861 * How much data is in the first TRB?
2863 * There are three forces at work for TRB buffer pointers and lengths:
2864 * 1. We don't want to walk off the end of this sg-list entry buffer.
2865 * 2. The transfer length that the driver requested may be smaller than
2866 * the amount of memory allocated for this scatter-gather list.
2867 * 3. TRBs buffers can't cross 64KB boundaries.
2870 addr
= (u64
) sg_dma_address(sg
);
2871 this_sg_len
= sg_dma_len(sg
);
2872 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2873 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2874 if (trb_buff_len
> urb
->transfer_buffer_length
)
2875 trb_buff_len
= urb
->transfer_buffer_length
;
2878 /* Queue the first TRB, even if it's zero-length */
2881 u32 length_field
= 0;
2884 /* Don't change the cycle bit of the first TRB until later */
2887 if (start_cycle
== 0)
2890 field
|= ep_ring
->cycle_state
;
2892 /* Chain all the TRBs together; clear the chain bit in the last
2893 * TRB to indicate it's the last TRB in the chain.
2898 /* FIXME - add check for ZERO_PACKET flag before this */
2899 td
->last_trb
= ep_ring
->enqueue
;
2903 /* Only set interrupt on short packet for IN endpoints */
2904 if (usb_urb_dir_in(urb
))
2907 if (TRB_MAX_BUFF_SIZE
-
2908 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
2909 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2910 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
2911 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2912 (unsigned int) addr
+ trb_buff_len
);
2915 /* Set the TRB length, TD size, and interrupter fields. */
2916 if (xhci
->hci_version
< 0x100) {
2917 remainder
= xhci_td_remainder(
2918 urb
->transfer_buffer_length
-
2921 remainder
= xhci_v1_0_td_remainder(running_total
,
2922 trb_buff_len
, total_packet_count
, urb
);
2924 length_field
= TRB_LEN(trb_buff_len
) |
2929 more_trbs_coming
= true;
2931 more_trbs_coming
= false;
2932 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
2933 lower_32_bits(addr
),
2934 upper_32_bits(addr
),
2936 field
| TRB_TYPE(TRB_NORMAL
));
2938 running_total
+= trb_buff_len
;
2940 /* Calculate length for next transfer --
2941 * Are we done queueing all the TRBs for this sg entry?
2943 this_sg_len
-= trb_buff_len
;
2944 if (this_sg_len
== 0) {
2949 addr
= (u64
) sg_dma_address(sg
);
2950 this_sg_len
= sg_dma_len(sg
);
2952 addr
+= trb_buff_len
;
2955 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2956 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2957 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2958 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
2960 urb
->transfer_buffer_length
- running_total
;
2961 } while (running_total
< urb
->transfer_buffer_length
);
2963 check_trb_math(urb
, num_trbs
, running_total
);
2964 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2965 start_cycle
, start_trb
);
2969 /* This is very similar to what ehci-q.c qtd_fill() does */
2970 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2971 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2973 struct xhci_ring
*ep_ring
;
2974 struct urb_priv
*urb_priv
;
2977 struct xhci_generic_trb
*start_trb
;
2979 bool more_trbs_coming
;
2981 u32 field
, length_field
;
2983 int running_total
, trb_buff_len
, ret
;
2984 unsigned int total_packet_count
;
2988 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2990 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2995 /* How much data is (potentially) left before the 64KB boundary? */
2996 running_total
= TRB_MAX_BUFF_SIZE
-
2997 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2998 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3000 /* If there's some data on this 64KB chunk, or we have to send a
3001 * zero-length transfer, we need at least one TRB
3003 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
3005 /* How many more 64KB chunks to transfer, how many more TRBs? */
3006 while (running_total
< urb
->transfer_buffer_length
) {
3008 running_total
+= TRB_MAX_BUFF_SIZE
;
3010 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3012 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3013 ep_index
, urb
->stream_id
,
3014 num_trbs
, urb
, 0, mem_flags
);
3018 urb_priv
= urb
->hcpriv
;
3019 td
= urb_priv
->td
[0];
3022 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3023 * until we've finished creating all the other TRBs. The ring's cycle
3024 * state may change as we enqueue the other TRBs, so save it too.
3026 start_trb
= &ep_ring
->enqueue
->generic
;
3027 start_cycle
= ep_ring
->cycle_state
;
3030 total_packet_count
= roundup(urb
->transfer_buffer_length
,
3031 usb_endpoint_maxp(&urb
->ep
->desc
));
3032 /* How much data is in the first TRB? */
3033 addr
= (u64
) urb
->transfer_dma
;
3034 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3035 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3036 if (trb_buff_len
> urb
->transfer_buffer_length
)
3037 trb_buff_len
= urb
->transfer_buffer_length
;
3041 /* Queue the first TRB, even if it's zero-length */
3046 /* Don't change the cycle bit of the first TRB until later */
3049 if (start_cycle
== 0)
3052 field
|= ep_ring
->cycle_state
;
3054 /* Chain all the TRBs together; clear the chain bit in the last
3055 * TRB to indicate it's the last TRB in the chain.
3060 /* FIXME - add check for ZERO_PACKET flag before this */
3061 td
->last_trb
= ep_ring
->enqueue
;
3065 /* Only set interrupt on short packet for IN endpoints */
3066 if (usb_urb_dir_in(urb
))
3069 /* Set the TRB length, TD size, and interrupter fields. */
3070 if (xhci
->hci_version
< 0x100) {
3071 remainder
= xhci_td_remainder(
3072 urb
->transfer_buffer_length
-
3075 remainder
= xhci_v1_0_td_remainder(running_total
,
3076 trb_buff_len
, total_packet_count
, urb
);
3078 length_field
= TRB_LEN(trb_buff_len
) |
3083 more_trbs_coming
= true;
3085 more_trbs_coming
= false;
3086 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3087 lower_32_bits(addr
),
3088 upper_32_bits(addr
),
3090 field
| TRB_TYPE(TRB_NORMAL
));
3092 running_total
+= trb_buff_len
;
3094 /* Calculate length for next transfer */
3095 addr
+= trb_buff_len
;
3096 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
3097 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
3098 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
3099 } while (running_total
< urb
->transfer_buffer_length
);
3101 check_trb_math(urb
, num_trbs
, running_total
);
3102 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3103 start_cycle
, start_trb
);
3107 /* Caller must have locked xhci->lock */
3108 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3109 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3111 struct xhci_ring
*ep_ring
;
3114 struct usb_ctrlrequest
*setup
;
3115 struct xhci_generic_trb
*start_trb
;
3117 u32 field
, length_field
;
3118 struct urb_priv
*urb_priv
;
3121 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3126 * Need to copy setup packet into setup TRB, so we can't use the setup
3129 if (!urb
->setup_packet
)
3132 /* 1 TRB for setup, 1 for status */
3135 * Don't need to check if we need additional event data and normal TRBs,
3136 * since data in control transfers will never get bigger than 16MB
3137 * XXX: can we get a buffer that crosses 64KB boundaries?
3139 if (urb
->transfer_buffer_length
> 0)
3141 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3142 ep_index
, urb
->stream_id
,
3143 num_trbs
, urb
, 0, mem_flags
);
3147 urb_priv
= urb
->hcpriv
;
3148 td
= urb_priv
->td
[0];
3151 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3152 * until we've finished creating all the other TRBs. The ring's cycle
3153 * state may change as we enqueue the other TRBs, so save it too.
3155 start_trb
= &ep_ring
->enqueue
->generic
;
3156 start_cycle
= ep_ring
->cycle_state
;
3158 /* Queue setup TRB - see section 6.4.1.2.1 */
3159 /* FIXME better way to translate setup_packet into two u32 fields? */
3160 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3162 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3163 if (start_cycle
== 0)
3166 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3167 if (xhci
->hci_version
== 0x100) {
3168 if (urb
->transfer_buffer_length
> 0) {
3169 if (setup
->bRequestType
& USB_DIR_IN
)
3170 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3172 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3176 queue_trb(xhci
, ep_ring
, true,
3177 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3178 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3179 TRB_LEN(8) | TRB_INTR_TARGET(0),
3180 /* Immediate data in pointer */
3183 /* If there's data, queue data TRBs */
3184 /* Only set interrupt on short packet for IN endpoints */
3185 if (usb_urb_dir_in(urb
))
3186 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3188 field
= TRB_TYPE(TRB_DATA
);
3190 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3191 xhci_td_remainder(urb
->transfer_buffer_length
) |
3193 if (urb
->transfer_buffer_length
> 0) {
3194 if (setup
->bRequestType
& USB_DIR_IN
)
3195 field
|= TRB_DIR_IN
;
3196 queue_trb(xhci
, ep_ring
, true,
3197 lower_32_bits(urb
->transfer_dma
),
3198 upper_32_bits(urb
->transfer_dma
),
3200 field
| ep_ring
->cycle_state
);
3203 /* Save the DMA address of the last TRB in the TD */
3204 td
->last_trb
= ep_ring
->enqueue
;
3206 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3207 /* If the device sent data, the status stage is an OUT transfer */
3208 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3212 queue_trb(xhci
, ep_ring
, false,
3216 /* Event on completion */
3217 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3219 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3220 start_cycle
, start_trb
);
3224 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3225 struct urb
*urb
, int i
)
3230 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3231 td_len
= urb
->iso_frame_desc
[i
].length
;
3233 num_trbs
= DIV_ROUND_UP(td_len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3242 * The transfer burst count field of the isochronous TRB defines the number of
3243 * bursts that are required to move all packets in this TD. Only SuperSpeed
3244 * devices can burst up to bMaxBurst number of packets per service interval.
3245 * This field is zero based, meaning a value of zero in the field means one
3246 * burst. Basically, for everything but SuperSpeed devices, this field will be
3247 * zero. Only xHCI 1.0 host controllers support this field.
3249 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3250 struct usb_device
*udev
,
3251 struct urb
*urb
, unsigned int total_packet_count
)
3253 unsigned int max_burst
;
3255 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3258 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3259 return roundup(total_packet_count
, max_burst
+ 1) - 1;
3263 * Returns the number of packets in the last "burst" of packets. This field is
3264 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3265 * the last burst packet count is equal to the total number of packets in the
3266 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3267 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3268 * contain 1 to (bMaxBurst + 1) packets.
3270 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3271 struct usb_device
*udev
,
3272 struct urb
*urb
, unsigned int total_packet_count
)
3274 unsigned int max_burst
;
3275 unsigned int residue
;
3277 if (xhci
->hci_version
< 0x100)
3280 switch (udev
->speed
) {
3281 case USB_SPEED_SUPER
:
3282 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3283 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3284 residue
= total_packet_count
% (max_burst
+ 1);
3285 /* If residue is zero, the last burst contains (max_burst + 1)
3286 * number of packets, but the TLBPC field is zero-based.
3292 if (total_packet_count
== 0)
3294 return total_packet_count
- 1;
3298 /* This is for isoc transfer */
3299 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3300 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3302 struct xhci_ring
*ep_ring
;
3303 struct urb_priv
*urb_priv
;
3305 int num_tds
, trbs_per_td
;
3306 struct xhci_generic_trb
*start_trb
;
3309 u32 field
, length_field
;
3310 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3311 u64 start_addr
, addr
;
3313 bool more_trbs_coming
;
3315 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3317 num_tds
= urb
->number_of_packets
;
3319 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3323 start_addr
= (u64
) urb
->transfer_dma
;
3324 start_trb
= &ep_ring
->enqueue
->generic
;
3325 start_cycle
= ep_ring
->cycle_state
;
3327 urb_priv
= urb
->hcpriv
;
3328 /* Queue the first TRB, even if it's zero-length */
3329 for (i
= 0; i
< num_tds
; i
++) {
3330 unsigned int total_packet_count
;
3331 unsigned int burst_count
;
3332 unsigned int residue
;
3336 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3337 td_len
= urb
->iso_frame_desc
[i
].length
;
3338 td_remain_len
= td_len
;
3339 total_packet_count
= roundup(td_len
,
3340 usb_endpoint_maxp(&urb
->ep
->desc
));
3341 /* A zero-length transfer still involves at least one packet. */
3342 if (total_packet_count
== 0)
3343 total_packet_count
++;
3344 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3345 total_packet_count
);
3346 residue
= xhci_get_last_burst_packet_count(xhci
,
3347 urb
->dev
, urb
, total_packet_count
);
3349 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3351 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3352 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3359 td
= urb_priv
->td
[i
];
3360 for (j
= 0; j
< trbs_per_td
; j
++) {
3362 field
= TRB_TBC(burst_count
) | TRB_TLBPC(residue
);
3365 /* Queue the isoc TRB */
3366 field
|= TRB_TYPE(TRB_ISOC
);
3367 /* Assume URB_ISO_ASAP is set */
3370 if (start_cycle
== 0)
3373 field
|= ep_ring
->cycle_state
;
3376 /* Queue other normal TRBs */
3377 field
|= TRB_TYPE(TRB_NORMAL
);
3378 field
|= ep_ring
->cycle_state
;
3381 /* Only set interrupt on short packet for IN EPs */
3382 if (usb_urb_dir_in(urb
))
3385 /* Chain all the TRBs together; clear the chain bit in
3386 * the last TRB to indicate it's the last TRB in the
3389 if (j
< trbs_per_td
- 1) {
3391 more_trbs_coming
= true;
3393 td
->last_trb
= ep_ring
->enqueue
;
3395 if (xhci
->hci_version
== 0x100) {
3396 /* Set BEI bit except for the last td */
3397 if (i
< num_tds
- 1)
3400 more_trbs_coming
= false;
3403 /* Calculate TRB length */
3404 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3405 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3406 if (trb_buff_len
> td_remain_len
)
3407 trb_buff_len
= td_remain_len
;
3409 /* Set the TRB length, TD size, & interrupter fields. */
3410 if (xhci
->hci_version
< 0x100) {
3411 remainder
= xhci_td_remainder(
3412 td_len
- running_total
);
3414 remainder
= xhci_v1_0_td_remainder(
3415 running_total
, trb_buff_len
,
3416 total_packet_count
, urb
);
3418 length_field
= TRB_LEN(trb_buff_len
) |
3422 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3423 lower_32_bits(addr
),
3424 upper_32_bits(addr
),
3427 running_total
+= trb_buff_len
;
3429 addr
+= trb_buff_len
;
3430 td_remain_len
-= trb_buff_len
;
3433 /* Check TD length */
3434 if (running_total
!= td_len
) {
3435 xhci_err(xhci
, "ISOC TD length unmatch\n");
3441 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3442 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3443 usb_amd_quirk_pll_disable();
3445 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3447 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3448 start_cycle
, start_trb
);
3451 /* Clean up a partially enqueued isoc transfer. */
3453 for (i
--; i
>= 0; i
--)
3454 list_del_init(&urb_priv
->td
[i
]->td_list
);
3456 /* Use the first TD as a temporary variable to turn the TDs we've queued
3457 * into No-ops with a software-owned cycle bit. That way the hardware
3458 * won't accidentally start executing bogus TDs when we partially
3459 * overwrite them. td->first_trb and td->start_seg are already set.
3461 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3462 /* Every TRB except the first & last will have its cycle bit flipped. */
3463 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3465 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3466 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3467 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3468 ep_ring
->cycle_state
= start_cycle
;
3469 ep_ring
->num_trbs_free
= ep_ring
->num_trbs_free_temp
;
3470 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3475 * Check transfer ring to guarantee there is enough room for the urb.
3476 * Update ISO URB start_frame and interval.
3477 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3478 * update the urb->start_frame by now.
3479 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3481 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3482 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3484 struct xhci_virt_device
*xdev
;
3485 struct xhci_ring
*ep_ring
;
3486 struct xhci_ep_ctx
*ep_ctx
;
3490 int num_tds
, num_trbs
, i
;
3493 xdev
= xhci
->devs
[slot_id
];
3494 ep_ring
= xdev
->eps
[ep_index
].ring
;
3495 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3498 num_tds
= urb
->number_of_packets
;
3499 for (i
= 0; i
< num_tds
; i
++)
3500 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3502 /* Check the ring to guarantee there is enough room for the whole urb.
3503 * Do not insert any td of the urb to the ring if the check failed.
3505 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3506 num_trbs
, mem_flags
);
3510 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3511 start_frame
&= 0x3fff;
3513 urb
->start_frame
= start_frame
;
3514 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3515 urb
->dev
->speed
== USB_SPEED_FULL
)
3516 urb
->start_frame
>>= 3;
3518 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3519 ep_interval
= urb
->interval
;
3520 /* Convert to microframes */
3521 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3522 urb
->dev
->speed
== USB_SPEED_FULL
)
3524 /* FIXME change this to a warning and a suggestion to use the new API
3525 * to set the polling interval (once the API is added).
3527 if (xhci_interval
!= ep_interval
) {
3528 if (printk_ratelimit())
3529 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3530 " (%d microframe%s) than xHCI "
3531 "(%d microframe%s)\n",
3533 ep_interval
== 1 ? "" : "s",
3535 xhci_interval
== 1 ? "" : "s");
3536 urb
->interval
= xhci_interval
;
3537 /* Convert back to frames for LS/FS devices */
3538 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3539 urb
->dev
->speed
== USB_SPEED_FULL
)
3542 ep_ring
->num_trbs_free_temp
= ep_ring
->num_trbs_free
;
3544 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3547 /**** Command Ring Operations ****/
3549 /* Generic function for queueing a command TRB on the command ring.
3550 * Check to make sure there's room on the command ring for one command TRB.
3551 * Also check that there's room reserved for commands that must not fail.
3552 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3553 * then only check for the number of reserved spots.
3554 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3555 * because the command event handler may want to resubmit a failed command.
3557 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3558 u32 field3
, u32 field4
, bool command_must_succeed
)
3560 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3563 if (!command_must_succeed
)
3566 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3567 reserved_trbs
, GFP_ATOMIC
);
3569 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3570 if (command_must_succeed
)
3571 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3572 "unfailable commands failed.\n");
3575 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
3576 field4
| xhci
->cmd_ring
->cycle_state
);
3580 /* Queue a slot enable or disable request on the command ring */
3581 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3583 return queue_command(xhci
, 0, 0, 0,
3584 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3587 /* Queue an address device command TRB */
3588 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3591 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3592 upper_32_bits(in_ctx_ptr
), 0,
3593 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3597 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3598 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3600 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3603 /* Queue a reset device command TRB */
3604 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3606 return queue_command(xhci
, 0, 0, 0,
3607 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3611 /* Queue a configure endpoint command TRB */
3612 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3613 u32 slot_id
, bool command_must_succeed
)
3615 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3616 upper_32_bits(in_ctx_ptr
), 0,
3617 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3618 command_must_succeed
);
3621 /* Queue an evaluate context command TRB */
3622 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3623 u32 slot_id
, bool command_must_succeed
)
3625 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3626 upper_32_bits(in_ctx_ptr
), 0,
3627 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3628 command_must_succeed
);
3632 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3633 * activity on an endpoint that is about to be suspended.
3635 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
3636 unsigned int ep_index
, int suspend
)
3638 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3639 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3640 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3641 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3643 return queue_command(xhci
, 0, 0, 0,
3644 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3647 /* Set Transfer Ring Dequeue Pointer command.
3648 * This should not be used for endpoints that have streams enabled.
3650 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
3651 unsigned int ep_index
, unsigned int stream_id
,
3652 struct xhci_segment
*deq_seg
,
3653 union xhci_trb
*deq_ptr
, u32 cycle_state
)
3656 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3657 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3658 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
3659 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
3660 struct xhci_virt_ep
*ep
;
3662 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
3664 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3665 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
3669 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3670 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
3671 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3672 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
3675 ep
->queued_deq_seg
= deq_seg
;
3676 ep
->queued_deq_ptr
= deq_ptr
;
3677 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
3678 upper_32_bits(addr
), trb_stream_id
,
3679 trb_slot_id
| trb_ep_index
| type
, false);
3682 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
3683 unsigned int ep_index
)
3685 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3686 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3687 u32 type
= TRB_TYPE(TRB_RESET_EP
);
3689 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,