2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
138 unsigned long long addr
;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
145 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
146 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
148 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring
->cycle_state
);
152 ring
->deq_seg
= ring
->deq_seg
->next
;
153 ring
->dequeue
= ring
->deq_seg
->trbs
;
154 next
= ring
->dequeue
;
156 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
157 if (ring
== xhci
->event_ring
)
158 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
159 else if (ring
== xhci
->cmd_ring
)
160 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
162 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set.
176 * Assume section 6.4.4.1 is wrong, and the chain bit can be set in a Link TRB.
178 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
181 union xhci_trb
*next
;
182 unsigned long long addr
;
184 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
185 next
= ++(ring
->enqueue
);
188 /* Update the dequeue pointer further if that was a link TRB or we're at
189 * the end of an event ring segment (which doesn't have link TRBS)
191 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
193 if (ring
!= xhci
->event_ring
) {
194 next
->link
.control
&= ~TRB_CHAIN
;
195 next
->link
.control
|= chain
;
196 /* Give this link TRB to the hardware */
198 if (next
->link
.control
& TRB_CYCLE
)
199 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
201 next
->link
.control
|= (u32
) TRB_CYCLE
;
203 /* Toggle the cycle bit after the last ring segment. */
204 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
205 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
207 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
209 (unsigned int) ring
->cycle_state
);
212 ring
->enq_seg
= ring
->enq_seg
->next
;
213 ring
->enqueue
= ring
->enq_seg
->trbs
;
214 next
= ring
->enqueue
;
216 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
217 if (ring
== xhci
->event_ring
)
218 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
219 else if (ring
== xhci
->cmd_ring
)
220 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
222 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
226 * Check to see if there's room to enqueue num_trbs on the ring. See rules
228 * FIXME: this would be simpler and faster if we just kept track of the number
229 * of free TRBs in a ring.
231 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
232 unsigned int num_trbs
)
235 union xhci_trb
*enq
= ring
->enqueue
;
236 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
238 /* Check if ring is empty */
239 if (enq
== ring
->dequeue
)
241 /* Make sure there's an extra empty TRB available */
242 for (i
= 0; i
<= num_trbs
; ++i
) {
243 if (enq
== ring
->dequeue
)
246 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
247 enq_seg
= enq_seg
->next
;
254 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
259 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
260 xhci
->event_ring
->dequeue
);
261 if (deq
== 0 && !in_interrupt())
262 xhci_warn(xhci
, "WARN something wrong with SW event ring "
264 /* Update HC event ring dequeue pointer */
265 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
266 temp
&= ERST_PTR_MASK
;
267 /* Don't clear the EHB bit (which is RW1C) because
268 * there might be more events to service.
271 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
272 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
273 &xhci
->ir_set
->erst_dequeue
);
276 /* Ring the host controller doorbell after placing a command on the ring */
277 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
281 xhci_dbg(xhci
, "// Ding dong!\n");
282 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
283 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
284 /* Flush PCI posted writes */
285 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
288 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
289 unsigned int slot_id
,
290 unsigned int ep_index
)
292 struct xhci_ring
*ep_ring
;
294 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
296 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
297 /* Don't ring the doorbell for this endpoint if there are pending
298 * cancellations because the we don't want to interrupt processing.
300 if (!ep_ring
->cancels_pending
&& !(ep_ring
->state
& SET_DEQ_PENDING
)
301 && !(ep_ring
->state
& EP_HALTED
)) {
302 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
303 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
304 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
305 * isn't time-critical and we shouldn't make the CPU wait for
308 xhci_readl(xhci
, db_addr
);
313 * Find the segment that trb is in. Start searching in start_seg.
314 * If we must move past a segment that has a link TRB with a toggle cycle state
315 * bit set, then we will toggle the value pointed at by cycle_state.
317 static struct xhci_segment
*find_trb_seg(
318 struct xhci_segment
*start_seg
,
319 union xhci_trb
*trb
, int *cycle_state
)
321 struct xhci_segment
*cur_seg
= start_seg
;
322 struct xhci_generic_trb
*generic_trb
;
324 while (cur_seg
->trbs
> trb
||
325 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
326 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
327 if (TRB_TYPE(generic_trb
->field
[3]) == TRB_LINK
&&
328 (generic_trb
->field
[3] & LINK_TOGGLE
))
329 *cycle_state
= ~(*cycle_state
) & 0x1;
330 cur_seg
= cur_seg
->next
;
331 if (cur_seg
== start_seg
)
332 /* Looped over the entire list. Oops! */
338 struct dequeue_state
{
339 struct xhci_segment
*new_deq_seg
;
340 union xhci_trb
*new_deq_ptr
;
345 * Move the xHC's endpoint ring dequeue pointer past cur_td.
346 * Record the new state of the xHC's endpoint ring dequeue segment,
347 * dequeue pointer, and new consumer cycle state in state.
348 * Update our internal representation of the ring's dequeue pointer.
350 * We do this in three jumps:
351 * - First we update our new ring state to be the same as when the xHC stopped.
352 * - Then we traverse the ring to find the segment that contains
353 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
354 * any link TRBs with the toggle cycle bit set.
355 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
356 * if we've moved it past a link TRB with the toggle cycle bit set.
358 static void find_new_dequeue_state(struct xhci_hcd
*xhci
,
359 unsigned int slot_id
, unsigned int ep_index
,
360 struct xhci_td
*cur_td
, struct dequeue_state
*state
)
362 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
363 struct xhci_ring
*ep_ring
= dev
->ep_rings
[ep_index
];
364 struct xhci_generic_trb
*trb
;
365 struct xhci_ep_ctx
*ep_ctx
;
367 state
->new_cycle_state
= 0;
368 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
369 ep_ring
->stopped_trb
,
370 &state
->new_cycle_state
);
371 if (!state
->new_deq_seg
)
373 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
374 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
375 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
377 state
->new_deq_ptr
= cur_td
->last_trb
;
378 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
380 &state
->new_cycle_state
);
381 if (!state
->new_deq_seg
)
384 trb
= &state
->new_deq_ptr
->generic
;
385 if (TRB_TYPE(trb
->field
[3]) == TRB_LINK
&&
386 (trb
->field
[3] & LINK_TOGGLE
))
387 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
388 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
390 /* Don't update the ring cycle state for the producer (us). */
391 ep_ring
->dequeue
= state
->new_deq_ptr
;
392 ep_ring
->deq_seg
= state
->new_deq_seg
;
395 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
396 struct xhci_td
*cur_td
)
398 struct xhci_segment
*cur_seg
;
399 union xhci_trb
*cur_trb
;
401 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
403 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
404 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
405 TRB_TYPE(TRB_LINK
)) {
406 /* Unchain any chained Link TRBs, but
407 * leave the pointers intact.
409 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
410 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
411 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
412 "in seg %p (0x%llx dma)\n",
414 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
416 (unsigned long long)cur_seg
->dma
);
418 cur_trb
->generic
.field
[0] = 0;
419 cur_trb
->generic
.field
[1] = 0;
420 cur_trb
->generic
.field
[2] = 0;
421 /* Preserve only the cycle bit of this TRB */
422 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
423 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
424 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
425 "in seg %p (0x%llx dma)\n",
427 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
429 (unsigned long long)cur_seg
->dma
);
431 if (cur_trb
== cur_td
->last_trb
)
436 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
437 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
438 union xhci_trb
*deq_ptr
, u32 cycle_state
);
441 * When we get a command completion for a Stop Endpoint Command, we need to
442 * unlink any cancelled TDs from the ring. There are two ways to do that:
444 * 1. If the HW was in the middle of processing the TD that needs to be
445 * cancelled, then we must move the ring's dequeue pointer past the last TRB
446 * in the TD with a Set Dequeue Pointer Command.
447 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
448 * bit cleared) so that the HW will skip over them.
450 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
453 unsigned int slot_id
;
454 unsigned int ep_index
;
455 struct xhci_ring
*ep_ring
;
456 struct list_head
*entry
;
457 struct xhci_td
*cur_td
= 0;
458 struct xhci_td
*last_unlinked_td
;
460 struct dequeue_state deq_state
;
461 #ifdef CONFIG_USB_HCD_STAT
462 ktime_t stop_time
= ktime_get();
465 memset(&deq_state
, 0, sizeof(deq_state
));
466 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
467 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
468 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
470 if (list_empty(&ep_ring
->cancelled_td_list
))
473 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
474 * We have the xHCI lock, so nothing can modify this list until we drop
475 * it. We're also in the event handler, so we can't get re-interrupted
476 * if another Stop Endpoint command completes
478 list_for_each(entry
, &ep_ring
->cancelled_td_list
) {
479 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
480 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
482 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
484 * If we stopped on the TD we need to cancel, then we have to
485 * move the xHC endpoint ring dequeue pointer past this TD.
487 if (cur_td
== ep_ring
->stopped_td
)
488 find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
491 td_to_noop(xhci
, ep_ring
, cur_td
);
493 * The event handler won't see a completion for this TD anymore,
494 * so remove it from the endpoint ring's TD list. Keep it in
495 * the cancelled TD list for URB completion later.
497 list_del(&cur_td
->td_list
);
498 ep_ring
->cancels_pending
--;
500 last_unlinked_td
= cur_td
;
502 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
503 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
504 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
505 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
506 deq_state
.new_deq_seg
,
507 (unsigned long long)deq_state
.new_deq_seg
->dma
,
508 deq_state
.new_deq_ptr
,
509 (unsigned long long)xhci_trb_virt_to_dma(deq_state
.new_deq_seg
, deq_state
.new_deq_ptr
),
510 deq_state
.new_cycle_state
);
511 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
512 deq_state
.new_deq_seg
,
513 deq_state
.new_deq_ptr
,
514 (u32
) deq_state
.new_cycle_state
);
515 /* Stop the TD queueing code from ringing the doorbell until
516 * this command completes. The HC won't set the dequeue pointer
517 * if the ring is running, and ringing the doorbell starts the
520 ep_ring
->state
|= SET_DEQ_PENDING
;
521 xhci_ring_cmd_db(xhci
);
523 /* Otherwise just ring the doorbell to restart the ring */
524 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
528 * Drop the lock and complete the URBs in the cancelled TD list.
529 * New TDs to be cancelled might be added to the end of the list before
530 * we can complete all the URBs for the TDs we already unlinked.
531 * So stop when we've completed the URB for the last TD we unlinked.
534 cur_td
= list_entry(ep_ring
->cancelled_td_list
.next
,
535 struct xhci_td
, cancelled_td_list
);
536 list_del(&cur_td
->cancelled_td_list
);
538 /* Clean up the cancelled URB */
539 #ifdef CONFIG_USB_HCD_STAT
540 hcd_stat_update(xhci
->tp_stat
, cur_td
->urb
->actual_length
,
541 ktime_sub(stop_time
, cur_td
->start_time
));
543 cur_td
->urb
->hcpriv
= NULL
;
544 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), cur_td
->urb
);
546 xhci_dbg(xhci
, "Giveback cancelled URB %p\n", cur_td
->urb
);
547 spin_unlock(&xhci
->lock
);
548 /* Doesn't matter what we pass for status, since the core will
549 * just overwrite it (because the URB has been unlinked).
551 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), cur_td
->urb
, 0);
554 spin_lock(&xhci
->lock
);
555 } while (cur_td
!= last_unlinked_td
);
557 /* Return to the event handler with xhci->lock re-acquired */
561 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
562 * we need to clear the set deq pending flag in the endpoint ring state, so that
563 * the TD queueing code can ring the doorbell again. We also need to ring the
564 * endpoint doorbell to restart the ring, but only if there aren't more
565 * cancellations pending.
567 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
568 struct xhci_event_cmd
*event
,
571 unsigned int slot_id
;
572 unsigned int ep_index
;
573 struct xhci_ring
*ep_ring
;
574 struct xhci_virt_device
*dev
;
575 struct xhci_ep_ctx
*ep_ctx
;
576 struct xhci_slot_ctx
*slot_ctx
;
578 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
579 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
580 dev
= xhci
->devs
[slot_id
];
581 ep_ring
= dev
->ep_rings
[ep_index
];
582 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
583 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
585 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
586 unsigned int ep_state
;
587 unsigned int slot_state
;
589 switch (GET_COMP_CODE(event
->status
)) {
591 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
592 "of stream ID configuration\n");
595 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
596 "to incorrect slot or ep state.\n");
597 ep_state
= ep_ctx
->ep_info
;
598 ep_state
&= EP_STATE_MASK
;
599 slot_state
= slot_ctx
->dev_state
;
600 slot_state
= GET_SLOT_STATE(slot_state
);
601 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
602 slot_state
, ep_state
);
605 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
606 "slot %u was not enabled.\n", slot_id
);
609 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
610 "completion code of %u.\n",
611 GET_COMP_CODE(event
->status
));
614 /* OK what do we do now? The endpoint state is hosed, and we
615 * should never get to this point if the synchronization between
616 * queueing, and endpoint state are correct. This might happen
617 * if the device gets disconnected after we've finished
618 * cancelling URBs, which might not be an error...
621 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
625 ep_ring
->state
&= ~SET_DEQ_PENDING
;
626 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
629 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
630 struct xhci_event_cmd
*event
,
634 unsigned int ep_index
;
636 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
637 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
638 /* This command will only fail if the endpoint wasn't halted,
641 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
642 (unsigned int) GET_COMP_CODE(event
->status
));
644 /* Clear our internal halted state and restart the ring */
645 xhci
->devs
[slot_id
]->ep_rings
[ep_index
]->state
&= ~EP_HALTED
;
646 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
649 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
650 struct xhci_event_cmd
*event
)
652 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
654 dma_addr_t cmd_dequeue_dma
;
656 cmd_dma
= event
->cmd_trb
;
657 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
658 xhci
->cmd_ring
->dequeue
);
659 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
660 if (cmd_dequeue_dma
== 0) {
661 xhci
->error_bitmask
|= 1 << 4;
664 /* Does the DMA address match our internal dequeue pointer address? */
665 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
666 xhci
->error_bitmask
|= 1 << 5;
669 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
670 case TRB_TYPE(TRB_ENABLE_SLOT
):
671 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
672 xhci
->slot_id
= slot_id
;
675 complete(&xhci
->addr_dev
);
677 case TRB_TYPE(TRB_DISABLE_SLOT
):
678 if (xhci
->devs
[slot_id
])
679 xhci_free_virt_device(xhci
, slot_id
);
681 case TRB_TYPE(TRB_CONFIG_EP
):
682 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
683 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
685 case TRB_TYPE(TRB_ADDR_DEV
):
686 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
687 complete(&xhci
->addr_dev
);
689 case TRB_TYPE(TRB_STOP_RING
):
690 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
692 case TRB_TYPE(TRB_SET_DEQ
):
693 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
695 case TRB_TYPE(TRB_CMD_NOOP
):
696 ++xhci
->noops_handled
;
698 case TRB_TYPE(TRB_RESET_EP
):
699 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
702 /* Skip over unknown commands on the event ring */
703 xhci
->error_bitmask
|= 1 << 6;
706 inc_deq(xhci
, xhci
->cmd_ring
, false);
709 static void handle_port_status(struct xhci_hcd
*xhci
,
710 union xhci_trb
*event
)
714 /* Port status change events always have a successful completion code */
715 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
716 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
717 xhci
->error_bitmask
|= 1 << 8;
719 /* FIXME: core doesn't care about all port link state changes yet */
720 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
721 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
723 /* Update event ring dequeue pointer before dropping the lock */
724 inc_deq(xhci
, xhci
->event_ring
, true);
725 xhci_set_hc_event_deq(xhci
);
727 spin_unlock(&xhci
->lock
);
728 /* Pass this up to the core */
729 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
730 spin_lock(&xhci
->lock
);
734 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
735 * at end_trb, which may be in another segment. If the suspect DMA address is a
736 * TRB in this TD, this function returns that TRB's segment. Otherwise it
739 static struct xhci_segment
*trb_in_td(
740 struct xhci_segment
*start_seg
,
741 union xhci_trb
*start_trb
,
742 union xhci_trb
*end_trb
,
743 dma_addr_t suspect_dma
)
745 dma_addr_t start_dma
;
746 dma_addr_t end_seg_dma
;
747 dma_addr_t end_trb_dma
;
748 struct xhci_segment
*cur_seg
;
750 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
754 /* We may get an event for a Link TRB in the middle of a TD */
755 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
756 &start_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
757 /* If the end TRB isn't in this segment, this is set to 0 */
758 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
760 if (end_trb_dma
> 0) {
761 /* The end TRB is in this segment, so suspect should be here */
762 if (start_dma
<= end_trb_dma
) {
763 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
766 /* Case for one segment with
767 * a TD wrapped around to the top
769 if ((suspect_dma
>= start_dma
&&
770 suspect_dma
<= end_seg_dma
) ||
771 (suspect_dma
>= cur_seg
->dma
&&
772 suspect_dma
<= end_trb_dma
))
777 /* Might still be somewhere in this segment */
778 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
781 cur_seg
= cur_seg
->next
;
782 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
788 * If this function returns an error condition, it means it got a Transfer
789 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
790 * At this point, the host controller is probably hosed and should be reset.
792 static int handle_tx_event(struct xhci_hcd
*xhci
,
793 struct xhci_transfer_event
*event
)
795 struct xhci_virt_device
*xdev
;
796 struct xhci_ring
*ep_ring
;
798 struct xhci_td
*td
= 0;
799 dma_addr_t event_dma
;
800 struct xhci_segment
*event_seg
;
801 union xhci_trb
*event_trb
;
803 int status
= -EINPROGRESS
;
804 struct xhci_ep_ctx
*ep_ctx
;
806 xhci_dbg(xhci
, "In %s\n", __func__
);
807 xdev
= xhci
->devs
[TRB_TO_SLOT_ID(event
->flags
)];
809 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
813 /* Endpoint ID is 1 based, our index is zero based */
814 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
815 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
816 ep_ring
= xdev
->ep_rings
[ep_index
];
817 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
818 if (!ep_ring
|| (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
819 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
823 event_dma
= event
->buffer
;
824 /* This TRB should be in the TD at the head of this ring's TD list */
825 xhci_dbg(xhci
, "%s - checking for list empty\n", __func__
);
826 if (list_empty(&ep_ring
->td_list
)) {
827 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
828 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
829 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
830 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
831 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
835 xhci_dbg(xhci
, "%s - getting list entry\n", __func__
);
836 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
838 /* Is this a TRB in the currently executing TD? */
839 xhci_dbg(xhci
, "%s - looking for TD\n", __func__
);
840 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
841 td
->last_trb
, event_dma
);
842 xhci_dbg(xhci
, "%s - found event_seg = %p\n", __func__
, event_seg
);
844 /* HC is busted, give up! */
845 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
848 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
849 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
850 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
851 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
852 lower_32_bits(event
->buffer
));
853 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
854 upper_32_bits(event
->buffer
));
855 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
856 (unsigned int) event
->transfer_len
);
857 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
858 (unsigned int) event
->flags
);
860 /* Look for common error cases */
861 switch (GET_COMP_CODE(event
->transfer_len
)) {
862 /* Skip codes that require special handling depending on
869 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
871 case COMP_STOP_INVAL
:
872 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
875 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
876 ep_ring
->state
|= EP_HALTED
;
880 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
884 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
888 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
892 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
896 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
900 /* Now update the urb's actual_length and give back to the core */
901 /* Was this a control transfer? */
902 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
903 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
904 switch (GET_COMP_CODE(event
->transfer_len
)) {
906 if (event_trb
== ep_ring
->dequeue
) {
907 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
909 } else if (event_trb
!= td
->last_trb
) {
910 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
913 xhci_dbg(xhci
, "Successful control transfer!\n");
918 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
922 /* Others already handled above */
926 * Did we transfer any data, despite the errors that might have
927 * happened? I.e. did we get past the setup stage?
929 if (event_trb
!= ep_ring
->dequeue
) {
930 /* The event was for the status stage */
931 if (event_trb
== td
->last_trb
) {
932 /* Did we already see a short data stage? */
933 if (td
->urb
->actual_length
!= 0)
936 td
->urb
->actual_length
=
937 td
->urb
->transfer_buffer_length
;
939 /* Maybe the event was for the data stage? */
940 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STOP_INVAL
) {
941 /* We didn't stop on a link TRB in the middle */
942 td
->urb
->actual_length
=
943 td
->urb
->transfer_buffer_length
-
944 TRB_LEN(event
->transfer_len
);
945 xhci_dbg(xhci
, "Waiting for status stage event\n");
952 switch (GET_COMP_CODE(event
->transfer_len
)) {
954 /* Double check that the HW transferred everything. */
955 if (event_trb
!= td
->last_trb
) {
956 xhci_warn(xhci
, "WARN Successful completion "
958 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
963 xhci_dbg(xhci
, "Successful bulk transfer!\n");
968 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
974 /* Others already handled above */
977 dev_dbg(&td
->urb
->dev
->dev
,
978 "ep %#x - asked for %d bytes, "
979 "%d bytes untransferred\n",
980 td
->urb
->ep
->desc
.bEndpointAddress
,
981 td
->urb
->transfer_buffer_length
,
982 TRB_LEN(event
->transfer_len
));
983 /* Fast path - was this the last TRB in the TD for this URB? */
984 if (event_trb
== td
->last_trb
) {
985 if (TRB_LEN(event
->transfer_len
) != 0) {
986 td
->urb
->actual_length
=
987 td
->urb
->transfer_buffer_length
-
988 TRB_LEN(event
->transfer_len
);
989 if (td
->urb
->actual_length
< 0) {
990 xhci_warn(xhci
, "HC gave bad length "
991 "of %d bytes left\n",
992 TRB_LEN(event
->transfer_len
));
993 td
->urb
->actual_length
= 0;
995 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1000 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
1001 /* Ignore a short packet completion if the
1002 * untransferred length was zero.
1007 /* Slow path - walk the list, starting from the dequeue
1008 * pointer, to get the actual length transferred.
1010 union xhci_trb
*cur_trb
;
1011 struct xhci_segment
*cur_seg
;
1013 td
->urb
->actual_length
= 0;
1014 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1015 cur_trb
!= event_trb
;
1016 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1017 if (TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_TR_NOOP
&&
1018 TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_LINK
)
1019 td
->urb
->actual_length
+=
1020 TRB_LEN(cur_trb
->generic
.field
[2]);
1022 /* If the ring didn't stop on a Link or No-op TRB, add
1023 * in the actual bytes transferred from the Normal TRB
1025 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STOP_INVAL
)
1026 td
->urb
->actual_length
+=
1027 TRB_LEN(cur_trb
->generic
.field
[2]) -
1028 TRB_LEN(event
->transfer_len
);
1031 /* The Endpoint Stop Command completion will take care of
1032 * any stopped TDs. A stopped TD may be restarted, so don't update the
1033 * ring dequeue pointer or take this TD off any lists yet.
1035 if (GET_COMP_CODE(event
->transfer_len
) == COMP_STOP_INVAL
||
1036 GET_COMP_CODE(event
->transfer_len
) == COMP_STOP
) {
1037 ep_ring
->stopped_td
= td
;
1038 ep_ring
->stopped_trb
= event_trb
;
1040 /* Update ring dequeue pointer */
1041 while (ep_ring
->dequeue
!= td
->last_trb
)
1042 inc_deq(xhci
, ep_ring
, false);
1043 inc_deq(xhci
, ep_ring
, false);
1045 /* Clean up the endpoint's TD list */
1047 list_del(&td
->td_list
);
1048 /* Was this TD slated to be cancelled but completed anyway? */
1049 if (!list_empty(&td
->cancelled_td_list
)) {
1050 list_del(&td
->cancelled_td_list
);
1051 ep_ring
->cancels_pending
--;
1057 inc_deq(xhci
, xhci
->event_ring
, true);
1058 xhci_set_hc_event_deq(xhci
);
1060 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1062 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1063 xhci_dbg(xhci
, "Giveback URB %p, len = %d, status = %d\n",
1064 urb
, td
->urb
->actual_length
, status
);
1065 spin_unlock(&xhci
->lock
);
1066 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1067 spin_lock(&xhci
->lock
);
1073 * This function handles all OS-owned events on the event ring. It may drop
1074 * xhci->lock between event processing (e.g. to pass up port status changes).
1076 void xhci_handle_event(struct xhci_hcd
*xhci
)
1078 union xhci_trb
*event
;
1079 int update_ptrs
= 1;
1082 xhci_dbg(xhci
, "In %s\n", __func__
);
1083 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1084 xhci
->error_bitmask
|= 1 << 1;
1088 event
= xhci
->event_ring
->dequeue
;
1089 /* Does the HC or OS own the TRB? */
1090 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1091 xhci
->event_ring
->cycle_state
) {
1092 xhci
->error_bitmask
|= 1 << 2;
1095 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1097 /* FIXME: Handle more event types. */
1098 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1099 case TRB_TYPE(TRB_COMPLETION
):
1100 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1101 handle_cmd_completion(xhci
, &event
->event_cmd
);
1102 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1104 case TRB_TYPE(TRB_PORT_STATUS
):
1105 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1106 handle_port_status(xhci
, event
);
1107 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
1110 case TRB_TYPE(TRB_TRANSFER
):
1111 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
1112 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1113 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
1115 xhci
->error_bitmask
|= 1 << 9;
1120 xhci
->error_bitmask
|= 1 << 3;
1124 /* Update SW and HC event ring dequeue pointer */
1125 inc_deq(xhci
, xhci
->event_ring
, true);
1126 xhci_set_hc_event_deq(xhci
);
1128 /* Are there more items on the event ring? */
1129 xhci_handle_event(xhci
);
1132 /**** Endpoint Ring Operations ****/
1135 * Generic function for queueing a TRB on a ring.
1136 * The caller must have checked to make sure there's room on the ring.
1138 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1140 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1142 struct xhci_generic_trb
*trb
;
1144 trb
= &ring
->enqueue
->generic
;
1145 trb
->field
[0] = field1
;
1146 trb
->field
[1] = field2
;
1147 trb
->field
[2] = field3
;
1148 trb
->field
[3] = field4
;
1149 inc_enq(xhci
, ring
, consumer
);
1153 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1154 * FIXME allocate segments if the ring is full.
1156 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1157 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1159 /* Make sure the endpoint has been added to xHC schedule */
1160 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1162 case EP_STATE_DISABLED
:
1164 * USB core changed config/interfaces without notifying us,
1165 * or hardware is reporting the wrong state.
1167 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1169 case EP_STATE_HALTED
:
1170 case EP_STATE_ERROR
:
1171 xhci_warn(xhci
, "WARN waiting for halt or error on ep "
1173 /* FIXME event handling code for error needs to clear it */
1174 /* XXX not sure if this should be -ENOENT or not */
1176 case EP_STATE_STOPPED
:
1177 case EP_STATE_RUNNING
:
1180 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1182 * FIXME issue Configure Endpoint command to try to get the HC
1183 * back into a known state.
1187 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1188 /* FIXME allocate more room */
1189 xhci_err(xhci
, "ERROR no room on ep ring\n");
1195 static int prepare_transfer(struct xhci_hcd
*xhci
,
1196 struct xhci_virt_device
*xdev
,
1197 unsigned int ep_index
,
1198 unsigned int num_trbs
,
1200 struct xhci_td
**td
,
1204 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1205 ret
= prepare_ring(xhci
, xdev
->ep_rings
[ep_index
],
1206 ep_ctx
->ep_info
& EP_STATE_MASK
,
1207 num_trbs
, mem_flags
);
1210 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1213 INIT_LIST_HEAD(&(*td
)->td_list
);
1214 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1216 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1217 if (unlikely(ret
)) {
1223 urb
->hcpriv
= (void *) (*td
);
1224 /* Add this TD to the tail of the endpoint ring's TD list */
1225 list_add_tail(&(*td
)->td_list
, &xdev
->ep_rings
[ep_index
]->td_list
);
1226 (*td
)->start_seg
= xdev
->ep_rings
[ep_index
]->enq_seg
;
1227 (*td
)->first_trb
= xdev
->ep_rings
[ep_index
]->enqueue
;
1232 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1234 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1235 struct scatterlist
*sg
;
1238 num_sgs
= urb
->num_sgs
;
1239 temp
= urb
->transfer_buffer_length
;
1241 xhci_dbg(xhci
, "count sg list trbs: \n");
1243 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1244 unsigned int previous_total_trbs
= num_trbs
;
1245 unsigned int len
= sg_dma_len(sg
);
1247 /* Scatter gather list entries may cross 64KB boundaries */
1248 running_total
= TRB_MAX_BUFF_SIZE
-
1249 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1250 if (running_total
!= 0)
1253 /* How many more 64KB chunks to transfer, how many more TRBs? */
1254 while (running_total
< sg_dma_len(sg
)) {
1256 running_total
+= TRB_MAX_BUFF_SIZE
;
1258 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1259 i
, (unsigned long long)sg_dma_address(sg
),
1260 len
, len
, num_trbs
- previous_total_trbs
);
1262 len
= min_t(int, len
, temp
);
1267 xhci_dbg(xhci
, "\n");
1268 if (!in_interrupt())
1269 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1270 urb
->ep
->desc
.bEndpointAddress
,
1271 urb
->transfer_buffer_length
,
1276 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1279 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1280 "TRBs, %d left\n", __func__
,
1281 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1282 if (running_total
!= urb
->transfer_buffer_length
)
1283 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1284 "queued %#x (%d), asked for %#x (%d)\n",
1286 urb
->ep
->desc
.bEndpointAddress
,
1287 running_total
, running_total
,
1288 urb
->transfer_buffer_length
,
1289 urb
->transfer_buffer_length
);
1292 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1293 unsigned int ep_index
, int start_cycle
,
1294 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1297 * Pass all the TRBs to the hardware at once and make sure this write
1301 start_trb
->field
[3] |= start_cycle
;
1302 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1305 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1306 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1308 struct xhci_ring
*ep_ring
;
1309 unsigned int num_trbs
;
1311 struct scatterlist
*sg
;
1313 int trb_buff_len
, this_sg_len
, running_total
;
1317 struct xhci_generic_trb
*start_trb
;
1320 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1321 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1322 num_sgs
= urb
->num_sgs
;
1324 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1325 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1326 if (trb_buff_len
< 0)
1327 return trb_buff_len
;
1329 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1330 * until we've finished creating all the other TRBs. The ring's cycle
1331 * state may change as we enqueue the other TRBs, so save it too.
1333 start_trb
= &ep_ring
->enqueue
->generic
;
1334 start_cycle
= ep_ring
->cycle_state
;
1338 * How much data is in the first TRB?
1340 * There are three forces at work for TRB buffer pointers and lengths:
1341 * 1. We don't want to walk off the end of this sg-list entry buffer.
1342 * 2. The transfer length that the driver requested may be smaller than
1343 * the amount of memory allocated for this scatter-gather list.
1344 * 3. TRBs buffers can't cross 64KB boundaries.
1347 addr
= (u64
) sg_dma_address(sg
);
1348 this_sg_len
= sg_dma_len(sg
);
1349 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1350 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1351 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1352 if (trb_buff_len
> urb
->transfer_buffer_length
)
1353 trb_buff_len
= urb
->transfer_buffer_length
;
1354 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1358 /* Queue the first TRB, even if it's zero-length */
1361 u32 length_field
= 0;
1363 /* Don't change the cycle bit of the first TRB until later */
1367 field
|= ep_ring
->cycle_state
;
1369 /* Chain all the TRBs together; clear the chain bit in the last
1370 * TRB to indicate it's the last TRB in the chain.
1375 /* FIXME - add check for ZERO_PACKET flag before this */
1376 td
->last_trb
= ep_ring
->enqueue
;
1379 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1380 "64KB boundary at %#x, end dma = %#x\n",
1381 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1382 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1383 (unsigned int) addr
+ trb_buff_len
);
1384 if (TRB_MAX_BUFF_SIZE
-
1385 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
1386 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1387 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1388 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1389 (unsigned int) addr
+ trb_buff_len
);
1391 length_field
= TRB_LEN(trb_buff_len
) |
1392 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1394 queue_trb(xhci
, ep_ring
, false,
1395 lower_32_bits(addr
),
1396 upper_32_bits(addr
),
1398 /* We always want to know if the TRB was short,
1399 * or we won't get an event when it completes.
1400 * (Unless we use event data TRBs, which are a
1401 * waste of space and HC resources.)
1403 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1405 running_total
+= trb_buff_len
;
1407 /* Calculate length for next transfer --
1408 * Are we done queueing all the TRBs for this sg entry?
1410 this_sg_len
-= trb_buff_len
;
1411 if (this_sg_len
== 0) {
1416 addr
= (u64
) sg_dma_address(sg
);
1417 this_sg_len
= sg_dma_len(sg
);
1419 addr
+= trb_buff_len
;
1422 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1423 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1424 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1425 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1427 urb
->transfer_buffer_length
- running_total
;
1428 } while (running_total
< urb
->transfer_buffer_length
);
1430 check_trb_math(urb
, num_trbs
, running_total
);
1431 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1435 /* This is very similar to what ehci-q.c qtd_fill() does */
1436 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1437 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1439 struct xhci_ring
*ep_ring
;
1442 struct xhci_generic_trb
*start_trb
;
1445 u32 field
, length_field
;
1447 int running_total
, trb_buff_len
, ret
;
1451 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1453 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1456 /* How much data is (potentially) left before the 64KB boundary? */
1457 running_total
= TRB_MAX_BUFF_SIZE
-
1458 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1460 /* If there's some data on this 64KB chunk, or we have to send a
1461 * zero-length transfer, we need at least one TRB
1463 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1465 /* How many more 64KB chunks to transfer, how many more TRBs? */
1466 while (running_total
< urb
->transfer_buffer_length
) {
1468 running_total
+= TRB_MAX_BUFF_SIZE
;
1470 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1472 if (!in_interrupt())
1473 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1474 urb
->ep
->desc
.bEndpointAddress
,
1475 urb
->transfer_buffer_length
,
1476 urb
->transfer_buffer_length
,
1477 (unsigned long long)urb
->transfer_dma
,
1480 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1481 num_trbs
, urb
, &td
, mem_flags
);
1486 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1487 * until we've finished creating all the other TRBs. The ring's cycle
1488 * state may change as we enqueue the other TRBs, so save it too.
1490 start_trb
= &ep_ring
->enqueue
->generic
;
1491 start_cycle
= ep_ring
->cycle_state
;
1494 /* How much data is in the first TRB? */
1495 addr
= (u64
) urb
->transfer_dma
;
1496 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1497 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1498 if (urb
->transfer_buffer_length
< trb_buff_len
)
1499 trb_buff_len
= urb
->transfer_buffer_length
;
1503 /* Queue the first TRB, even if it's zero-length */
1507 /* Don't change the cycle bit of the first TRB until later */
1511 field
|= ep_ring
->cycle_state
;
1513 /* Chain all the TRBs together; clear the chain bit in the last
1514 * TRB to indicate it's the last TRB in the chain.
1519 /* FIXME - add check for ZERO_PACKET flag before this */
1520 td
->last_trb
= ep_ring
->enqueue
;
1523 length_field
= TRB_LEN(trb_buff_len
) |
1524 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1526 queue_trb(xhci
, ep_ring
, false,
1527 lower_32_bits(addr
),
1528 upper_32_bits(addr
),
1530 /* We always want to know if the TRB was short,
1531 * or we won't get an event when it completes.
1532 * (Unless we use event data TRBs, which are a
1533 * waste of space and HC resources.)
1535 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1537 running_total
+= trb_buff_len
;
1539 /* Calculate length for next transfer */
1540 addr
+= trb_buff_len
;
1541 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
1542 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
1543 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
1544 } while (running_total
< urb
->transfer_buffer_length
);
1546 check_trb_math(urb
, num_trbs
, running_total
);
1547 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1551 /* Caller must have locked xhci->lock */
1552 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1553 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1555 struct xhci_ring
*ep_ring
;
1558 struct usb_ctrlrequest
*setup
;
1559 struct xhci_generic_trb
*start_trb
;
1561 u32 field
, length_field
;
1564 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1567 * Need to copy setup packet into setup TRB, so we can't use the setup
1570 if (!urb
->setup_packet
)
1573 if (!in_interrupt())
1574 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
1576 /* 1 TRB for setup, 1 for status */
1579 * Don't need to check if we need additional event data and normal TRBs,
1580 * since data in control transfers will never get bigger than 16MB
1581 * XXX: can we get a buffer that crosses 64KB boundaries?
1583 if (urb
->transfer_buffer_length
> 0)
1585 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
1586 urb
, &td
, mem_flags
);
1591 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1592 * until we've finished creating all the other TRBs. The ring's cycle
1593 * state may change as we enqueue the other TRBs, so save it too.
1595 start_trb
= &ep_ring
->enqueue
->generic
;
1596 start_cycle
= ep_ring
->cycle_state
;
1598 /* Queue setup TRB - see section 6.4.1.2.1 */
1599 /* FIXME better way to translate setup_packet into two u32 fields? */
1600 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
1601 queue_trb(xhci
, ep_ring
, false,
1602 /* FIXME endianness is probably going to bite my ass here. */
1603 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
1604 setup
->wIndex
| setup
->wLength
<< 16,
1605 TRB_LEN(8) | TRB_INTR_TARGET(0),
1606 /* Immediate data in pointer */
1607 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
1609 /* If there's data, queue data TRBs */
1611 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
1612 TD_REMAINDER(urb
->transfer_buffer_length
) |
1614 if (urb
->transfer_buffer_length
> 0) {
1615 if (setup
->bRequestType
& USB_DIR_IN
)
1616 field
|= TRB_DIR_IN
;
1617 queue_trb(xhci
, ep_ring
, false,
1618 lower_32_bits(urb
->transfer_dma
),
1619 upper_32_bits(urb
->transfer_dma
),
1621 /* Event on short tx */
1622 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
1625 /* Save the DMA address of the last TRB in the TD */
1626 td
->last_trb
= ep_ring
->enqueue
;
1628 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1629 /* If the device sent data, the status stage is an OUT transfer */
1630 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
1634 queue_trb(xhci
, ep_ring
, false,
1638 /* Event on completion */
1639 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
1641 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1645 /**** Command Ring Operations ****/
1647 /* Generic function for queueing a command TRB on the command ring */
1648 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1650 if (!room_on_ring(xhci
, xhci
->cmd_ring
, 1)) {
1651 if (!in_interrupt())
1652 xhci_err(xhci
, "ERR: No room for command on command ring\n");
1655 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
1656 field4
| xhci
->cmd_ring
->cycle_state
);
1660 /* Queue a no-op command on the command ring */
1661 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
1663 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
));
1667 * Place a no-op command on the command ring to test the command and
1670 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
1672 if (queue_cmd_noop(xhci
) < 0)
1674 xhci
->noops_submitted
++;
1675 return xhci_ring_cmd_db
;
1678 /* Queue a slot enable or disable request on the command ring */
1679 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
1681 return queue_command(xhci
, 0, 0, 0,
1682 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
));
1685 /* Queue an address device command TRB */
1686 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1689 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1690 upper_32_bits(in_ctx_ptr
), 0,
1691 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
));
1694 /* Queue a configure endpoint command TRB */
1695 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1698 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1699 upper_32_bits(in_ctx_ptr
), 0,
1700 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
));
1703 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
1704 unsigned int ep_index
)
1706 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1707 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1708 u32 type
= TRB_TYPE(TRB_STOP_RING
);
1710 return queue_command(xhci
, 0, 0, 0,
1711 trb_slot_id
| trb_ep_index
| type
);
1714 /* Set Transfer Ring Dequeue Pointer command.
1715 * This should not be used for endpoints that have streams enabled.
1717 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
1718 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
1719 union xhci_trb
*deq_ptr
, u32 cycle_state
)
1722 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1723 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1724 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
1726 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
1728 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
1729 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
1731 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
1732 upper_32_bits(addr
), 0,
1733 trb_slot_id
| trb_ep_index
| type
);
1736 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1737 unsigned int ep_index
)
1739 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1740 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1741 u32 type
= TRB_TYPE(TRB_RESET_EP
);
1743 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
);