2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
138 unsigned long long addr
;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
145 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
146 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
148 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring
->cycle_state
);
152 ring
->deq_seg
= ring
->deq_seg
->next
;
153 ring
->dequeue
= ring
->deq_seg
->trbs
;
154 next
= ring
->dequeue
;
156 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
157 if (ring
== xhci
->event_ring
)
158 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
159 else if (ring
== xhci
->cmd_ring
)
160 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
162 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
179 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
182 union xhci_trb
*next
;
183 unsigned long long addr
;
185 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
186 next
= ++(ring
->enqueue
);
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
192 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
194 if (ring
!= xhci
->event_ring
) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
199 if (!xhci_link_trb_quirk(xhci
)) {
200 next
->link
.control
&= ~TRB_CHAIN
;
201 next
->link
.control
|= chain
;
203 /* Give this link TRB to the hardware */
205 if (next
->link
.control
& TRB_CYCLE
)
206 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
208 next
->link
.control
|= (u32
) TRB_CYCLE
;
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
212 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
214 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
216 (unsigned int) ring
->cycle_state
);
219 ring
->enq_seg
= ring
->enq_seg
->next
;
220 ring
->enqueue
= ring
->enq_seg
->trbs
;
221 next
= ring
->enqueue
;
223 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
224 if (ring
== xhci
->event_ring
)
225 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
226 else if (ring
== xhci
->cmd_ring
)
227 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
229 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
238 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
239 unsigned int num_trbs
)
242 union xhci_trb
*enq
= ring
->enqueue
;
243 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
245 /* Check if ring is empty */
246 if (enq
== ring
->dequeue
)
248 /* Make sure there's an extra empty TRB available */
249 for (i
= 0; i
<= num_trbs
; ++i
) {
250 if (enq
== ring
->dequeue
)
253 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
254 enq_seg
= enq_seg
->next
;
261 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
266 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
267 xhci
->event_ring
->dequeue
);
268 if (deq
== 0 && !in_interrupt())
269 xhci_warn(xhci
, "WARN something wrong with SW event ring "
271 /* Update HC event ring dequeue pointer */
272 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
273 temp
&= ERST_PTR_MASK
;
274 /* Don't clear the EHB bit (which is RW1C) because
275 * there might be more events to service.
278 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
279 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
280 &xhci
->ir_set
->erst_dequeue
);
283 /* Ring the host controller doorbell after placing a command on the ring */
284 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
288 xhci_dbg(xhci
, "// Ding dong!\n");
289 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
290 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
291 /* Flush PCI posted writes */
292 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
295 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
296 unsigned int slot_id
,
297 unsigned int ep_index
)
299 struct xhci_virt_ep
*ep
;
300 unsigned int ep_state
;
302 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
304 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
305 ep_state
= ep
->ep_state
;
306 /* Don't ring the doorbell for this endpoint if there are pending
307 * cancellations because the we don't want to interrupt processing.
309 if (!(ep_state
& EP_HALT_PENDING
) && !(ep_state
& SET_DEQ_PENDING
)
310 && !(ep_state
& EP_HALTED
)) {
311 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
312 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
313 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
314 * isn't time-critical and we shouldn't make the CPU wait for
317 xhci_readl(xhci
, db_addr
);
322 * Find the segment that trb is in. Start searching in start_seg.
323 * If we must move past a segment that has a link TRB with a toggle cycle state
324 * bit set, then we will toggle the value pointed at by cycle_state.
326 static struct xhci_segment
*find_trb_seg(
327 struct xhci_segment
*start_seg
,
328 union xhci_trb
*trb
, int *cycle_state
)
330 struct xhci_segment
*cur_seg
= start_seg
;
331 struct xhci_generic_trb
*generic_trb
;
333 while (cur_seg
->trbs
> trb
||
334 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
335 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
336 if (TRB_TYPE(generic_trb
->field
[3]) == TRB_LINK
&&
337 (generic_trb
->field
[3] & LINK_TOGGLE
))
338 *cycle_state
= ~(*cycle_state
) & 0x1;
339 cur_seg
= cur_seg
->next
;
340 if (cur_seg
== start_seg
)
341 /* Looped over the entire list. Oops! */
348 * Move the xHC's endpoint ring dequeue pointer past cur_td.
349 * Record the new state of the xHC's endpoint ring dequeue segment,
350 * dequeue pointer, and new consumer cycle state in state.
351 * Update our internal representation of the ring's dequeue pointer.
353 * We do this in three jumps:
354 * - First we update our new ring state to be the same as when the xHC stopped.
355 * - Then we traverse the ring to find the segment that contains
356 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
357 * any link TRBs with the toggle cycle bit set.
358 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
359 * if we've moved it past a link TRB with the toggle cycle bit set.
361 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
362 unsigned int slot_id
, unsigned int ep_index
,
363 struct xhci_td
*cur_td
, struct xhci_dequeue_state
*state
)
365 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
366 struct xhci_ring
*ep_ring
= dev
->eps
[ep_index
].ring
;
367 struct xhci_generic_trb
*trb
;
368 struct xhci_ep_ctx
*ep_ctx
;
371 state
->new_cycle_state
= 0;
372 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
373 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
374 dev
->eps
[ep_index
].stopped_trb
,
375 &state
->new_cycle_state
);
376 if (!state
->new_deq_seg
)
378 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
379 xhci_dbg(xhci
, "Finding endpoint context\n");
380 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
381 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
383 state
->new_deq_ptr
= cur_td
->last_trb
;
384 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
385 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
387 &state
->new_cycle_state
);
388 if (!state
->new_deq_seg
)
391 trb
= &state
->new_deq_ptr
->generic
;
392 if (TRB_TYPE(trb
->field
[3]) == TRB_LINK
&&
393 (trb
->field
[3] & LINK_TOGGLE
))
394 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
395 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
397 /* Don't update the ring cycle state for the producer (us). */
398 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
400 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
401 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
402 (unsigned long long) addr
);
403 xhci_dbg(xhci
, "Setting dequeue pointer in internal ring state.\n");
404 ep_ring
->dequeue
= state
->new_deq_ptr
;
405 ep_ring
->deq_seg
= state
->new_deq_seg
;
408 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
409 struct xhci_td
*cur_td
)
411 struct xhci_segment
*cur_seg
;
412 union xhci_trb
*cur_trb
;
414 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
416 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
417 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
418 TRB_TYPE(TRB_LINK
)) {
419 /* Unchain any chained Link TRBs, but
420 * leave the pointers intact.
422 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
423 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
424 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
425 "in seg %p (0x%llx dma)\n",
427 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
429 (unsigned long long)cur_seg
->dma
);
431 cur_trb
->generic
.field
[0] = 0;
432 cur_trb
->generic
.field
[1] = 0;
433 cur_trb
->generic
.field
[2] = 0;
434 /* Preserve only the cycle bit of this TRB */
435 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
436 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
437 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
438 "in seg %p (0x%llx dma)\n",
440 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
442 (unsigned long long)cur_seg
->dma
);
444 if (cur_trb
== cur_td
->last_trb
)
449 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
450 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
451 union xhci_trb
*deq_ptr
, u32 cycle_state
);
453 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
454 unsigned int slot_id
, unsigned int ep_index
,
455 struct xhci_dequeue_state
*deq_state
)
457 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
459 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
460 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
461 deq_state
->new_deq_seg
,
462 (unsigned long long)deq_state
->new_deq_seg
->dma
,
463 deq_state
->new_deq_ptr
,
464 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
465 deq_state
->new_cycle_state
);
466 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
467 deq_state
->new_deq_seg
,
468 deq_state
->new_deq_ptr
,
469 (u32
) deq_state
->new_cycle_state
);
470 /* Stop the TD queueing code from ringing the doorbell until
471 * this command completes. The HC won't set the dequeue pointer
472 * if the ring is running, and ringing the doorbell starts the
475 ep
->ep_state
|= SET_DEQ_PENDING
;
478 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
479 struct xhci_virt_ep
*ep
)
481 ep
->ep_state
&= ~EP_HALT_PENDING
;
482 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
483 * timer is running on another CPU, we don't decrement stop_cmds_pending
484 * (since we didn't successfully stop the watchdog timer).
486 if (del_timer(&ep
->stop_cmd_timer
))
487 ep
->stop_cmds_pending
--;
490 /* Must be called with xhci->lock held in interrupt context */
491 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
492 struct xhci_td
*cur_td
, int status
, char *adjective
)
494 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
496 cur_td
->urb
->hcpriv
= NULL
;
497 usb_hcd_unlink_urb_from_ep(hcd
, cur_td
->urb
);
498 xhci_dbg(xhci
, "Giveback %s URB %p\n", adjective
, cur_td
->urb
);
500 spin_unlock(&xhci
->lock
);
501 usb_hcd_giveback_urb(hcd
, cur_td
->urb
, status
);
503 spin_lock(&xhci
->lock
);
504 xhci_dbg(xhci
, "%s URB given back\n", adjective
);
508 * When we get a command completion for a Stop Endpoint Command, we need to
509 * unlink any cancelled TDs from the ring. There are two ways to do that:
511 * 1. If the HW was in the middle of processing the TD that needs to be
512 * cancelled, then we must move the ring's dequeue pointer past the last TRB
513 * in the TD with a Set Dequeue Pointer Command.
514 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
515 * bit cleared) so that the HW will skip over them.
517 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
520 unsigned int slot_id
;
521 unsigned int ep_index
;
522 struct xhci_ring
*ep_ring
;
523 struct xhci_virt_ep
*ep
;
524 struct list_head
*entry
;
525 struct xhci_td
*cur_td
= 0;
526 struct xhci_td
*last_unlinked_td
;
528 struct xhci_dequeue_state deq_state
;
530 memset(&deq_state
, 0, sizeof(deq_state
));
531 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
532 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
533 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
536 if (list_empty(&ep
->cancelled_td_list
)) {
537 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
538 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
542 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
543 * We have the xHCI lock, so nothing can modify this list until we drop
544 * it. We're also in the event handler, so we can't get re-interrupted
545 * if another Stop Endpoint command completes
547 list_for_each(entry
, &ep
->cancelled_td_list
) {
548 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
549 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
551 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
553 * If we stopped on the TD we need to cancel, then we have to
554 * move the xHC endpoint ring dequeue pointer past this TD.
556 if (cur_td
== ep
->stopped_td
)
557 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
560 td_to_noop(xhci
, ep_ring
, cur_td
);
562 * The event handler won't see a completion for this TD anymore,
563 * so remove it from the endpoint ring's TD list. Keep it in
564 * the cancelled TD list for URB completion later.
566 list_del(&cur_td
->td_list
);
568 last_unlinked_td
= cur_td
;
569 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
571 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
572 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
573 xhci_queue_new_dequeue_state(xhci
,
574 slot_id
, ep_index
, &deq_state
);
575 xhci_ring_cmd_db(xhci
);
577 /* Otherwise just ring the doorbell to restart the ring */
578 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
582 * Drop the lock and complete the URBs in the cancelled TD list.
583 * New TDs to be cancelled might be added to the end of the list before
584 * we can complete all the URBs for the TDs we already unlinked.
585 * So stop when we've completed the URB for the last TD we unlinked.
588 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
589 struct xhci_td
, cancelled_td_list
);
590 list_del(&cur_td
->cancelled_td_list
);
592 /* Clean up the cancelled URB */
593 /* Doesn't matter what we pass for status, since the core will
594 * just overwrite it (because the URB has been unlinked).
596 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
598 /* Stop processing the cancelled list if the watchdog timer is
601 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
603 } while (cur_td
!= last_unlinked_td
);
605 /* Return to the event handler with xhci->lock re-acquired */
608 /* Watchdog timer function for when a stop endpoint command fails to complete.
609 * In this case, we assume the host controller is broken or dying or dead. The
610 * host may still be completing some other events, so we have to be careful to
611 * let the event ring handler and the URB dequeueing/enqueueing functions know
612 * through xhci->state.
614 * The timer may also fire if the host takes a very long time to respond to the
615 * command, and the stop endpoint command completion handler cannot delete the
616 * timer before the timer function is called. Another endpoint cancellation may
617 * sneak in before the timer function can grab the lock, and that may queue
618 * another stop endpoint command and add the timer back. So we cannot use a
619 * simple flag to say whether there is a pending stop endpoint command for a
620 * particular endpoint.
622 * Instead we use a combination of that flag and a counter for the number of
623 * pending stop endpoint commands. If the timer is the tail end of the last
624 * stop endpoint command, and the endpoint's command is still pending, we assume
627 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
629 struct xhci_hcd
*xhci
;
630 struct xhci_virt_ep
*ep
;
631 struct xhci_virt_ep
*temp_ep
;
632 struct xhci_ring
*ring
;
633 struct xhci_td
*cur_td
;
636 ep
= (struct xhci_virt_ep
*) arg
;
639 spin_lock(&xhci
->lock
);
641 ep
->stop_cmds_pending
--;
642 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
643 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
644 "xHCI as DYING, exiting.\n");
645 spin_unlock(&xhci
->lock
);
648 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
649 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
651 spin_unlock(&xhci
->lock
);
655 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
656 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
657 /* Oops, HC is dead or dying or at least not responding to the stop
660 xhci
->xhc_state
|= XHCI_STATE_DYING
;
661 /* Disable interrupts from the host controller and start halting it */
663 spin_unlock(&xhci
->lock
);
665 ret
= xhci_halt(xhci
);
667 spin_lock(&xhci
->lock
);
669 /* This is bad; the host is not responding to commands and it's
670 * not allowing itself to be halted. At least interrupts are
671 * disabled, so we can set HC_STATE_HALT and notify the
672 * USB core. But if we call usb_hc_died(), it will attempt to
673 * disconnect all device drivers under this host. Those
674 * disconnect() methods will wait for all URBs to be unlinked,
675 * so we must complete them.
677 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
678 xhci_warn(xhci
, "Completing active URBs anyway.\n");
679 /* We could turn all TDs on the rings to no-ops. This won't
680 * help if the host has cached part of the ring, and is slow if
681 * we want to preserve the cycle bit. Skip it and hope the host
682 * doesn't touch the memory.
685 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
688 for (j
= 0; j
< 31; j
++) {
689 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
690 ring
= temp_ep
->ring
;
693 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
694 "ep index %u\n", i
, j
);
695 while (!list_empty(&ring
->td_list
)) {
696 cur_td
= list_first_entry(&ring
->td_list
,
699 list_del(&cur_td
->td_list
);
700 if (!list_empty(&cur_td
->cancelled_td_list
))
701 list_del(&cur_td
->cancelled_td_list
);
702 xhci_giveback_urb_in_irq(xhci
, cur_td
,
703 -ESHUTDOWN
, "killed");
705 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
706 cur_td
= list_first_entry(
707 &temp_ep
->cancelled_td_list
,
710 list_del(&cur_td
->cancelled_td_list
);
711 xhci_giveback_urb_in_irq(xhci
, cur_td
,
712 -ESHUTDOWN
, "killed");
716 spin_unlock(&xhci
->lock
);
717 xhci_to_hcd(xhci
)->state
= HC_STATE_HALT
;
718 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
719 usb_hc_died(xhci_to_hcd(xhci
));
720 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
724 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
725 * we need to clear the set deq pending flag in the endpoint ring state, so that
726 * the TD queueing code can ring the doorbell again. We also need to ring the
727 * endpoint doorbell to restart the ring, but only if there aren't more
728 * cancellations pending.
730 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
731 struct xhci_event_cmd
*event
,
734 unsigned int slot_id
;
735 unsigned int ep_index
;
736 struct xhci_ring
*ep_ring
;
737 struct xhci_virt_device
*dev
;
738 struct xhci_ep_ctx
*ep_ctx
;
739 struct xhci_slot_ctx
*slot_ctx
;
741 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
742 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
743 dev
= xhci
->devs
[slot_id
];
744 ep_ring
= dev
->eps
[ep_index
].ring
;
745 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
746 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
748 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
749 unsigned int ep_state
;
750 unsigned int slot_state
;
752 switch (GET_COMP_CODE(event
->status
)) {
754 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
755 "of stream ID configuration\n");
758 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
759 "to incorrect slot or ep state.\n");
760 ep_state
= ep_ctx
->ep_info
;
761 ep_state
&= EP_STATE_MASK
;
762 slot_state
= slot_ctx
->dev_state
;
763 slot_state
= GET_SLOT_STATE(slot_state
);
764 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
765 slot_state
, ep_state
);
768 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
769 "slot %u was not enabled.\n", slot_id
);
772 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
773 "completion code of %u.\n",
774 GET_COMP_CODE(event
->status
));
777 /* OK what do we do now? The endpoint state is hosed, and we
778 * should never get to this point if the synchronization between
779 * queueing, and endpoint state are correct. This might happen
780 * if the device gets disconnected after we've finished
781 * cancelling URBs, which might not be an error...
784 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
788 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
789 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
792 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
793 struct xhci_event_cmd
*event
,
797 unsigned int ep_index
;
798 struct xhci_ring
*ep_ring
;
800 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
801 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
802 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
803 /* This command will only fail if the endpoint wasn't halted,
806 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
807 (unsigned int) GET_COMP_CODE(event
->status
));
809 /* HW with the reset endpoint quirk needs to have a configure endpoint
810 * command complete before the endpoint can be used. Queue that here
811 * because the HW can't handle two commands being queued in a row.
813 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
814 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
815 xhci_queue_configure_endpoint(xhci
,
816 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
818 xhci_ring_cmd_db(xhci
);
820 /* Clear our internal halted state and restart the ring */
821 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
822 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
826 /* Check to see if a command in the device's command queue matches this one.
827 * Signal the completion or free the command, and return 1. Return 0 if the
828 * completed command isn't at the head of the command list.
830 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
831 struct xhci_virt_device
*virt_dev
,
832 struct xhci_event_cmd
*event
)
834 struct xhci_command
*command
;
836 if (list_empty(&virt_dev
->cmd_list
))
839 command
= list_entry(virt_dev
->cmd_list
.next
,
840 struct xhci_command
, cmd_list
);
841 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
845 GET_COMP_CODE(event
->status
);
846 list_del(&command
->cmd_list
);
847 if (command
->completion
)
848 complete(command
->completion
);
850 xhci_free_command(xhci
, command
);
854 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
855 struct xhci_event_cmd
*event
)
857 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
859 dma_addr_t cmd_dequeue_dma
;
860 struct xhci_input_control_ctx
*ctrl_ctx
;
861 struct xhci_virt_device
*virt_dev
;
862 unsigned int ep_index
;
863 struct xhci_ring
*ep_ring
;
864 unsigned int ep_state
;
866 cmd_dma
= event
->cmd_trb
;
867 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
868 xhci
->cmd_ring
->dequeue
);
869 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
870 if (cmd_dequeue_dma
== 0) {
871 xhci
->error_bitmask
|= 1 << 4;
874 /* Does the DMA address match our internal dequeue pointer address? */
875 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
876 xhci
->error_bitmask
|= 1 << 5;
879 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
880 case TRB_TYPE(TRB_ENABLE_SLOT
):
881 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
882 xhci
->slot_id
= slot_id
;
885 complete(&xhci
->addr_dev
);
887 case TRB_TYPE(TRB_DISABLE_SLOT
):
888 if (xhci
->devs
[slot_id
])
889 xhci_free_virt_device(xhci
, slot_id
);
891 case TRB_TYPE(TRB_CONFIG_EP
):
892 virt_dev
= xhci
->devs
[slot_id
];
893 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
896 * Configure endpoint commands can come from the USB core
897 * configuration or alt setting changes, or because the HW
898 * needed an extra configure endpoint command after a reset
899 * endpoint command. In the latter case, the xHCI driver is
900 * not waiting on the configure endpoint command.
902 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
904 /* Input ctx add_flags are the endpoint index plus one */
905 ep_index
= xhci_last_valid_endpoint(ctrl_ctx
->add_flags
) - 1;
906 /* A usb_set_interface() call directly after clearing a halted
907 * condition may race on this quirky hardware.
908 * Not worth worrying about, since this is prototype hardware.
910 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
911 ep_index
!= (unsigned int) -1 &&
912 ctrl_ctx
->add_flags
- SLOT_FLAG
==
913 ctrl_ctx
->drop_flags
) {
914 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
915 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
916 if (!(ep_state
& EP_HALTED
))
917 goto bandwidth_change
;
918 xhci_dbg(xhci
, "Completed config ep cmd - "
919 "last ep index = %d, state = %d\n",
921 /* Clear our internal halted state and restart ring */
922 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
924 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
928 xhci_dbg(xhci
, "Completed config ep cmd\n");
929 xhci
->devs
[slot_id
]->cmd_status
=
930 GET_COMP_CODE(event
->status
);
931 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
933 case TRB_TYPE(TRB_EVAL_CONTEXT
):
934 virt_dev
= xhci
->devs
[slot_id
];
935 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
937 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
938 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
940 case TRB_TYPE(TRB_ADDR_DEV
):
941 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
942 complete(&xhci
->addr_dev
);
944 case TRB_TYPE(TRB_STOP_RING
):
945 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
947 case TRB_TYPE(TRB_SET_DEQ
):
948 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
950 case TRB_TYPE(TRB_CMD_NOOP
):
951 ++xhci
->noops_handled
;
953 case TRB_TYPE(TRB_RESET_EP
):
954 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
957 /* Skip over unknown commands on the event ring */
958 xhci
->error_bitmask
|= 1 << 6;
961 inc_deq(xhci
, xhci
->cmd_ring
, false);
964 static void handle_port_status(struct xhci_hcd
*xhci
,
965 union xhci_trb
*event
)
969 /* Port status change events always have a successful completion code */
970 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
971 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
972 xhci
->error_bitmask
|= 1 << 8;
974 /* FIXME: core doesn't care about all port link state changes yet */
975 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
976 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
978 /* Update event ring dequeue pointer before dropping the lock */
979 inc_deq(xhci
, xhci
->event_ring
, true);
980 xhci_set_hc_event_deq(xhci
);
982 spin_unlock(&xhci
->lock
);
983 /* Pass this up to the core */
984 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
985 spin_lock(&xhci
->lock
);
989 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
990 * at end_trb, which may be in another segment. If the suspect DMA address is a
991 * TRB in this TD, this function returns that TRB's segment. Otherwise it
994 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
995 union xhci_trb
*start_trb
,
996 union xhci_trb
*end_trb
,
997 dma_addr_t suspect_dma
)
999 dma_addr_t start_dma
;
1000 dma_addr_t end_seg_dma
;
1001 dma_addr_t end_trb_dma
;
1002 struct xhci_segment
*cur_seg
;
1004 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1005 cur_seg
= start_seg
;
1010 /* We may get an event for a Link TRB in the middle of a TD */
1011 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1012 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1013 /* If the end TRB isn't in this segment, this is set to 0 */
1014 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1016 if (end_trb_dma
> 0) {
1017 /* The end TRB is in this segment, so suspect should be here */
1018 if (start_dma
<= end_trb_dma
) {
1019 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1022 /* Case for one segment with
1023 * a TD wrapped around to the top
1025 if ((suspect_dma
>= start_dma
&&
1026 suspect_dma
<= end_seg_dma
) ||
1027 (suspect_dma
>= cur_seg
->dma
&&
1028 suspect_dma
<= end_trb_dma
))
1033 /* Might still be somewhere in this segment */
1034 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1037 cur_seg
= cur_seg
->next
;
1038 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1039 } while (cur_seg
!= start_seg
);
1044 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1045 unsigned int slot_id
, unsigned int ep_index
,
1046 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1048 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1049 ep
->ep_state
|= EP_HALTED
;
1050 ep
->stopped_td
= td
;
1051 ep
->stopped_trb
= event_trb
;
1052 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1053 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1054 xhci_ring_cmd_db(xhci
);
1057 /* Check if an error has halted the endpoint ring. The class driver will
1058 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1059 * However, a babble and other errors also halt the endpoint ring, and the class
1060 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1061 * Ring Dequeue Pointer command manually.
1063 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1064 struct xhci_ep_ctx
*ep_ctx
,
1065 unsigned int trb_comp_code
)
1067 /* TRB completion codes that may require a manual halt cleanup */
1068 if (trb_comp_code
== COMP_TX_ERR
||
1069 trb_comp_code
== COMP_BABBLE
||
1070 trb_comp_code
== COMP_SPLIT_ERR
)
1071 /* The 0.96 spec says a babbling control endpoint
1072 * is not halted. The 0.96 spec says it is. Some HW
1073 * claims to be 0.95 compliant, but it halts the control
1074 * endpoint anyway. Check if a babble halted the
1077 if ((ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_HALTED
)
1084 * If this function returns an error condition, it means it got a Transfer
1085 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1086 * At this point, the host controller is probably hosed and should be reset.
1088 static int handle_tx_event(struct xhci_hcd
*xhci
,
1089 struct xhci_transfer_event
*event
)
1091 struct xhci_virt_device
*xdev
;
1092 struct xhci_virt_ep
*ep
;
1093 struct xhci_ring
*ep_ring
;
1094 unsigned int slot_id
;
1096 struct xhci_td
*td
= 0;
1097 dma_addr_t event_dma
;
1098 struct xhci_segment
*event_seg
;
1099 union xhci_trb
*event_trb
;
1100 struct urb
*urb
= 0;
1101 int status
= -EINPROGRESS
;
1102 struct xhci_ep_ctx
*ep_ctx
;
1105 xhci_dbg(xhci
, "In %s\n", __func__
);
1106 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
1107 xdev
= xhci
->devs
[slot_id
];
1109 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
1113 /* Endpoint ID is 1 based, our index is zero based */
1114 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
1115 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
1116 ep
= &xdev
->eps
[ep_index
];
1118 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1119 if (!ep_ring
|| (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
1120 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
1124 event_dma
= event
->buffer
;
1125 /* This TRB should be in the TD at the head of this ring's TD list */
1126 xhci_dbg(xhci
, "%s - checking for list empty\n", __func__
);
1127 if (list_empty(&ep_ring
->td_list
)) {
1128 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
1129 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
1130 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
1131 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
1132 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
1136 xhci_dbg(xhci
, "%s - getting list entry\n", __func__
);
1137 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
1139 /* Is this a TRB in the currently executing TD? */
1140 xhci_dbg(xhci
, "%s - looking for TD\n", __func__
);
1141 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
1142 td
->last_trb
, event_dma
);
1143 xhci_dbg(xhci
, "%s - found event_seg = %p\n", __func__
, event_seg
);
1145 /* HC is busted, give up! */
1146 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1149 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
1150 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
1151 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
1152 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
1153 lower_32_bits(event
->buffer
));
1154 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
1155 upper_32_bits(event
->buffer
));
1156 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
1157 (unsigned int) event
->transfer_len
);
1158 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
1159 (unsigned int) event
->flags
);
1161 /* Look for common error cases */
1162 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
1163 switch (trb_comp_code
) {
1164 /* Skip codes that require special handling depending on
1171 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
1173 case COMP_STOP_INVAL
:
1174 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1177 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1178 ep
->ep_state
|= EP_HALTED
;
1182 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1185 case COMP_SPLIT_ERR
:
1187 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1191 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1192 status
= -EOVERFLOW
;
1195 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1199 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1200 /* Vendor defined "informational" completion code,
1201 * treat as not-an-error.
1203 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1205 xhci_dbg(xhci
, "Treating code as success.\n");
1209 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
1213 /* Now update the urb's actual_length and give back to the core */
1214 /* Was this a control transfer? */
1215 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
1216 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1217 switch (trb_comp_code
) {
1219 if (event_trb
== ep_ring
->dequeue
) {
1220 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
1221 status
= -ESHUTDOWN
;
1222 } else if (event_trb
!= td
->last_trb
) {
1223 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
1224 status
= -ESHUTDOWN
;
1226 xhci_dbg(xhci
, "Successful control transfer!\n");
1231 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1232 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1233 status
= -EREMOTEIO
;
1239 if (!xhci_requires_manual_halt_cleanup(xhci
,
1240 ep_ctx
, trb_comp_code
))
1242 xhci_dbg(xhci
, "TRB error code %u, "
1243 "halted endpoint index = %u\n",
1244 trb_comp_code
, ep_index
);
1245 /* else fall through */
1247 /* Did we transfer part of the data (middle) phase? */
1248 if (event_trb
!= ep_ring
->dequeue
&&
1249 event_trb
!= td
->last_trb
)
1250 td
->urb
->actual_length
=
1251 td
->urb
->transfer_buffer_length
1252 - TRB_LEN(event
->transfer_len
);
1254 td
->urb
->actual_length
= 0;
1256 xhci_cleanup_halted_endpoint(xhci
,
1257 slot_id
, ep_index
, td
, event_trb
);
1261 * Did we transfer any data, despite the errors that might have
1262 * happened? I.e. did we get past the setup stage?
1264 if (event_trb
!= ep_ring
->dequeue
) {
1265 /* The event was for the status stage */
1266 if (event_trb
== td
->last_trb
) {
1267 if (td
->urb
->actual_length
!= 0) {
1268 /* Don't overwrite a previously set error code */
1269 if ((status
== -EINPROGRESS
||
1271 (td
->urb
->transfer_flags
1272 & URB_SHORT_NOT_OK
))
1273 /* Did we already see a short data stage? */
1274 status
= -EREMOTEIO
;
1276 td
->urb
->actual_length
=
1277 td
->urb
->transfer_buffer_length
;
1280 /* Maybe the event was for the data stage? */
1281 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1282 /* We didn't stop on a link TRB in the middle */
1283 td
->urb
->actual_length
=
1284 td
->urb
->transfer_buffer_length
-
1285 TRB_LEN(event
->transfer_len
);
1286 xhci_dbg(xhci
, "Waiting for status stage event\n");
1293 switch (trb_comp_code
) {
1295 /* Double check that the HW transferred everything. */
1296 if (event_trb
!= td
->last_trb
) {
1297 xhci_warn(xhci
, "WARN Successful completion "
1299 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1300 status
= -EREMOTEIO
;
1304 if (usb_endpoint_xfer_bulk(&td
->urb
->ep
->desc
))
1305 xhci_dbg(xhci
, "Successful bulk "
1308 xhci_dbg(xhci
, "Successful interrupt "
1314 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1315 status
= -EREMOTEIO
;
1320 /* Others already handled above */
1323 dev_dbg(&td
->urb
->dev
->dev
,
1324 "ep %#x - asked for %d bytes, "
1325 "%d bytes untransferred\n",
1326 td
->urb
->ep
->desc
.bEndpointAddress
,
1327 td
->urb
->transfer_buffer_length
,
1328 TRB_LEN(event
->transfer_len
));
1329 /* Fast path - was this the last TRB in the TD for this URB? */
1330 if (event_trb
== td
->last_trb
) {
1331 if (TRB_LEN(event
->transfer_len
) != 0) {
1332 td
->urb
->actual_length
=
1333 td
->urb
->transfer_buffer_length
-
1334 TRB_LEN(event
->transfer_len
);
1335 if (td
->urb
->transfer_buffer_length
<
1336 td
->urb
->actual_length
) {
1337 xhci_warn(xhci
, "HC gave bad length "
1338 "of %d bytes left\n",
1339 TRB_LEN(event
->transfer_len
));
1340 td
->urb
->actual_length
= 0;
1341 if (td
->urb
->transfer_flags
&
1343 status
= -EREMOTEIO
;
1347 /* Don't overwrite a previously set error code */
1348 if (status
== -EINPROGRESS
) {
1349 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1350 status
= -EREMOTEIO
;
1355 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
1356 /* Ignore a short packet completion if the
1357 * untransferred length was zero.
1359 if (status
== -EREMOTEIO
)
1363 /* Slow path - walk the list, starting from the dequeue
1364 * pointer, to get the actual length transferred.
1366 union xhci_trb
*cur_trb
;
1367 struct xhci_segment
*cur_seg
;
1369 td
->urb
->actual_length
= 0;
1370 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1371 cur_trb
!= event_trb
;
1372 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1373 if (TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_TR_NOOP
&&
1374 TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_LINK
)
1375 td
->urb
->actual_length
+=
1376 TRB_LEN(cur_trb
->generic
.field
[2]);
1378 /* If the ring didn't stop on a Link or No-op TRB, add
1379 * in the actual bytes transferred from the Normal TRB
1381 if (trb_comp_code
!= COMP_STOP_INVAL
)
1382 td
->urb
->actual_length
+=
1383 TRB_LEN(cur_trb
->generic
.field
[2]) -
1384 TRB_LEN(event
->transfer_len
);
1387 if (trb_comp_code
== COMP_STOP_INVAL
||
1388 trb_comp_code
== COMP_STOP
) {
1389 /* The Endpoint Stop Command completion will take care of any
1390 * stopped TDs. A stopped TD may be restarted, so don't update
1391 * the ring dequeue pointer or take this TD off any lists yet.
1393 ep
->stopped_td
= td
;
1394 ep
->stopped_trb
= event_trb
;
1396 if (trb_comp_code
== COMP_STALL
) {
1397 /* The transfer is completed from the driver's
1398 * perspective, but we need to issue a set dequeue
1399 * command for this stalled endpoint to move the dequeue
1400 * pointer past the TD. We can't do that here because
1401 * the halt condition must be cleared first. Let the
1402 * USB class driver clear the stall later.
1404 ep
->stopped_td
= td
;
1405 ep
->stopped_trb
= event_trb
;
1406 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1407 ep_ctx
, trb_comp_code
)) {
1408 /* Other types of errors halt the endpoint, but the
1409 * class driver doesn't call usb_reset_endpoint() unless
1410 * the error is -EPIPE. Clear the halted status in the
1411 * xHCI hardware manually.
1413 xhci_cleanup_halted_endpoint(xhci
,
1414 slot_id
, ep_index
, td
, event_trb
);
1416 /* Update ring dequeue pointer */
1417 while (ep_ring
->dequeue
!= td
->last_trb
)
1418 inc_deq(xhci
, ep_ring
, false);
1419 inc_deq(xhci
, ep_ring
, false);
1423 /* Clean up the endpoint's TD list */
1425 /* Do one last check of the actual transfer length.
1426 * If the host controller said we transferred more data than
1427 * the buffer length, urb->actual_length will be a very big
1428 * number (since it's unsigned). Play it safe and say we didn't
1429 * transfer anything.
1431 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1432 xhci_warn(xhci
, "URB transfer length is wrong, "
1433 "xHC issue? req. len = %u, "
1435 urb
->transfer_buffer_length
,
1436 urb
->actual_length
);
1437 urb
->actual_length
= 0;
1438 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1439 status
= -EREMOTEIO
;
1443 list_del(&td
->td_list
);
1444 /* Was this TD slated to be cancelled but completed anyway? */
1445 if (!list_empty(&td
->cancelled_td_list
))
1446 list_del(&td
->cancelled_td_list
);
1448 /* Leave the TD around for the reset endpoint function to use
1449 * (but only if it's not a control endpoint, since we already
1450 * queued the Set TR dequeue pointer command for stalled
1451 * control endpoints).
1453 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
1454 (trb_comp_code
!= COMP_STALL
&&
1455 trb_comp_code
!= COMP_BABBLE
)) {
1461 inc_deq(xhci
, xhci
->event_ring
, true);
1462 xhci_set_hc_event_deq(xhci
);
1464 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1466 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1467 xhci_dbg(xhci
, "Giveback URB %p, len = %d, status = %d\n",
1468 urb
, urb
->actual_length
, status
);
1469 spin_unlock(&xhci
->lock
);
1470 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1471 spin_lock(&xhci
->lock
);
1477 * This function handles all OS-owned events on the event ring. It may drop
1478 * xhci->lock between event processing (e.g. to pass up port status changes).
1480 void xhci_handle_event(struct xhci_hcd
*xhci
)
1482 union xhci_trb
*event
;
1483 int update_ptrs
= 1;
1486 xhci_dbg(xhci
, "In %s\n", __func__
);
1487 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1488 xhci
->error_bitmask
|= 1 << 1;
1492 event
= xhci
->event_ring
->dequeue
;
1493 /* Does the HC or OS own the TRB? */
1494 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1495 xhci
->event_ring
->cycle_state
) {
1496 xhci
->error_bitmask
|= 1 << 2;
1499 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1501 /* FIXME: Handle more event types. */
1502 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1503 case TRB_TYPE(TRB_COMPLETION
):
1504 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1505 handle_cmd_completion(xhci
, &event
->event_cmd
);
1506 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1508 case TRB_TYPE(TRB_PORT_STATUS
):
1509 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1510 handle_port_status(xhci
, event
);
1511 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
1514 case TRB_TYPE(TRB_TRANSFER
):
1515 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
1516 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1517 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
1519 xhci
->error_bitmask
|= 1 << 9;
1524 xhci
->error_bitmask
|= 1 << 3;
1526 /* Any of the above functions may drop and re-acquire the lock, so check
1527 * to make sure a watchdog timer didn't mark the host as non-responsive.
1529 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
1530 xhci_dbg(xhci
, "xHCI host dying, returning from "
1531 "event handler.\n");
1536 /* Update SW and HC event ring dequeue pointer */
1537 inc_deq(xhci
, xhci
->event_ring
, true);
1538 xhci_set_hc_event_deq(xhci
);
1540 /* Are there more items on the event ring? */
1541 xhci_handle_event(xhci
);
1544 /**** Endpoint Ring Operations ****/
1547 * Generic function for queueing a TRB on a ring.
1548 * The caller must have checked to make sure there's room on the ring.
1550 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1552 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1554 struct xhci_generic_trb
*trb
;
1556 trb
= &ring
->enqueue
->generic
;
1557 trb
->field
[0] = field1
;
1558 trb
->field
[1] = field2
;
1559 trb
->field
[2] = field3
;
1560 trb
->field
[3] = field4
;
1561 inc_enq(xhci
, ring
, consumer
);
1565 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1566 * FIXME allocate segments if the ring is full.
1568 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1569 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1571 /* Make sure the endpoint has been added to xHC schedule */
1572 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1574 case EP_STATE_DISABLED
:
1576 * USB core changed config/interfaces without notifying us,
1577 * or hardware is reporting the wrong state.
1579 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1581 case EP_STATE_ERROR
:
1582 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
1583 /* FIXME event handling code for error needs to clear it */
1584 /* XXX not sure if this should be -ENOENT or not */
1586 case EP_STATE_HALTED
:
1587 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
1588 case EP_STATE_STOPPED
:
1589 case EP_STATE_RUNNING
:
1592 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1594 * FIXME issue Configure Endpoint command to try to get the HC
1595 * back into a known state.
1599 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1600 /* FIXME allocate more room */
1601 xhci_err(xhci
, "ERROR no room on ep ring\n");
1607 static int prepare_transfer(struct xhci_hcd
*xhci
,
1608 struct xhci_virt_device
*xdev
,
1609 unsigned int ep_index
,
1610 unsigned int num_trbs
,
1612 struct xhci_td
**td
,
1616 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1617 ret
= prepare_ring(xhci
, xdev
->eps
[ep_index
].ring
,
1618 ep_ctx
->ep_info
& EP_STATE_MASK
,
1619 num_trbs
, mem_flags
);
1622 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1625 INIT_LIST_HEAD(&(*td
)->td_list
);
1626 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1628 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1629 if (unlikely(ret
)) {
1635 urb
->hcpriv
= (void *) (*td
);
1636 /* Add this TD to the tail of the endpoint ring's TD list */
1637 list_add_tail(&(*td
)->td_list
, &xdev
->eps
[ep_index
].ring
->td_list
);
1638 (*td
)->start_seg
= xdev
->eps
[ep_index
].ring
->enq_seg
;
1639 (*td
)->first_trb
= xdev
->eps
[ep_index
].ring
->enqueue
;
1644 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1646 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1647 struct scatterlist
*sg
;
1650 num_sgs
= urb
->num_sgs
;
1651 temp
= urb
->transfer_buffer_length
;
1653 xhci_dbg(xhci
, "count sg list trbs: \n");
1655 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1656 unsigned int previous_total_trbs
= num_trbs
;
1657 unsigned int len
= sg_dma_len(sg
);
1659 /* Scatter gather list entries may cross 64KB boundaries */
1660 running_total
= TRB_MAX_BUFF_SIZE
-
1661 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1662 if (running_total
!= 0)
1665 /* How many more 64KB chunks to transfer, how many more TRBs? */
1666 while (running_total
< sg_dma_len(sg
)) {
1668 running_total
+= TRB_MAX_BUFF_SIZE
;
1670 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1671 i
, (unsigned long long)sg_dma_address(sg
),
1672 len
, len
, num_trbs
- previous_total_trbs
);
1674 len
= min_t(int, len
, temp
);
1679 xhci_dbg(xhci
, "\n");
1680 if (!in_interrupt())
1681 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1682 urb
->ep
->desc
.bEndpointAddress
,
1683 urb
->transfer_buffer_length
,
1688 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1691 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1692 "TRBs, %d left\n", __func__
,
1693 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1694 if (running_total
!= urb
->transfer_buffer_length
)
1695 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1696 "queued %#x (%d), asked for %#x (%d)\n",
1698 urb
->ep
->desc
.bEndpointAddress
,
1699 running_total
, running_total
,
1700 urb
->transfer_buffer_length
,
1701 urb
->transfer_buffer_length
);
1704 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1705 unsigned int ep_index
, int start_cycle
,
1706 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1709 * Pass all the TRBs to the hardware at once and make sure this write
1713 start_trb
->field
[3] |= start_cycle
;
1714 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1718 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1719 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1720 * (comprised of sg list entries) can take several service intervals to
1723 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1724 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1726 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
1727 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1731 xhci_interval
= EP_INTERVAL_TO_UFRAMES(ep_ctx
->ep_info
);
1732 ep_interval
= urb
->interval
;
1733 /* Convert to microframes */
1734 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1735 urb
->dev
->speed
== USB_SPEED_FULL
)
1737 /* FIXME change this to a warning and a suggestion to use the new API
1738 * to set the polling interval (once the API is added).
1740 if (xhci_interval
!= ep_interval
) {
1741 if (!printk_ratelimit())
1742 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
1743 " (%d microframe%s) than xHCI "
1744 "(%d microframe%s)\n",
1746 ep_interval
== 1 ? "" : "s",
1748 xhci_interval
== 1 ? "" : "s");
1749 urb
->interval
= xhci_interval
;
1750 /* Convert back to frames for LS/FS devices */
1751 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1752 urb
->dev
->speed
== USB_SPEED_FULL
)
1755 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
1759 * The TD size is the number of bytes remaining in the TD (including this TRB),
1760 * right shifted by 10.
1761 * It must fit in bits 21:17, so it can't be bigger than 31.
1763 static u32
xhci_td_remainder(unsigned int remainder
)
1765 u32 max
= (1 << (21 - 17 + 1)) - 1;
1767 if ((remainder
>> 10) >= max
)
1770 return (remainder
>> 10) << 17;
1773 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1774 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1776 struct xhci_ring
*ep_ring
;
1777 unsigned int num_trbs
;
1779 struct scatterlist
*sg
;
1781 int trb_buff_len
, this_sg_len
, running_total
;
1785 struct xhci_generic_trb
*start_trb
;
1788 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1789 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1790 num_sgs
= urb
->num_sgs
;
1792 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1793 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1794 if (trb_buff_len
< 0)
1795 return trb_buff_len
;
1797 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1798 * until we've finished creating all the other TRBs. The ring's cycle
1799 * state may change as we enqueue the other TRBs, so save it too.
1801 start_trb
= &ep_ring
->enqueue
->generic
;
1802 start_cycle
= ep_ring
->cycle_state
;
1806 * How much data is in the first TRB?
1808 * There are three forces at work for TRB buffer pointers and lengths:
1809 * 1. We don't want to walk off the end of this sg-list entry buffer.
1810 * 2. The transfer length that the driver requested may be smaller than
1811 * the amount of memory allocated for this scatter-gather list.
1812 * 3. TRBs buffers can't cross 64KB boundaries.
1815 addr
= (u64
) sg_dma_address(sg
);
1816 this_sg_len
= sg_dma_len(sg
);
1817 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1818 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1819 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1820 if (trb_buff_len
> urb
->transfer_buffer_length
)
1821 trb_buff_len
= urb
->transfer_buffer_length
;
1822 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1826 /* Queue the first TRB, even if it's zero-length */
1829 u32 length_field
= 0;
1832 /* Don't change the cycle bit of the first TRB until later */
1836 field
|= ep_ring
->cycle_state
;
1838 /* Chain all the TRBs together; clear the chain bit in the last
1839 * TRB to indicate it's the last TRB in the chain.
1844 /* FIXME - add check for ZERO_PACKET flag before this */
1845 td
->last_trb
= ep_ring
->enqueue
;
1848 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1849 "64KB boundary at %#x, end dma = %#x\n",
1850 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1851 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1852 (unsigned int) addr
+ trb_buff_len
);
1853 if (TRB_MAX_BUFF_SIZE
-
1854 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
1855 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1856 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1857 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1858 (unsigned int) addr
+ trb_buff_len
);
1860 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
-
1862 length_field
= TRB_LEN(trb_buff_len
) |
1865 queue_trb(xhci
, ep_ring
, false,
1866 lower_32_bits(addr
),
1867 upper_32_bits(addr
),
1869 /* We always want to know if the TRB was short,
1870 * or we won't get an event when it completes.
1871 * (Unless we use event data TRBs, which are a
1872 * waste of space and HC resources.)
1874 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1876 running_total
+= trb_buff_len
;
1878 /* Calculate length for next transfer --
1879 * Are we done queueing all the TRBs for this sg entry?
1881 this_sg_len
-= trb_buff_len
;
1882 if (this_sg_len
== 0) {
1887 addr
= (u64
) sg_dma_address(sg
);
1888 this_sg_len
= sg_dma_len(sg
);
1890 addr
+= trb_buff_len
;
1893 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1894 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1895 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1896 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1898 urb
->transfer_buffer_length
- running_total
;
1899 } while (running_total
< urb
->transfer_buffer_length
);
1901 check_trb_math(urb
, num_trbs
, running_total
);
1902 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1906 /* This is very similar to what ehci-q.c qtd_fill() does */
1907 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1908 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1910 struct xhci_ring
*ep_ring
;
1913 struct xhci_generic_trb
*start_trb
;
1916 u32 field
, length_field
;
1918 int running_total
, trb_buff_len
, ret
;
1922 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1924 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1927 /* How much data is (potentially) left before the 64KB boundary? */
1928 running_total
= TRB_MAX_BUFF_SIZE
-
1929 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1931 /* If there's some data on this 64KB chunk, or we have to send a
1932 * zero-length transfer, we need at least one TRB
1934 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1936 /* How many more 64KB chunks to transfer, how many more TRBs? */
1937 while (running_total
< urb
->transfer_buffer_length
) {
1939 running_total
+= TRB_MAX_BUFF_SIZE
;
1941 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1943 if (!in_interrupt())
1944 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1945 urb
->ep
->desc
.bEndpointAddress
,
1946 urb
->transfer_buffer_length
,
1947 urb
->transfer_buffer_length
,
1948 (unsigned long long)urb
->transfer_dma
,
1951 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1952 num_trbs
, urb
, &td
, mem_flags
);
1957 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1958 * until we've finished creating all the other TRBs. The ring's cycle
1959 * state may change as we enqueue the other TRBs, so save it too.
1961 start_trb
= &ep_ring
->enqueue
->generic
;
1962 start_cycle
= ep_ring
->cycle_state
;
1965 /* How much data is in the first TRB? */
1966 addr
= (u64
) urb
->transfer_dma
;
1967 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1968 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1969 if (urb
->transfer_buffer_length
< trb_buff_len
)
1970 trb_buff_len
= urb
->transfer_buffer_length
;
1974 /* Queue the first TRB, even if it's zero-length */
1979 /* Don't change the cycle bit of the first TRB until later */
1983 field
|= ep_ring
->cycle_state
;
1985 /* Chain all the TRBs together; clear the chain bit in the last
1986 * TRB to indicate it's the last TRB in the chain.
1991 /* FIXME - add check for ZERO_PACKET flag before this */
1992 td
->last_trb
= ep_ring
->enqueue
;
1995 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
-
1997 length_field
= TRB_LEN(trb_buff_len
) |
2000 queue_trb(xhci
, ep_ring
, false,
2001 lower_32_bits(addr
),
2002 upper_32_bits(addr
),
2004 /* We always want to know if the TRB was short,
2005 * or we won't get an event when it completes.
2006 * (Unless we use event data TRBs, which are a
2007 * waste of space and HC resources.)
2009 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
2011 running_total
+= trb_buff_len
;
2013 /* Calculate length for next transfer */
2014 addr
+= trb_buff_len
;
2015 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
2016 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
2017 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
2018 } while (running_total
< urb
->transfer_buffer_length
);
2020 check_trb_math(urb
, num_trbs
, running_total
);
2021 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
2025 /* Caller must have locked xhci->lock */
2026 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2027 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2029 struct xhci_ring
*ep_ring
;
2032 struct usb_ctrlrequest
*setup
;
2033 struct xhci_generic_trb
*start_trb
;
2035 u32 field
, length_field
;
2038 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
2041 * Need to copy setup packet into setup TRB, so we can't use the setup
2044 if (!urb
->setup_packet
)
2047 if (!in_interrupt())
2048 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
2050 /* 1 TRB for setup, 1 for status */
2053 * Don't need to check if we need additional event data and normal TRBs,
2054 * since data in control transfers will never get bigger than 16MB
2055 * XXX: can we get a buffer that crosses 64KB boundaries?
2057 if (urb
->transfer_buffer_length
> 0)
2059 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
2060 urb
, &td
, mem_flags
);
2065 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2066 * until we've finished creating all the other TRBs. The ring's cycle
2067 * state may change as we enqueue the other TRBs, so save it too.
2069 start_trb
= &ep_ring
->enqueue
->generic
;
2070 start_cycle
= ep_ring
->cycle_state
;
2072 /* Queue setup TRB - see section 6.4.1.2.1 */
2073 /* FIXME better way to translate setup_packet into two u32 fields? */
2074 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
2075 queue_trb(xhci
, ep_ring
, false,
2076 /* FIXME endianness is probably going to bite my ass here. */
2077 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
2078 setup
->wIndex
| setup
->wLength
<< 16,
2079 TRB_LEN(8) | TRB_INTR_TARGET(0),
2080 /* Immediate data in pointer */
2081 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
2083 /* If there's data, queue data TRBs */
2085 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
2086 xhci_td_remainder(urb
->transfer_buffer_length
) |
2088 if (urb
->transfer_buffer_length
> 0) {
2089 if (setup
->bRequestType
& USB_DIR_IN
)
2090 field
|= TRB_DIR_IN
;
2091 queue_trb(xhci
, ep_ring
, false,
2092 lower_32_bits(urb
->transfer_dma
),
2093 upper_32_bits(urb
->transfer_dma
),
2095 /* Event on short tx */
2096 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
2099 /* Save the DMA address of the last TRB in the TD */
2100 td
->last_trb
= ep_ring
->enqueue
;
2102 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2103 /* If the device sent data, the status stage is an OUT transfer */
2104 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
2108 queue_trb(xhci
, ep_ring
, false,
2112 /* Event on completion */
2113 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
2115 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
2119 /**** Command Ring Operations ****/
2121 /* Generic function for queueing a command TRB on the command ring.
2122 * Check to make sure there's room on the command ring for one command TRB.
2123 * Also check that there's room reserved for commands that must not fail.
2124 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2125 * then only check for the number of reserved spots.
2126 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2127 * because the command event handler may want to resubmit a failed command.
2129 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
2130 u32 field3
, u32 field4
, bool command_must_succeed
)
2132 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
2133 if (!command_must_succeed
)
2136 if (!room_on_ring(xhci
, xhci
->cmd_ring
, reserved_trbs
)) {
2137 if (!in_interrupt())
2138 xhci_err(xhci
, "ERR: No room for command on command ring\n");
2139 if (command_must_succeed
)
2140 xhci_err(xhci
, "ERR: Reserved TRB counting for "
2141 "unfailable commands failed.\n");
2144 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
2145 field4
| xhci
->cmd_ring
->cycle_state
);
2149 /* Queue a no-op command on the command ring */
2150 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
2152 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
), false);
2156 * Place a no-op command on the command ring to test the command and
2159 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
2161 if (queue_cmd_noop(xhci
) < 0)
2163 xhci
->noops_submitted
++;
2164 return xhci_ring_cmd_db
;
2167 /* Queue a slot enable or disable request on the command ring */
2168 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
2170 return queue_command(xhci
, 0, 0, 0,
2171 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
2174 /* Queue an address device command TRB */
2175 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2178 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2179 upper_32_bits(in_ctx_ptr
), 0,
2180 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
2184 /* Queue a configure endpoint command TRB */
2185 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2186 u32 slot_id
, bool command_must_succeed
)
2188 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2189 upper_32_bits(in_ctx_ptr
), 0,
2190 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
2191 command_must_succeed
);
2194 /* Queue an evaluate context command TRB */
2195 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2198 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2199 upper_32_bits(in_ctx_ptr
), 0,
2200 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
2204 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
2205 unsigned int ep_index
)
2207 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2208 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2209 u32 type
= TRB_TYPE(TRB_STOP_RING
);
2211 return queue_command(xhci
, 0, 0, 0,
2212 trb_slot_id
| trb_ep_index
| type
, false);
2215 /* Set Transfer Ring Dequeue Pointer command.
2216 * This should not be used for endpoints that have streams enabled.
2218 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
2219 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
2220 union xhci_trb
*deq_ptr
, u32 cycle_state
)
2223 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2224 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2225 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
2227 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
2229 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
2230 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
2234 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
2235 upper_32_bits(addr
), 0,
2236 trb_slot_id
| trb_ep_index
| type
, false);
2239 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
2240 unsigned int ep_index
)
2242 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2243 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2244 u32 type
= TRB_TYPE(TRB_RESET_EP
);
2246 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,