2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
140 /* Update the dequeue pointer further if that was a link TRB or we're at
141 * the end of an event ring segment (which doesn't have link TRBS)
143 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
144 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
145 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
147 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
149 (unsigned int) ring
->cycle_state
);
151 ring
->deq_seg
= ring
->deq_seg
->next
;
152 ring
->dequeue
= ring
->deq_seg
->trbs
;
153 next
= ring
->dequeue
;
158 * See Cycle bit rules. SW is the consumer for the event ring only.
159 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
161 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
162 * chain bit is set), then set the chain bit in all the following link TRBs.
163 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
164 * have their chain bit cleared (so that each Link TRB is a separate TD).
166 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
167 * set, but other sections talk about dealing with the chain bit set.
168 * Assume section 6.4.4.1 is wrong, and the chain bit can be set in a Link TRB.
170 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
173 union xhci_trb
*next
;
175 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
176 next
= ++(ring
->enqueue
);
179 /* Update the dequeue pointer further if that was a link TRB or we're at
180 * the end of an event ring segment (which doesn't have link TRBS)
182 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
184 if (ring
!= xhci
->event_ring
) {
185 next
->link
.control
&= ~TRB_CHAIN
;
186 next
->link
.control
|= chain
;
187 /* Give this link TRB to the hardware */
189 if (next
->link
.control
& TRB_CYCLE
)
190 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
192 next
->link
.control
|= (u32
) TRB_CYCLE
;
194 /* Toggle the cycle bit after the last ring segment. */
195 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
196 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
198 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
200 (unsigned int) ring
->cycle_state
);
203 ring
->enq_seg
= ring
->enq_seg
->next
;
204 ring
->enqueue
= ring
->enq_seg
->trbs
;
205 next
= ring
->enqueue
;
210 * Check to see if there's room to enqueue num_trbs on the ring. See rules
212 * FIXME: this would be simpler and faster if we just kept track of the number
213 * of free TRBs in a ring.
215 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
216 unsigned int num_trbs
)
219 union xhci_trb
*enq
= ring
->enqueue
;
220 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
222 /* Check if ring is empty */
223 if (enq
== ring
->dequeue
)
225 /* Make sure there's an extra empty TRB available */
226 for (i
= 0; i
<= num_trbs
; ++i
) {
227 if (enq
== ring
->dequeue
)
230 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
231 enq_seg
= enq_seg
->next
;
238 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
243 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
244 xhci
->event_ring
->dequeue
);
245 if (deq
== 0 && !in_interrupt())
246 xhci_warn(xhci
, "WARN something wrong with SW event ring "
248 /* Update HC event ring dequeue pointer */
249 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
250 temp
&= ERST_PTR_MASK
;
251 /* Don't clear the EHB bit (which is RW1C) because
252 * there might be more events to service.
256 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
257 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
258 &xhci
->ir_set
->erst_dequeue
);
261 /* Ring the host controller doorbell after placing a command on the ring */
262 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
266 xhci_dbg(xhci
, "// Ding dong!\n");
267 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
268 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
269 /* Flush PCI posted writes */
270 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
273 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
274 unsigned int slot_id
,
275 unsigned int ep_index
)
277 struct xhci_ring
*ep_ring
;
279 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
281 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
282 /* Don't ring the doorbell for this endpoint if there are pending
283 * cancellations because the we don't want to interrupt processing.
285 if (!ep_ring
->cancels_pending
&& !(ep_ring
->state
& SET_DEQ_PENDING
)
286 && !(ep_ring
->state
& EP_HALTED
)) {
287 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
288 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
289 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
290 * isn't time-critical and we shouldn't make the CPU wait for
293 xhci_readl(xhci
, db_addr
);
298 * Find the segment that trb is in. Start searching in start_seg.
299 * If we must move past a segment that has a link TRB with a toggle cycle state
300 * bit set, then we will toggle the value pointed at by cycle_state.
302 static struct xhci_segment
*find_trb_seg(
303 struct xhci_segment
*start_seg
,
304 union xhci_trb
*trb
, int *cycle_state
)
306 struct xhci_segment
*cur_seg
= start_seg
;
307 struct xhci_generic_trb
*generic_trb
;
309 while (cur_seg
->trbs
> trb
||
310 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
311 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
312 if (TRB_TYPE(generic_trb
->field
[3]) == TRB_LINK
&&
313 (generic_trb
->field
[3] & LINK_TOGGLE
))
314 *cycle_state
= ~(*cycle_state
) & 0x1;
315 cur_seg
= cur_seg
->next
;
316 if (cur_seg
== start_seg
)
317 /* Looped over the entire list. Oops! */
323 struct dequeue_state
{
324 struct xhci_segment
*new_deq_seg
;
325 union xhci_trb
*new_deq_ptr
;
330 * Move the xHC's endpoint ring dequeue pointer past cur_td.
331 * Record the new state of the xHC's endpoint ring dequeue segment,
332 * dequeue pointer, and new consumer cycle state in state.
333 * Update our internal representation of the ring's dequeue pointer.
335 * We do this in three jumps:
336 * - First we update our new ring state to be the same as when the xHC stopped.
337 * - Then we traverse the ring to find the segment that contains
338 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
339 * any link TRBs with the toggle cycle bit set.
340 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
341 * if we've moved it past a link TRB with the toggle cycle bit set.
343 static void find_new_dequeue_state(struct xhci_hcd
*xhci
,
344 unsigned int slot_id
, unsigned int ep_index
,
345 struct xhci_td
*cur_td
, struct dequeue_state
*state
)
347 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
348 struct xhci_ring
*ep_ring
= dev
->ep_rings
[ep_index
];
349 struct xhci_generic_trb
*trb
;
351 state
->new_cycle_state
= 0;
352 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
353 ep_ring
->stopped_trb
,
354 &state
->new_cycle_state
);
355 if (!state
->new_deq_seg
)
357 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
358 state
->new_cycle_state
= 0x1 & dev
->out_ctx
->ep
[ep_index
].deq
;
360 state
->new_deq_ptr
= cur_td
->last_trb
;
361 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
363 &state
->new_cycle_state
);
364 if (!state
->new_deq_seg
)
367 trb
= &state
->new_deq_ptr
->generic
;
368 if (TRB_TYPE(trb
->field
[3]) == TRB_LINK
&&
369 (trb
->field
[3] & LINK_TOGGLE
))
370 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
371 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
373 /* Don't update the ring cycle state for the producer (us). */
374 ep_ring
->dequeue
= state
->new_deq_ptr
;
375 ep_ring
->deq_seg
= state
->new_deq_seg
;
378 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
379 struct xhci_td
*cur_td
)
381 struct xhci_segment
*cur_seg
;
382 union xhci_trb
*cur_trb
;
384 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
386 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
387 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
388 TRB_TYPE(TRB_LINK
)) {
389 /* Unchain any chained Link TRBs, but
390 * leave the pointers intact.
392 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
393 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
394 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
395 "in seg %p (0x%llx dma)\n",
397 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
399 (unsigned long long)cur_seg
->dma
);
401 cur_trb
->generic
.field
[0] = 0;
402 cur_trb
->generic
.field
[1] = 0;
403 cur_trb
->generic
.field
[2] = 0;
404 /* Preserve only the cycle bit of this TRB */
405 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
406 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
407 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
408 "in seg %p (0x%llx dma)\n",
410 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
412 (unsigned long long)cur_seg
->dma
);
414 if (cur_trb
== cur_td
->last_trb
)
419 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
420 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
421 union xhci_trb
*deq_ptr
, u32 cycle_state
);
424 * When we get a command completion for a Stop Endpoint Command, we need to
425 * unlink any cancelled TDs from the ring. There are two ways to do that:
427 * 1. If the HW was in the middle of processing the TD that needs to be
428 * cancelled, then we must move the ring's dequeue pointer past the last TRB
429 * in the TD with a Set Dequeue Pointer Command.
430 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
431 * bit cleared) so that the HW will skip over them.
433 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
436 unsigned int slot_id
;
437 unsigned int ep_index
;
438 struct xhci_ring
*ep_ring
;
439 struct list_head
*entry
;
440 struct xhci_td
*cur_td
= 0;
441 struct xhci_td
*last_unlinked_td
;
443 struct dequeue_state deq_state
;
444 #ifdef CONFIG_USB_HCD_STAT
445 ktime_t stop_time
= ktime_get();
448 memset(&deq_state
, 0, sizeof(deq_state
));
449 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
450 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
451 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
453 if (list_empty(&ep_ring
->cancelled_td_list
))
456 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
457 * We have the xHCI lock, so nothing can modify this list until we drop
458 * it. We're also in the event handler, so we can't get re-interrupted
459 * if another Stop Endpoint command completes
461 list_for_each(entry
, &ep_ring
->cancelled_td_list
) {
462 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
463 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
465 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
467 * If we stopped on the TD we need to cancel, then we have to
468 * move the xHC endpoint ring dequeue pointer past this TD.
470 if (cur_td
== ep_ring
->stopped_td
)
471 find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
474 td_to_noop(xhci
, ep_ring
, cur_td
);
476 * The event handler won't see a completion for this TD anymore,
477 * so remove it from the endpoint ring's TD list. Keep it in
478 * the cancelled TD list for URB completion later.
480 list_del(&cur_td
->td_list
);
481 ep_ring
->cancels_pending
--;
483 last_unlinked_td
= cur_td
;
485 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
486 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
487 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
488 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
489 deq_state
.new_deq_seg
,
490 (unsigned long long)deq_state
.new_deq_seg
->dma
,
491 deq_state
.new_deq_ptr
,
492 (unsigned long long)xhci_trb_virt_to_dma(deq_state
.new_deq_seg
, deq_state
.new_deq_ptr
),
493 deq_state
.new_cycle_state
);
494 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
495 deq_state
.new_deq_seg
,
496 deq_state
.new_deq_ptr
,
497 (u32
) deq_state
.new_cycle_state
);
498 /* Stop the TD queueing code from ringing the doorbell until
499 * this command completes. The HC won't set the dequeue pointer
500 * if the ring is running, and ringing the doorbell starts the
503 ep_ring
->state
|= SET_DEQ_PENDING
;
504 xhci_ring_cmd_db(xhci
);
506 /* Otherwise just ring the doorbell to restart the ring */
507 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
511 * Drop the lock and complete the URBs in the cancelled TD list.
512 * New TDs to be cancelled might be added to the end of the list before
513 * we can complete all the URBs for the TDs we already unlinked.
514 * So stop when we've completed the URB for the last TD we unlinked.
517 cur_td
= list_entry(ep_ring
->cancelled_td_list
.next
,
518 struct xhci_td
, cancelled_td_list
);
519 list_del(&cur_td
->cancelled_td_list
);
521 /* Clean up the cancelled URB */
522 #ifdef CONFIG_USB_HCD_STAT
523 hcd_stat_update(xhci
->tp_stat
, cur_td
->urb
->actual_length
,
524 ktime_sub(stop_time
, cur_td
->start_time
));
526 cur_td
->urb
->hcpriv
= NULL
;
527 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), cur_td
->urb
);
529 xhci_dbg(xhci
, "Giveback cancelled URB %p\n", cur_td
->urb
);
530 spin_unlock(&xhci
->lock
);
531 /* Doesn't matter what we pass for status, since the core will
532 * just overwrite it (because the URB has been unlinked).
534 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), cur_td
->urb
, 0);
537 spin_lock(&xhci
->lock
);
538 } while (cur_td
!= last_unlinked_td
);
540 /* Return to the event handler with xhci->lock re-acquired */
544 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
545 * we need to clear the set deq pending flag in the endpoint ring state, so that
546 * the TD queueing code can ring the doorbell again. We also need to ring the
547 * endpoint doorbell to restart the ring, but only if there aren't more
548 * cancellations pending.
550 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
551 struct xhci_event_cmd
*event
,
554 unsigned int slot_id
;
555 unsigned int ep_index
;
556 struct xhci_ring
*ep_ring
;
557 struct xhci_virt_device
*dev
;
559 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
560 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
561 dev
= xhci
->devs
[slot_id
];
562 ep_ring
= dev
->ep_rings
[ep_index
];
564 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
565 unsigned int ep_state
;
566 unsigned int slot_state
;
568 switch (GET_COMP_CODE(event
->status
)) {
570 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
571 "of stream ID configuration\n");
574 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
575 "to incorrect slot or ep state.\n");
576 ep_state
= dev
->out_ctx
->ep
[ep_index
].ep_info
;
577 ep_state
&= EP_STATE_MASK
;
578 slot_state
= dev
->out_ctx
->slot
.dev_state
;
579 slot_state
= GET_SLOT_STATE(slot_state
);
580 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
581 slot_state
, ep_state
);
584 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
585 "slot %u was not enabled.\n", slot_id
);
588 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
589 "completion code of %u.\n",
590 GET_COMP_CODE(event
->status
));
593 /* OK what do we do now? The endpoint state is hosed, and we
594 * should never get to this point if the synchronization between
595 * queueing, and endpoint state are correct. This might happen
596 * if the device gets disconnected after we've finished
597 * cancelling URBs, which might not be an error...
600 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
601 dev
->out_ctx
->ep
[ep_index
].deq
);
604 ep_ring
->state
&= ~SET_DEQ_PENDING
;
605 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
608 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
609 struct xhci_event_cmd
*event
,
613 unsigned int ep_index
;
615 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
616 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
617 /* This command will only fail if the endpoint wasn't halted,
620 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
621 (unsigned int) GET_COMP_CODE(event
->status
));
623 /* Clear our internal halted state and restart the ring */
624 xhci
->devs
[slot_id
]->ep_rings
[ep_index
]->state
&= ~EP_HALTED
;
625 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
628 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
629 struct xhci_event_cmd
*event
)
631 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
633 dma_addr_t cmd_dequeue_dma
;
635 cmd_dma
= event
->cmd_trb
;
636 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
637 xhci
->cmd_ring
->dequeue
);
638 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
639 if (cmd_dequeue_dma
== 0) {
640 xhci
->error_bitmask
|= 1 << 4;
643 /* Does the DMA address match our internal dequeue pointer address? */
644 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
645 xhci
->error_bitmask
|= 1 << 5;
648 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
649 case TRB_TYPE(TRB_ENABLE_SLOT
):
650 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
651 xhci
->slot_id
= slot_id
;
654 complete(&xhci
->addr_dev
);
656 case TRB_TYPE(TRB_DISABLE_SLOT
):
657 if (xhci
->devs
[slot_id
])
658 xhci_free_virt_device(xhci
, slot_id
);
660 case TRB_TYPE(TRB_CONFIG_EP
):
661 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
662 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
664 case TRB_TYPE(TRB_ADDR_DEV
):
665 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
666 complete(&xhci
->addr_dev
);
668 case TRB_TYPE(TRB_STOP_RING
):
669 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
671 case TRB_TYPE(TRB_SET_DEQ
):
672 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
674 case TRB_TYPE(TRB_CMD_NOOP
):
675 ++xhci
->noops_handled
;
677 case TRB_TYPE(TRB_RESET_EP
):
678 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
681 /* Skip over unknown commands on the event ring */
682 xhci
->error_bitmask
|= 1 << 6;
685 inc_deq(xhci
, xhci
->cmd_ring
, false);
688 static void handle_port_status(struct xhci_hcd
*xhci
,
689 union xhci_trb
*event
)
693 /* Port status change events always have a successful completion code */
694 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
695 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
696 xhci
->error_bitmask
|= 1 << 8;
698 /* FIXME: core doesn't care about all port link state changes yet */
699 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
700 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
702 /* Update event ring dequeue pointer before dropping the lock */
703 inc_deq(xhci
, xhci
->event_ring
, true);
704 xhci_set_hc_event_deq(xhci
);
706 spin_unlock(&xhci
->lock
);
707 /* Pass this up to the core */
708 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
709 spin_lock(&xhci
->lock
);
713 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
714 * at end_trb, which may be in another segment. If the suspect DMA address is a
715 * TRB in this TD, this function returns that TRB's segment. Otherwise it
718 static struct xhci_segment
*trb_in_td(
719 struct xhci_segment
*start_seg
,
720 union xhci_trb
*start_trb
,
721 union xhci_trb
*end_trb
,
722 dma_addr_t suspect_dma
)
724 dma_addr_t start_dma
;
725 dma_addr_t end_seg_dma
;
726 dma_addr_t end_trb_dma
;
727 struct xhci_segment
*cur_seg
;
729 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
733 /* We may get an event for a Link TRB in the middle of a TD */
734 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
735 &start_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
736 /* If the end TRB isn't in this segment, this is set to 0 */
737 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
739 if (end_trb_dma
> 0) {
740 /* The end TRB is in this segment, so suspect should be here */
741 if (start_dma
<= end_trb_dma
) {
742 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
745 /* Case for one segment with
746 * a TD wrapped around to the top
748 if ((suspect_dma
>= start_dma
&&
749 suspect_dma
<= end_seg_dma
) ||
750 (suspect_dma
>= cur_seg
->dma
&&
751 suspect_dma
<= end_trb_dma
))
756 /* Might still be somewhere in this segment */
757 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
760 cur_seg
= cur_seg
->next
;
761 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
767 * If this function returns an error condition, it means it got a Transfer
768 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
769 * At this point, the host controller is probably hosed and should be reset.
771 static int handle_tx_event(struct xhci_hcd
*xhci
,
772 struct xhci_transfer_event
*event
)
774 struct xhci_virt_device
*xdev
;
775 struct xhci_ring
*ep_ring
;
777 struct xhci_td
*td
= 0;
778 dma_addr_t event_dma
;
779 struct xhci_segment
*event_seg
;
780 union xhci_trb
*event_trb
;
782 int status
= -EINPROGRESS
;
784 xdev
= xhci
->devs
[TRB_TO_SLOT_ID(event
->flags
)];
786 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
790 /* Endpoint ID is 1 based, our index is zero based */
791 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
792 ep_ring
= xdev
->ep_rings
[ep_index
];
793 if (!ep_ring
|| (xdev
->out_ctx
->ep
[ep_index
].ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
794 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
798 event_dma
= event
->buffer
;
799 /* This TRB should be in the TD at the head of this ring's TD list */
800 if (list_empty(&ep_ring
->td_list
)) {
801 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
802 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
803 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
804 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
805 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
809 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
811 /* Is this a TRB in the currently executing TD? */
812 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
813 td
->last_trb
, event_dma
);
815 /* HC is busted, give up! */
816 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
819 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
820 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
821 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
822 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
823 lower_32_bits(event
->buffer
));
824 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
825 upper_32_bits(event
->buffer
));
826 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
827 (unsigned int) event
->transfer_len
);
828 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
829 (unsigned int) event
->flags
);
831 /* Look for common error cases */
832 switch (GET_COMP_CODE(event
->transfer_len
)) {
833 /* Skip codes that require special handling depending on
840 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
842 case COMP_STOP_INVAL
:
843 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
846 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
847 ep_ring
->state
|= EP_HALTED
;
851 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
855 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
859 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
863 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
867 /* Now update the urb's actual_length and give back to the core */
868 /* Was this a control transfer? */
869 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
870 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
871 switch (GET_COMP_CODE(event
->transfer_len
)) {
873 if (event_trb
== ep_ring
->dequeue
) {
874 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
876 } else if (event_trb
!= td
->last_trb
) {
877 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
880 xhci_dbg(xhci
, "Successful control transfer!\n");
885 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
889 /* Others already handled above */
893 * Did we transfer any data, despite the errors that might have
894 * happened? I.e. did we get past the setup stage?
896 if (event_trb
!= ep_ring
->dequeue
) {
897 /* The event was for the status stage */
898 if (event_trb
== td
->last_trb
) {
899 /* Did we already see a short data stage? */
900 if (td
->urb
->actual_length
!= 0)
903 td
->urb
->actual_length
=
904 td
->urb
->transfer_buffer_length
;
906 /* Maybe the event was for the data stage? */
907 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STOP_INVAL
) {
908 /* We didn't stop on a link TRB in the middle */
909 td
->urb
->actual_length
=
910 td
->urb
->transfer_buffer_length
-
911 TRB_LEN(event
->transfer_len
);
912 xhci_dbg(xhci
, "Waiting for status stage event\n");
919 switch (GET_COMP_CODE(event
->transfer_len
)) {
921 /* Double check that the HW transferred everything. */
922 if (event_trb
!= td
->last_trb
) {
923 xhci_warn(xhci
, "WARN Successful completion "
925 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
930 xhci_dbg(xhci
, "Successful bulk transfer!\n");
935 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
941 /* Others already handled above */
944 dev_dbg(&td
->urb
->dev
->dev
,
945 "ep %#x - asked for %d bytes, "
946 "%d bytes untransferred\n",
947 td
->urb
->ep
->desc
.bEndpointAddress
,
948 td
->urb
->transfer_buffer_length
,
949 TRB_LEN(event
->transfer_len
));
950 /* Fast path - was this the last TRB in the TD for this URB? */
951 if (event_trb
== td
->last_trb
) {
952 if (TRB_LEN(event
->transfer_len
) != 0) {
953 td
->urb
->actual_length
=
954 td
->urb
->transfer_buffer_length
-
955 TRB_LEN(event
->transfer_len
);
956 if (td
->urb
->actual_length
< 0) {
957 xhci_warn(xhci
, "HC gave bad length "
958 "of %d bytes left\n",
959 TRB_LEN(event
->transfer_len
));
960 td
->urb
->actual_length
= 0;
962 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
967 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
968 /* Ignore a short packet completion if the
969 * untransferred length was zero.
974 /* Slow path - walk the list, starting from the dequeue
975 * pointer, to get the actual length transferred.
977 union xhci_trb
*cur_trb
;
978 struct xhci_segment
*cur_seg
;
980 td
->urb
->actual_length
= 0;
981 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
982 cur_trb
!= event_trb
;
983 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
984 if (TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_TR_NOOP
&&
985 TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_LINK
)
986 td
->urb
->actual_length
+=
987 TRB_LEN(cur_trb
->generic
.field
[2]);
989 /* If the ring didn't stop on a Link or No-op TRB, add
990 * in the actual bytes transferred from the Normal TRB
992 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STOP_INVAL
)
993 td
->urb
->actual_length
+=
994 TRB_LEN(cur_trb
->generic
.field
[2]) -
995 TRB_LEN(event
->transfer_len
);
998 /* The Endpoint Stop Command completion will take care of
999 * any stopped TDs. A stopped TD may be restarted, so don't update the
1000 * ring dequeue pointer or take this TD off any lists yet.
1002 if (GET_COMP_CODE(event
->transfer_len
) == COMP_STOP_INVAL
||
1003 GET_COMP_CODE(event
->transfer_len
) == COMP_STOP
) {
1004 ep_ring
->stopped_td
= td
;
1005 ep_ring
->stopped_trb
= event_trb
;
1007 /* Update ring dequeue pointer */
1008 while (ep_ring
->dequeue
!= td
->last_trb
)
1009 inc_deq(xhci
, ep_ring
, false);
1010 inc_deq(xhci
, ep_ring
, false);
1012 /* Clean up the endpoint's TD list */
1014 list_del(&td
->td_list
);
1015 /* Was this TD slated to be cancelled but completed anyway? */
1016 if (!list_empty(&td
->cancelled_td_list
)) {
1017 list_del(&td
->cancelled_td_list
);
1018 ep_ring
->cancels_pending
--;
1024 inc_deq(xhci
, xhci
->event_ring
, true);
1025 xhci_set_hc_event_deq(xhci
);
1027 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1029 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1030 spin_unlock(&xhci
->lock
);
1031 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1032 spin_lock(&xhci
->lock
);
1038 * This function handles all OS-owned events on the event ring. It may drop
1039 * xhci->lock between event processing (e.g. to pass up port status changes).
1041 void xhci_handle_event(struct xhci_hcd
*xhci
)
1043 union xhci_trb
*event
;
1044 int update_ptrs
= 1;
1047 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1048 xhci
->error_bitmask
|= 1 << 1;
1052 event
= xhci
->event_ring
->dequeue
;
1053 /* Does the HC or OS own the TRB? */
1054 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1055 xhci
->event_ring
->cycle_state
) {
1056 xhci
->error_bitmask
|= 1 << 2;
1060 /* FIXME: Handle more event types. */
1061 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1062 case TRB_TYPE(TRB_COMPLETION
):
1063 handle_cmd_completion(xhci
, &event
->event_cmd
);
1065 case TRB_TYPE(TRB_PORT_STATUS
):
1066 handle_port_status(xhci
, event
);
1069 case TRB_TYPE(TRB_TRANSFER
):
1070 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1072 xhci
->error_bitmask
|= 1 << 9;
1077 xhci
->error_bitmask
|= 1 << 3;
1081 /* Update SW and HC event ring dequeue pointer */
1082 inc_deq(xhci
, xhci
->event_ring
, true);
1083 xhci_set_hc_event_deq(xhci
);
1085 /* Are there more items on the event ring? */
1086 xhci_handle_event(xhci
);
1089 /**** Endpoint Ring Operations ****/
1092 * Generic function for queueing a TRB on a ring.
1093 * The caller must have checked to make sure there's room on the ring.
1095 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1097 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1099 struct xhci_generic_trb
*trb
;
1101 trb
= &ring
->enqueue
->generic
;
1102 trb
->field
[0] = field1
;
1103 trb
->field
[1] = field2
;
1104 trb
->field
[2] = field3
;
1105 trb
->field
[3] = field4
;
1106 inc_enq(xhci
, ring
, consumer
);
1110 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1111 * FIXME allocate segments if the ring is full.
1113 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1114 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1116 /* Make sure the endpoint has been added to xHC schedule */
1117 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1119 case EP_STATE_DISABLED
:
1121 * USB core changed config/interfaces without notifying us,
1122 * or hardware is reporting the wrong state.
1124 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1126 case EP_STATE_HALTED
:
1127 case EP_STATE_ERROR
:
1128 xhci_warn(xhci
, "WARN waiting for halt or error on ep "
1130 /* FIXME event handling code for error needs to clear it */
1131 /* XXX not sure if this should be -ENOENT or not */
1133 case EP_STATE_STOPPED
:
1134 case EP_STATE_RUNNING
:
1137 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1139 * FIXME issue Configure Endpoint command to try to get the HC
1140 * back into a known state.
1144 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1145 /* FIXME allocate more room */
1146 xhci_err(xhci
, "ERROR no room on ep ring\n");
1152 static int prepare_transfer(struct xhci_hcd
*xhci
,
1153 struct xhci_virt_device
*xdev
,
1154 unsigned int ep_index
,
1155 unsigned int num_trbs
,
1157 struct xhci_td
**td
,
1162 ret
= prepare_ring(xhci
, xdev
->ep_rings
[ep_index
],
1163 xdev
->out_ctx
->ep
[ep_index
].ep_info
& EP_STATE_MASK
,
1164 num_trbs
, mem_flags
);
1167 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1170 INIT_LIST_HEAD(&(*td
)->td_list
);
1171 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1173 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1174 if (unlikely(ret
)) {
1180 urb
->hcpriv
= (void *) (*td
);
1181 /* Add this TD to the tail of the endpoint ring's TD list */
1182 list_add_tail(&(*td
)->td_list
, &xdev
->ep_rings
[ep_index
]->td_list
);
1183 (*td
)->start_seg
= xdev
->ep_rings
[ep_index
]->enq_seg
;
1184 (*td
)->first_trb
= xdev
->ep_rings
[ep_index
]->enqueue
;
1189 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1191 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1192 struct scatterlist
*sg
;
1195 num_sgs
= urb
->num_sgs
;
1196 temp
= urb
->transfer_buffer_length
;
1198 xhci_dbg(xhci
, "count sg list trbs: \n");
1200 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1201 unsigned int previous_total_trbs
= num_trbs
;
1202 unsigned int len
= sg_dma_len(sg
);
1204 /* Scatter gather list entries may cross 64KB boundaries */
1205 running_total
= TRB_MAX_BUFF_SIZE
-
1206 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1207 if (running_total
!= 0)
1210 /* How many more 64KB chunks to transfer, how many more TRBs? */
1211 while (running_total
< sg_dma_len(sg
)) {
1213 running_total
+= TRB_MAX_BUFF_SIZE
;
1215 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1216 i
, (unsigned long long)sg_dma_address(sg
),
1217 len
, len
, num_trbs
- previous_total_trbs
);
1219 len
= min_t(int, len
, temp
);
1224 xhci_dbg(xhci
, "\n");
1225 if (!in_interrupt())
1226 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1227 urb
->ep
->desc
.bEndpointAddress
,
1228 urb
->transfer_buffer_length
,
1233 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1236 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1237 "TRBs, %d left\n", __func__
,
1238 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1239 if (running_total
!= urb
->transfer_buffer_length
)
1240 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1241 "queued %#x (%d), asked for %#x (%d)\n",
1243 urb
->ep
->desc
.bEndpointAddress
,
1244 running_total
, running_total
,
1245 urb
->transfer_buffer_length
,
1246 urb
->transfer_buffer_length
);
1249 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1250 unsigned int ep_index
, int start_cycle
,
1251 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1254 * Pass all the TRBs to the hardware at once and make sure this write
1258 start_trb
->field
[3] |= start_cycle
;
1259 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1262 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1263 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1265 struct xhci_ring
*ep_ring
;
1266 unsigned int num_trbs
;
1268 struct scatterlist
*sg
;
1270 int trb_buff_len
, this_sg_len
, running_total
;
1274 struct xhci_generic_trb
*start_trb
;
1277 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1278 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1279 num_sgs
= urb
->num_sgs
;
1281 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1282 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1283 if (trb_buff_len
< 0)
1284 return trb_buff_len
;
1286 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1287 * until we've finished creating all the other TRBs. The ring's cycle
1288 * state may change as we enqueue the other TRBs, so save it too.
1290 start_trb
= &ep_ring
->enqueue
->generic
;
1291 start_cycle
= ep_ring
->cycle_state
;
1295 * How much data is in the first TRB?
1297 * There are three forces at work for TRB buffer pointers and lengths:
1298 * 1. We don't want to walk off the end of this sg-list entry buffer.
1299 * 2. The transfer length that the driver requested may be smaller than
1300 * the amount of memory allocated for this scatter-gather list.
1301 * 3. TRBs buffers can't cross 64KB boundaries.
1304 addr
= (u64
) sg_dma_address(sg
);
1305 this_sg_len
= sg_dma_len(sg
);
1306 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1307 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1308 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1309 if (trb_buff_len
> urb
->transfer_buffer_length
)
1310 trb_buff_len
= urb
->transfer_buffer_length
;
1311 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1315 /* Queue the first TRB, even if it's zero-length */
1318 u32 length_field
= 0;
1320 /* Don't change the cycle bit of the first TRB until later */
1324 field
|= ep_ring
->cycle_state
;
1326 /* Chain all the TRBs together; clear the chain bit in the last
1327 * TRB to indicate it's the last TRB in the chain.
1332 /* FIXME - add check for ZERO_PACKET flag before this */
1333 td
->last_trb
= ep_ring
->enqueue
;
1336 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1337 "64KB boundary at %#x, end dma = %#x\n",
1338 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1339 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1340 (unsigned int) addr
+ trb_buff_len
);
1341 if (TRB_MAX_BUFF_SIZE
-
1342 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
1343 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1344 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1345 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1346 (unsigned int) addr
+ trb_buff_len
);
1348 length_field
= TRB_LEN(trb_buff_len
) |
1349 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1351 queue_trb(xhci
, ep_ring
, false,
1352 lower_32_bits(addr
),
1353 upper_32_bits(addr
),
1355 /* We always want to know if the TRB was short,
1356 * or we won't get an event when it completes.
1357 * (Unless we use event data TRBs, which are a
1358 * waste of space and HC resources.)
1360 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1362 running_total
+= trb_buff_len
;
1364 /* Calculate length for next transfer --
1365 * Are we done queueing all the TRBs for this sg entry?
1367 this_sg_len
-= trb_buff_len
;
1368 if (this_sg_len
== 0) {
1373 addr
= (u64
) sg_dma_address(sg
);
1374 this_sg_len
= sg_dma_len(sg
);
1376 addr
+= trb_buff_len
;
1379 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1380 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1381 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1382 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1384 urb
->transfer_buffer_length
- running_total
;
1385 } while (running_total
< urb
->transfer_buffer_length
);
1387 check_trb_math(urb
, num_trbs
, running_total
);
1388 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1392 /* This is very similar to what ehci-q.c qtd_fill() does */
1393 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1394 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1396 struct xhci_ring
*ep_ring
;
1399 struct xhci_generic_trb
*start_trb
;
1402 u32 field
, length_field
;
1404 int running_total
, trb_buff_len
, ret
;
1408 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1410 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1413 /* How much data is (potentially) left before the 64KB boundary? */
1414 running_total
= TRB_MAX_BUFF_SIZE
-
1415 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1417 /* If there's some data on this 64KB chunk, or we have to send a
1418 * zero-length transfer, we need at least one TRB
1420 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1422 /* How many more 64KB chunks to transfer, how many more TRBs? */
1423 while (running_total
< urb
->transfer_buffer_length
) {
1425 running_total
+= TRB_MAX_BUFF_SIZE
;
1427 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1429 if (!in_interrupt())
1430 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1431 urb
->ep
->desc
.bEndpointAddress
,
1432 urb
->transfer_buffer_length
,
1433 urb
->transfer_buffer_length
,
1434 (unsigned long long)urb
->transfer_dma
,
1437 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1438 num_trbs
, urb
, &td
, mem_flags
);
1443 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1444 * until we've finished creating all the other TRBs. The ring's cycle
1445 * state may change as we enqueue the other TRBs, so save it too.
1447 start_trb
= &ep_ring
->enqueue
->generic
;
1448 start_cycle
= ep_ring
->cycle_state
;
1451 /* How much data is in the first TRB? */
1452 addr
= (u64
) urb
->transfer_dma
;
1453 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1454 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1455 if (urb
->transfer_buffer_length
< trb_buff_len
)
1456 trb_buff_len
= urb
->transfer_buffer_length
;
1460 /* Queue the first TRB, even if it's zero-length */
1464 /* Don't change the cycle bit of the first TRB until later */
1468 field
|= ep_ring
->cycle_state
;
1470 /* Chain all the TRBs together; clear the chain bit in the last
1471 * TRB to indicate it's the last TRB in the chain.
1476 /* FIXME - add check for ZERO_PACKET flag before this */
1477 td
->last_trb
= ep_ring
->enqueue
;
1480 length_field
= TRB_LEN(trb_buff_len
) |
1481 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1483 queue_trb(xhci
, ep_ring
, false,
1484 lower_32_bits(addr
),
1485 upper_32_bits(addr
),
1487 /* We always want to know if the TRB was short,
1488 * or we won't get an event when it completes.
1489 * (Unless we use event data TRBs, which are a
1490 * waste of space and HC resources.)
1492 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1494 running_total
+= trb_buff_len
;
1496 /* Calculate length for next transfer */
1497 addr
+= trb_buff_len
;
1498 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
1499 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
1500 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
1501 } while (running_total
< urb
->transfer_buffer_length
);
1503 check_trb_math(urb
, num_trbs
, running_total
);
1504 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1508 /* Caller must have locked xhci->lock */
1509 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1510 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1512 struct xhci_ring
*ep_ring
;
1515 struct usb_ctrlrequest
*setup
;
1516 struct xhci_generic_trb
*start_trb
;
1518 u32 field
, length_field
;
1521 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1524 * Need to copy setup packet into setup TRB, so we can't use the setup
1527 if (!urb
->setup_packet
)
1530 if (!in_interrupt())
1531 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
1533 /* 1 TRB for setup, 1 for status */
1536 * Don't need to check if we need additional event data and normal TRBs,
1537 * since data in control transfers will never get bigger than 16MB
1538 * XXX: can we get a buffer that crosses 64KB boundaries?
1540 if (urb
->transfer_buffer_length
> 0)
1542 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
1543 urb
, &td
, mem_flags
);
1548 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1549 * until we've finished creating all the other TRBs. The ring's cycle
1550 * state may change as we enqueue the other TRBs, so save it too.
1552 start_trb
= &ep_ring
->enqueue
->generic
;
1553 start_cycle
= ep_ring
->cycle_state
;
1555 /* Queue setup TRB - see section 6.4.1.2.1 */
1556 /* FIXME better way to translate setup_packet into two u32 fields? */
1557 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
1558 queue_trb(xhci
, ep_ring
, false,
1559 /* FIXME endianness is probably going to bite my ass here. */
1560 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
1561 setup
->wIndex
| setup
->wLength
<< 16,
1562 TRB_LEN(8) | TRB_INTR_TARGET(0),
1563 /* Immediate data in pointer */
1564 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
1566 /* If there's data, queue data TRBs */
1568 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
1569 TD_REMAINDER(urb
->transfer_buffer_length
) |
1571 if (urb
->transfer_buffer_length
> 0) {
1572 if (setup
->bRequestType
& USB_DIR_IN
)
1573 field
|= TRB_DIR_IN
;
1574 queue_trb(xhci
, ep_ring
, false,
1575 lower_32_bits(urb
->transfer_dma
),
1576 upper_32_bits(urb
->transfer_dma
),
1578 /* Event on short tx */
1579 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
1582 /* Save the DMA address of the last TRB in the TD */
1583 td
->last_trb
= ep_ring
->enqueue
;
1585 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1586 /* If the device sent data, the status stage is an OUT transfer */
1587 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
1591 queue_trb(xhci
, ep_ring
, false,
1595 /* Event on completion */
1596 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
1598 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1602 /**** Command Ring Operations ****/
1604 /* Generic function for queueing a command TRB on the command ring */
1605 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1607 if (!room_on_ring(xhci
, xhci
->cmd_ring
, 1)) {
1608 if (!in_interrupt())
1609 xhci_err(xhci
, "ERR: No room for command on command ring\n");
1612 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
1613 field4
| xhci
->cmd_ring
->cycle_state
);
1617 /* Queue a no-op command on the command ring */
1618 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
1620 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
));
1624 * Place a no-op command on the command ring to test the command and
1627 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
1629 if (queue_cmd_noop(xhci
) < 0)
1631 xhci
->noops_submitted
++;
1632 return xhci_ring_cmd_db
;
1635 /* Queue a slot enable or disable request on the command ring */
1636 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
1638 return queue_command(xhci
, 0, 0, 0,
1639 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
));
1642 /* Queue an address device command TRB */
1643 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1646 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1647 upper_32_bits(in_ctx_ptr
), 0,
1648 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
));
1651 /* Queue a configure endpoint command TRB */
1652 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1655 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1656 upper_32_bits(in_ctx_ptr
), 0,
1657 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
));
1660 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
1661 unsigned int ep_index
)
1663 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1664 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1665 u32 type
= TRB_TYPE(TRB_STOP_RING
);
1667 return queue_command(xhci
, 0, 0, 0,
1668 trb_slot_id
| trb_ep_index
| type
);
1671 /* Set Transfer Ring Dequeue Pointer command.
1672 * This should not be used for endpoints that have streams enabled.
1674 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
1675 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
1676 union xhci_trb
*deq_ptr
, u32 cycle_state
)
1679 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1680 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1681 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
1683 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
1685 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
1686 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
1688 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
1689 upper_32_bits(addr
), 0,
1690 trb_slot_id
| trb_ep_index
| type
);
1693 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1694 unsigned int ep_index
)
1696 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1697 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1698 u32 type
= TRB_TYPE(TRB_RESET_EP
);
1700 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
);