2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
72 struct xhci_virt_device
*virt_dev
,
73 struct xhci_event_cmd
*event
);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
82 unsigned long segment_offset
;
84 if (!seg
|| !trb
|| trb
< seg
->trbs
)
87 segment_offset
= trb
- seg
->trbs
;
88 if (segment_offset
> TRBS_PER_SEGMENT
)
90 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
97 struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 if (ring
== xhci
->event_ring
)
100 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
101 (seg
->next
== xhci
->event_ring
->first_seg
);
103 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
111 struct xhci_segment
*seg
, union xhci_trb
*trb
)
113 if (ring
== xhci
->event_ring
)
114 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
116 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
119 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
121 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
122 return TRB_TYPE_LINK_LE32(link
->control
);
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd
*xhci
,
130 struct xhci_ring
*ring
,
131 struct xhci_segment
**seg
,
132 union xhci_trb
**trb
)
134 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
136 *trb
= ((*seg
)->trbs
);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
148 union xhci_trb
*next
= ++(ring
->dequeue
);
149 unsigned long long addr
;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
155 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
156 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
157 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
159 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
161 (unsigned int) ring
->cycle_state
);
163 ring
->deq_seg
= ring
->deq_seg
->next
;
164 ring
->dequeue
= ring
->deq_seg
->trbs
;
165 next
= ring
->dequeue
;
167 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
171 * See Cycle bit rules. SW is the consumer for the event ring only.
172 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
174 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
175 * chain bit is set), then set the chain bit in all the following link TRBs.
176 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
177 * have their chain bit cleared (so that each Link TRB is a separate TD).
179 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
180 * set, but other sections talk about dealing with the chain bit set. This was
181 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
182 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
184 * @more_trbs_coming: Will you enqueue more TRBs before calling
185 * prepare_transfer()?
187 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
188 bool consumer
, bool more_trbs_coming
)
191 union xhci_trb
*next
;
192 unsigned long long addr
;
194 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
195 next
= ++(ring
->enqueue
);
198 /* Update the dequeue pointer further if that was a link TRB or we're at
199 * the end of an event ring segment (which doesn't have link TRBS)
201 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
203 if (ring
!= xhci
->event_ring
) {
205 * If the caller doesn't plan on enqueueing more
206 * TDs before ringing the doorbell, then we
207 * don't want to give the link TRB to the
208 * hardware just yet. We'll give the link TRB
209 * back in prepare_ring() just before we enqueue
210 * the TD at the top of the ring.
212 if (!chain
&& !more_trbs_coming
)
215 /* If we're not dealing with 0.95 hardware,
216 * carry over the chain bit of the previous TRB
217 * (which may mean the chain bit is cleared).
219 if (!xhci_link_trb_quirk(xhci
)) {
220 next
->link
.control
&=
221 cpu_to_le32(~TRB_CHAIN
);
222 next
->link
.control
|=
225 /* Give this link TRB to the hardware */
227 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
229 /* Toggle the cycle bit after the last ring segment. */
230 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
231 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
233 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
235 (unsigned int) ring
->cycle_state
);
238 ring
->enq_seg
= ring
->enq_seg
->next
;
239 ring
->enqueue
= ring
->enq_seg
->trbs
;
240 next
= ring
->enqueue
;
242 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
246 * Check to see if there's room to enqueue num_trbs on the ring. See rules
248 * FIXME: this would be simpler and faster if we just kept track of the number
249 * of free TRBs in a ring.
251 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
252 unsigned int num_trbs
)
255 union xhci_trb
*enq
= ring
->enqueue
;
256 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
257 struct xhci_segment
*cur_seg
;
258 unsigned int left_on_ring
;
260 /* If we are currently pointing to a link TRB, advance the
261 * enqueue pointer before checking for space */
262 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
263 enq_seg
= enq_seg
->next
;
267 /* Check if ring is empty */
268 if (enq
== ring
->dequeue
) {
269 /* Can't use link trbs */
270 left_on_ring
= TRBS_PER_SEGMENT
- 1;
271 for (cur_seg
= enq_seg
->next
; cur_seg
!= enq_seg
;
272 cur_seg
= cur_seg
->next
)
273 left_on_ring
+= TRBS_PER_SEGMENT
- 1;
275 /* Always need one TRB free in the ring. */
277 if (num_trbs
> left_on_ring
) {
278 xhci_warn(xhci
, "Not enough room on ring; "
279 "need %u TRBs, %u TRBs left\n",
280 num_trbs
, left_on_ring
);
285 /* Make sure there's an extra empty TRB available */
286 for (i
= 0; i
<= num_trbs
; ++i
) {
287 if (enq
== ring
->dequeue
)
290 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
291 enq_seg
= enq_seg
->next
;
298 /* Ring the host controller doorbell after placing a command on the ring */
299 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
301 xhci_dbg(xhci
, "// Ding dong!\n");
302 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
303 /* Flush PCI posted writes */
304 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
307 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
308 unsigned int slot_id
,
309 unsigned int ep_index
,
310 unsigned int stream_id
)
312 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
313 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
314 unsigned int ep_state
= ep
->ep_state
;
316 /* Don't ring the doorbell for this endpoint if there are pending
317 * cancellations because we don't want to interrupt processing.
318 * We don't want to restart any stream rings if there's a set dequeue
319 * pointer command pending because the device can choose to start any
320 * stream once the endpoint is on the HW schedule.
321 * FIXME - check all the stream rings for pending cancellations.
323 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
324 (ep_state
& EP_HALTED
))
326 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
327 /* The CPU has better things to do at this point than wait for a
328 * write-posting flush. It'll get there soon enough.
332 /* Ring the doorbell for any rings with pending URBs */
333 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
334 unsigned int slot_id
,
335 unsigned int ep_index
)
337 unsigned int stream_id
;
338 struct xhci_virt_ep
*ep
;
340 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
342 /* A ring has pending URBs if its TD list is not empty */
343 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
344 if (!(list_empty(&ep
->ring
->td_list
)))
345 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
349 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
351 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
352 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
353 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
359 * Find the segment that trb is in. Start searching in start_seg.
360 * If we must move past a segment that has a link TRB with a toggle cycle state
361 * bit set, then we will toggle the value pointed at by cycle_state.
363 static struct xhci_segment
*find_trb_seg(
364 struct xhci_segment
*start_seg
,
365 union xhci_trb
*trb
, int *cycle_state
)
367 struct xhci_segment
*cur_seg
= start_seg
;
368 struct xhci_generic_trb
*generic_trb
;
370 while (cur_seg
->trbs
> trb
||
371 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
372 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
373 if (generic_trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
))
375 cur_seg
= cur_seg
->next
;
376 if (cur_seg
== start_seg
)
377 /* Looped over the entire list. Oops! */
384 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
385 unsigned int slot_id
, unsigned int ep_index
,
386 unsigned int stream_id
)
388 struct xhci_virt_ep
*ep
;
390 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
391 /* Common case: no streams */
392 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
395 if (stream_id
== 0) {
397 "WARN: Slot ID %u, ep index %u has streams, "
398 "but URB has no stream ID.\n",
403 if (stream_id
< ep
->stream_info
->num_streams
)
404 return ep
->stream_info
->stream_rings
[stream_id
];
407 "WARN: Slot ID %u, ep index %u has "
408 "stream IDs 1 to %u allocated, "
409 "but stream ID %u is requested.\n",
411 ep
->stream_info
->num_streams
- 1,
416 /* Get the right ring for the given URB.
417 * If the endpoint supports streams, boundary check the URB's stream ID.
418 * If the endpoint doesn't support streams, return the singular endpoint ring.
420 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
423 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
424 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
428 * Move the xHC's endpoint ring dequeue pointer past cur_td.
429 * Record the new state of the xHC's endpoint ring dequeue segment,
430 * dequeue pointer, and new consumer cycle state in state.
431 * Update our internal representation of the ring's dequeue pointer.
433 * We do this in three jumps:
434 * - First we update our new ring state to be the same as when the xHC stopped.
435 * - Then we traverse the ring to find the segment that contains
436 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
437 * any link TRBs with the toggle cycle bit set.
438 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
439 * if we've moved it past a link TRB with the toggle cycle bit set.
441 * Some of the uses of xhci_generic_trb are grotty, but if they're done
442 * with correct __le32 accesses they should work fine. Only users of this are
445 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
446 unsigned int slot_id
, unsigned int ep_index
,
447 unsigned int stream_id
, struct xhci_td
*cur_td
,
448 struct xhci_dequeue_state
*state
)
450 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
451 struct xhci_ring
*ep_ring
;
452 struct xhci_generic_trb
*trb
;
453 struct xhci_ep_ctx
*ep_ctx
;
456 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
457 ep_index
, stream_id
);
459 xhci_warn(xhci
, "WARN can't find new dequeue state "
460 "for invalid stream ID %u.\n",
464 state
->new_cycle_state
= 0;
465 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
466 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
467 dev
->eps
[ep_index
].stopped_trb
,
468 &state
->new_cycle_state
);
469 if (!state
->new_deq_seg
) {
474 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
475 xhci_dbg(xhci
, "Finding endpoint context\n");
476 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
477 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
479 state
->new_deq_ptr
= cur_td
->last_trb
;
480 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
481 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
483 &state
->new_cycle_state
);
484 if (!state
->new_deq_seg
) {
489 trb
= &state
->new_deq_ptr
->generic
;
490 if (TRB_TYPE_LINK_LE32(trb
->field
[3]) &&
491 (trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
)))
492 state
->new_cycle_state
^= 0x1;
493 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
496 * If there is only one segment in a ring, find_trb_seg()'s while loop
497 * will not run, and it will return before it has a chance to see if it
498 * needs to toggle the cycle bit. It can't tell if the stalled transfer
499 * ended just before the link TRB on a one-segment ring, or if the TD
500 * wrapped around the top of the ring, because it doesn't have the TD in
501 * question. Look for the one-segment case where stalled TRB's address
502 * is greater than the new dequeue pointer address.
504 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
505 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
506 state
->new_cycle_state
^= 0x1;
507 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
509 /* Don't update the ring cycle state for the producer (us). */
510 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
512 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
513 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
514 (unsigned long long) addr
);
517 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
518 * (The last TRB actually points to the ring enqueue pointer, which is not part
519 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
521 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
522 struct xhci_td
*cur_td
, bool flip_cycle
)
524 struct xhci_segment
*cur_seg
;
525 union xhci_trb
*cur_trb
;
527 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
529 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
530 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
531 /* Unchain any chained Link TRBs, but
532 * leave the pointers intact.
534 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
535 /* Flip the cycle bit (link TRBs can't be the first
539 cur_trb
->generic
.field
[3] ^=
540 cpu_to_le32(TRB_CYCLE
);
541 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
542 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
543 "in seg %p (0x%llx dma)\n",
545 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
547 (unsigned long long)cur_seg
->dma
);
549 cur_trb
->generic
.field
[0] = 0;
550 cur_trb
->generic
.field
[1] = 0;
551 cur_trb
->generic
.field
[2] = 0;
552 /* Preserve only the cycle bit of this TRB */
553 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
554 /* Flip the cycle bit except on the first or last TRB */
555 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
556 cur_trb
!= cur_td
->last_trb
)
557 cur_trb
->generic
.field
[3] ^=
558 cpu_to_le32(TRB_CYCLE
);
559 cur_trb
->generic
.field
[3] |= cpu_to_le32(
560 TRB_TYPE(TRB_TR_NOOP
));
561 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
562 "in seg %p (0x%llx dma)\n",
564 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
566 (unsigned long long)cur_seg
->dma
);
568 if (cur_trb
== cur_td
->last_trb
)
573 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
574 unsigned int ep_index
, unsigned int stream_id
,
575 struct xhci_segment
*deq_seg
,
576 union xhci_trb
*deq_ptr
, u32 cycle_state
);
578 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
579 unsigned int slot_id
, unsigned int ep_index
,
580 unsigned int stream_id
,
581 struct xhci_dequeue_state
*deq_state
)
583 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
585 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
586 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
587 deq_state
->new_deq_seg
,
588 (unsigned long long)deq_state
->new_deq_seg
->dma
,
589 deq_state
->new_deq_ptr
,
590 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
591 deq_state
->new_cycle_state
);
592 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
593 deq_state
->new_deq_seg
,
594 deq_state
->new_deq_ptr
,
595 (u32
) deq_state
->new_cycle_state
);
596 /* Stop the TD queueing code from ringing the doorbell until
597 * this command completes. The HC won't set the dequeue pointer
598 * if the ring is running, and ringing the doorbell starts the
601 ep
->ep_state
|= SET_DEQ_PENDING
;
604 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
605 struct xhci_virt_ep
*ep
)
607 ep
->ep_state
&= ~EP_HALT_PENDING
;
608 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
609 * timer is running on another CPU, we don't decrement stop_cmds_pending
610 * (since we didn't successfully stop the watchdog timer).
612 if (del_timer(&ep
->stop_cmd_timer
))
613 ep
->stop_cmds_pending
--;
616 /* Must be called with xhci->lock held in interrupt context */
617 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
618 struct xhci_td
*cur_td
, int status
, char *adjective
)
622 struct urb_priv
*urb_priv
;
625 urb_priv
= urb
->hcpriv
;
627 hcd
= bus_to_hcd(urb
->dev
->bus
);
629 /* Only giveback urb when this is the last td in urb */
630 if (urb_priv
->td_cnt
== urb_priv
->length
) {
631 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
632 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
633 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
634 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
635 usb_amd_quirk_pll_enable();
638 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
640 spin_unlock(&xhci
->lock
);
641 usb_hcd_giveback_urb(hcd
, urb
, status
);
642 xhci_urb_free_priv(xhci
, urb_priv
);
643 spin_lock(&xhci
->lock
);
648 * When we get a command completion for a Stop Endpoint Command, we need to
649 * unlink any cancelled TDs from the ring. There are two ways to do that:
651 * 1. If the HW was in the middle of processing the TD that needs to be
652 * cancelled, then we must move the ring's dequeue pointer past the last TRB
653 * in the TD with a Set Dequeue Pointer Command.
654 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
655 * bit cleared) so that the HW will skip over them.
657 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
658 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
660 unsigned int slot_id
;
661 unsigned int ep_index
;
662 struct xhci_virt_device
*virt_dev
;
663 struct xhci_ring
*ep_ring
;
664 struct xhci_virt_ep
*ep
;
665 struct list_head
*entry
;
666 struct xhci_td
*cur_td
= NULL
;
667 struct xhci_td
*last_unlinked_td
;
669 struct xhci_dequeue_state deq_state
;
671 if (unlikely(TRB_TO_SUSPEND_PORT(
672 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
673 slot_id
= TRB_TO_SLOT_ID(
674 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
675 virt_dev
= xhci
->devs
[slot_id
];
677 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
680 xhci_warn(xhci
, "Stop endpoint command "
681 "completion for disabled slot %u\n",
686 memset(&deq_state
, 0, sizeof(deq_state
));
687 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
688 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
689 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
691 if (list_empty(&ep
->cancelled_td_list
)) {
692 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
693 ep
->stopped_td
= NULL
;
694 ep
->stopped_trb
= NULL
;
695 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
699 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
700 * We have the xHCI lock, so nothing can modify this list until we drop
701 * it. We're also in the event handler, so we can't get re-interrupted
702 * if another Stop Endpoint command completes
704 list_for_each(entry
, &ep
->cancelled_td_list
) {
705 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
706 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
708 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
709 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
711 /* This shouldn't happen unless a driver is mucking
712 * with the stream ID after submission. This will
713 * leave the TD on the hardware ring, and the hardware
714 * will try to execute it, and may access a buffer
715 * that has already been freed. In the best case, the
716 * hardware will execute it, and the event handler will
717 * ignore the completion event for that TD, since it was
718 * removed from the td_list for that endpoint. In
719 * short, don't muck with the stream ID after
722 xhci_warn(xhci
, "WARN Cancelled URB %p "
723 "has invalid stream ID %u.\n",
725 cur_td
->urb
->stream_id
);
726 goto remove_finished_td
;
729 * If we stopped on the TD we need to cancel, then we have to
730 * move the xHC endpoint ring dequeue pointer past this TD.
732 if (cur_td
== ep
->stopped_td
)
733 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
734 cur_td
->urb
->stream_id
,
737 td_to_noop(xhci
, ep_ring
, cur_td
, false);
740 * The event handler won't see a completion for this TD anymore,
741 * so remove it from the endpoint ring's TD list. Keep it in
742 * the cancelled TD list for URB completion later.
744 list_del_init(&cur_td
->td_list
);
746 last_unlinked_td
= cur_td
;
747 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
749 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
750 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
751 xhci_queue_new_dequeue_state(xhci
,
753 ep
->stopped_td
->urb
->stream_id
,
755 xhci_ring_cmd_db(xhci
);
757 /* Otherwise ring the doorbell(s) to restart queued transfers */
758 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
760 ep
->stopped_td
= NULL
;
761 ep
->stopped_trb
= NULL
;
764 * Drop the lock and complete the URBs in the cancelled TD list.
765 * New TDs to be cancelled might be added to the end of the list before
766 * we can complete all the URBs for the TDs we already unlinked.
767 * So stop when we've completed the URB for the last TD we unlinked.
770 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
771 struct xhci_td
, cancelled_td_list
);
772 list_del_init(&cur_td
->cancelled_td_list
);
774 /* Clean up the cancelled URB */
775 /* Doesn't matter what we pass for status, since the core will
776 * just overwrite it (because the URB has been unlinked).
778 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
780 /* Stop processing the cancelled list if the watchdog timer is
783 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
785 } while (cur_td
!= last_unlinked_td
);
787 /* Return to the event handler with xhci->lock re-acquired */
790 /* Watchdog timer function for when a stop endpoint command fails to complete.
791 * In this case, we assume the host controller is broken or dying or dead. The
792 * host may still be completing some other events, so we have to be careful to
793 * let the event ring handler and the URB dequeueing/enqueueing functions know
794 * through xhci->state.
796 * The timer may also fire if the host takes a very long time to respond to the
797 * command, and the stop endpoint command completion handler cannot delete the
798 * timer before the timer function is called. Another endpoint cancellation may
799 * sneak in before the timer function can grab the lock, and that may queue
800 * another stop endpoint command and add the timer back. So we cannot use a
801 * simple flag to say whether there is a pending stop endpoint command for a
802 * particular endpoint.
804 * Instead we use a combination of that flag and a counter for the number of
805 * pending stop endpoint commands. If the timer is the tail end of the last
806 * stop endpoint command, and the endpoint's command is still pending, we assume
809 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
811 struct xhci_hcd
*xhci
;
812 struct xhci_virt_ep
*ep
;
813 struct xhci_virt_ep
*temp_ep
;
814 struct xhci_ring
*ring
;
815 struct xhci_td
*cur_td
;
818 ep
= (struct xhci_virt_ep
*) arg
;
821 spin_lock(&xhci
->lock
);
823 ep
->stop_cmds_pending
--;
824 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
825 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
826 "xHCI as DYING, exiting.\n");
827 spin_unlock(&xhci
->lock
);
830 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
831 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
833 spin_unlock(&xhci
->lock
);
837 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
838 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
839 /* Oops, HC is dead or dying or at least not responding to the stop
842 xhci
->xhc_state
|= XHCI_STATE_DYING
;
843 /* Disable interrupts from the host controller and start halting it */
845 spin_unlock(&xhci
->lock
);
847 ret
= xhci_halt(xhci
);
849 spin_lock(&xhci
->lock
);
851 /* This is bad; the host is not responding to commands and it's
852 * not allowing itself to be halted. At least interrupts are
853 * disabled. If we call usb_hc_died(), it will attempt to
854 * disconnect all device drivers under this host. Those
855 * disconnect() methods will wait for all URBs to be unlinked,
856 * so we must complete them.
858 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
859 xhci_warn(xhci
, "Completing active URBs anyway.\n");
860 /* We could turn all TDs on the rings to no-ops. This won't
861 * help if the host has cached part of the ring, and is slow if
862 * we want to preserve the cycle bit. Skip it and hope the host
863 * doesn't touch the memory.
866 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
869 for (j
= 0; j
< 31; j
++) {
870 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
871 ring
= temp_ep
->ring
;
874 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
875 "ep index %u\n", i
, j
);
876 while (!list_empty(&ring
->td_list
)) {
877 cur_td
= list_first_entry(&ring
->td_list
,
880 list_del_init(&cur_td
->td_list
);
881 if (!list_empty(&cur_td
->cancelled_td_list
))
882 list_del_init(&cur_td
->cancelled_td_list
);
883 xhci_giveback_urb_in_irq(xhci
, cur_td
,
884 -ESHUTDOWN
, "killed");
886 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
887 cur_td
= list_first_entry(
888 &temp_ep
->cancelled_td_list
,
891 list_del_init(&cur_td
->cancelled_td_list
);
892 xhci_giveback_urb_in_irq(xhci
, cur_td
,
893 -ESHUTDOWN
, "killed");
897 spin_unlock(&xhci
->lock
);
898 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
899 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
900 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
904 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
905 * we need to clear the set deq pending flag in the endpoint ring state, so that
906 * the TD queueing code can ring the doorbell again. We also need to ring the
907 * endpoint doorbell to restart the ring, but only if there aren't more
908 * cancellations pending.
910 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
911 struct xhci_event_cmd
*event
,
914 unsigned int slot_id
;
915 unsigned int ep_index
;
916 unsigned int stream_id
;
917 struct xhci_ring
*ep_ring
;
918 struct xhci_virt_device
*dev
;
919 struct xhci_ep_ctx
*ep_ctx
;
920 struct xhci_slot_ctx
*slot_ctx
;
922 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
923 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
924 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
925 dev
= xhci
->devs
[slot_id
];
927 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
929 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
930 "freed stream ID %u\n",
932 /* XXX: Harmless??? */
933 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
937 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
938 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
940 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
941 unsigned int ep_state
;
942 unsigned int slot_state
;
944 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
946 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
947 "of stream ID configuration\n");
950 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
951 "to incorrect slot or ep state.\n");
952 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
953 ep_state
&= EP_STATE_MASK
;
954 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
955 slot_state
= GET_SLOT_STATE(slot_state
);
956 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
957 slot_state
, ep_state
);
960 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
961 "slot %u was not enabled.\n", slot_id
);
964 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
965 "completion code of %u.\n",
966 GET_COMP_CODE(le32_to_cpu(event
->status
)));
969 /* OK what do we do now? The endpoint state is hosed, and we
970 * should never get to this point if the synchronization between
971 * queueing, and endpoint state are correct. This might happen
972 * if the device gets disconnected after we've finished
973 * cancelling URBs, which might not be an error...
976 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
977 le64_to_cpu(ep_ctx
->deq
));
978 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
979 dev
->eps
[ep_index
].queued_deq_ptr
) ==
980 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
981 /* Update the ring's dequeue segment and dequeue pointer
982 * to reflect the new position.
984 ep_ring
->deq_seg
= dev
->eps
[ep_index
].queued_deq_seg
;
985 ep_ring
->dequeue
= dev
->eps
[ep_index
].queued_deq_ptr
;
987 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
988 "Ptr command & xHCI internal state.\n");
989 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
990 dev
->eps
[ep_index
].queued_deq_seg
,
991 dev
->eps
[ep_index
].queued_deq_ptr
);
995 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
996 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
997 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
998 /* Restart any rings with pending URBs */
999 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1002 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
1003 struct xhci_event_cmd
*event
,
1004 union xhci_trb
*trb
)
1007 unsigned int ep_index
;
1009 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1010 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1011 /* This command will only fail if the endpoint wasn't halted,
1012 * but we don't care.
1014 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
1015 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1017 /* HW with the reset endpoint quirk needs to have a configure endpoint
1018 * command complete before the endpoint can be used. Queue that here
1019 * because the HW can't handle two commands being queued in a row.
1021 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1022 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
1023 xhci_queue_configure_endpoint(xhci
,
1024 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1026 xhci_ring_cmd_db(xhci
);
1028 /* Clear our internal halted state and restart the ring(s) */
1029 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1030 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1034 /* Check to see if a command in the device's command queue matches this one.
1035 * Signal the completion or free the command, and return 1. Return 0 if the
1036 * completed command isn't at the head of the command list.
1038 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1039 struct xhci_virt_device
*virt_dev
,
1040 struct xhci_event_cmd
*event
)
1042 struct xhci_command
*command
;
1044 if (list_empty(&virt_dev
->cmd_list
))
1047 command
= list_entry(virt_dev
->cmd_list
.next
,
1048 struct xhci_command
, cmd_list
);
1049 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1052 command
->status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1053 list_del(&command
->cmd_list
);
1054 if (command
->completion
)
1055 complete(command
->completion
);
1057 xhci_free_command(xhci
, command
);
1061 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1062 struct xhci_event_cmd
*event
)
1064 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1066 dma_addr_t cmd_dequeue_dma
;
1067 struct xhci_input_control_ctx
*ctrl_ctx
;
1068 struct xhci_virt_device
*virt_dev
;
1069 unsigned int ep_index
;
1070 struct xhci_ring
*ep_ring
;
1071 unsigned int ep_state
;
1073 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1074 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1075 xhci
->cmd_ring
->dequeue
);
1076 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1077 if (cmd_dequeue_dma
== 0) {
1078 xhci
->error_bitmask
|= 1 << 4;
1081 /* Does the DMA address match our internal dequeue pointer address? */
1082 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1083 xhci
->error_bitmask
|= 1 << 5;
1086 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1087 & TRB_TYPE_BITMASK
) {
1088 case TRB_TYPE(TRB_ENABLE_SLOT
):
1089 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1090 xhci
->slot_id
= slot_id
;
1093 complete(&xhci
->addr_dev
);
1095 case TRB_TYPE(TRB_DISABLE_SLOT
):
1096 if (xhci
->devs
[slot_id
]) {
1097 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1098 /* Delete default control endpoint resources */
1099 xhci_free_device_endpoint_resources(xhci
,
1100 xhci
->devs
[slot_id
], true);
1101 xhci_free_virt_device(xhci
, slot_id
);
1104 case TRB_TYPE(TRB_CONFIG_EP
):
1105 virt_dev
= xhci
->devs
[slot_id
];
1106 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1109 * Configure endpoint commands can come from the USB core
1110 * configuration or alt setting changes, or because the HW
1111 * needed an extra configure endpoint command after a reset
1112 * endpoint command or streams were being configured.
1113 * If the command was for a halted endpoint, the xHCI driver
1114 * is not waiting on the configure endpoint command.
1116 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1118 /* Input ctx add_flags are the endpoint index plus one */
1119 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1120 /* A usb_set_interface() call directly after clearing a halted
1121 * condition may race on this quirky hardware. Not worth
1122 * worrying about, since this is prototype hardware. Not sure
1123 * if this will work for streams, but streams support was
1124 * untested on this prototype.
1126 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1127 ep_index
!= (unsigned int) -1 &&
1128 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1129 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1130 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1131 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1132 if (!(ep_state
& EP_HALTED
))
1133 goto bandwidth_change
;
1134 xhci_dbg(xhci
, "Completed config ep cmd - "
1135 "last ep index = %d, state = %d\n",
1136 ep_index
, ep_state
);
1137 /* Clear internal halted state and restart ring(s) */
1138 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1140 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1144 xhci_dbg(xhci
, "Completed config ep cmd\n");
1145 xhci
->devs
[slot_id
]->cmd_status
=
1146 GET_COMP_CODE(le32_to_cpu(event
->status
));
1147 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1149 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1150 virt_dev
= xhci
->devs
[slot_id
];
1151 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1153 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1154 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1156 case TRB_TYPE(TRB_ADDR_DEV
):
1157 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1158 complete(&xhci
->addr_dev
);
1160 case TRB_TYPE(TRB_STOP_RING
):
1161 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1163 case TRB_TYPE(TRB_SET_DEQ
):
1164 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1166 case TRB_TYPE(TRB_CMD_NOOP
):
1168 case TRB_TYPE(TRB_RESET_EP
):
1169 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1171 case TRB_TYPE(TRB_RESET_DEV
):
1172 xhci_dbg(xhci
, "Completed reset device command.\n");
1173 slot_id
= TRB_TO_SLOT_ID(
1174 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1175 virt_dev
= xhci
->devs
[slot_id
];
1177 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1179 xhci_warn(xhci
, "Reset device command completion "
1180 "for disabled slot %u\n", slot_id
);
1182 case TRB_TYPE(TRB_NEC_GET_FW
):
1183 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1184 xhci
->error_bitmask
|= 1 << 6;
1187 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1188 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1189 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1192 /* Skip over unknown commands on the event ring */
1193 xhci
->error_bitmask
|= 1 << 6;
1196 inc_deq(xhci
, xhci
->cmd_ring
, false);
1199 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1200 union xhci_trb
*event
)
1204 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1205 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1206 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1207 handle_cmd_completion(xhci
, &event
->event_cmd
);
1210 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1211 * port registers -- USB 3.0 and USB 2.0).
1213 * Returns a zero-based port number, which is suitable for indexing into each of
1214 * the split roothubs' port arrays and bus state arrays.
1216 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1217 struct xhci_hcd
*xhci
, u32 port_id
)
1220 unsigned int num_similar_speed_ports
= 0;
1222 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1223 * and usb2_ports are 0-based indexes. Count the number of similar
1224 * speed ports, up to 1 port before this port.
1226 for (i
= 0; i
< (port_id
- 1); i
++) {
1227 u8 port_speed
= xhci
->port_array
[i
];
1230 * Skip ports that don't have known speeds, or have duplicate
1231 * Extended Capabilities port speed entries.
1233 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1237 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1238 * 1.1 ports are under the USB 2.0 hub. If the port speed
1239 * matches the device speed, it's a similar speed port.
1241 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1242 num_similar_speed_ports
++;
1244 return num_similar_speed_ports
;
1247 static void handle_port_status(struct xhci_hcd
*xhci
,
1248 union xhci_trb
*event
)
1250 struct usb_hcd
*hcd
;
1255 unsigned int faked_port_index
;
1257 struct xhci_bus_state
*bus_state
;
1258 __le32 __iomem
**port_array
;
1259 bool bogus_port_status
= false;
1261 /* Port status change events always have a successful completion code */
1262 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1263 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1264 xhci
->error_bitmask
|= 1 << 8;
1266 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1267 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1269 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1270 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1271 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1272 bogus_port_status
= true;
1276 /* Figure out which usb_hcd this port is attached to:
1277 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1279 major_revision
= xhci
->port_array
[port_id
- 1];
1280 if (major_revision
== 0) {
1281 xhci_warn(xhci
, "Event for port %u not in "
1282 "Extended Capabilities, ignoring.\n",
1284 bogus_port_status
= true;
1287 if (major_revision
== DUPLICATE_ENTRY
) {
1288 xhci_warn(xhci
, "Event for port %u duplicated in"
1289 "Extended Capabilities, ignoring.\n",
1291 bogus_port_status
= true;
1296 * Hardware port IDs reported by a Port Status Change Event include USB
1297 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1298 * resume event, but we first need to translate the hardware port ID
1299 * into the index into the ports on the correct split roothub, and the
1300 * correct bus_state structure.
1302 /* Find the right roothub. */
1303 hcd
= xhci_to_hcd(xhci
);
1304 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1305 hcd
= xhci
->shared_hcd
;
1306 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1307 if (hcd
->speed
== HCD_USB3
)
1308 port_array
= xhci
->usb3_ports
;
1310 port_array
= xhci
->usb2_ports
;
1311 /* Find the faked port hub number */
1312 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1315 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1316 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1317 xhci_dbg(xhci
, "resume root hub\n");
1318 usb_hcd_resume_root_hub(hcd
);
1321 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1322 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1324 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1325 if (!(temp1
& CMD_RUN
)) {
1326 xhci_warn(xhci
, "xHC is not running.\n");
1330 if (DEV_SUPERSPEED(temp
)) {
1331 xhci_dbg(xhci
, "resume SS port %d\n", port_id
);
1332 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1334 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1337 xhci_dbg(xhci
, "slot_id is zero\n");
1340 xhci_ring_device(xhci
, slot_id
);
1341 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1342 /* Clear PORT_PLC */
1343 xhci_test_and_clear_bit(xhci
, port_array
,
1344 faked_port_index
, PORT_PLC
);
1346 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1347 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1348 msecs_to_jiffies(20);
1349 mod_timer(&hcd
->rh_timer
,
1350 bus_state
->resume_done
[faked_port_index
]);
1351 /* Do the rest in GetPortStatus */
1356 /* Update event ring dequeue pointer before dropping the lock */
1357 inc_deq(xhci
, xhci
->event_ring
, true);
1359 /* Don't make the USB core poll the roothub if we got a bad port status
1360 * change event. Besides, at that point we can't tell which roothub
1361 * (USB 2.0 or USB 3.0) to kick.
1363 if (bogus_port_status
)
1366 spin_unlock(&xhci
->lock
);
1367 /* Pass this up to the core */
1368 usb_hcd_poll_rh_status(hcd
);
1369 spin_lock(&xhci
->lock
);
1373 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1374 * at end_trb, which may be in another segment. If the suspect DMA address is a
1375 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1378 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1379 union xhci_trb
*start_trb
,
1380 union xhci_trb
*end_trb
,
1381 dma_addr_t suspect_dma
)
1383 dma_addr_t start_dma
;
1384 dma_addr_t end_seg_dma
;
1385 dma_addr_t end_trb_dma
;
1386 struct xhci_segment
*cur_seg
;
1388 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1389 cur_seg
= start_seg
;
1394 /* We may get an event for a Link TRB in the middle of a TD */
1395 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1396 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1397 /* If the end TRB isn't in this segment, this is set to 0 */
1398 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1400 if (end_trb_dma
> 0) {
1401 /* The end TRB is in this segment, so suspect should be here */
1402 if (start_dma
<= end_trb_dma
) {
1403 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1406 /* Case for one segment with
1407 * a TD wrapped around to the top
1409 if ((suspect_dma
>= start_dma
&&
1410 suspect_dma
<= end_seg_dma
) ||
1411 (suspect_dma
>= cur_seg
->dma
&&
1412 suspect_dma
<= end_trb_dma
))
1417 /* Might still be somewhere in this segment */
1418 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1421 cur_seg
= cur_seg
->next
;
1422 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1423 } while (cur_seg
!= start_seg
);
1428 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1429 unsigned int slot_id
, unsigned int ep_index
,
1430 unsigned int stream_id
,
1431 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1433 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1434 ep
->ep_state
|= EP_HALTED
;
1435 ep
->stopped_td
= td
;
1436 ep
->stopped_trb
= event_trb
;
1437 ep
->stopped_stream
= stream_id
;
1439 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1440 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1442 ep
->stopped_td
= NULL
;
1443 ep
->stopped_trb
= NULL
;
1444 ep
->stopped_stream
= 0;
1446 xhci_ring_cmd_db(xhci
);
1449 /* Check if an error has halted the endpoint ring. The class driver will
1450 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1451 * However, a babble and other errors also halt the endpoint ring, and the class
1452 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1453 * Ring Dequeue Pointer command manually.
1455 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1456 struct xhci_ep_ctx
*ep_ctx
,
1457 unsigned int trb_comp_code
)
1459 /* TRB completion codes that may require a manual halt cleanup */
1460 if (trb_comp_code
== COMP_TX_ERR
||
1461 trb_comp_code
== COMP_BABBLE
||
1462 trb_comp_code
== COMP_SPLIT_ERR
)
1463 /* The 0.96 spec says a babbling control endpoint
1464 * is not halted. The 0.96 spec says it is. Some HW
1465 * claims to be 0.95 compliant, but it halts the control
1466 * endpoint anyway. Check if a babble halted the
1469 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1470 cpu_to_le32(EP_STATE_HALTED
))
1476 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1478 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1479 /* Vendor defined "informational" completion code,
1480 * treat as not-an-error.
1482 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1484 xhci_dbg(xhci
, "Treating code as success.\n");
1491 * Finish the td processing, remove the td from td list;
1492 * Return 1 if the urb can be given back.
1494 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1495 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1496 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1498 struct xhci_virt_device
*xdev
;
1499 struct xhci_ring
*ep_ring
;
1500 unsigned int slot_id
;
1502 struct urb
*urb
= NULL
;
1503 struct xhci_ep_ctx
*ep_ctx
;
1505 struct urb_priv
*urb_priv
;
1508 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1509 xdev
= xhci
->devs
[slot_id
];
1510 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1511 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1512 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1513 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1518 if (trb_comp_code
== COMP_STOP_INVAL
||
1519 trb_comp_code
== COMP_STOP
) {
1520 /* The Endpoint Stop Command completion will take care of any
1521 * stopped TDs. A stopped TD may be restarted, so don't update
1522 * the ring dequeue pointer or take this TD off any lists yet.
1524 ep
->stopped_td
= td
;
1525 ep
->stopped_trb
= event_trb
;
1528 if (trb_comp_code
== COMP_STALL
) {
1529 /* The transfer is completed from the driver's
1530 * perspective, but we need to issue a set dequeue
1531 * command for this stalled endpoint to move the dequeue
1532 * pointer past the TD. We can't do that here because
1533 * the halt condition must be cleared first. Let the
1534 * USB class driver clear the stall later.
1536 ep
->stopped_td
= td
;
1537 ep
->stopped_trb
= event_trb
;
1538 ep
->stopped_stream
= ep_ring
->stream_id
;
1539 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1540 ep_ctx
, trb_comp_code
)) {
1541 /* Other types of errors halt the endpoint, but the
1542 * class driver doesn't call usb_reset_endpoint() unless
1543 * the error is -EPIPE. Clear the halted status in the
1544 * xHCI hardware manually.
1546 xhci_cleanup_halted_endpoint(xhci
,
1547 slot_id
, ep_index
, ep_ring
->stream_id
,
1550 /* Update ring dequeue pointer */
1551 while (ep_ring
->dequeue
!= td
->last_trb
)
1552 inc_deq(xhci
, ep_ring
, false);
1553 inc_deq(xhci
, ep_ring
, false);
1557 /* Clean up the endpoint's TD list */
1559 urb_priv
= urb
->hcpriv
;
1561 /* Do one last check of the actual transfer length.
1562 * If the host controller said we transferred more data than
1563 * the buffer length, urb->actual_length will be a very big
1564 * number (since it's unsigned). Play it safe and say we didn't
1565 * transfer anything.
1567 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1568 xhci_warn(xhci
, "URB transfer length is wrong, "
1569 "xHC issue? req. len = %u, "
1571 urb
->transfer_buffer_length
,
1572 urb
->actual_length
);
1573 urb
->actual_length
= 0;
1574 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1575 *status
= -EREMOTEIO
;
1579 list_del_init(&td
->td_list
);
1580 /* Was this TD slated to be cancelled but completed anyway? */
1581 if (!list_empty(&td
->cancelled_td_list
))
1582 list_del_init(&td
->cancelled_td_list
);
1585 /* Giveback the urb when all the tds are completed */
1586 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1588 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1589 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1590 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
1592 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1593 usb_amd_quirk_pll_enable();
1603 * Process control tds, update urb status and actual_length.
1605 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1606 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1607 struct xhci_virt_ep
*ep
, int *status
)
1609 struct xhci_virt_device
*xdev
;
1610 struct xhci_ring
*ep_ring
;
1611 unsigned int slot_id
;
1613 struct xhci_ep_ctx
*ep_ctx
;
1616 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1617 xdev
= xhci
->devs
[slot_id
];
1618 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1619 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1620 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1621 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1623 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1624 switch (trb_comp_code
) {
1626 if (event_trb
== ep_ring
->dequeue
) {
1627 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1628 "without IOC set??\n");
1629 *status
= -ESHUTDOWN
;
1630 } else if (event_trb
!= td
->last_trb
) {
1631 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1632 "without IOC set??\n");
1633 *status
= -ESHUTDOWN
;
1639 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1640 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1641 *status
= -EREMOTEIO
;
1645 case COMP_STOP_INVAL
:
1647 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1649 if (!xhci_requires_manual_halt_cleanup(xhci
,
1650 ep_ctx
, trb_comp_code
))
1652 xhci_dbg(xhci
, "TRB error code %u, "
1653 "halted endpoint index = %u\n",
1654 trb_comp_code
, ep_index
);
1655 /* else fall through */
1657 /* Did we transfer part of the data (middle) phase? */
1658 if (event_trb
!= ep_ring
->dequeue
&&
1659 event_trb
!= td
->last_trb
)
1660 td
->urb
->actual_length
=
1661 td
->urb
->transfer_buffer_length
1662 - TRB_LEN(le32_to_cpu(event
->transfer_len
));
1664 td
->urb
->actual_length
= 0;
1666 xhci_cleanup_halted_endpoint(xhci
,
1667 slot_id
, ep_index
, 0, td
, event_trb
);
1668 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
1671 * Did we transfer any data, despite the errors that might have
1672 * happened? I.e. did we get past the setup stage?
1674 if (event_trb
!= ep_ring
->dequeue
) {
1675 /* The event was for the status stage */
1676 if (event_trb
== td
->last_trb
) {
1677 if (td
->urb
->actual_length
!= 0) {
1678 /* Don't overwrite a previously set error code
1680 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
1681 (td
->urb
->transfer_flags
1682 & URB_SHORT_NOT_OK
))
1683 /* Did we already see a short data
1685 *status
= -EREMOTEIO
;
1687 td
->urb
->actual_length
=
1688 td
->urb
->transfer_buffer_length
;
1691 /* Maybe the event was for the data stage? */
1692 td
->urb
->actual_length
=
1693 td
->urb
->transfer_buffer_length
-
1694 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1695 xhci_dbg(xhci
, "Waiting for status "
1701 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1705 * Process isochronous tds, update urb packet status and actual_length.
1707 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1708 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1709 struct xhci_virt_ep
*ep
, int *status
)
1711 struct xhci_ring
*ep_ring
;
1712 struct urb_priv
*urb_priv
;
1715 union xhci_trb
*cur_trb
;
1716 struct xhci_segment
*cur_seg
;
1717 struct usb_iso_packet_descriptor
*frame
;
1719 bool skip_td
= false;
1721 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1722 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1723 urb_priv
= td
->urb
->hcpriv
;
1724 idx
= urb_priv
->td_cnt
;
1725 frame
= &td
->urb
->iso_frame_desc
[idx
];
1727 /* handle completion code */
1728 switch (trb_comp_code
) {
1733 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
1737 frame
->status
= -ECOMM
;
1740 case COMP_BUFF_OVER
:
1742 frame
->status
= -EOVERFLOW
;
1747 frame
->status
= -EPROTO
;
1751 case COMP_STOP_INVAL
:
1758 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
1759 frame
->actual_length
= frame
->length
;
1760 td
->urb
->actual_length
+= frame
->length
;
1762 for (cur_trb
= ep_ring
->dequeue
,
1763 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
1764 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1765 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
1766 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
1767 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1769 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1770 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1772 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1773 frame
->actual_length
= len
;
1774 td
->urb
->actual_length
+= len
;
1778 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1781 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1782 struct xhci_transfer_event
*event
,
1783 struct xhci_virt_ep
*ep
, int *status
)
1785 struct xhci_ring
*ep_ring
;
1786 struct urb_priv
*urb_priv
;
1787 struct usb_iso_packet_descriptor
*frame
;
1790 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1791 urb_priv
= td
->urb
->hcpriv
;
1792 idx
= urb_priv
->td_cnt
;
1793 frame
= &td
->urb
->iso_frame_desc
[idx
];
1795 /* The transfer is partly done. */
1796 frame
->status
= -EXDEV
;
1798 /* calc actual length */
1799 frame
->actual_length
= 0;
1801 /* Update ring dequeue pointer */
1802 while (ep_ring
->dequeue
!= td
->last_trb
)
1803 inc_deq(xhci
, ep_ring
, false);
1804 inc_deq(xhci
, ep_ring
, false);
1806 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
1810 * Process bulk and interrupt tds, update urb status and actual_length.
1812 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1813 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1814 struct xhci_virt_ep
*ep
, int *status
)
1816 struct xhci_ring
*ep_ring
;
1817 union xhci_trb
*cur_trb
;
1818 struct xhci_segment
*cur_seg
;
1821 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1822 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1824 switch (trb_comp_code
) {
1826 /* Double check that the HW transferred everything. */
1827 if (event_trb
!= td
->last_trb
) {
1828 xhci_warn(xhci
, "WARN Successful completion "
1830 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1831 *status
= -EREMOTEIO
;
1839 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1840 *status
= -EREMOTEIO
;
1845 /* Others already handled above */
1848 if (trb_comp_code
== COMP_SHORT_TX
)
1849 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
1850 "%d bytes untransferred\n",
1851 td
->urb
->ep
->desc
.bEndpointAddress
,
1852 td
->urb
->transfer_buffer_length
,
1853 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1854 /* Fast path - was this the last TRB in the TD for this URB? */
1855 if (event_trb
== td
->last_trb
) {
1856 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
1857 td
->urb
->actual_length
=
1858 td
->urb
->transfer_buffer_length
-
1859 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1860 if (td
->urb
->transfer_buffer_length
<
1861 td
->urb
->actual_length
) {
1862 xhci_warn(xhci
, "HC gave bad length "
1863 "of %d bytes left\n",
1864 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1865 td
->urb
->actual_length
= 0;
1866 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1867 *status
= -EREMOTEIO
;
1871 /* Don't overwrite a previously set error code */
1872 if (*status
== -EINPROGRESS
) {
1873 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1874 *status
= -EREMOTEIO
;
1879 td
->urb
->actual_length
=
1880 td
->urb
->transfer_buffer_length
;
1881 /* Ignore a short packet completion if the
1882 * untransferred length was zero.
1884 if (*status
== -EREMOTEIO
)
1888 /* Slow path - walk the list, starting from the dequeue
1889 * pointer, to get the actual length transferred.
1891 td
->urb
->actual_length
= 0;
1892 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1893 cur_trb
!= event_trb
;
1894 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1895 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
1896 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
1897 td
->urb
->actual_length
+=
1898 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1900 /* If the ring didn't stop on a Link or No-op TRB, add
1901 * in the actual bytes transferred from the Normal TRB
1903 if (trb_comp_code
!= COMP_STOP_INVAL
)
1904 td
->urb
->actual_length
+=
1905 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1906 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1909 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1913 * If this function returns an error condition, it means it got a Transfer
1914 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1915 * At this point, the host controller is probably hosed and should be reset.
1917 static int handle_tx_event(struct xhci_hcd
*xhci
,
1918 struct xhci_transfer_event
*event
)
1920 struct xhci_virt_device
*xdev
;
1921 struct xhci_virt_ep
*ep
;
1922 struct xhci_ring
*ep_ring
;
1923 unsigned int slot_id
;
1925 struct xhci_td
*td
= NULL
;
1926 dma_addr_t event_dma
;
1927 struct xhci_segment
*event_seg
;
1928 union xhci_trb
*event_trb
;
1929 struct urb
*urb
= NULL
;
1930 int status
= -EINPROGRESS
;
1931 struct urb_priv
*urb_priv
;
1932 struct xhci_ep_ctx
*ep_ctx
;
1936 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1937 xdev
= xhci
->devs
[slot_id
];
1939 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
1943 /* Endpoint ID is 1 based, our index is zero based */
1944 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1945 ep
= &xdev
->eps
[ep_index
];
1946 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1947 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1949 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
1950 EP_STATE_DISABLED
) {
1951 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
1952 "or incorrect stream ring\n");
1956 event_dma
= le64_to_cpu(event
->buffer
);
1957 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1958 /* Look for common error cases */
1959 switch (trb_comp_code
) {
1960 /* Skip codes that require special handling depending on
1967 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
1969 case COMP_STOP_INVAL
:
1970 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1973 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1974 ep
->ep_state
|= EP_HALTED
;
1978 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1981 case COMP_SPLIT_ERR
:
1983 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1987 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1988 status
= -EOVERFLOW
;
1991 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1995 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
1997 case COMP_BUFF_OVER
:
1998 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2002 * When the Isoch ring is empty, the xHC will generate
2003 * a Ring Overrun Event for IN Isoch endpoint or Ring
2004 * Underrun Event for OUT Isoch endpoint.
2006 xhci_dbg(xhci
, "underrun event on endpoint\n");
2007 if (!list_empty(&ep_ring
->td_list
))
2008 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2009 "still with TDs queued?\n",
2010 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2014 xhci_dbg(xhci
, "overrun event on endpoint\n");
2015 if (!list_empty(&ep_ring
->td_list
))
2016 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2017 "still with TDs queued?\n",
2018 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2022 xhci_warn(xhci
, "WARN: detect an incompatible device");
2025 case COMP_MISSED_INT
:
2027 * When encounter missed service error, one or more isoc tds
2028 * may be missed by xHC.
2029 * Set skip flag of the ep_ring; Complete the missed tds as
2030 * short transfer when process the ep_ring next time.
2033 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2036 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2040 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2046 /* This TRB should be in the TD at the head of this ring's
2049 if (list_empty(&ep_ring
->td_list
)) {
2050 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d "
2051 "with no TDs queued?\n",
2052 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2054 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2055 (le32_to_cpu(event
->flags
) &
2056 TRB_TYPE_BITMASK
)>>10);
2057 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2060 xhci_dbg(xhci
, "td_list is empty while skip "
2061 "flag set. Clear skip flag.\n");
2067 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2069 /* Is this a TRB in the currently executing TD? */
2070 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2071 td
->last_trb
, event_dma
);
2074 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2075 * is not in the current TD pointed by ep_ring->dequeue because
2076 * that the hardware dequeue pointer still at the previous TRB
2077 * of the current TD. The previous TRB maybe a Link TD or the
2078 * last TRB of the previous TD. The command completion handle
2079 * will take care the rest.
2081 if (!event_seg
&& trb_comp_code
== COMP_STOP_INVAL
) {
2088 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2089 /* Some host controllers give a spurious
2090 * successful event after a short transfer.
2093 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2094 ep_ring
->last_td_was_short
) {
2095 ep_ring
->last_td_was_short
= false;
2099 /* HC is busted, give up! */
2101 "ERROR Transfer event TRB DMA ptr not "
2102 "part of current TD\n");
2106 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2109 if (trb_comp_code
== COMP_SHORT_TX
)
2110 ep_ring
->last_td_was_short
= true;
2112 ep_ring
->last_td_was_short
= false;
2115 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2119 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2120 sizeof(*event_trb
)];
2122 * No-op TRB should not trigger interrupts.
2123 * If event_trb is a no-op TRB, it means the
2124 * corresponding TD has been cancelled. Just ignore
2127 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2129 "event_trb is a no-op TRB. Skip it\n");
2133 /* Now update the urb's actual_length and give back to
2136 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2137 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2139 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2140 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2143 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2148 * Do not update event ring dequeue pointer if ep->skip is set.
2149 * Will roll back to continue process missed tds.
2151 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2152 inc_deq(xhci
, xhci
->event_ring
, true);
2157 urb_priv
= urb
->hcpriv
;
2158 /* Leave the TD around for the reset endpoint function
2159 * to use(but only if it's not a control endpoint,
2160 * since we already queued the Set TR dequeue pointer
2161 * command for stalled control endpoints).
2163 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2164 (trb_comp_code
!= COMP_STALL
&&
2165 trb_comp_code
!= COMP_BABBLE
))
2166 xhci_urb_free_priv(xhci
, urb_priv
);
2168 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2169 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2170 (urb
->transfer_flags
&
2171 URB_SHORT_NOT_OK
)) ||
2173 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2174 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2175 "expected = %x, status = %d\n",
2176 urb
, urb
->actual_length
,
2177 urb
->transfer_buffer_length
,
2179 spin_unlock(&xhci
->lock
);
2180 /* EHCI, UHCI, and OHCI always unconditionally set the
2181 * urb->status of an isochronous endpoint to 0.
2183 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2185 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2186 spin_lock(&xhci
->lock
);
2190 * If ep->skip is set, it means there are missed tds on the
2191 * endpoint ring need to take care of.
2192 * Process them as short transfer until reach the td pointed by
2195 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2201 * This function handles all OS-owned events on the event ring. It may drop
2202 * xhci->lock between event processing (e.g. to pass up port status changes).
2203 * Returns >0 for "possibly more events to process" (caller should call again),
2204 * otherwise 0 if done. In future, <0 returns should indicate error code.
2206 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2208 union xhci_trb
*event
;
2209 int update_ptrs
= 1;
2212 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2213 xhci
->error_bitmask
|= 1 << 1;
2217 event
= xhci
->event_ring
->dequeue
;
2218 /* Does the HC or OS own the TRB? */
2219 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2220 xhci
->event_ring
->cycle_state
) {
2221 xhci
->error_bitmask
|= 1 << 2;
2226 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2227 * speculative reads of the event's flags/data below.
2230 /* FIXME: Handle more event types. */
2231 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2232 case TRB_TYPE(TRB_COMPLETION
):
2233 handle_cmd_completion(xhci
, &event
->event_cmd
);
2235 case TRB_TYPE(TRB_PORT_STATUS
):
2236 handle_port_status(xhci
, event
);
2239 case TRB_TYPE(TRB_TRANSFER
):
2240 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2242 xhci
->error_bitmask
|= 1 << 9;
2247 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2249 handle_vendor_event(xhci
, event
);
2251 xhci
->error_bitmask
|= 1 << 3;
2253 /* Any of the above functions may drop and re-acquire the lock, so check
2254 * to make sure a watchdog timer didn't mark the host as non-responsive.
2256 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2257 xhci_dbg(xhci
, "xHCI host dying, returning from "
2258 "event handler.\n");
2263 /* Update SW event ring dequeue pointer */
2264 inc_deq(xhci
, xhci
->event_ring
, true);
2266 /* Are there more items on the event ring? Caller will call us again to
2273 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2274 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2275 * indicators of an event TRB error, but we check the status *first* to be safe.
2277 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2279 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2281 union xhci_trb
*trb
;
2283 union xhci_trb
*event_ring_deq
;
2286 spin_lock(&xhci
->lock
);
2287 trb
= xhci
->event_ring
->dequeue
;
2288 /* Check if the xHC generated the interrupt, or the irq is shared */
2289 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2290 if (status
== 0xffffffff)
2293 if (!(status
& STS_EINT
)) {
2294 spin_unlock(&xhci
->lock
);
2297 if (status
& STS_FATAL
) {
2298 xhci_warn(xhci
, "WARNING: Host System Error\n");
2301 spin_unlock(&xhci
->lock
);
2306 * Clear the op reg interrupt status first,
2307 * so we can receive interrupts from other MSI-X interrupters.
2308 * Write 1 to clear the interrupt status.
2311 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2312 /* FIXME when MSI-X is supported and there are multiple vectors */
2313 /* Clear the MSI-X event interrupt status */
2315 if (hcd
->irq
!= -1) {
2317 /* Acknowledge the PCI interrupt */
2318 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2320 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2323 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2324 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2325 "Shouldn't IRQs be disabled?\n");
2326 /* Clear the event handler busy flag (RW1C);
2327 * the event ring should be empty.
2329 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2330 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2331 &xhci
->ir_set
->erst_dequeue
);
2332 spin_unlock(&xhci
->lock
);
2337 event_ring_deq
= xhci
->event_ring
->dequeue
;
2338 /* FIXME this should be a delayed service routine
2339 * that clears the EHB.
2341 while (xhci_handle_event(xhci
) > 0) {}
2343 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2344 /* If necessary, update the HW's version of the event ring deq ptr. */
2345 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2346 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2347 xhci
->event_ring
->dequeue
);
2349 xhci_warn(xhci
, "WARN something wrong with SW event "
2350 "ring dequeue ptr.\n");
2351 /* Update HC event ring dequeue pointer */
2352 temp_64
&= ERST_PTR_MASK
;
2353 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2356 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2357 temp_64
|= ERST_EHB
;
2358 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2360 spin_unlock(&xhci
->lock
);
2365 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2368 struct xhci_hcd
*xhci
;
2370 xhci
= hcd_to_xhci(hcd
);
2371 set_bit(HCD_FLAG_SAW_IRQ
, &hcd
->flags
);
2372 if (xhci
->shared_hcd
)
2373 set_bit(HCD_FLAG_SAW_IRQ
, &xhci
->shared_hcd
->flags
);
2375 ret
= xhci_irq(hcd
);
2380 /**** Endpoint Ring Operations ****/
2383 * Generic function for queueing a TRB on a ring.
2384 * The caller must have checked to make sure there's room on the ring.
2386 * @more_trbs_coming: Will you enqueue more TRBs before calling
2387 * prepare_transfer()?
2389 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2390 bool consumer
, bool more_trbs_coming
,
2391 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2393 struct xhci_generic_trb
*trb
;
2395 trb
= &ring
->enqueue
->generic
;
2396 trb
->field
[0] = cpu_to_le32(field1
);
2397 trb
->field
[1] = cpu_to_le32(field2
);
2398 trb
->field
[2] = cpu_to_le32(field3
);
2399 trb
->field
[3] = cpu_to_le32(field4
);
2400 inc_enq(xhci
, ring
, consumer
, more_trbs_coming
);
2404 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2405 * FIXME allocate segments if the ring is full.
2407 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2408 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2410 /* Make sure the endpoint has been added to xHC schedule */
2412 case EP_STATE_DISABLED
:
2414 * USB core changed config/interfaces without notifying us,
2415 * or hardware is reporting the wrong state.
2417 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2419 case EP_STATE_ERROR
:
2420 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2421 /* FIXME event handling code for error needs to clear it */
2422 /* XXX not sure if this should be -ENOENT or not */
2424 case EP_STATE_HALTED
:
2425 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2426 case EP_STATE_STOPPED
:
2427 case EP_STATE_RUNNING
:
2430 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2432 * FIXME issue Configure Endpoint command to try to get the HC
2433 * back into a known state.
2437 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
2438 /* FIXME allocate more room */
2439 xhci_err(xhci
, "ERROR no room on ep ring\n");
2443 if (enqueue_is_link_trb(ep_ring
)) {
2444 struct xhci_ring
*ring
= ep_ring
;
2445 union xhci_trb
*next
;
2447 next
= ring
->enqueue
;
2449 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2450 /* If we're not dealing with 0.95 hardware,
2451 * clear the chain bit.
2453 if (!xhci_link_trb_quirk(xhci
))
2454 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2456 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2459 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2461 /* Toggle the cycle bit after the last ring segment. */
2462 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2463 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2464 if (!in_interrupt()) {
2465 xhci_dbg(xhci
, "queue_trb: Toggle cycle "
2466 "state for ring %p = %i\n",
2467 ring
, (unsigned int)ring
->cycle_state
);
2470 ring
->enq_seg
= ring
->enq_seg
->next
;
2471 ring
->enqueue
= ring
->enq_seg
->trbs
;
2472 next
= ring
->enqueue
;
2479 static int prepare_transfer(struct xhci_hcd
*xhci
,
2480 struct xhci_virt_device
*xdev
,
2481 unsigned int ep_index
,
2482 unsigned int stream_id
,
2483 unsigned int num_trbs
,
2485 unsigned int td_index
,
2489 struct urb_priv
*urb_priv
;
2491 struct xhci_ring
*ep_ring
;
2492 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2494 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2496 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2501 ret
= prepare_ring(xhci
, ep_ring
,
2502 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2503 num_trbs
, mem_flags
);
2507 urb_priv
= urb
->hcpriv
;
2508 td
= urb_priv
->td
[td_index
];
2510 INIT_LIST_HEAD(&td
->td_list
);
2511 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2513 if (td_index
== 0) {
2514 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2520 /* Add this TD to the tail of the endpoint ring's TD list */
2521 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2522 td
->start_seg
= ep_ring
->enq_seg
;
2523 td
->first_trb
= ep_ring
->enqueue
;
2525 urb_priv
->td
[td_index
] = td
;
2530 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
2532 int num_sgs
, num_trbs
, running_total
, temp
, i
;
2533 struct scatterlist
*sg
;
2536 num_sgs
= urb
->num_sgs
;
2537 temp
= urb
->transfer_buffer_length
;
2539 xhci_dbg(xhci
, "count sg list trbs: \n");
2541 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
2542 unsigned int previous_total_trbs
= num_trbs
;
2543 unsigned int len
= sg_dma_len(sg
);
2545 /* Scatter gather list entries may cross 64KB boundaries */
2546 running_total
= TRB_MAX_BUFF_SIZE
-
2547 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
2548 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2549 if (running_total
!= 0)
2552 /* How many more 64KB chunks to transfer, how many more TRBs? */
2553 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
2555 running_total
+= TRB_MAX_BUFF_SIZE
;
2557 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2558 i
, (unsigned long long)sg_dma_address(sg
),
2559 len
, len
, num_trbs
- previous_total_trbs
);
2561 len
= min_t(int, len
, temp
);
2566 xhci_dbg(xhci
, "\n");
2567 if (!in_interrupt())
2568 xhci_dbg(xhci
, "ep %#x - urb len = %d, sglist used, "
2570 urb
->ep
->desc
.bEndpointAddress
,
2571 urb
->transfer_buffer_length
,
2576 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
2579 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
2580 "TRBs, %d left\n", __func__
,
2581 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
2582 if (running_total
!= urb
->transfer_buffer_length
)
2583 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
2584 "queued %#x (%d), asked for %#x (%d)\n",
2586 urb
->ep
->desc
.bEndpointAddress
,
2587 running_total
, running_total
,
2588 urb
->transfer_buffer_length
,
2589 urb
->transfer_buffer_length
);
2592 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
2593 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
2594 struct xhci_generic_trb
*start_trb
)
2597 * Pass all the TRBs to the hardware at once and make sure this write
2602 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
2604 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
2605 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
2609 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2610 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2611 * (comprised of sg list entries) can take several service intervals to
2614 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2615 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2617 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
2618 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2622 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
2623 ep_interval
= urb
->interval
;
2624 /* Convert to microframes */
2625 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2626 urb
->dev
->speed
== USB_SPEED_FULL
)
2628 /* FIXME change this to a warning and a suggestion to use the new API
2629 * to set the polling interval (once the API is added).
2631 if (xhci_interval
!= ep_interval
) {
2632 if (printk_ratelimit())
2633 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
2634 " (%d microframe%s) than xHCI "
2635 "(%d microframe%s)\n",
2637 ep_interval
== 1 ? "" : "s",
2639 xhci_interval
== 1 ? "" : "s");
2640 urb
->interval
= xhci_interval
;
2641 /* Convert back to frames for LS/FS devices */
2642 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2643 urb
->dev
->speed
== USB_SPEED_FULL
)
2646 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
2650 * The TD size is the number of bytes remaining in the TD (including this TRB),
2651 * right shifted by 10.
2652 * It must fit in bits 21:17, so it can't be bigger than 31.
2654 static u32
xhci_td_remainder(unsigned int remainder
)
2656 u32 max
= (1 << (21 - 17 + 1)) - 1;
2658 if ((remainder
>> 10) >= max
)
2661 return (remainder
>> 10) << 17;
2665 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2666 * the TD (*not* including this TRB).
2668 * Total TD packet count = total_packet_count =
2669 * roundup(TD size in bytes / wMaxPacketSize)
2671 * Packets transferred up to and including this TRB = packets_transferred =
2672 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2674 * TD size = total_packet_count - packets_transferred
2676 * It must fit in bits 21:17, so it can't be bigger than 31.
2679 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
2680 unsigned int total_packet_count
, struct urb
*urb
)
2682 int packets_transferred
;
2684 /* One TRB with a zero-length data packet. */
2685 if (running_total
== 0 && trb_buff_len
== 0)
2688 /* All the TRB queueing functions don't count the current TRB in
2691 packets_transferred
= (running_total
+ trb_buff_len
) /
2692 usb_endpoint_maxp(&urb
->ep
->desc
);
2694 return xhci_td_remainder(total_packet_count
- packets_transferred
);
2697 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2698 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2700 struct xhci_ring
*ep_ring
;
2701 unsigned int num_trbs
;
2702 struct urb_priv
*urb_priv
;
2704 struct scatterlist
*sg
;
2706 int trb_buff_len
, this_sg_len
, running_total
;
2707 unsigned int total_packet_count
;
2710 bool more_trbs_coming
;
2712 struct xhci_generic_trb
*start_trb
;
2715 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2719 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
2720 num_sgs
= urb
->num_sgs
;
2721 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2722 usb_endpoint_maxp(&urb
->ep
->desc
));
2724 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2725 ep_index
, urb
->stream_id
,
2726 num_trbs
, urb
, 0, mem_flags
);
2727 if (trb_buff_len
< 0)
2728 return trb_buff_len
;
2730 urb_priv
= urb
->hcpriv
;
2731 td
= urb_priv
->td
[0];
2734 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2735 * until we've finished creating all the other TRBs. The ring's cycle
2736 * state may change as we enqueue the other TRBs, so save it too.
2738 start_trb
= &ep_ring
->enqueue
->generic
;
2739 start_cycle
= ep_ring
->cycle_state
;
2743 * How much data is in the first TRB?
2745 * There are three forces at work for TRB buffer pointers and lengths:
2746 * 1. We don't want to walk off the end of this sg-list entry buffer.
2747 * 2. The transfer length that the driver requested may be smaller than
2748 * the amount of memory allocated for this scatter-gather list.
2749 * 3. TRBs buffers can't cross 64KB boundaries.
2752 addr
= (u64
) sg_dma_address(sg
);
2753 this_sg_len
= sg_dma_len(sg
);
2754 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2755 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2756 if (trb_buff_len
> urb
->transfer_buffer_length
)
2757 trb_buff_len
= urb
->transfer_buffer_length
;
2758 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
2762 /* Queue the first TRB, even if it's zero-length */
2765 u32 length_field
= 0;
2768 /* Don't change the cycle bit of the first TRB until later */
2771 if (start_cycle
== 0)
2774 field
|= ep_ring
->cycle_state
;
2776 /* Chain all the TRBs together; clear the chain bit in the last
2777 * TRB to indicate it's the last TRB in the chain.
2782 /* FIXME - add check for ZERO_PACKET flag before this */
2783 td
->last_trb
= ep_ring
->enqueue
;
2787 /* Only set interrupt on short packet for IN endpoints */
2788 if (usb_urb_dir_in(urb
))
2791 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
2792 "64KB boundary at %#x, end dma = %#x\n",
2793 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
2794 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2795 (unsigned int) addr
+ trb_buff_len
);
2796 if (TRB_MAX_BUFF_SIZE
-
2797 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
2798 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2799 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
2800 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2801 (unsigned int) addr
+ trb_buff_len
);
2804 /* Set the TRB length, TD size, and interrupter fields. */
2805 if (xhci
->hci_version
< 0x100) {
2806 remainder
= xhci_td_remainder(
2807 urb
->transfer_buffer_length
-
2810 remainder
= xhci_v1_0_td_remainder(running_total
,
2811 trb_buff_len
, total_packet_count
, urb
);
2813 length_field
= TRB_LEN(trb_buff_len
) |
2818 more_trbs_coming
= true;
2820 more_trbs_coming
= false;
2821 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
2822 lower_32_bits(addr
),
2823 upper_32_bits(addr
),
2825 field
| TRB_TYPE(TRB_NORMAL
));
2827 running_total
+= trb_buff_len
;
2829 /* Calculate length for next transfer --
2830 * Are we done queueing all the TRBs for this sg entry?
2832 this_sg_len
-= trb_buff_len
;
2833 if (this_sg_len
== 0) {
2838 addr
= (u64
) sg_dma_address(sg
);
2839 this_sg_len
= sg_dma_len(sg
);
2841 addr
+= trb_buff_len
;
2844 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2845 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2846 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2847 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
2849 urb
->transfer_buffer_length
- running_total
;
2850 } while (running_total
< urb
->transfer_buffer_length
);
2852 check_trb_math(urb
, num_trbs
, running_total
);
2853 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2854 start_cycle
, start_trb
);
2858 /* This is very similar to what ehci-q.c qtd_fill() does */
2859 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2860 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2862 struct xhci_ring
*ep_ring
;
2863 struct urb_priv
*urb_priv
;
2866 struct xhci_generic_trb
*start_trb
;
2868 bool more_trbs_coming
;
2870 u32 field
, length_field
;
2872 int running_total
, trb_buff_len
, ret
;
2873 unsigned int total_packet_count
;
2877 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2879 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2884 /* How much data is (potentially) left before the 64KB boundary? */
2885 running_total
= TRB_MAX_BUFF_SIZE
-
2886 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2887 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2889 /* If there's some data on this 64KB chunk, or we have to send a
2890 * zero-length transfer, we need at least one TRB
2892 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
2894 /* How many more 64KB chunks to transfer, how many more TRBs? */
2895 while (running_total
< urb
->transfer_buffer_length
) {
2897 running_total
+= TRB_MAX_BUFF_SIZE
;
2899 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2901 if (!in_interrupt())
2902 xhci_dbg(xhci
, "ep %#x - urb len = %#x (%d), "
2903 "addr = %#llx, num_trbs = %d\n",
2904 urb
->ep
->desc
.bEndpointAddress
,
2905 urb
->transfer_buffer_length
,
2906 urb
->transfer_buffer_length
,
2907 (unsigned long long)urb
->transfer_dma
,
2910 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2911 ep_index
, urb
->stream_id
,
2912 num_trbs
, urb
, 0, mem_flags
);
2916 urb_priv
= urb
->hcpriv
;
2917 td
= urb_priv
->td
[0];
2920 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2921 * until we've finished creating all the other TRBs. The ring's cycle
2922 * state may change as we enqueue the other TRBs, so save it too.
2924 start_trb
= &ep_ring
->enqueue
->generic
;
2925 start_cycle
= ep_ring
->cycle_state
;
2928 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2929 usb_endpoint_maxp(&urb
->ep
->desc
));
2930 /* How much data is in the first TRB? */
2931 addr
= (u64
) urb
->transfer_dma
;
2932 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2933 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2934 if (trb_buff_len
> urb
->transfer_buffer_length
)
2935 trb_buff_len
= urb
->transfer_buffer_length
;
2939 /* Queue the first TRB, even if it's zero-length */
2944 /* Don't change the cycle bit of the first TRB until later */
2947 if (start_cycle
== 0)
2950 field
|= ep_ring
->cycle_state
;
2952 /* Chain all the TRBs together; clear the chain bit in the last
2953 * TRB to indicate it's the last TRB in the chain.
2958 /* FIXME - add check for ZERO_PACKET flag before this */
2959 td
->last_trb
= ep_ring
->enqueue
;
2963 /* Only set interrupt on short packet for IN endpoints */
2964 if (usb_urb_dir_in(urb
))
2967 /* Set the TRB length, TD size, and interrupter fields. */
2968 if (xhci
->hci_version
< 0x100) {
2969 remainder
= xhci_td_remainder(
2970 urb
->transfer_buffer_length
-
2973 remainder
= xhci_v1_0_td_remainder(running_total
,
2974 trb_buff_len
, total_packet_count
, urb
);
2976 length_field
= TRB_LEN(trb_buff_len
) |
2981 more_trbs_coming
= true;
2983 more_trbs_coming
= false;
2984 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
2985 lower_32_bits(addr
),
2986 upper_32_bits(addr
),
2988 field
| TRB_TYPE(TRB_NORMAL
));
2990 running_total
+= trb_buff_len
;
2992 /* Calculate length for next transfer */
2993 addr
+= trb_buff_len
;
2994 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
2995 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
2996 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
2997 } while (running_total
< urb
->transfer_buffer_length
);
2999 check_trb_math(urb
, num_trbs
, running_total
);
3000 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3001 start_cycle
, start_trb
);
3005 /* Caller must have locked xhci->lock */
3006 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3007 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3009 struct xhci_ring
*ep_ring
;
3012 struct usb_ctrlrequest
*setup
;
3013 struct xhci_generic_trb
*start_trb
;
3015 u32 field
, length_field
;
3016 struct urb_priv
*urb_priv
;
3019 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3024 * Need to copy setup packet into setup TRB, so we can't use the setup
3027 if (!urb
->setup_packet
)
3030 if (!in_interrupt())
3031 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
3033 /* 1 TRB for setup, 1 for status */
3036 * Don't need to check if we need additional event data and normal TRBs,
3037 * since data in control transfers will never get bigger than 16MB
3038 * XXX: can we get a buffer that crosses 64KB boundaries?
3040 if (urb
->transfer_buffer_length
> 0)
3042 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3043 ep_index
, urb
->stream_id
,
3044 num_trbs
, urb
, 0, mem_flags
);
3048 urb_priv
= urb
->hcpriv
;
3049 td
= urb_priv
->td
[0];
3052 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3053 * until we've finished creating all the other TRBs. The ring's cycle
3054 * state may change as we enqueue the other TRBs, so save it too.
3056 start_trb
= &ep_ring
->enqueue
->generic
;
3057 start_cycle
= ep_ring
->cycle_state
;
3059 /* Queue setup TRB - see section 6.4.1.2.1 */
3060 /* FIXME better way to translate setup_packet into two u32 fields? */
3061 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3063 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3064 if (start_cycle
== 0)
3067 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3068 if (xhci
->hci_version
== 0x100) {
3069 if (urb
->transfer_buffer_length
> 0) {
3070 if (setup
->bRequestType
& USB_DIR_IN
)
3071 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3073 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3077 queue_trb(xhci
, ep_ring
, false, true,
3078 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3079 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3080 TRB_LEN(8) | TRB_INTR_TARGET(0),
3081 /* Immediate data in pointer */
3084 /* If there's data, queue data TRBs */
3085 /* Only set interrupt on short packet for IN endpoints */
3086 if (usb_urb_dir_in(urb
))
3087 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3089 field
= TRB_TYPE(TRB_DATA
);
3091 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3092 xhci_td_remainder(urb
->transfer_buffer_length
) |
3094 if (urb
->transfer_buffer_length
> 0) {
3095 if (setup
->bRequestType
& USB_DIR_IN
)
3096 field
|= TRB_DIR_IN
;
3097 queue_trb(xhci
, ep_ring
, false, true,
3098 lower_32_bits(urb
->transfer_dma
),
3099 upper_32_bits(urb
->transfer_dma
),
3101 field
| ep_ring
->cycle_state
);
3104 /* Save the DMA address of the last TRB in the TD */
3105 td
->last_trb
= ep_ring
->enqueue
;
3107 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3108 /* If the device sent data, the status stage is an OUT transfer */
3109 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3113 queue_trb(xhci
, ep_ring
, false, false,
3117 /* Event on completion */
3118 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3120 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3121 start_cycle
, start_trb
);
3125 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3126 struct urb
*urb
, int i
)
3131 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3132 td_len
= urb
->iso_frame_desc
[i
].length
;
3134 num_trbs
= DIV_ROUND_UP(td_len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3143 * The transfer burst count field of the isochronous TRB defines the number of
3144 * bursts that are required to move all packets in this TD. Only SuperSpeed
3145 * devices can burst up to bMaxBurst number of packets per service interval.
3146 * This field is zero based, meaning a value of zero in the field means one
3147 * burst. Basically, for everything but SuperSpeed devices, this field will be
3148 * zero. Only xHCI 1.0 host controllers support this field.
3150 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3151 struct usb_device
*udev
,
3152 struct urb
*urb
, unsigned int total_packet_count
)
3154 unsigned int max_burst
;
3156 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3159 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3160 return roundup(total_packet_count
, max_burst
+ 1) - 1;
3164 * Returns the number of packets in the last "burst" of packets. This field is
3165 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3166 * the last burst packet count is equal to the total number of packets in the
3167 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3168 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3169 * contain 1 to (bMaxBurst + 1) packets.
3171 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3172 struct usb_device
*udev
,
3173 struct urb
*urb
, unsigned int total_packet_count
)
3175 unsigned int max_burst
;
3176 unsigned int residue
;
3178 if (xhci
->hci_version
< 0x100)
3181 switch (udev
->speed
) {
3182 case USB_SPEED_SUPER
:
3183 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3184 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3185 residue
= total_packet_count
% (max_burst
+ 1);
3186 /* If residue is zero, the last burst contains (max_burst + 1)
3187 * number of packets, but the TLBPC field is zero-based.
3193 if (total_packet_count
== 0)
3195 return total_packet_count
- 1;
3199 /* This is for isoc transfer */
3200 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3201 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3203 struct xhci_ring
*ep_ring
;
3204 struct urb_priv
*urb_priv
;
3206 int num_tds
, trbs_per_td
;
3207 struct xhci_generic_trb
*start_trb
;
3210 u32 field
, length_field
;
3211 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3212 u64 start_addr
, addr
;
3214 bool more_trbs_coming
;
3216 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3218 num_tds
= urb
->number_of_packets
;
3220 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3224 if (!in_interrupt())
3225 xhci_dbg(xhci
, "ep %#x - urb len = %#x (%d),"
3226 " addr = %#llx, num_tds = %d\n",
3227 urb
->ep
->desc
.bEndpointAddress
,
3228 urb
->transfer_buffer_length
,
3229 urb
->transfer_buffer_length
,
3230 (unsigned long long)urb
->transfer_dma
,
3233 start_addr
= (u64
) urb
->transfer_dma
;
3234 start_trb
= &ep_ring
->enqueue
->generic
;
3235 start_cycle
= ep_ring
->cycle_state
;
3237 urb_priv
= urb
->hcpriv
;
3238 /* Queue the first TRB, even if it's zero-length */
3239 for (i
= 0; i
< num_tds
; i
++) {
3240 unsigned int total_packet_count
;
3241 unsigned int burst_count
;
3242 unsigned int residue
;
3246 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3247 td_len
= urb
->iso_frame_desc
[i
].length
;
3248 td_remain_len
= td_len
;
3249 total_packet_count
= roundup(td_len
,
3250 usb_endpoint_maxp(&urb
->ep
->desc
));
3251 /* A zero-length transfer still involves at least one packet. */
3252 if (total_packet_count
== 0)
3253 total_packet_count
++;
3254 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3255 total_packet_count
);
3256 residue
= xhci_get_last_burst_packet_count(xhci
,
3257 urb
->dev
, urb
, total_packet_count
);
3259 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3261 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3262 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3269 td
= urb_priv
->td
[i
];
3270 for (j
= 0; j
< trbs_per_td
; j
++) {
3272 field
= TRB_TBC(burst_count
) | TRB_TLBPC(residue
);
3275 /* Queue the isoc TRB */
3276 field
|= TRB_TYPE(TRB_ISOC
);
3277 /* Assume URB_ISO_ASAP is set */
3280 if (start_cycle
== 0)
3283 field
|= ep_ring
->cycle_state
;
3286 /* Queue other normal TRBs */
3287 field
|= TRB_TYPE(TRB_NORMAL
);
3288 field
|= ep_ring
->cycle_state
;
3291 /* Only set interrupt on short packet for IN EPs */
3292 if (usb_urb_dir_in(urb
))
3295 /* Chain all the TRBs together; clear the chain bit in
3296 * the last TRB to indicate it's the last TRB in the
3299 if (j
< trbs_per_td
- 1) {
3301 more_trbs_coming
= true;
3303 td
->last_trb
= ep_ring
->enqueue
;
3305 if (xhci
->hci_version
== 0x100) {
3306 /* Set BEI bit except for the last td */
3307 if (i
< num_tds
- 1)
3310 more_trbs_coming
= false;
3313 /* Calculate TRB length */
3314 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3315 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3316 if (trb_buff_len
> td_remain_len
)
3317 trb_buff_len
= td_remain_len
;
3319 /* Set the TRB length, TD size, & interrupter fields. */
3320 if (xhci
->hci_version
< 0x100) {
3321 remainder
= xhci_td_remainder(
3322 td_len
- running_total
);
3324 remainder
= xhci_v1_0_td_remainder(
3325 running_total
, trb_buff_len
,
3326 total_packet_count
, urb
);
3328 length_field
= TRB_LEN(trb_buff_len
) |
3332 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
3333 lower_32_bits(addr
),
3334 upper_32_bits(addr
),
3337 running_total
+= trb_buff_len
;
3339 addr
+= trb_buff_len
;
3340 td_remain_len
-= trb_buff_len
;
3343 /* Check TD length */
3344 if (running_total
!= td_len
) {
3345 xhci_err(xhci
, "ISOC TD length unmatch\n");
3350 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3351 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3352 usb_amd_quirk_pll_disable();
3354 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3356 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3357 start_cycle
, start_trb
);
3360 /* Clean up a partially enqueued isoc transfer. */
3362 for (i
--; i
>= 0; i
--)
3363 list_del_init(&urb_priv
->td
[i
]->td_list
);
3365 /* Use the first TD as a temporary variable to turn the TDs we've queued
3366 * into No-ops with a software-owned cycle bit. That way the hardware
3367 * won't accidentally start executing bogus TDs when we partially
3368 * overwrite them. td->first_trb and td->start_seg are already set.
3370 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3371 /* Every TRB except the first & last will have its cycle bit flipped. */
3372 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3374 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3375 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3376 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3377 ep_ring
->cycle_state
= start_cycle
;
3378 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3383 * Check transfer ring to guarantee there is enough room for the urb.
3384 * Update ISO URB start_frame and interval.
3385 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3386 * update the urb->start_frame by now.
3387 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3389 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3390 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3392 struct xhci_virt_device
*xdev
;
3393 struct xhci_ring
*ep_ring
;
3394 struct xhci_ep_ctx
*ep_ctx
;
3398 int num_tds
, num_trbs
, i
;
3401 xdev
= xhci
->devs
[slot_id
];
3402 ep_ring
= xdev
->eps
[ep_index
].ring
;
3403 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3406 num_tds
= urb
->number_of_packets
;
3407 for (i
= 0; i
< num_tds
; i
++)
3408 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3410 /* Check the ring to guarantee there is enough room for the whole urb.
3411 * Do not insert any td of the urb to the ring if the check failed.
3413 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3414 num_trbs
, mem_flags
);
3418 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3419 start_frame
&= 0x3fff;
3421 urb
->start_frame
= start_frame
;
3422 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3423 urb
->dev
->speed
== USB_SPEED_FULL
)
3424 urb
->start_frame
>>= 3;
3426 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3427 ep_interval
= urb
->interval
;
3428 /* Convert to microframes */
3429 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3430 urb
->dev
->speed
== USB_SPEED_FULL
)
3432 /* FIXME change this to a warning and a suggestion to use the new API
3433 * to set the polling interval (once the API is added).
3435 if (xhci_interval
!= ep_interval
) {
3436 if (printk_ratelimit())
3437 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3438 " (%d microframe%s) than xHCI "
3439 "(%d microframe%s)\n",
3441 ep_interval
== 1 ? "" : "s",
3443 xhci_interval
== 1 ? "" : "s");
3444 urb
->interval
= xhci_interval
;
3445 /* Convert back to frames for LS/FS devices */
3446 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3447 urb
->dev
->speed
== USB_SPEED_FULL
)
3450 return xhci_queue_isoc_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
3453 /**** Command Ring Operations ****/
3455 /* Generic function for queueing a command TRB on the command ring.
3456 * Check to make sure there's room on the command ring for one command TRB.
3457 * Also check that there's room reserved for commands that must not fail.
3458 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3459 * then only check for the number of reserved spots.
3460 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3461 * because the command event handler may want to resubmit a failed command.
3463 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3464 u32 field3
, u32 field4
, bool command_must_succeed
)
3466 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3469 if (!command_must_succeed
)
3472 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3473 reserved_trbs
, GFP_ATOMIC
);
3475 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3476 if (command_must_succeed
)
3477 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3478 "unfailable commands failed.\n");
3481 queue_trb(xhci
, xhci
->cmd_ring
, false, false, field1
, field2
, field3
,
3482 field4
| xhci
->cmd_ring
->cycle_state
);
3486 /* Queue a slot enable or disable request on the command ring */
3487 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3489 return queue_command(xhci
, 0, 0, 0,
3490 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3493 /* Queue an address device command TRB */
3494 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3497 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3498 upper_32_bits(in_ctx_ptr
), 0,
3499 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3503 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3504 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3506 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3509 /* Queue a reset device command TRB */
3510 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3512 return queue_command(xhci
, 0, 0, 0,
3513 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3517 /* Queue a configure endpoint command TRB */
3518 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3519 u32 slot_id
, bool command_must_succeed
)
3521 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3522 upper_32_bits(in_ctx_ptr
), 0,
3523 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3524 command_must_succeed
);
3527 /* Queue an evaluate context command TRB */
3528 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3531 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3532 upper_32_bits(in_ctx_ptr
), 0,
3533 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3538 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3539 * activity on an endpoint that is about to be suspended.
3541 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
3542 unsigned int ep_index
, int suspend
)
3544 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3545 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3546 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3547 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3549 return queue_command(xhci
, 0, 0, 0,
3550 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3553 /* Set Transfer Ring Dequeue Pointer command.
3554 * This should not be used for endpoints that have streams enabled.
3556 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
3557 unsigned int ep_index
, unsigned int stream_id
,
3558 struct xhci_segment
*deq_seg
,
3559 union xhci_trb
*deq_ptr
, u32 cycle_state
)
3562 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3563 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3564 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
3565 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
3566 struct xhci_virt_ep
*ep
;
3568 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
3570 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3571 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
3575 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3576 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
3577 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3578 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
3581 ep
->queued_deq_seg
= deq_seg
;
3582 ep
->queued_deq_ptr
= deq_ptr
;
3583 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
3584 upper_32_bits(addr
), trb_stream_id
,
3585 trb_slot_id
| trb_ep_index
| type
, false);
3588 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
3589 unsigned int ep_index
)
3591 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3592 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3593 u32 type
= TRB_TYPE(TRB_RESET_EP
);
3595 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,