Merge branch 'for-linville' of git://github.com/kvalo/ath6kl
[deliverable/linux.git] / drivers / usb / host / xhci.c
1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30
31 #include "xhci.h"
32
33 #define DRIVER_AUTHOR "Sarah Sharp"
34 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
35
36 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
37 static int link_quirk;
38 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
39 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
40
41 /* TODO: copied from ehci-hcd.c - can this be refactored? */
42 /*
43 * xhci_handshake - spin reading hc until handshake completes or fails
44 * @ptr: address of hc register to be read
45 * @mask: bits to look at in result of read
46 * @done: value of those bits when handshake succeeds
47 * @usec: timeout in microseconds
48 *
49 * Returns negative errno, or zero on success
50 *
51 * Success happens when the "mask" bits have the specified value (hardware
52 * handshake done). There are two failure modes: "usec" have passed (major
53 * hardware flakeout), or the register reads as all-ones (hardware removed).
54 */
55 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
56 u32 mask, u32 done, int usec)
57 {
58 u32 result;
59
60 do {
61 result = xhci_readl(xhci, ptr);
62 if (result == ~(u32)0) /* card removed */
63 return -ENODEV;
64 result &= mask;
65 if (result == done)
66 return 0;
67 udelay(1);
68 usec--;
69 } while (usec > 0);
70 return -ETIMEDOUT;
71 }
72
73 /*
74 * Disable interrupts and begin the xHCI halting process.
75 */
76 void xhci_quiesce(struct xhci_hcd *xhci)
77 {
78 u32 halted;
79 u32 cmd;
80 u32 mask;
81
82 mask = ~(XHCI_IRQS);
83 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
84 if (!halted)
85 mask &= ~CMD_RUN;
86
87 cmd = xhci_readl(xhci, &xhci->op_regs->command);
88 cmd &= mask;
89 xhci_writel(xhci, cmd, &xhci->op_regs->command);
90 }
91
92 /*
93 * Force HC into halt state.
94 *
95 * Disable any IRQs and clear the run/stop bit.
96 * HC will complete any current and actively pipelined transactions, and
97 * should halt within 16 ms of the run/stop bit being cleared.
98 * Read HC Halted bit in the status register to see when the HC is finished.
99 */
100 int xhci_halt(struct xhci_hcd *xhci)
101 {
102 int ret;
103 xhci_dbg(xhci, "// Halt the HC\n");
104 xhci_quiesce(xhci);
105
106 ret = xhci_handshake(xhci, &xhci->op_regs->status,
107 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
108 if (!ret) {
109 xhci->xhc_state |= XHCI_STATE_HALTED;
110 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
111 } else
112 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
113 XHCI_MAX_HALT_USEC);
114 return ret;
115 }
116
117 /*
118 * Set the run bit and wait for the host to be running.
119 */
120 static int xhci_start(struct xhci_hcd *xhci)
121 {
122 u32 temp;
123 int ret;
124
125 temp = xhci_readl(xhci, &xhci->op_regs->command);
126 temp |= (CMD_RUN);
127 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
128 temp);
129 xhci_writel(xhci, temp, &xhci->op_regs->command);
130
131 /*
132 * Wait for the HCHalted Status bit to be 0 to indicate the host is
133 * running.
134 */
135 ret = xhci_handshake(xhci, &xhci->op_regs->status,
136 STS_HALT, 0, XHCI_MAX_HALT_USEC);
137 if (ret == -ETIMEDOUT)
138 xhci_err(xhci, "Host took too long to start, "
139 "waited %u microseconds.\n",
140 XHCI_MAX_HALT_USEC);
141 if (!ret)
142 xhci->xhc_state &= ~XHCI_STATE_HALTED;
143 return ret;
144 }
145
146 /*
147 * Reset a halted HC.
148 *
149 * This resets pipelines, timers, counters, state machines, etc.
150 * Transactions will be terminated immediately, and operational registers
151 * will be set to their defaults.
152 */
153 int xhci_reset(struct xhci_hcd *xhci)
154 {
155 u32 command;
156 u32 state;
157 int ret, i;
158
159 state = xhci_readl(xhci, &xhci->op_regs->status);
160 if ((state & STS_HALT) == 0) {
161 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
162 return 0;
163 }
164
165 xhci_dbg(xhci, "// Reset the HC\n");
166 command = xhci_readl(xhci, &xhci->op_regs->command);
167 command |= CMD_RESET;
168 xhci_writel(xhci, command, &xhci->op_regs->command);
169
170 ret = xhci_handshake(xhci, &xhci->op_regs->command,
171 CMD_RESET, 0, 10 * 1000 * 1000);
172 if (ret)
173 return ret;
174
175 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
176 /*
177 * xHCI cannot write to any doorbells or operational registers other
178 * than status until the "Controller Not Ready" flag is cleared.
179 */
180 ret = xhci_handshake(xhci, &xhci->op_regs->status,
181 STS_CNR, 0, 10 * 1000 * 1000);
182
183 for (i = 0; i < 2; ++i) {
184 xhci->bus_state[i].port_c_suspend = 0;
185 xhci->bus_state[i].suspended_ports = 0;
186 xhci->bus_state[i].resuming_ports = 0;
187 }
188
189 return ret;
190 }
191
192 #ifdef CONFIG_PCI
193 static int xhci_free_msi(struct xhci_hcd *xhci)
194 {
195 int i;
196
197 if (!xhci->msix_entries)
198 return -EINVAL;
199
200 for (i = 0; i < xhci->msix_count; i++)
201 if (xhci->msix_entries[i].vector)
202 free_irq(xhci->msix_entries[i].vector,
203 xhci_to_hcd(xhci));
204 return 0;
205 }
206
207 /*
208 * Set up MSI
209 */
210 static int xhci_setup_msi(struct xhci_hcd *xhci)
211 {
212 int ret;
213 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
214
215 ret = pci_enable_msi(pdev);
216 if (ret) {
217 xhci_dbg(xhci, "failed to allocate MSI entry\n");
218 return ret;
219 }
220
221 ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
222 0, "xhci_hcd", xhci_to_hcd(xhci));
223 if (ret) {
224 xhci_dbg(xhci, "disable MSI interrupt\n");
225 pci_disable_msi(pdev);
226 }
227
228 return ret;
229 }
230
231 /*
232 * Free IRQs
233 * free all IRQs request
234 */
235 static void xhci_free_irq(struct xhci_hcd *xhci)
236 {
237 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
238 int ret;
239
240 /* return if using legacy interrupt */
241 if (xhci_to_hcd(xhci)->irq > 0)
242 return;
243
244 ret = xhci_free_msi(xhci);
245 if (!ret)
246 return;
247 if (pdev->irq > 0)
248 free_irq(pdev->irq, xhci_to_hcd(xhci));
249
250 return;
251 }
252
253 /*
254 * Set up MSI-X
255 */
256 static int xhci_setup_msix(struct xhci_hcd *xhci)
257 {
258 int i, ret = 0;
259 struct usb_hcd *hcd = xhci_to_hcd(xhci);
260 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
261
262 /*
263 * calculate number of msi-x vectors supported.
264 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
265 * with max number of interrupters based on the xhci HCSPARAMS1.
266 * - num_online_cpus: maximum msi-x vectors per CPUs core.
267 * Add additional 1 vector to ensure always available interrupt.
268 */
269 xhci->msix_count = min(num_online_cpus() + 1,
270 HCS_MAX_INTRS(xhci->hcs_params1));
271
272 xhci->msix_entries =
273 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
274 GFP_KERNEL);
275 if (!xhci->msix_entries) {
276 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
277 return -ENOMEM;
278 }
279
280 for (i = 0; i < xhci->msix_count; i++) {
281 xhci->msix_entries[i].entry = i;
282 xhci->msix_entries[i].vector = 0;
283 }
284
285 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
286 if (ret) {
287 xhci_dbg(xhci, "Failed to enable MSI-X\n");
288 goto free_entries;
289 }
290
291 for (i = 0; i < xhci->msix_count; i++) {
292 ret = request_irq(xhci->msix_entries[i].vector,
293 (irq_handler_t)xhci_msi_irq,
294 0, "xhci_hcd", xhci_to_hcd(xhci));
295 if (ret)
296 goto disable_msix;
297 }
298
299 hcd->msix_enabled = 1;
300 return ret;
301
302 disable_msix:
303 xhci_dbg(xhci, "disable MSI-X interrupt\n");
304 xhci_free_irq(xhci);
305 pci_disable_msix(pdev);
306 free_entries:
307 kfree(xhci->msix_entries);
308 xhci->msix_entries = NULL;
309 return ret;
310 }
311
312 /* Free any IRQs and disable MSI-X */
313 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
314 {
315 struct usb_hcd *hcd = xhci_to_hcd(xhci);
316 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
317
318 xhci_free_irq(xhci);
319
320 if (xhci->msix_entries) {
321 pci_disable_msix(pdev);
322 kfree(xhci->msix_entries);
323 xhci->msix_entries = NULL;
324 } else {
325 pci_disable_msi(pdev);
326 }
327
328 hcd->msix_enabled = 0;
329 return;
330 }
331
332 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
333 {
334 int i;
335
336 if (xhci->msix_entries) {
337 for (i = 0; i < xhci->msix_count; i++)
338 synchronize_irq(xhci->msix_entries[i].vector);
339 }
340 }
341
342 static int xhci_try_enable_msi(struct usb_hcd *hcd)
343 {
344 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
345 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
346 int ret;
347
348 /*
349 * Some Fresco Logic host controllers advertise MSI, but fail to
350 * generate interrupts. Don't even try to enable MSI.
351 */
352 if (xhci->quirks & XHCI_BROKEN_MSI)
353 return 0;
354
355 /* unregister the legacy interrupt */
356 if (hcd->irq)
357 free_irq(hcd->irq, hcd);
358 hcd->irq = 0;
359
360 ret = xhci_setup_msix(xhci);
361 if (ret)
362 /* fall back to msi*/
363 ret = xhci_setup_msi(xhci);
364
365 if (!ret)
366 /* hcd->irq is 0, we have MSI */
367 return 0;
368
369 if (!pdev->irq) {
370 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
371 return -EINVAL;
372 }
373
374 /* fall back to legacy interrupt*/
375 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
376 hcd->irq_descr, hcd);
377 if (ret) {
378 xhci_err(xhci, "request interrupt %d failed\n",
379 pdev->irq);
380 return ret;
381 }
382 hcd->irq = pdev->irq;
383 return 0;
384 }
385
386 #else
387
388 static int xhci_try_enable_msi(struct usb_hcd *hcd)
389 {
390 return 0;
391 }
392
393 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
394 {
395 }
396
397 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
398 {
399 }
400
401 #endif
402
403 static void compliance_mode_recovery(unsigned long arg)
404 {
405 struct xhci_hcd *xhci;
406 struct usb_hcd *hcd;
407 u32 temp;
408 int i;
409
410 xhci = (struct xhci_hcd *)arg;
411
412 for (i = 0; i < xhci->num_usb3_ports; i++) {
413 temp = xhci_readl(xhci, xhci->usb3_ports[i]);
414 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
415 /*
416 * Compliance Mode Detected. Letting USB Core
417 * handle the Warm Reset
418 */
419 xhci_dbg(xhci, "Compliance Mode Detected->Port %d!\n",
420 i + 1);
421 xhci_dbg(xhci, "Attempting Recovery routine!\n");
422 hcd = xhci->shared_hcd;
423
424 if (hcd->state == HC_STATE_SUSPENDED)
425 usb_hcd_resume_root_hub(hcd);
426
427 usb_hcd_poll_rh_status(hcd);
428 }
429 }
430
431 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
432 mod_timer(&xhci->comp_mode_recovery_timer,
433 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
434 }
435
436 /*
437 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
438 * that causes ports behind that hardware to enter compliance mode sometimes.
439 * The quirk creates a timer that polls every 2 seconds the link state of
440 * each host controller's port and recovers it by issuing a Warm reset
441 * if Compliance mode is detected, otherwise the port will become "dead" (no
442 * device connections or disconnections will be detected anymore). Becasue no
443 * status event is generated when entering compliance mode (per xhci spec),
444 * this quirk is needed on systems that have the failing hardware installed.
445 */
446 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
447 {
448 xhci->port_status_u0 = 0;
449 init_timer(&xhci->comp_mode_recovery_timer);
450
451 xhci->comp_mode_recovery_timer.data = (unsigned long) xhci;
452 xhci->comp_mode_recovery_timer.function = compliance_mode_recovery;
453 xhci->comp_mode_recovery_timer.expires = jiffies +
454 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
455
456 set_timer_slack(&xhci->comp_mode_recovery_timer,
457 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
458 add_timer(&xhci->comp_mode_recovery_timer);
459 xhci_dbg(xhci, "Compliance Mode Recovery Timer Initialized.\n");
460 }
461
462 /*
463 * This function identifies the systems that have installed the SN65LVPE502CP
464 * USB3.0 re-driver and that need the Compliance Mode Quirk.
465 * Systems:
466 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
467 */
468 static bool compliance_mode_recovery_timer_quirk_check(void)
469 {
470 const char *dmi_product_name, *dmi_sys_vendor;
471
472 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
473 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
474 if (!dmi_product_name || !dmi_sys_vendor)
475 return false;
476
477 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
478 return false;
479
480 if (strstr(dmi_product_name, "Z420") ||
481 strstr(dmi_product_name, "Z620") ||
482 strstr(dmi_product_name, "Z820") ||
483 strstr(dmi_product_name, "Z1 Workstation"))
484 return true;
485
486 return false;
487 }
488
489 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
490 {
491 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
492 }
493
494
495 /*
496 * Initialize memory for HCD and xHC (one-time init).
497 *
498 * Program the PAGESIZE register, initialize the device context array, create
499 * device contexts (?), set up a command ring segment (or two?), create event
500 * ring (one for now).
501 */
502 int xhci_init(struct usb_hcd *hcd)
503 {
504 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
505 int retval = 0;
506
507 xhci_dbg(xhci, "xhci_init\n");
508 spin_lock_init(&xhci->lock);
509 if (xhci->hci_version == 0x95 && link_quirk) {
510 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
511 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
512 } else {
513 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
514 }
515 retval = xhci_mem_init(xhci, GFP_KERNEL);
516 xhci_dbg(xhci, "Finished xhci_init\n");
517
518 /* Initializing Compliance Mode Recovery Data If Needed */
519 if (compliance_mode_recovery_timer_quirk_check()) {
520 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
521 compliance_mode_recovery_timer_init(xhci);
522 }
523
524 return retval;
525 }
526
527 /*-------------------------------------------------------------------------*/
528
529
530 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
531 static void xhci_event_ring_work(unsigned long arg)
532 {
533 unsigned long flags;
534 int temp;
535 u64 temp_64;
536 struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
537 int i, j;
538
539 xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
540
541 spin_lock_irqsave(&xhci->lock, flags);
542 temp = xhci_readl(xhci, &xhci->op_regs->status);
543 xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
544 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
545 (xhci->xhc_state & XHCI_STATE_HALTED)) {
546 xhci_dbg(xhci, "HW died, polling stopped.\n");
547 spin_unlock_irqrestore(&xhci->lock, flags);
548 return;
549 }
550
551 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
552 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
553 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
554 xhci->error_bitmask = 0;
555 xhci_dbg(xhci, "Event ring:\n");
556 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
557 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
558 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
559 temp_64 &= ~ERST_PTR_MASK;
560 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
561 xhci_dbg(xhci, "Command ring:\n");
562 xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
563 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
564 xhci_dbg_cmd_ptrs(xhci);
565 for (i = 0; i < MAX_HC_SLOTS; ++i) {
566 if (!xhci->devs[i])
567 continue;
568 for (j = 0; j < 31; ++j) {
569 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
570 }
571 }
572 spin_unlock_irqrestore(&xhci->lock, flags);
573
574 if (!xhci->zombie)
575 mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
576 else
577 xhci_dbg(xhci, "Quit polling the event ring.\n");
578 }
579 #endif
580
581 static int xhci_run_finished(struct xhci_hcd *xhci)
582 {
583 if (xhci_start(xhci)) {
584 xhci_halt(xhci);
585 return -ENODEV;
586 }
587 xhci->shared_hcd->state = HC_STATE_RUNNING;
588 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
589
590 if (xhci->quirks & XHCI_NEC_HOST)
591 xhci_ring_cmd_db(xhci);
592
593 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
594 return 0;
595 }
596
597 /*
598 * Start the HC after it was halted.
599 *
600 * This function is called by the USB core when the HC driver is added.
601 * Its opposite is xhci_stop().
602 *
603 * xhci_init() must be called once before this function can be called.
604 * Reset the HC, enable device slot contexts, program DCBAAP, and
605 * set command ring pointer and event ring pointer.
606 *
607 * Setup MSI-X vectors and enable interrupts.
608 */
609 int xhci_run(struct usb_hcd *hcd)
610 {
611 u32 temp;
612 u64 temp_64;
613 int ret;
614 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
615
616 /* Start the xHCI host controller running only after the USB 2.0 roothub
617 * is setup.
618 */
619
620 hcd->uses_new_polling = 1;
621 if (!usb_hcd_is_primary_hcd(hcd))
622 return xhci_run_finished(xhci);
623
624 xhci_dbg(xhci, "xhci_run\n");
625
626 ret = xhci_try_enable_msi(hcd);
627 if (ret)
628 return ret;
629
630 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
631 init_timer(&xhci->event_ring_timer);
632 xhci->event_ring_timer.data = (unsigned long) xhci;
633 xhci->event_ring_timer.function = xhci_event_ring_work;
634 /* Poll the event ring */
635 xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
636 xhci->zombie = 0;
637 xhci_dbg(xhci, "Setting event ring polling timer\n");
638 add_timer(&xhci->event_ring_timer);
639 #endif
640
641 xhci_dbg(xhci, "Command ring memory map follows:\n");
642 xhci_debug_ring(xhci, xhci->cmd_ring);
643 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
644 xhci_dbg_cmd_ptrs(xhci);
645
646 xhci_dbg(xhci, "ERST memory map follows:\n");
647 xhci_dbg_erst(xhci, &xhci->erst);
648 xhci_dbg(xhci, "Event ring:\n");
649 xhci_debug_ring(xhci, xhci->event_ring);
650 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
651 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
652 temp_64 &= ~ERST_PTR_MASK;
653 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
654
655 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
656 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
657 temp &= ~ER_IRQ_INTERVAL_MASK;
658 temp |= (u32) 160;
659 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
660
661 /* Set the HCD state before we enable the irqs */
662 temp = xhci_readl(xhci, &xhci->op_regs->command);
663 temp |= (CMD_EIE);
664 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
665 temp);
666 xhci_writel(xhci, temp, &xhci->op_regs->command);
667
668 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
669 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
670 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
671 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
672 &xhci->ir_set->irq_pending);
673 xhci_print_ir_set(xhci, 0);
674
675 if (xhci->quirks & XHCI_NEC_HOST)
676 xhci_queue_vendor_command(xhci, 0, 0, 0,
677 TRB_TYPE(TRB_NEC_GET_FW));
678
679 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
680 return 0;
681 }
682
683 static void xhci_only_stop_hcd(struct usb_hcd *hcd)
684 {
685 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
686
687 spin_lock_irq(&xhci->lock);
688 xhci_halt(xhci);
689
690 /* The shared_hcd is going to be deallocated shortly (the USB core only
691 * calls this function when allocation fails in usb_add_hcd(), or
692 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
693 */
694 xhci->shared_hcd = NULL;
695 spin_unlock_irq(&xhci->lock);
696 }
697
698 /*
699 * Stop xHCI driver.
700 *
701 * This function is called by the USB core when the HC driver is removed.
702 * Its opposite is xhci_run().
703 *
704 * Disable device contexts, disable IRQs, and quiesce the HC.
705 * Reset the HC, finish any completed transactions, and cleanup memory.
706 */
707 void xhci_stop(struct usb_hcd *hcd)
708 {
709 u32 temp;
710 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
711
712 if (!usb_hcd_is_primary_hcd(hcd)) {
713 xhci_only_stop_hcd(xhci->shared_hcd);
714 return;
715 }
716
717 spin_lock_irq(&xhci->lock);
718 /* Make sure the xHC is halted for a USB3 roothub
719 * (xhci_stop() could be called as part of failed init).
720 */
721 xhci_halt(xhci);
722 xhci_reset(xhci);
723 spin_unlock_irq(&xhci->lock);
724
725 xhci_cleanup_msix(xhci);
726
727 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
728 /* Tell the event ring poll function not to reschedule */
729 xhci->zombie = 1;
730 del_timer_sync(&xhci->event_ring_timer);
731 #endif
732
733 /* Deleting Compliance Mode Recovery Timer */
734 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
735 (!(xhci_all_ports_seen_u0(xhci))))
736 del_timer_sync(&xhci->comp_mode_recovery_timer);
737
738 if (xhci->quirks & XHCI_AMD_PLL_FIX)
739 usb_amd_dev_put();
740
741 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
742 temp = xhci_readl(xhci, &xhci->op_regs->status);
743 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
744 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
745 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
746 &xhci->ir_set->irq_pending);
747 xhci_print_ir_set(xhci, 0);
748
749 xhci_dbg(xhci, "cleaning up memory\n");
750 xhci_mem_cleanup(xhci);
751 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
752 xhci_readl(xhci, &xhci->op_regs->status));
753 }
754
755 /*
756 * Shutdown HC (not bus-specific)
757 *
758 * This is called when the machine is rebooting or halting. We assume that the
759 * machine will be powered off, and the HC's internal state will be reset.
760 * Don't bother to free memory.
761 *
762 * This will only ever be called with the main usb_hcd (the USB3 roothub).
763 */
764 void xhci_shutdown(struct usb_hcd *hcd)
765 {
766 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
767
768 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
769 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
770
771 spin_lock_irq(&xhci->lock);
772 xhci_halt(xhci);
773 spin_unlock_irq(&xhci->lock);
774
775 xhci_cleanup_msix(xhci);
776
777 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
778 xhci_readl(xhci, &xhci->op_regs->status));
779 }
780
781 #ifdef CONFIG_PM
782 static void xhci_save_registers(struct xhci_hcd *xhci)
783 {
784 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
785 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
786 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
787 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
788 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
789 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
790 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
791 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
792 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
793 }
794
795 static void xhci_restore_registers(struct xhci_hcd *xhci)
796 {
797 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
798 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
799 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
800 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
801 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
802 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
803 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
804 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
805 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
806 }
807
808 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
809 {
810 u64 val_64;
811
812 /* step 2: initialize command ring buffer */
813 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
814 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
815 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
816 xhci->cmd_ring->dequeue) &
817 (u64) ~CMD_RING_RSVD_BITS) |
818 xhci->cmd_ring->cycle_state;
819 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
820 (long unsigned long) val_64);
821 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
822 }
823
824 /*
825 * The whole command ring must be cleared to zero when we suspend the host.
826 *
827 * The host doesn't save the command ring pointer in the suspend well, so we
828 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
829 * aligned, because of the reserved bits in the command ring dequeue pointer
830 * register. Therefore, we can't just set the dequeue pointer back in the
831 * middle of the ring (TRBs are 16-byte aligned).
832 */
833 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
834 {
835 struct xhci_ring *ring;
836 struct xhci_segment *seg;
837
838 ring = xhci->cmd_ring;
839 seg = ring->deq_seg;
840 do {
841 memset(seg->trbs, 0,
842 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
843 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
844 cpu_to_le32(~TRB_CYCLE);
845 seg = seg->next;
846 } while (seg != ring->deq_seg);
847
848 /* Reset the software enqueue and dequeue pointers */
849 ring->deq_seg = ring->first_seg;
850 ring->dequeue = ring->first_seg->trbs;
851 ring->enq_seg = ring->deq_seg;
852 ring->enqueue = ring->dequeue;
853
854 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
855 /*
856 * Ring is now zeroed, so the HW should look for change of ownership
857 * when the cycle bit is set to 1.
858 */
859 ring->cycle_state = 1;
860
861 /*
862 * Reset the hardware dequeue pointer.
863 * Yes, this will need to be re-written after resume, but we're paranoid
864 * and want to make sure the hardware doesn't access bogus memory
865 * because, say, the BIOS or an SMI started the host without changing
866 * the command ring pointers.
867 */
868 xhci_set_cmd_ring_deq(xhci);
869 }
870
871 /*
872 * Stop HC (not bus-specific)
873 *
874 * This is called when the machine transition into S3/S4 mode.
875 *
876 */
877 int xhci_suspend(struct xhci_hcd *xhci)
878 {
879 int rc = 0;
880 struct usb_hcd *hcd = xhci_to_hcd(xhci);
881 u32 command;
882
883 if (hcd->state != HC_STATE_SUSPENDED ||
884 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
885 return -EINVAL;
886
887 spin_lock_irq(&xhci->lock);
888 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
889 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
890 /* step 1: stop endpoint */
891 /* skipped assuming that port suspend has done */
892
893 /* step 2: clear Run/Stop bit */
894 command = xhci_readl(xhci, &xhci->op_regs->command);
895 command &= ~CMD_RUN;
896 xhci_writel(xhci, command, &xhci->op_regs->command);
897 if (xhci_handshake(xhci, &xhci->op_regs->status,
898 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC)) {
899 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
900 spin_unlock_irq(&xhci->lock);
901 return -ETIMEDOUT;
902 }
903 xhci_clear_command_ring(xhci);
904
905 /* step 3: save registers */
906 xhci_save_registers(xhci);
907
908 /* step 4: set CSS flag */
909 command = xhci_readl(xhci, &xhci->op_regs->command);
910 command |= CMD_CSS;
911 xhci_writel(xhci, command, &xhci->op_regs->command);
912 if (xhci_handshake(xhci, &xhci->op_regs->status,
913 STS_SAVE, 0, 10 * 1000)) {
914 xhci_warn(xhci, "WARN: xHC save state timeout\n");
915 spin_unlock_irq(&xhci->lock);
916 return -ETIMEDOUT;
917 }
918 spin_unlock_irq(&xhci->lock);
919
920 /*
921 * Deleting Compliance Mode Recovery Timer because the xHCI Host
922 * is about to be suspended.
923 */
924 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
925 (!(xhci_all_ports_seen_u0(xhci)))) {
926 del_timer_sync(&xhci->comp_mode_recovery_timer);
927 xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted!\n");
928 }
929
930 /* step 5: remove core well power */
931 /* synchronize irq when using MSI-X */
932 xhci_msix_sync_irqs(xhci);
933
934 return rc;
935 }
936
937 /*
938 * start xHC (not bus-specific)
939 *
940 * This is called when the machine transition from S3/S4 mode.
941 *
942 */
943 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
944 {
945 u32 command, temp = 0;
946 struct usb_hcd *hcd = xhci_to_hcd(xhci);
947 struct usb_hcd *secondary_hcd;
948 int retval = 0;
949
950 /* Wait a bit if either of the roothubs need to settle from the
951 * transition into bus suspend.
952 */
953 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
954 time_before(jiffies,
955 xhci->bus_state[1].next_statechange))
956 msleep(100);
957
958 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
959 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
960
961 spin_lock_irq(&xhci->lock);
962 if (xhci->quirks & XHCI_RESET_ON_RESUME)
963 hibernated = true;
964
965 if (!hibernated) {
966 /* step 1: restore register */
967 xhci_restore_registers(xhci);
968 /* step 2: initialize command ring buffer */
969 xhci_set_cmd_ring_deq(xhci);
970 /* step 3: restore state and start state*/
971 /* step 3: set CRS flag */
972 command = xhci_readl(xhci, &xhci->op_regs->command);
973 command |= CMD_CRS;
974 xhci_writel(xhci, command, &xhci->op_regs->command);
975 if (xhci_handshake(xhci, &xhci->op_regs->status,
976 STS_RESTORE, 0, 10 * 1000)) {
977 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
978 spin_unlock_irq(&xhci->lock);
979 return -ETIMEDOUT;
980 }
981 temp = xhci_readl(xhci, &xhci->op_regs->status);
982 }
983
984 /* If restore operation fails, re-initialize the HC during resume */
985 if ((temp & STS_SRE) || hibernated) {
986 /* Let the USB core know _both_ roothubs lost power. */
987 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
988 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
989
990 xhci_dbg(xhci, "Stop HCD\n");
991 xhci_halt(xhci);
992 xhci_reset(xhci);
993 spin_unlock_irq(&xhci->lock);
994 xhci_cleanup_msix(xhci);
995
996 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
997 /* Tell the event ring poll function not to reschedule */
998 xhci->zombie = 1;
999 del_timer_sync(&xhci->event_ring_timer);
1000 #endif
1001
1002 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1003 temp = xhci_readl(xhci, &xhci->op_regs->status);
1004 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
1005 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
1006 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
1007 &xhci->ir_set->irq_pending);
1008 xhci_print_ir_set(xhci, 0);
1009
1010 xhci_dbg(xhci, "cleaning up memory\n");
1011 xhci_mem_cleanup(xhci);
1012 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1013 xhci_readl(xhci, &xhci->op_regs->status));
1014
1015 /* USB core calls the PCI reinit and start functions twice:
1016 * first with the primary HCD, and then with the secondary HCD.
1017 * If we don't do the same, the host will never be started.
1018 */
1019 if (!usb_hcd_is_primary_hcd(hcd))
1020 secondary_hcd = hcd;
1021 else
1022 secondary_hcd = xhci->shared_hcd;
1023
1024 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1025 retval = xhci_init(hcd->primary_hcd);
1026 if (retval)
1027 return retval;
1028 xhci_dbg(xhci, "Start the primary HCD\n");
1029 retval = xhci_run(hcd->primary_hcd);
1030 if (!retval) {
1031 xhci_dbg(xhci, "Start the secondary HCD\n");
1032 retval = xhci_run(secondary_hcd);
1033 }
1034 hcd->state = HC_STATE_SUSPENDED;
1035 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1036 goto done;
1037 }
1038
1039 /* step 4: set Run/Stop bit */
1040 command = xhci_readl(xhci, &xhci->op_regs->command);
1041 command |= CMD_RUN;
1042 xhci_writel(xhci, command, &xhci->op_regs->command);
1043 xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,
1044 0, 250 * 1000);
1045
1046 /* step 5: walk topology and initialize portsc,
1047 * portpmsc and portli
1048 */
1049 /* this is done in bus_resume */
1050
1051 /* step 6: restart each of the previously
1052 * Running endpoints by ringing their doorbells
1053 */
1054
1055 spin_unlock_irq(&xhci->lock);
1056
1057 done:
1058 if (retval == 0) {
1059 usb_hcd_resume_root_hub(hcd);
1060 usb_hcd_resume_root_hub(xhci->shared_hcd);
1061 }
1062
1063 /*
1064 * If system is subject to the Quirk, Compliance Mode Timer needs to
1065 * be re-initialized Always after a system resume. Ports are subject
1066 * to suffer the Compliance Mode issue again. It doesn't matter if
1067 * ports have entered previously to U0 before system's suspension.
1068 */
1069 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
1070 compliance_mode_recovery_timer_init(xhci);
1071
1072 return retval;
1073 }
1074 #endif /* CONFIG_PM */
1075
1076 /*-------------------------------------------------------------------------*/
1077
1078 /**
1079 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1080 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1081 * value to right shift 1 for the bitmask.
1082 *
1083 * Index = (epnum * 2) + direction - 1,
1084 * where direction = 0 for OUT, 1 for IN.
1085 * For control endpoints, the IN index is used (OUT index is unused), so
1086 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1087 */
1088 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1089 {
1090 unsigned int index;
1091 if (usb_endpoint_xfer_control(desc))
1092 index = (unsigned int) (usb_endpoint_num(desc)*2);
1093 else
1094 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1095 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1096 return index;
1097 }
1098
1099 /* Find the flag for this endpoint (for use in the control context). Use the
1100 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1101 * bit 1, etc.
1102 */
1103 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1104 {
1105 return 1 << (xhci_get_endpoint_index(desc) + 1);
1106 }
1107
1108 /* Find the flag for this endpoint (for use in the control context). Use the
1109 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1110 * bit 1, etc.
1111 */
1112 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1113 {
1114 return 1 << (ep_index + 1);
1115 }
1116
1117 /* Compute the last valid endpoint context index. Basically, this is the
1118 * endpoint index plus one. For slot contexts with more than valid endpoint,
1119 * we find the most significant bit set in the added contexts flags.
1120 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1121 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1122 */
1123 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1124 {
1125 return fls(added_ctxs) - 1;
1126 }
1127
1128 /* Returns 1 if the arguments are OK;
1129 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1130 */
1131 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1132 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1133 const char *func) {
1134 struct xhci_hcd *xhci;
1135 struct xhci_virt_device *virt_dev;
1136
1137 if (!hcd || (check_ep && !ep) || !udev) {
1138 printk(KERN_DEBUG "xHCI %s called with invalid args\n",
1139 func);
1140 return -EINVAL;
1141 }
1142 if (!udev->parent) {
1143 printk(KERN_DEBUG "xHCI %s called for root hub\n",
1144 func);
1145 return 0;
1146 }
1147
1148 xhci = hcd_to_xhci(hcd);
1149 if (xhci->xhc_state & XHCI_STATE_HALTED)
1150 return -ENODEV;
1151
1152 if (check_virt_dev) {
1153 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1154 printk(KERN_DEBUG "xHCI %s called with unaddressed "
1155 "device\n", func);
1156 return -EINVAL;
1157 }
1158
1159 virt_dev = xhci->devs[udev->slot_id];
1160 if (virt_dev->udev != udev) {
1161 printk(KERN_DEBUG "xHCI %s called with udev and "
1162 "virt_dev does not match\n", func);
1163 return -EINVAL;
1164 }
1165 }
1166
1167 return 1;
1168 }
1169
1170 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1171 struct usb_device *udev, struct xhci_command *command,
1172 bool ctx_change, bool must_succeed);
1173
1174 /*
1175 * Full speed devices may have a max packet size greater than 8 bytes, but the
1176 * USB core doesn't know that until it reads the first 8 bytes of the
1177 * descriptor. If the usb_device's max packet size changes after that point,
1178 * we need to issue an evaluate context command and wait on it.
1179 */
1180 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1181 unsigned int ep_index, struct urb *urb)
1182 {
1183 struct xhci_container_ctx *in_ctx;
1184 struct xhci_container_ctx *out_ctx;
1185 struct xhci_input_control_ctx *ctrl_ctx;
1186 struct xhci_ep_ctx *ep_ctx;
1187 int max_packet_size;
1188 int hw_max_packet_size;
1189 int ret = 0;
1190
1191 out_ctx = xhci->devs[slot_id]->out_ctx;
1192 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1193 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1194 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1195 if (hw_max_packet_size != max_packet_size) {
1196 xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
1197 xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
1198 max_packet_size);
1199 xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
1200 hw_max_packet_size);
1201 xhci_dbg(xhci, "Issuing evaluate context command.\n");
1202
1203 /* Set up the modified control endpoint 0 */
1204 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1205 xhci->devs[slot_id]->out_ctx, ep_index);
1206 in_ctx = xhci->devs[slot_id]->in_ctx;
1207 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1208 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1209 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1210
1211 /* Set up the input context flags for the command */
1212 /* FIXME: This won't work if a non-default control endpoint
1213 * changes max packet sizes.
1214 */
1215 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1216 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1217 ctrl_ctx->drop_flags = 0;
1218
1219 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1220 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1221 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1222 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1223
1224 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1225 true, false);
1226
1227 /* Clean up the input context for later use by bandwidth
1228 * functions.
1229 */
1230 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1231 }
1232 return ret;
1233 }
1234
1235 /*
1236 * non-error returns are a promise to giveback() the urb later
1237 * we drop ownership so next owner (or urb unlink) can get it
1238 */
1239 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1240 {
1241 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1242 struct xhci_td *buffer;
1243 unsigned long flags;
1244 int ret = 0;
1245 unsigned int slot_id, ep_index;
1246 struct urb_priv *urb_priv;
1247 int size, i;
1248
1249 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1250 true, true, __func__) <= 0)
1251 return -EINVAL;
1252
1253 slot_id = urb->dev->slot_id;
1254 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1255
1256 if (!HCD_HW_ACCESSIBLE(hcd)) {
1257 if (!in_interrupt())
1258 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1259 ret = -ESHUTDOWN;
1260 goto exit;
1261 }
1262
1263 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1264 size = urb->number_of_packets;
1265 else
1266 size = 1;
1267
1268 urb_priv = kzalloc(sizeof(struct urb_priv) +
1269 size * sizeof(struct xhci_td *), mem_flags);
1270 if (!urb_priv)
1271 return -ENOMEM;
1272
1273 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1274 if (!buffer) {
1275 kfree(urb_priv);
1276 return -ENOMEM;
1277 }
1278
1279 for (i = 0; i < size; i++) {
1280 urb_priv->td[i] = buffer;
1281 buffer++;
1282 }
1283
1284 urb_priv->length = size;
1285 urb_priv->td_cnt = 0;
1286 urb->hcpriv = urb_priv;
1287
1288 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1289 /* Check to see if the max packet size for the default control
1290 * endpoint changed during FS device enumeration
1291 */
1292 if (urb->dev->speed == USB_SPEED_FULL) {
1293 ret = xhci_check_maxpacket(xhci, slot_id,
1294 ep_index, urb);
1295 if (ret < 0) {
1296 xhci_urb_free_priv(xhci, urb_priv);
1297 urb->hcpriv = NULL;
1298 return ret;
1299 }
1300 }
1301
1302 /* We have a spinlock and interrupts disabled, so we must pass
1303 * atomic context to this function, which may allocate memory.
1304 */
1305 spin_lock_irqsave(&xhci->lock, flags);
1306 if (xhci->xhc_state & XHCI_STATE_DYING)
1307 goto dying;
1308 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1309 slot_id, ep_index);
1310 if (ret)
1311 goto free_priv;
1312 spin_unlock_irqrestore(&xhci->lock, flags);
1313 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1314 spin_lock_irqsave(&xhci->lock, flags);
1315 if (xhci->xhc_state & XHCI_STATE_DYING)
1316 goto dying;
1317 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1318 EP_GETTING_STREAMS) {
1319 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1320 "is transitioning to using streams.\n");
1321 ret = -EINVAL;
1322 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1323 EP_GETTING_NO_STREAMS) {
1324 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1325 "is transitioning to "
1326 "not having streams.\n");
1327 ret = -EINVAL;
1328 } else {
1329 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1330 slot_id, ep_index);
1331 }
1332 if (ret)
1333 goto free_priv;
1334 spin_unlock_irqrestore(&xhci->lock, flags);
1335 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1336 spin_lock_irqsave(&xhci->lock, flags);
1337 if (xhci->xhc_state & XHCI_STATE_DYING)
1338 goto dying;
1339 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1340 slot_id, ep_index);
1341 if (ret)
1342 goto free_priv;
1343 spin_unlock_irqrestore(&xhci->lock, flags);
1344 } else {
1345 spin_lock_irqsave(&xhci->lock, flags);
1346 if (xhci->xhc_state & XHCI_STATE_DYING)
1347 goto dying;
1348 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1349 slot_id, ep_index);
1350 if (ret)
1351 goto free_priv;
1352 spin_unlock_irqrestore(&xhci->lock, flags);
1353 }
1354 exit:
1355 return ret;
1356 dying:
1357 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1358 "non-responsive xHCI host.\n",
1359 urb->ep->desc.bEndpointAddress, urb);
1360 ret = -ESHUTDOWN;
1361 free_priv:
1362 xhci_urb_free_priv(xhci, urb_priv);
1363 urb->hcpriv = NULL;
1364 spin_unlock_irqrestore(&xhci->lock, flags);
1365 return ret;
1366 }
1367
1368 /* Get the right ring for the given URB.
1369 * If the endpoint supports streams, boundary check the URB's stream ID.
1370 * If the endpoint doesn't support streams, return the singular endpoint ring.
1371 */
1372 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1373 struct urb *urb)
1374 {
1375 unsigned int slot_id;
1376 unsigned int ep_index;
1377 unsigned int stream_id;
1378 struct xhci_virt_ep *ep;
1379
1380 slot_id = urb->dev->slot_id;
1381 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1382 stream_id = urb->stream_id;
1383 ep = &xhci->devs[slot_id]->eps[ep_index];
1384 /* Common case: no streams */
1385 if (!(ep->ep_state & EP_HAS_STREAMS))
1386 return ep->ring;
1387
1388 if (stream_id == 0) {
1389 xhci_warn(xhci,
1390 "WARN: Slot ID %u, ep index %u has streams, "
1391 "but URB has no stream ID.\n",
1392 slot_id, ep_index);
1393 return NULL;
1394 }
1395
1396 if (stream_id < ep->stream_info->num_streams)
1397 return ep->stream_info->stream_rings[stream_id];
1398
1399 xhci_warn(xhci,
1400 "WARN: Slot ID %u, ep index %u has "
1401 "stream IDs 1 to %u allocated, "
1402 "but stream ID %u is requested.\n",
1403 slot_id, ep_index,
1404 ep->stream_info->num_streams - 1,
1405 stream_id);
1406 return NULL;
1407 }
1408
1409 /*
1410 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1411 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1412 * should pick up where it left off in the TD, unless a Set Transfer Ring
1413 * Dequeue Pointer is issued.
1414 *
1415 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1416 * the ring. Since the ring is a contiguous structure, they can't be physically
1417 * removed. Instead, there are two options:
1418 *
1419 * 1) If the HC is in the middle of processing the URB to be canceled, we
1420 * simply move the ring's dequeue pointer past those TRBs using the Set
1421 * Transfer Ring Dequeue Pointer command. This will be the common case,
1422 * when drivers timeout on the last submitted URB and attempt to cancel.
1423 *
1424 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1425 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1426 * HC will need to invalidate the any TRBs it has cached after the stop
1427 * endpoint command, as noted in the xHCI 0.95 errata.
1428 *
1429 * 3) The TD may have completed by the time the Stop Endpoint Command
1430 * completes, so software needs to handle that case too.
1431 *
1432 * This function should protect against the TD enqueueing code ringing the
1433 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1434 * It also needs to account for multiple cancellations on happening at the same
1435 * time for the same endpoint.
1436 *
1437 * Note that this function can be called in any context, or so says
1438 * usb_hcd_unlink_urb()
1439 */
1440 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1441 {
1442 unsigned long flags;
1443 int ret, i;
1444 u32 temp;
1445 struct xhci_hcd *xhci;
1446 struct urb_priv *urb_priv;
1447 struct xhci_td *td;
1448 unsigned int ep_index;
1449 struct xhci_ring *ep_ring;
1450 struct xhci_virt_ep *ep;
1451
1452 xhci = hcd_to_xhci(hcd);
1453 spin_lock_irqsave(&xhci->lock, flags);
1454 /* Make sure the URB hasn't completed or been unlinked already */
1455 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1456 if (ret || !urb->hcpriv)
1457 goto done;
1458 temp = xhci_readl(xhci, &xhci->op_regs->status);
1459 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1460 xhci_dbg(xhci, "HW died, freeing TD.\n");
1461 urb_priv = urb->hcpriv;
1462 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1463 td = urb_priv->td[i];
1464 if (!list_empty(&td->td_list))
1465 list_del_init(&td->td_list);
1466 if (!list_empty(&td->cancelled_td_list))
1467 list_del_init(&td->cancelled_td_list);
1468 }
1469
1470 usb_hcd_unlink_urb_from_ep(hcd, urb);
1471 spin_unlock_irqrestore(&xhci->lock, flags);
1472 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1473 xhci_urb_free_priv(xhci, urb_priv);
1474 return ret;
1475 }
1476 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1477 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1478 xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1479 "non-responsive xHCI host.\n",
1480 urb->ep->desc.bEndpointAddress, urb);
1481 /* Let the stop endpoint command watchdog timer (which set this
1482 * state) finish cleaning up the endpoint TD lists. We must
1483 * have caught it in the middle of dropping a lock and giving
1484 * back an URB.
1485 */
1486 goto done;
1487 }
1488
1489 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1490 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1491 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1492 if (!ep_ring) {
1493 ret = -EINVAL;
1494 goto done;
1495 }
1496
1497 urb_priv = urb->hcpriv;
1498 i = urb_priv->td_cnt;
1499 if (i < urb_priv->length)
1500 xhci_dbg(xhci, "Cancel URB %p, dev %s, ep 0x%x, "
1501 "starting at offset 0x%llx\n",
1502 urb, urb->dev->devpath,
1503 urb->ep->desc.bEndpointAddress,
1504 (unsigned long long) xhci_trb_virt_to_dma(
1505 urb_priv->td[i]->start_seg,
1506 urb_priv->td[i]->first_trb));
1507
1508 for (; i < urb_priv->length; i++) {
1509 td = urb_priv->td[i];
1510 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1511 }
1512
1513 /* Queue a stop endpoint command, but only if this is
1514 * the first cancellation to be handled.
1515 */
1516 if (!(ep->ep_state & EP_HALT_PENDING)) {
1517 ep->ep_state |= EP_HALT_PENDING;
1518 ep->stop_cmds_pending++;
1519 ep->stop_cmd_timer.expires = jiffies +
1520 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1521 add_timer(&ep->stop_cmd_timer);
1522 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1523 xhci_ring_cmd_db(xhci);
1524 }
1525 done:
1526 spin_unlock_irqrestore(&xhci->lock, flags);
1527 return ret;
1528 }
1529
1530 /* Drop an endpoint from a new bandwidth configuration for this device.
1531 * Only one call to this function is allowed per endpoint before
1532 * check_bandwidth() or reset_bandwidth() must be called.
1533 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1534 * add the endpoint to the schedule with possibly new parameters denoted by a
1535 * different endpoint descriptor in usb_host_endpoint.
1536 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1537 * not allowed.
1538 *
1539 * The USB core will not allow URBs to be queued to an endpoint that is being
1540 * disabled, so there's no need for mutual exclusion to protect
1541 * the xhci->devs[slot_id] structure.
1542 */
1543 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1544 struct usb_host_endpoint *ep)
1545 {
1546 struct xhci_hcd *xhci;
1547 struct xhci_container_ctx *in_ctx, *out_ctx;
1548 struct xhci_input_control_ctx *ctrl_ctx;
1549 struct xhci_slot_ctx *slot_ctx;
1550 unsigned int last_ctx;
1551 unsigned int ep_index;
1552 struct xhci_ep_ctx *ep_ctx;
1553 u32 drop_flag;
1554 u32 new_add_flags, new_drop_flags, new_slot_info;
1555 int ret;
1556
1557 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1558 if (ret <= 0)
1559 return ret;
1560 xhci = hcd_to_xhci(hcd);
1561 if (xhci->xhc_state & XHCI_STATE_DYING)
1562 return -ENODEV;
1563
1564 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1565 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1566 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1567 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1568 __func__, drop_flag);
1569 return 0;
1570 }
1571
1572 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1573 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1574 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1575 ep_index = xhci_get_endpoint_index(&ep->desc);
1576 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1577 /* If the HC already knows the endpoint is disabled,
1578 * or the HCD has noted it is disabled, ignore this request
1579 */
1580 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1581 cpu_to_le32(EP_STATE_DISABLED)) ||
1582 le32_to_cpu(ctrl_ctx->drop_flags) &
1583 xhci_get_endpoint_flag(&ep->desc)) {
1584 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1585 __func__, ep);
1586 return 0;
1587 }
1588
1589 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1590 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1591
1592 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1593 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1594
1595 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
1596 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1597 /* Update the last valid endpoint context, if we deleted the last one */
1598 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1599 LAST_CTX(last_ctx)) {
1600 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1601 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1602 }
1603 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1604
1605 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1606
1607 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1608 (unsigned int) ep->desc.bEndpointAddress,
1609 udev->slot_id,
1610 (unsigned int) new_drop_flags,
1611 (unsigned int) new_add_flags,
1612 (unsigned int) new_slot_info);
1613 return 0;
1614 }
1615
1616 /* Add an endpoint to a new possible bandwidth configuration for this device.
1617 * Only one call to this function is allowed per endpoint before
1618 * check_bandwidth() or reset_bandwidth() must be called.
1619 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1620 * add the endpoint to the schedule with possibly new parameters denoted by a
1621 * different endpoint descriptor in usb_host_endpoint.
1622 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1623 * not allowed.
1624 *
1625 * The USB core will not allow URBs to be queued to an endpoint until the
1626 * configuration or alt setting is installed in the device, so there's no need
1627 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1628 */
1629 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1630 struct usb_host_endpoint *ep)
1631 {
1632 struct xhci_hcd *xhci;
1633 struct xhci_container_ctx *in_ctx, *out_ctx;
1634 unsigned int ep_index;
1635 struct xhci_slot_ctx *slot_ctx;
1636 struct xhci_input_control_ctx *ctrl_ctx;
1637 u32 added_ctxs;
1638 unsigned int last_ctx;
1639 u32 new_add_flags, new_drop_flags, new_slot_info;
1640 struct xhci_virt_device *virt_dev;
1641 int ret = 0;
1642
1643 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1644 if (ret <= 0) {
1645 /* So we won't queue a reset ep command for a root hub */
1646 ep->hcpriv = NULL;
1647 return ret;
1648 }
1649 xhci = hcd_to_xhci(hcd);
1650 if (xhci->xhc_state & XHCI_STATE_DYING)
1651 return -ENODEV;
1652
1653 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1654 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1655 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1656 /* FIXME when we have to issue an evaluate endpoint command to
1657 * deal with ep0 max packet size changing once we get the
1658 * descriptors
1659 */
1660 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1661 __func__, added_ctxs);
1662 return 0;
1663 }
1664
1665 virt_dev = xhci->devs[udev->slot_id];
1666 in_ctx = virt_dev->in_ctx;
1667 out_ctx = virt_dev->out_ctx;
1668 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1669 ep_index = xhci_get_endpoint_index(&ep->desc);
1670
1671 /* If this endpoint is already in use, and the upper layers are trying
1672 * to add it again without dropping it, reject the addition.
1673 */
1674 if (virt_dev->eps[ep_index].ring &&
1675 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1676 xhci_get_endpoint_flag(&ep->desc))) {
1677 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1678 "without dropping it.\n",
1679 (unsigned int) ep->desc.bEndpointAddress);
1680 return -EINVAL;
1681 }
1682
1683 /* If the HCD has already noted the endpoint is enabled,
1684 * ignore this request.
1685 */
1686 if (le32_to_cpu(ctrl_ctx->add_flags) &
1687 xhci_get_endpoint_flag(&ep->desc)) {
1688 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1689 __func__, ep);
1690 return 0;
1691 }
1692
1693 /*
1694 * Configuration and alternate setting changes must be done in
1695 * process context, not interrupt context (or so documenation
1696 * for usb_set_interface() and usb_set_configuration() claim).
1697 */
1698 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1699 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1700 __func__, ep->desc.bEndpointAddress);
1701 return -ENOMEM;
1702 }
1703
1704 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1705 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1706
1707 /* If xhci_endpoint_disable() was called for this endpoint, but the
1708 * xHC hasn't been notified yet through the check_bandwidth() call,
1709 * this re-adds a new state for the endpoint from the new endpoint
1710 * descriptors. We must drop and re-add this endpoint, so we leave the
1711 * drop flags alone.
1712 */
1713 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1714
1715 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1716 /* Update the last valid endpoint context, if we just added one past */
1717 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1718 LAST_CTX(last_ctx)) {
1719 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1720 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1721 }
1722 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1723
1724 /* Store the usb_device pointer for later use */
1725 ep->hcpriv = udev;
1726
1727 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1728 (unsigned int) ep->desc.bEndpointAddress,
1729 udev->slot_id,
1730 (unsigned int) new_drop_flags,
1731 (unsigned int) new_add_flags,
1732 (unsigned int) new_slot_info);
1733 return 0;
1734 }
1735
1736 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1737 {
1738 struct xhci_input_control_ctx *ctrl_ctx;
1739 struct xhci_ep_ctx *ep_ctx;
1740 struct xhci_slot_ctx *slot_ctx;
1741 int i;
1742
1743 /* When a device's add flag and drop flag are zero, any subsequent
1744 * configure endpoint command will leave that endpoint's state
1745 * untouched. Make sure we don't leave any old state in the input
1746 * endpoint contexts.
1747 */
1748 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1749 ctrl_ctx->drop_flags = 0;
1750 ctrl_ctx->add_flags = 0;
1751 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1752 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1753 /* Endpoint 0 is always valid */
1754 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1755 for (i = 1; i < 31; ++i) {
1756 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1757 ep_ctx->ep_info = 0;
1758 ep_ctx->ep_info2 = 0;
1759 ep_ctx->deq = 0;
1760 ep_ctx->tx_info = 0;
1761 }
1762 }
1763
1764 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1765 struct usb_device *udev, u32 *cmd_status)
1766 {
1767 int ret;
1768
1769 switch (*cmd_status) {
1770 case COMP_ENOMEM:
1771 dev_warn(&udev->dev, "Not enough host controller resources "
1772 "for new device state.\n");
1773 ret = -ENOMEM;
1774 /* FIXME: can we allocate more resources for the HC? */
1775 break;
1776 case COMP_BW_ERR:
1777 case COMP_2ND_BW_ERR:
1778 dev_warn(&udev->dev, "Not enough bandwidth "
1779 "for new device state.\n");
1780 ret = -ENOSPC;
1781 /* FIXME: can we go back to the old state? */
1782 break;
1783 case COMP_TRB_ERR:
1784 /* the HCD set up something wrong */
1785 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1786 "add flag = 1, "
1787 "and endpoint is not disabled.\n");
1788 ret = -EINVAL;
1789 break;
1790 case COMP_DEV_ERR:
1791 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1792 "configure command.\n");
1793 ret = -ENODEV;
1794 break;
1795 case COMP_SUCCESS:
1796 dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1797 ret = 0;
1798 break;
1799 default:
1800 xhci_err(xhci, "ERROR: unexpected command completion "
1801 "code 0x%x.\n", *cmd_status);
1802 ret = -EINVAL;
1803 break;
1804 }
1805 return ret;
1806 }
1807
1808 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1809 struct usb_device *udev, u32 *cmd_status)
1810 {
1811 int ret;
1812 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1813
1814 switch (*cmd_status) {
1815 case COMP_EINVAL:
1816 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1817 "context command.\n");
1818 ret = -EINVAL;
1819 break;
1820 case COMP_EBADSLT:
1821 dev_warn(&udev->dev, "WARN: slot not enabled for"
1822 "evaluate context command.\n");
1823 ret = -EINVAL;
1824 break;
1825 case COMP_CTX_STATE:
1826 dev_warn(&udev->dev, "WARN: invalid context state for "
1827 "evaluate context command.\n");
1828 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1829 ret = -EINVAL;
1830 break;
1831 case COMP_DEV_ERR:
1832 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1833 "context command.\n");
1834 ret = -ENODEV;
1835 break;
1836 case COMP_MEL_ERR:
1837 /* Max Exit Latency too large error */
1838 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1839 ret = -EINVAL;
1840 break;
1841 case COMP_SUCCESS:
1842 dev_dbg(&udev->dev, "Successful evaluate context command\n");
1843 ret = 0;
1844 break;
1845 default:
1846 xhci_err(xhci, "ERROR: unexpected command completion "
1847 "code 0x%x.\n", *cmd_status);
1848 ret = -EINVAL;
1849 break;
1850 }
1851 return ret;
1852 }
1853
1854 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1855 struct xhci_container_ctx *in_ctx)
1856 {
1857 struct xhci_input_control_ctx *ctrl_ctx;
1858 u32 valid_add_flags;
1859 u32 valid_drop_flags;
1860
1861 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1862 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1863 * (bit 1). The default control endpoint is added during the Address
1864 * Device command and is never removed until the slot is disabled.
1865 */
1866 valid_add_flags = ctrl_ctx->add_flags >> 2;
1867 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1868
1869 /* Use hweight32 to count the number of ones in the add flags, or
1870 * number of endpoints added. Don't count endpoints that are changed
1871 * (both added and dropped).
1872 */
1873 return hweight32(valid_add_flags) -
1874 hweight32(valid_add_flags & valid_drop_flags);
1875 }
1876
1877 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1878 struct xhci_container_ctx *in_ctx)
1879 {
1880 struct xhci_input_control_ctx *ctrl_ctx;
1881 u32 valid_add_flags;
1882 u32 valid_drop_flags;
1883
1884 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1885 valid_add_flags = ctrl_ctx->add_flags >> 2;
1886 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1887
1888 return hweight32(valid_drop_flags) -
1889 hweight32(valid_add_flags & valid_drop_flags);
1890 }
1891
1892 /*
1893 * We need to reserve the new number of endpoints before the configure endpoint
1894 * command completes. We can't subtract the dropped endpoints from the number
1895 * of active endpoints until the command completes because we can oversubscribe
1896 * the host in this case:
1897 *
1898 * - the first configure endpoint command drops more endpoints than it adds
1899 * - a second configure endpoint command that adds more endpoints is queued
1900 * - the first configure endpoint command fails, so the config is unchanged
1901 * - the second command may succeed, even though there isn't enough resources
1902 *
1903 * Must be called with xhci->lock held.
1904 */
1905 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1906 struct xhci_container_ctx *in_ctx)
1907 {
1908 u32 added_eps;
1909
1910 added_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1911 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1912 xhci_dbg(xhci, "Not enough ep ctxs: "
1913 "%u active, need to add %u, limit is %u.\n",
1914 xhci->num_active_eps, added_eps,
1915 xhci->limit_active_eps);
1916 return -ENOMEM;
1917 }
1918 xhci->num_active_eps += added_eps;
1919 xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
1920 xhci->num_active_eps);
1921 return 0;
1922 }
1923
1924 /*
1925 * The configure endpoint was failed by the xHC for some other reason, so we
1926 * need to revert the resources that failed configuration would have used.
1927 *
1928 * Must be called with xhci->lock held.
1929 */
1930 static void xhci_free_host_resources(struct xhci_hcd *xhci,
1931 struct xhci_container_ctx *in_ctx)
1932 {
1933 u32 num_failed_eps;
1934
1935 num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1936 xhci->num_active_eps -= num_failed_eps;
1937 xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
1938 num_failed_eps,
1939 xhci->num_active_eps);
1940 }
1941
1942 /*
1943 * Now that the command has completed, clean up the active endpoint count by
1944 * subtracting out the endpoints that were dropped (but not changed).
1945 *
1946 * Must be called with xhci->lock held.
1947 */
1948 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1949 struct xhci_container_ctx *in_ctx)
1950 {
1951 u32 num_dropped_eps;
1952
1953 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx);
1954 xhci->num_active_eps -= num_dropped_eps;
1955 if (num_dropped_eps)
1956 xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
1957 num_dropped_eps,
1958 xhci->num_active_eps);
1959 }
1960
1961 static unsigned int xhci_get_block_size(struct usb_device *udev)
1962 {
1963 switch (udev->speed) {
1964 case USB_SPEED_LOW:
1965 case USB_SPEED_FULL:
1966 return FS_BLOCK;
1967 case USB_SPEED_HIGH:
1968 return HS_BLOCK;
1969 case USB_SPEED_SUPER:
1970 return SS_BLOCK;
1971 case USB_SPEED_UNKNOWN:
1972 case USB_SPEED_WIRELESS:
1973 default:
1974 /* Should never happen */
1975 return 1;
1976 }
1977 }
1978
1979 static unsigned int
1980 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
1981 {
1982 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
1983 return LS_OVERHEAD;
1984 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
1985 return FS_OVERHEAD;
1986 return HS_OVERHEAD;
1987 }
1988
1989 /* If we are changing a LS/FS device under a HS hub,
1990 * make sure (if we are activating a new TT) that the HS bus has enough
1991 * bandwidth for this new TT.
1992 */
1993 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
1994 struct xhci_virt_device *virt_dev,
1995 int old_active_eps)
1996 {
1997 struct xhci_interval_bw_table *bw_table;
1998 struct xhci_tt_bw_info *tt_info;
1999
2000 /* Find the bandwidth table for the root port this TT is attached to. */
2001 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2002 tt_info = virt_dev->tt_info;
2003 /* If this TT already had active endpoints, the bandwidth for this TT
2004 * has already been added. Removing all periodic endpoints (and thus
2005 * making the TT enactive) will only decrease the bandwidth used.
2006 */
2007 if (old_active_eps)
2008 return 0;
2009 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2010 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2011 return -ENOMEM;
2012 return 0;
2013 }
2014 /* Not sure why we would have no new active endpoints...
2015 *
2016 * Maybe because of an Evaluate Context change for a hub update or a
2017 * control endpoint 0 max packet size change?
2018 * FIXME: skip the bandwidth calculation in that case.
2019 */
2020 return 0;
2021 }
2022
2023 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2024 struct xhci_virt_device *virt_dev)
2025 {
2026 unsigned int bw_reserved;
2027
2028 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2029 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2030 return -ENOMEM;
2031
2032 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2033 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2034 return -ENOMEM;
2035
2036 return 0;
2037 }
2038
2039 /*
2040 * This algorithm is a very conservative estimate of the worst-case scheduling
2041 * scenario for any one interval. The hardware dynamically schedules the
2042 * packets, so we can't tell which microframe could be the limiting factor in
2043 * the bandwidth scheduling. This only takes into account periodic endpoints.
2044 *
2045 * Obviously, we can't solve an NP complete problem to find the minimum worst
2046 * case scenario. Instead, we come up with an estimate that is no less than
2047 * the worst case bandwidth used for any one microframe, but may be an
2048 * over-estimate.
2049 *
2050 * We walk the requirements for each endpoint by interval, starting with the
2051 * smallest interval, and place packets in the schedule where there is only one
2052 * possible way to schedule packets for that interval. In order to simplify
2053 * this algorithm, we record the largest max packet size for each interval, and
2054 * assume all packets will be that size.
2055 *
2056 * For interval 0, we obviously must schedule all packets for each interval.
2057 * The bandwidth for interval 0 is just the amount of data to be transmitted
2058 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2059 * the number of packets).
2060 *
2061 * For interval 1, we have two possible microframes to schedule those packets
2062 * in. For this algorithm, if we can schedule the same number of packets for
2063 * each possible scheduling opportunity (each microframe), we will do so. The
2064 * remaining number of packets will be saved to be transmitted in the gaps in
2065 * the next interval's scheduling sequence.
2066 *
2067 * As we move those remaining packets to be scheduled with interval 2 packets,
2068 * we have to double the number of remaining packets to transmit. This is
2069 * because the intervals are actually powers of 2, and we would be transmitting
2070 * the previous interval's packets twice in this interval. We also have to be
2071 * sure that when we look at the largest max packet size for this interval, we
2072 * also look at the largest max packet size for the remaining packets and take
2073 * the greater of the two.
2074 *
2075 * The algorithm continues to evenly distribute packets in each scheduling
2076 * opportunity, and push the remaining packets out, until we get to the last
2077 * interval. Then those packets and their associated overhead are just added
2078 * to the bandwidth used.
2079 */
2080 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2081 struct xhci_virt_device *virt_dev,
2082 int old_active_eps)
2083 {
2084 unsigned int bw_reserved;
2085 unsigned int max_bandwidth;
2086 unsigned int bw_used;
2087 unsigned int block_size;
2088 struct xhci_interval_bw_table *bw_table;
2089 unsigned int packet_size = 0;
2090 unsigned int overhead = 0;
2091 unsigned int packets_transmitted = 0;
2092 unsigned int packets_remaining = 0;
2093 unsigned int i;
2094
2095 if (virt_dev->udev->speed == USB_SPEED_SUPER)
2096 return xhci_check_ss_bw(xhci, virt_dev);
2097
2098 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2099 max_bandwidth = HS_BW_LIMIT;
2100 /* Convert percent of bus BW reserved to blocks reserved */
2101 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2102 } else {
2103 max_bandwidth = FS_BW_LIMIT;
2104 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2105 }
2106
2107 bw_table = virt_dev->bw_table;
2108 /* We need to translate the max packet size and max ESIT payloads into
2109 * the units the hardware uses.
2110 */
2111 block_size = xhci_get_block_size(virt_dev->udev);
2112
2113 /* If we are manipulating a LS/FS device under a HS hub, double check
2114 * that the HS bus has enough bandwidth if we are activing a new TT.
2115 */
2116 if (virt_dev->tt_info) {
2117 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
2118 virt_dev->real_port);
2119 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2120 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2121 "newly activated TT.\n");
2122 return -ENOMEM;
2123 }
2124 xhci_dbg(xhci, "Recalculating BW for TT slot %u port %u\n",
2125 virt_dev->tt_info->slot_id,
2126 virt_dev->tt_info->ttport);
2127 } else {
2128 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
2129 virt_dev->real_port);
2130 }
2131
2132 /* Add in how much bandwidth will be used for interval zero, or the
2133 * rounded max ESIT payload + number of packets * largest overhead.
2134 */
2135 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2136 bw_table->interval_bw[0].num_packets *
2137 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2138
2139 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2140 unsigned int bw_added;
2141 unsigned int largest_mps;
2142 unsigned int interval_overhead;
2143
2144 /*
2145 * How many packets could we transmit in this interval?
2146 * If packets didn't fit in the previous interval, we will need
2147 * to transmit that many packets twice within this interval.
2148 */
2149 packets_remaining = 2 * packets_remaining +
2150 bw_table->interval_bw[i].num_packets;
2151
2152 /* Find the largest max packet size of this or the previous
2153 * interval.
2154 */
2155 if (list_empty(&bw_table->interval_bw[i].endpoints))
2156 largest_mps = 0;
2157 else {
2158 struct xhci_virt_ep *virt_ep;
2159 struct list_head *ep_entry;
2160
2161 ep_entry = bw_table->interval_bw[i].endpoints.next;
2162 virt_ep = list_entry(ep_entry,
2163 struct xhci_virt_ep, bw_endpoint_list);
2164 /* Convert to blocks, rounding up */
2165 largest_mps = DIV_ROUND_UP(
2166 virt_ep->bw_info.max_packet_size,
2167 block_size);
2168 }
2169 if (largest_mps > packet_size)
2170 packet_size = largest_mps;
2171
2172 /* Use the larger overhead of this or the previous interval. */
2173 interval_overhead = xhci_get_largest_overhead(
2174 &bw_table->interval_bw[i]);
2175 if (interval_overhead > overhead)
2176 overhead = interval_overhead;
2177
2178 /* How many packets can we evenly distribute across
2179 * (1 << (i + 1)) possible scheduling opportunities?
2180 */
2181 packets_transmitted = packets_remaining >> (i + 1);
2182
2183 /* Add in the bandwidth used for those scheduled packets */
2184 bw_added = packets_transmitted * (overhead + packet_size);
2185
2186 /* How many packets do we have remaining to transmit? */
2187 packets_remaining = packets_remaining % (1 << (i + 1));
2188
2189 /* What largest max packet size should those packets have? */
2190 /* If we've transmitted all packets, don't carry over the
2191 * largest packet size.
2192 */
2193 if (packets_remaining == 0) {
2194 packet_size = 0;
2195 overhead = 0;
2196 } else if (packets_transmitted > 0) {
2197 /* Otherwise if we do have remaining packets, and we've
2198 * scheduled some packets in this interval, take the
2199 * largest max packet size from endpoints with this
2200 * interval.
2201 */
2202 packet_size = largest_mps;
2203 overhead = interval_overhead;
2204 }
2205 /* Otherwise carry over packet_size and overhead from the last
2206 * time we had a remainder.
2207 */
2208 bw_used += bw_added;
2209 if (bw_used > max_bandwidth) {
2210 xhci_warn(xhci, "Not enough bandwidth. "
2211 "Proposed: %u, Max: %u\n",
2212 bw_used, max_bandwidth);
2213 return -ENOMEM;
2214 }
2215 }
2216 /*
2217 * Ok, we know we have some packets left over after even-handedly
2218 * scheduling interval 15. We don't know which microframes they will
2219 * fit into, so we over-schedule and say they will be scheduled every
2220 * microframe.
2221 */
2222 if (packets_remaining > 0)
2223 bw_used += overhead + packet_size;
2224
2225 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2226 unsigned int port_index = virt_dev->real_port - 1;
2227
2228 /* OK, we're manipulating a HS device attached to a
2229 * root port bandwidth domain. Include the number of active TTs
2230 * in the bandwidth used.
2231 */
2232 bw_used += TT_HS_OVERHEAD *
2233 xhci->rh_bw[port_index].num_active_tts;
2234 }
2235
2236 xhci_dbg(xhci, "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2237 "Available: %u " "percent\n",
2238 bw_used, max_bandwidth, bw_reserved,
2239 (max_bandwidth - bw_used - bw_reserved) * 100 /
2240 max_bandwidth);
2241
2242 bw_used += bw_reserved;
2243 if (bw_used > max_bandwidth) {
2244 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2245 bw_used, max_bandwidth);
2246 return -ENOMEM;
2247 }
2248
2249 bw_table->bw_used = bw_used;
2250 return 0;
2251 }
2252
2253 static bool xhci_is_async_ep(unsigned int ep_type)
2254 {
2255 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2256 ep_type != ISOC_IN_EP &&
2257 ep_type != INT_IN_EP);
2258 }
2259
2260 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2261 {
2262 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2263 }
2264
2265 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2266 {
2267 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2268
2269 if (ep_bw->ep_interval == 0)
2270 return SS_OVERHEAD_BURST +
2271 (ep_bw->mult * ep_bw->num_packets *
2272 (SS_OVERHEAD + mps));
2273 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2274 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2275 1 << ep_bw->ep_interval);
2276
2277 }
2278
2279 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2280 struct xhci_bw_info *ep_bw,
2281 struct xhci_interval_bw_table *bw_table,
2282 struct usb_device *udev,
2283 struct xhci_virt_ep *virt_ep,
2284 struct xhci_tt_bw_info *tt_info)
2285 {
2286 struct xhci_interval_bw *interval_bw;
2287 int normalized_interval;
2288
2289 if (xhci_is_async_ep(ep_bw->type))
2290 return;
2291
2292 if (udev->speed == USB_SPEED_SUPER) {
2293 if (xhci_is_sync_in_ep(ep_bw->type))
2294 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2295 xhci_get_ss_bw_consumed(ep_bw);
2296 else
2297 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2298 xhci_get_ss_bw_consumed(ep_bw);
2299 return;
2300 }
2301
2302 /* SuperSpeed endpoints never get added to intervals in the table, so
2303 * this check is only valid for HS/FS/LS devices.
2304 */
2305 if (list_empty(&virt_ep->bw_endpoint_list))
2306 return;
2307 /* For LS/FS devices, we need to translate the interval expressed in
2308 * microframes to frames.
2309 */
2310 if (udev->speed == USB_SPEED_HIGH)
2311 normalized_interval = ep_bw->ep_interval;
2312 else
2313 normalized_interval = ep_bw->ep_interval - 3;
2314
2315 if (normalized_interval == 0)
2316 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2317 interval_bw = &bw_table->interval_bw[normalized_interval];
2318 interval_bw->num_packets -= ep_bw->num_packets;
2319 switch (udev->speed) {
2320 case USB_SPEED_LOW:
2321 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2322 break;
2323 case USB_SPEED_FULL:
2324 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2325 break;
2326 case USB_SPEED_HIGH:
2327 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2328 break;
2329 case USB_SPEED_SUPER:
2330 case USB_SPEED_UNKNOWN:
2331 case USB_SPEED_WIRELESS:
2332 /* Should never happen because only LS/FS/HS endpoints will get
2333 * added to the endpoint list.
2334 */
2335 return;
2336 }
2337 if (tt_info)
2338 tt_info->active_eps -= 1;
2339 list_del_init(&virt_ep->bw_endpoint_list);
2340 }
2341
2342 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2343 struct xhci_bw_info *ep_bw,
2344 struct xhci_interval_bw_table *bw_table,
2345 struct usb_device *udev,
2346 struct xhci_virt_ep *virt_ep,
2347 struct xhci_tt_bw_info *tt_info)
2348 {
2349 struct xhci_interval_bw *interval_bw;
2350 struct xhci_virt_ep *smaller_ep;
2351 int normalized_interval;
2352
2353 if (xhci_is_async_ep(ep_bw->type))
2354 return;
2355
2356 if (udev->speed == USB_SPEED_SUPER) {
2357 if (xhci_is_sync_in_ep(ep_bw->type))
2358 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2359 xhci_get_ss_bw_consumed(ep_bw);
2360 else
2361 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2362 xhci_get_ss_bw_consumed(ep_bw);
2363 return;
2364 }
2365
2366 /* For LS/FS devices, we need to translate the interval expressed in
2367 * microframes to frames.
2368 */
2369 if (udev->speed == USB_SPEED_HIGH)
2370 normalized_interval = ep_bw->ep_interval;
2371 else
2372 normalized_interval = ep_bw->ep_interval - 3;
2373
2374 if (normalized_interval == 0)
2375 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2376 interval_bw = &bw_table->interval_bw[normalized_interval];
2377 interval_bw->num_packets += ep_bw->num_packets;
2378 switch (udev->speed) {
2379 case USB_SPEED_LOW:
2380 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2381 break;
2382 case USB_SPEED_FULL:
2383 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2384 break;
2385 case USB_SPEED_HIGH:
2386 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2387 break;
2388 case USB_SPEED_SUPER:
2389 case USB_SPEED_UNKNOWN:
2390 case USB_SPEED_WIRELESS:
2391 /* Should never happen because only LS/FS/HS endpoints will get
2392 * added to the endpoint list.
2393 */
2394 return;
2395 }
2396
2397 if (tt_info)
2398 tt_info->active_eps += 1;
2399 /* Insert the endpoint into the list, largest max packet size first. */
2400 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2401 bw_endpoint_list) {
2402 if (ep_bw->max_packet_size >=
2403 smaller_ep->bw_info.max_packet_size) {
2404 /* Add the new ep before the smaller endpoint */
2405 list_add_tail(&virt_ep->bw_endpoint_list,
2406 &smaller_ep->bw_endpoint_list);
2407 return;
2408 }
2409 }
2410 /* Add the new endpoint at the end of the list. */
2411 list_add_tail(&virt_ep->bw_endpoint_list,
2412 &interval_bw->endpoints);
2413 }
2414
2415 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2416 struct xhci_virt_device *virt_dev,
2417 int old_active_eps)
2418 {
2419 struct xhci_root_port_bw_info *rh_bw_info;
2420 if (!virt_dev->tt_info)
2421 return;
2422
2423 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2424 if (old_active_eps == 0 &&
2425 virt_dev->tt_info->active_eps != 0) {
2426 rh_bw_info->num_active_tts += 1;
2427 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2428 } else if (old_active_eps != 0 &&
2429 virt_dev->tt_info->active_eps == 0) {
2430 rh_bw_info->num_active_tts -= 1;
2431 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2432 }
2433 }
2434
2435 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2436 struct xhci_virt_device *virt_dev,
2437 struct xhci_container_ctx *in_ctx)
2438 {
2439 struct xhci_bw_info ep_bw_info[31];
2440 int i;
2441 struct xhci_input_control_ctx *ctrl_ctx;
2442 int old_active_eps = 0;
2443
2444 if (virt_dev->tt_info)
2445 old_active_eps = virt_dev->tt_info->active_eps;
2446
2447 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2448
2449 for (i = 0; i < 31; i++) {
2450 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2451 continue;
2452
2453 /* Make a copy of the BW info in case we need to revert this */
2454 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2455 sizeof(ep_bw_info[i]));
2456 /* Drop the endpoint from the interval table if the endpoint is
2457 * being dropped or changed.
2458 */
2459 if (EP_IS_DROPPED(ctrl_ctx, i))
2460 xhci_drop_ep_from_interval_table(xhci,
2461 &virt_dev->eps[i].bw_info,
2462 virt_dev->bw_table,
2463 virt_dev->udev,
2464 &virt_dev->eps[i],
2465 virt_dev->tt_info);
2466 }
2467 /* Overwrite the information stored in the endpoints' bw_info */
2468 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2469 for (i = 0; i < 31; i++) {
2470 /* Add any changed or added endpoints to the interval table */
2471 if (EP_IS_ADDED(ctrl_ctx, i))
2472 xhci_add_ep_to_interval_table(xhci,
2473 &virt_dev->eps[i].bw_info,
2474 virt_dev->bw_table,
2475 virt_dev->udev,
2476 &virt_dev->eps[i],
2477 virt_dev->tt_info);
2478 }
2479
2480 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2481 /* Ok, this fits in the bandwidth we have.
2482 * Update the number of active TTs.
2483 */
2484 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2485 return 0;
2486 }
2487
2488 /* We don't have enough bandwidth for this, revert the stored info. */
2489 for (i = 0; i < 31; i++) {
2490 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2491 continue;
2492
2493 /* Drop the new copies of any added or changed endpoints from
2494 * the interval table.
2495 */
2496 if (EP_IS_ADDED(ctrl_ctx, i)) {
2497 xhci_drop_ep_from_interval_table(xhci,
2498 &virt_dev->eps[i].bw_info,
2499 virt_dev->bw_table,
2500 virt_dev->udev,
2501 &virt_dev->eps[i],
2502 virt_dev->tt_info);
2503 }
2504 /* Revert the endpoint back to its old information */
2505 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2506 sizeof(ep_bw_info[i]));
2507 /* Add any changed or dropped endpoints back into the table */
2508 if (EP_IS_DROPPED(ctrl_ctx, i))
2509 xhci_add_ep_to_interval_table(xhci,
2510 &virt_dev->eps[i].bw_info,
2511 virt_dev->bw_table,
2512 virt_dev->udev,
2513 &virt_dev->eps[i],
2514 virt_dev->tt_info);
2515 }
2516 return -ENOMEM;
2517 }
2518
2519
2520 /* Issue a configure endpoint command or evaluate context command
2521 * and wait for it to finish.
2522 */
2523 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2524 struct usb_device *udev,
2525 struct xhci_command *command,
2526 bool ctx_change, bool must_succeed)
2527 {
2528 int ret;
2529 int timeleft;
2530 unsigned long flags;
2531 struct xhci_container_ctx *in_ctx;
2532 struct completion *cmd_completion;
2533 u32 *cmd_status;
2534 struct xhci_virt_device *virt_dev;
2535 union xhci_trb *cmd_trb;
2536
2537 spin_lock_irqsave(&xhci->lock, flags);
2538 virt_dev = xhci->devs[udev->slot_id];
2539
2540 if (command)
2541 in_ctx = command->in_ctx;
2542 else
2543 in_ctx = virt_dev->in_ctx;
2544
2545 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2546 xhci_reserve_host_resources(xhci, in_ctx)) {
2547 spin_unlock_irqrestore(&xhci->lock, flags);
2548 xhci_warn(xhci, "Not enough host resources, "
2549 "active endpoint contexts = %u\n",
2550 xhci->num_active_eps);
2551 return -ENOMEM;
2552 }
2553 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2554 xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
2555 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2556 xhci_free_host_resources(xhci, in_ctx);
2557 spin_unlock_irqrestore(&xhci->lock, flags);
2558 xhci_warn(xhci, "Not enough bandwidth\n");
2559 return -ENOMEM;
2560 }
2561
2562 if (command) {
2563 cmd_completion = command->completion;
2564 cmd_status = &command->status;
2565 command->command_trb = xhci->cmd_ring->enqueue;
2566
2567 /* Enqueue pointer can be left pointing to the link TRB,
2568 * we must handle that
2569 */
2570 if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
2571 command->command_trb =
2572 xhci->cmd_ring->enq_seg->next->trbs;
2573
2574 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
2575 } else {
2576 cmd_completion = &virt_dev->cmd_completion;
2577 cmd_status = &virt_dev->cmd_status;
2578 }
2579 init_completion(cmd_completion);
2580
2581 cmd_trb = xhci->cmd_ring->dequeue;
2582 if (!ctx_change)
2583 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
2584 udev->slot_id, must_succeed);
2585 else
2586 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
2587 udev->slot_id, must_succeed);
2588 if (ret < 0) {
2589 if (command)
2590 list_del(&command->cmd_list);
2591 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2592 xhci_free_host_resources(xhci, in_ctx);
2593 spin_unlock_irqrestore(&xhci->lock, flags);
2594 xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
2595 return -ENOMEM;
2596 }
2597 xhci_ring_cmd_db(xhci);
2598 spin_unlock_irqrestore(&xhci->lock, flags);
2599
2600 /* Wait for the configure endpoint command to complete */
2601 timeleft = wait_for_completion_interruptible_timeout(
2602 cmd_completion,
2603 XHCI_CMD_DEFAULT_TIMEOUT);
2604 if (timeleft <= 0) {
2605 xhci_warn(xhci, "%s while waiting for %s command\n",
2606 timeleft == 0 ? "Timeout" : "Signal",
2607 ctx_change == 0 ?
2608 "configure endpoint" :
2609 "evaluate context");
2610 /* cancel the configure endpoint command */
2611 ret = xhci_cancel_cmd(xhci, command, cmd_trb);
2612 if (ret < 0)
2613 return ret;
2614 return -ETIME;
2615 }
2616
2617 if (!ctx_change)
2618 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
2619 else
2620 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
2621
2622 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2623 spin_lock_irqsave(&xhci->lock, flags);
2624 /* If the command failed, remove the reserved resources.
2625 * Otherwise, clean up the estimate to include dropped eps.
2626 */
2627 if (ret)
2628 xhci_free_host_resources(xhci, in_ctx);
2629 else
2630 xhci_finish_resource_reservation(xhci, in_ctx);
2631 spin_unlock_irqrestore(&xhci->lock, flags);
2632 }
2633 return ret;
2634 }
2635
2636 /* Called after one or more calls to xhci_add_endpoint() or
2637 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2638 * to call xhci_reset_bandwidth().
2639 *
2640 * Since we are in the middle of changing either configuration or
2641 * installing a new alt setting, the USB core won't allow URBs to be
2642 * enqueued for any endpoint on the old config or interface. Nothing
2643 * else should be touching the xhci->devs[slot_id] structure, so we
2644 * don't need to take the xhci->lock for manipulating that.
2645 */
2646 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2647 {
2648 int i;
2649 int ret = 0;
2650 struct xhci_hcd *xhci;
2651 struct xhci_virt_device *virt_dev;
2652 struct xhci_input_control_ctx *ctrl_ctx;
2653 struct xhci_slot_ctx *slot_ctx;
2654
2655 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2656 if (ret <= 0)
2657 return ret;
2658 xhci = hcd_to_xhci(hcd);
2659 if (xhci->xhc_state & XHCI_STATE_DYING)
2660 return -ENODEV;
2661
2662 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2663 virt_dev = xhci->devs[udev->slot_id];
2664
2665 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2666 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
2667 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2668 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2669 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2670
2671 /* Don't issue the command if there's no endpoints to update. */
2672 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2673 ctrl_ctx->drop_flags == 0)
2674 return 0;
2675
2676 xhci_dbg(xhci, "New Input Control Context:\n");
2677 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2678 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2679 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2680
2681 ret = xhci_configure_endpoint(xhci, udev, NULL,
2682 false, false);
2683 if (ret) {
2684 /* Callee should call reset_bandwidth() */
2685 return ret;
2686 }
2687
2688 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2689 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2690 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2691
2692 /* Free any rings that were dropped, but not changed. */
2693 for (i = 1; i < 31; ++i) {
2694 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2695 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
2696 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2697 }
2698 xhci_zero_in_ctx(xhci, virt_dev);
2699 /*
2700 * Install any rings for completely new endpoints or changed endpoints,
2701 * and free or cache any old rings from changed endpoints.
2702 */
2703 for (i = 1; i < 31; ++i) {
2704 if (!virt_dev->eps[i].new_ring)
2705 continue;
2706 /* Only cache or free the old ring if it exists.
2707 * It may not if this is the first add of an endpoint.
2708 */
2709 if (virt_dev->eps[i].ring) {
2710 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2711 }
2712 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2713 virt_dev->eps[i].new_ring = NULL;
2714 }
2715
2716 return ret;
2717 }
2718
2719 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2720 {
2721 struct xhci_hcd *xhci;
2722 struct xhci_virt_device *virt_dev;
2723 int i, ret;
2724
2725 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2726 if (ret <= 0)
2727 return;
2728 xhci = hcd_to_xhci(hcd);
2729
2730 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2731 virt_dev = xhci->devs[udev->slot_id];
2732 /* Free any rings allocated for added endpoints */
2733 for (i = 0; i < 31; ++i) {
2734 if (virt_dev->eps[i].new_ring) {
2735 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2736 virt_dev->eps[i].new_ring = NULL;
2737 }
2738 }
2739 xhci_zero_in_ctx(xhci, virt_dev);
2740 }
2741
2742 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2743 struct xhci_container_ctx *in_ctx,
2744 struct xhci_container_ctx *out_ctx,
2745 u32 add_flags, u32 drop_flags)
2746 {
2747 struct xhci_input_control_ctx *ctrl_ctx;
2748 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2749 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2750 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2751 xhci_slot_copy(xhci, in_ctx, out_ctx);
2752 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2753
2754 xhci_dbg(xhci, "Input Context:\n");
2755 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2756 }
2757
2758 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2759 unsigned int slot_id, unsigned int ep_index,
2760 struct xhci_dequeue_state *deq_state)
2761 {
2762 struct xhci_container_ctx *in_ctx;
2763 struct xhci_ep_ctx *ep_ctx;
2764 u32 added_ctxs;
2765 dma_addr_t addr;
2766
2767 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2768 xhci->devs[slot_id]->out_ctx, ep_index);
2769 in_ctx = xhci->devs[slot_id]->in_ctx;
2770 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2771 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2772 deq_state->new_deq_ptr);
2773 if (addr == 0) {
2774 xhci_warn(xhci, "WARN Cannot submit config ep after "
2775 "reset ep command\n");
2776 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2777 deq_state->new_deq_seg,
2778 deq_state->new_deq_ptr);
2779 return;
2780 }
2781 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2782
2783 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2784 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2785 xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
2786 }
2787
2788 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2789 struct usb_device *udev, unsigned int ep_index)
2790 {
2791 struct xhci_dequeue_state deq_state;
2792 struct xhci_virt_ep *ep;
2793
2794 xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
2795 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2796 /* We need to move the HW's dequeue pointer past this TD,
2797 * or it will attempt to resend it on the next doorbell ring.
2798 */
2799 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2800 ep_index, ep->stopped_stream, ep->stopped_td,
2801 &deq_state);
2802
2803 /* HW with the reset endpoint quirk will use the saved dequeue state to
2804 * issue a configure endpoint command later.
2805 */
2806 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2807 xhci_dbg(xhci, "Queueing new dequeue state\n");
2808 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2809 ep_index, ep->stopped_stream, &deq_state);
2810 } else {
2811 /* Better hope no one uses the input context between now and the
2812 * reset endpoint completion!
2813 * XXX: No idea how this hardware will react when stream rings
2814 * are enabled.
2815 */
2816 xhci_dbg(xhci, "Setting up input context for "
2817 "configure endpoint command\n");
2818 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2819 ep_index, &deq_state);
2820 }
2821 }
2822
2823 /* Deal with stalled endpoints. The core should have sent the control message
2824 * to clear the halt condition. However, we need to make the xHCI hardware
2825 * reset its sequence number, since a device will expect a sequence number of
2826 * zero after the halt condition is cleared.
2827 * Context: in_interrupt
2828 */
2829 void xhci_endpoint_reset(struct usb_hcd *hcd,
2830 struct usb_host_endpoint *ep)
2831 {
2832 struct xhci_hcd *xhci;
2833 struct usb_device *udev;
2834 unsigned int ep_index;
2835 unsigned long flags;
2836 int ret;
2837 struct xhci_virt_ep *virt_ep;
2838
2839 xhci = hcd_to_xhci(hcd);
2840 udev = (struct usb_device *) ep->hcpriv;
2841 /* Called with a root hub endpoint (or an endpoint that wasn't added
2842 * with xhci_add_endpoint()
2843 */
2844 if (!ep->hcpriv)
2845 return;
2846 ep_index = xhci_get_endpoint_index(&ep->desc);
2847 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2848 if (!virt_ep->stopped_td) {
2849 xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
2850 ep->desc.bEndpointAddress);
2851 return;
2852 }
2853 if (usb_endpoint_xfer_control(&ep->desc)) {
2854 xhci_dbg(xhci, "Control endpoint stall already handled.\n");
2855 return;
2856 }
2857
2858 xhci_dbg(xhci, "Queueing reset endpoint command\n");
2859 spin_lock_irqsave(&xhci->lock, flags);
2860 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
2861 /*
2862 * Can't change the ring dequeue pointer until it's transitioned to the
2863 * stopped state, which is only upon a successful reset endpoint
2864 * command. Better hope that last command worked!
2865 */
2866 if (!ret) {
2867 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2868 kfree(virt_ep->stopped_td);
2869 xhci_ring_cmd_db(xhci);
2870 }
2871 virt_ep->stopped_td = NULL;
2872 virt_ep->stopped_trb = NULL;
2873 virt_ep->stopped_stream = 0;
2874 spin_unlock_irqrestore(&xhci->lock, flags);
2875
2876 if (ret)
2877 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2878 }
2879
2880 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2881 struct usb_device *udev, struct usb_host_endpoint *ep,
2882 unsigned int slot_id)
2883 {
2884 int ret;
2885 unsigned int ep_index;
2886 unsigned int ep_state;
2887
2888 if (!ep)
2889 return -EINVAL;
2890 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2891 if (ret <= 0)
2892 return -EINVAL;
2893 if (ep->ss_ep_comp.bmAttributes == 0) {
2894 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2895 " descriptor for ep 0x%x does not support streams\n",
2896 ep->desc.bEndpointAddress);
2897 return -EINVAL;
2898 }
2899
2900 ep_index = xhci_get_endpoint_index(&ep->desc);
2901 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2902 if (ep_state & EP_HAS_STREAMS ||
2903 ep_state & EP_GETTING_STREAMS) {
2904 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2905 "already has streams set up.\n",
2906 ep->desc.bEndpointAddress);
2907 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2908 "dynamic stream context array reallocation.\n");
2909 return -EINVAL;
2910 }
2911 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2912 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2913 "endpoint 0x%x; URBs are pending.\n",
2914 ep->desc.bEndpointAddress);
2915 return -EINVAL;
2916 }
2917 return 0;
2918 }
2919
2920 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2921 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2922 {
2923 unsigned int max_streams;
2924
2925 /* The stream context array size must be a power of two */
2926 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2927 /*
2928 * Find out how many primary stream array entries the host controller
2929 * supports. Later we may use secondary stream arrays (similar to 2nd
2930 * level page entries), but that's an optional feature for xHCI host
2931 * controllers. xHCs must support at least 4 stream IDs.
2932 */
2933 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2934 if (*num_stream_ctxs > max_streams) {
2935 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2936 max_streams);
2937 *num_stream_ctxs = max_streams;
2938 *num_streams = max_streams;
2939 }
2940 }
2941
2942 /* Returns an error code if one of the endpoint already has streams.
2943 * This does not change any data structures, it only checks and gathers
2944 * information.
2945 */
2946 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2947 struct usb_device *udev,
2948 struct usb_host_endpoint **eps, unsigned int num_eps,
2949 unsigned int *num_streams, u32 *changed_ep_bitmask)
2950 {
2951 unsigned int max_streams;
2952 unsigned int endpoint_flag;
2953 int i;
2954 int ret;
2955
2956 for (i = 0; i < num_eps; i++) {
2957 ret = xhci_check_streams_endpoint(xhci, udev,
2958 eps[i], udev->slot_id);
2959 if (ret < 0)
2960 return ret;
2961
2962 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
2963 if (max_streams < (*num_streams - 1)) {
2964 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
2965 eps[i]->desc.bEndpointAddress,
2966 max_streams);
2967 *num_streams = max_streams+1;
2968 }
2969
2970 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
2971 if (*changed_ep_bitmask & endpoint_flag)
2972 return -EINVAL;
2973 *changed_ep_bitmask |= endpoint_flag;
2974 }
2975 return 0;
2976 }
2977
2978 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
2979 struct usb_device *udev,
2980 struct usb_host_endpoint **eps, unsigned int num_eps)
2981 {
2982 u32 changed_ep_bitmask = 0;
2983 unsigned int slot_id;
2984 unsigned int ep_index;
2985 unsigned int ep_state;
2986 int i;
2987
2988 slot_id = udev->slot_id;
2989 if (!xhci->devs[slot_id])
2990 return 0;
2991
2992 for (i = 0; i < num_eps; i++) {
2993 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2994 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2995 /* Are streams already being freed for the endpoint? */
2996 if (ep_state & EP_GETTING_NO_STREAMS) {
2997 xhci_warn(xhci, "WARN Can't disable streams for "
2998 "endpoint 0x%x\n, "
2999 "streams are being disabled already.",
3000 eps[i]->desc.bEndpointAddress);
3001 return 0;
3002 }
3003 /* Are there actually any streams to free? */
3004 if (!(ep_state & EP_HAS_STREAMS) &&
3005 !(ep_state & EP_GETTING_STREAMS)) {
3006 xhci_warn(xhci, "WARN Can't disable streams for "
3007 "endpoint 0x%x\n, "
3008 "streams are already disabled!",
3009 eps[i]->desc.bEndpointAddress);
3010 xhci_warn(xhci, "WARN xhci_free_streams() called "
3011 "with non-streams endpoint\n");
3012 return 0;
3013 }
3014 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3015 }
3016 return changed_ep_bitmask;
3017 }
3018
3019 /*
3020 * The USB device drivers use this function (though the HCD interface in USB
3021 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3022 * coordinate mass storage command queueing across multiple endpoints (basically
3023 * a stream ID == a task ID).
3024 *
3025 * Setting up streams involves allocating the same size stream context array
3026 * for each endpoint and issuing a configure endpoint command for all endpoints.
3027 *
3028 * Don't allow the call to succeed if one endpoint only supports one stream
3029 * (which means it doesn't support streams at all).
3030 *
3031 * Drivers may get less stream IDs than they asked for, if the host controller
3032 * hardware or endpoints claim they can't support the number of requested
3033 * stream IDs.
3034 */
3035 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3036 struct usb_host_endpoint **eps, unsigned int num_eps,
3037 unsigned int num_streams, gfp_t mem_flags)
3038 {
3039 int i, ret;
3040 struct xhci_hcd *xhci;
3041 struct xhci_virt_device *vdev;
3042 struct xhci_command *config_cmd;
3043 unsigned int ep_index;
3044 unsigned int num_stream_ctxs;
3045 unsigned long flags;
3046 u32 changed_ep_bitmask = 0;
3047
3048 if (!eps)
3049 return -EINVAL;
3050
3051 /* Add one to the number of streams requested to account for
3052 * stream 0 that is reserved for xHCI usage.
3053 */
3054 num_streams += 1;
3055 xhci = hcd_to_xhci(hcd);
3056 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3057 num_streams);
3058
3059 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3060 if (!config_cmd) {
3061 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3062 return -ENOMEM;
3063 }
3064
3065 /* Check to make sure all endpoints are not already configured for
3066 * streams. While we're at it, find the maximum number of streams that
3067 * all the endpoints will support and check for duplicate endpoints.
3068 */
3069 spin_lock_irqsave(&xhci->lock, flags);
3070 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3071 num_eps, &num_streams, &changed_ep_bitmask);
3072 if (ret < 0) {
3073 xhci_free_command(xhci, config_cmd);
3074 spin_unlock_irqrestore(&xhci->lock, flags);
3075 return ret;
3076 }
3077 if (num_streams <= 1) {
3078 xhci_warn(xhci, "WARN: endpoints can't handle "
3079 "more than one stream.\n");
3080 xhci_free_command(xhci, config_cmd);
3081 spin_unlock_irqrestore(&xhci->lock, flags);
3082 return -EINVAL;
3083 }
3084 vdev = xhci->devs[udev->slot_id];
3085 /* Mark each endpoint as being in transition, so
3086 * xhci_urb_enqueue() will reject all URBs.
3087 */
3088 for (i = 0; i < num_eps; i++) {
3089 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3090 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3091 }
3092 spin_unlock_irqrestore(&xhci->lock, flags);
3093
3094 /* Setup internal data structures and allocate HW data structures for
3095 * streams (but don't install the HW structures in the input context
3096 * until we're sure all memory allocation succeeded).
3097 */
3098 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3099 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3100 num_stream_ctxs, num_streams);
3101
3102 for (i = 0; i < num_eps; i++) {
3103 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3104 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3105 num_stream_ctxs,
3106 num_streams, mem_flags);
3107 if (!vdev->eps[ep_index].stream_info)
3108 goto cleanup;
3109 /* Set maxPstreams in endpoint context and update deq ptr to
3110 * point to stream context array. FIXME
3111 */
3112 }
3113
3114 /* Set up the input context for a configure endpoint command. */
3115 for (i = 0; i < num_eps; i++) {
3116 struct xhci_ep_ctx *ep_ctx;
3117
3118 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3119 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3120
3121 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3122 vdev->out_ctx, ep_index);
3123 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3124 vdev->eps[ep_index].stream_info);
3125 }
3126 /* Tell the HW to drop its old copy of the endpoint context info
3127 * and add the updated copy from the input context.
3128 */
3129 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3130 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
3131
3132 /* Issue and wait for the configure endpoint command */
3133 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3134 false, false);
3135
3136 /* xHC rejected the configure endpoint command for some reason, so we
3137 * leave the old ring intact and free our internal streams data
3138 * structure.
3139 */
3140 if (ret < 0)
3141 goto cleanup;
3142
3143 spin_lock_irqsave(&xhci->lock, flags);
3144 for (i = 0; i < num_eps; i++) {
3145 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3146 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3147 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3148 udev->slot_id, ep_index);
3149 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3150 }
3151 xhci_free_command(xhci, config_cmd);
3152 spin_unlock_irqrestore(&xhci->lock, flags);
3153
3154 /* Subtract 1 for stream 0, which drivers can't use */
3155 return num_streams - 1;
3156
3157 cleanup:
3158 /* If it didn't work, free the streams! */
3159 for (i = 0; i < num_eps; i++) {
3160 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3161 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3162 vdev->eps[ep_index].stream_info = NULL;
3163 /* FIXME Unset maxPstreams in endpoint context and
3164 * update deq ptr to point to normal string ring.
3165 */
3166 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3167 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3168 xhci_endpoint_zero(xhci, vdev, eps[i]);
3169 }
3170 xhci_free_command(xhci, config_cmd);
3171 return -ENOMEM;
3172 }
3173
3174 /* Transition the endpoint from using streams to being a "normal" endpoint
3175 * without streams.
3176 *
3177 * Modify the endpoint context state, submit a configure endpoint command,
3178 * and free all endpoint rings for streams if that completes successfully.
3179 */
3180 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3181 struct usb_host_endpoint **eps, unsigned int num_eps,
3182 gfp_t mem_flags)
3183 {
3184 int i, ret;
3185 struct xhci_hcd *xhci;
3186 struct xhci_virt_device *vdev;
3187 struct xhci_command *command;
3188 unsigned int ep_index;
3189 unsigned long flags;
3190 u32 changed_ep_bitmask;
3191
3192 xhci = hcd_to_xhci(hcd);
3193 vdev = xhci->devs[udev->slot_id];
3194
3195 /* Set up a configure endpoint command to remove the streams rings */
3196 spin_lock_irqsave(&xhci->lock, flags);
3197 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3198 udev, eps, num_eps);
3199 if (changed_ep_bitmask == 0) {
3200 spin_unlock_irqrestore(&xhci->lock, flags);
3201 return -EINVAL;
3202 }
3203
3204 /* Use the xhci_command structure from the first endpoint. We may have
3205 * allocated too many, but the driver may call xhci_free_streams() for
3206 * each endpoint it grouped into one call to xhci_alloc_streams().
3207 */
3208 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3209 command = vdev->eps[ep_index].stream_info->free_streams_command;
3210 for (i = 0; i < num_eps; i++) {
3211 struct xhci_ep_ctx *ep_ctx;
3212
3213 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3214 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3215 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3216 EP_GETTING_NO_STREAMS;
3217
3218 xhci_endpoint_copy(xhci, command->in_ctx,
3219 vdev->out_ctx, ep_index);
3220 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
3221 &vdev->eps[ep_index]);
3222 }
3223 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3224 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
3225 spin_unlock_irqrestore(&xhci->lock, flags);
3226
3227 /* Issue and wait for the configure endpoint command,
3228 * which must succeed.
3229 */
3230 ret = xhci_configure_endpoint(xhci, udev, command,
3231 false, true);
3232
3233 /* xHC rejected the configure endpoint command for some reason, so we
3234 * leave the streams rings intact.
3235 */
3236 if (ret < 0)
3237 return ret;
3238
3239 spin_lock_irqsave(&xhci->lock, flags);
3240 for (i = 0; i < num_eps; i++) {
3241 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3242 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3243 vdev->eps[ep_index].stream_info = NULL;
3244 /* FIXME Unset maxPstreams in endpoint context and
3245 * update deq ptr to point to normal string ring.
3246 */
3247 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3248 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3249 }
3250 spin_unlock_irqrestore(&xhci->lock, flags);
3251
3252 return 0;
3253 }
3254
3255 /*
3256 * Deletes endpoint resources for endpoints that were active before a Reset
3257 * Device command, or a Disable Slot command. The Reset Device command leaves
3258 * the control endpoint intact, whereas the Disable Slot command deletes it.
3259 *
3260 * Must be called with xhci->lock held.
3261 */
3262 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3263 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3264 {
3265 int i;
3266 unsigned int num_dropped_eps = 0;
3267 unsigned int drop_flags = 0;
3268
3269 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3270 if (virt_dev->eps[i].ring) {
3271 drop_flags |= 1 << i;
3272 num_dropped_eps++;
3273 }
3274 }
3275 xhci->num_active_eps -= num_dropped_eps;
3276 if (num_dropped_eps)
3277 xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
3278 "%u now active.\n",
3279 num_dropped_eps, drop_flags,
3280 xhci->num_active_eps);
3281 }
3282
3283 /*
3284 * This submits a Reset Device Command, which will set the device state to 0,
3285 * set the device address to 0, and disable all the endpoints except the default
3286 * control endpoint. The USB core should come back and call
3287 * xhci_address_device(), and then re-set up the configuration. If this is
3288 * called because of a usb_reset_and_verify_device(), then the old alternate
3289 * settings will be re-installed through the normal bandwidth allocation
3290 * functions.
3291 *
3292 * Wait for the Reset Device command to finish. Remove all structures
3293 * associated with the endpoints that were disabled. Clear the input device
3294 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3295 *
3296 * If the virt_dev to be reset does not exist or does not match the udev,
3297 * it means the device is lost, possibly due to the xHC restore error and
3298 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3299 * re-allocate the device.
3300 */
3301 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3302 {
3303 int ret, i;
3304 unsigned long flags;
3305 struct xhci_hcd *xhci;
3306 unsigned int slot_id;
3307 struct xhci_virt_device *virt_dev;
3308 struct xhci_command *reset_device_cmd;
3309 int timeleft;
3310 int last_freed_endpoint;
3311 struct xhci_slot_ctx *slot_ctx;
3312 int old_active_eps = 0;
3313
3314 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3315 if (ret <= 0)
3316 return ret;
3317 xhci = hcd_to_xhci(hcd);
3318 slot_id = udev->slot_id;
3319 virt_dev = xhci->devs[slot_id];
3320 if (!virt_dev) {
3321 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3322 "not exist. Re-allocate the device\n", slot_id);
3323 ret = xhci_alloc_dev(hcd, udev);
3324 if (ret == 1)
3325 return 0;
3326 else
3327 return -EINVAL;
3328 }
3329
3330 if (virt_dev->udev != udev) {
3331 /* If the virt_dev and the udev does not match, this virt_dev
3332 * may belong to another udev.
3333 * Re-allocate the device.
3334 */
3335 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3336 "not match the udev. Re-allocate the device\n",
3337 slot_id);
3338 ret = xhci_alloc_dev(hcd, udev);
3339 if (ret == 1)
3340 return 0;
3341 else
3342 return -EINVAL;
3343 }
3344
3345 /* If device is not setup, there is no point in resetting it */
3346 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3347 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3348 SLOT_STATE_DISABLED)
3349 return 0;
3350
3351 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3352 /* Allocate the command structure that holds the struct completion.
3353 * Assume we're in process context, since the normal device reset
3354 * process has to wait for the device anyway. Storage devices are
3355 * reset as part of error handling, so use GFP_NOIO instead of
3356 * GFP_KERNEL.
3357 */
3358 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3359 if (!reset_device_cmd) {
3360 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3361 return -ENOMEM;
3362 }
3363
3364 /* Attempt to submit the Reset Device command to the command ring */
3365 spin_lock_irqsave(&xhci->lock, flags);
3366 reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
3367
3368 /* Enqueue pointer can be left pointing to the link TRB,
3369 * we must handle that
3370 */
3371 if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
3372 reset_device_cmd->command_trb =
3373 xhci->cmd_ring->enq_seg->next->trbs;
3374
3375 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
3376 ret = xhci_queue_reset_device(xhci, slot_id);
3377 if (ret) {
3378 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3379 list_del(&reset_device_cmd->cmd_list);
3380 spin_unlock_irqrestore(&xhci->lock, flags);
3381 goto command_cleanup;
3382 }
3383 xhci_ring_cmd_db(xhci);
3384 spin_unlock_irqrestore(&xhci->lock, flags);
3385
3386 /* Wait for the Reset Device command to finish */
3387 timeleft = wait_for_completion_interruptible_timeout(
3388 reset_device_cmd->completion,
3389 USB_CTRL_SET_TIMEOUT);
3390 if (timeleft <= 0) {
3391 xhci_warn(xhci, "%s while waiting for reset device command\n",
3392 timeleft == 0 ? "Timeout" : "Signal");
3393 spin_lock_irqsave(&xhci->lock, flags);
3394 /* The timeout might have raced with the event ring handler, so
3395 * only delete from the list if the item isn't poisoned.
3396 */
3397 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
3398 list_del(&reset_device_cmd->cmd_list);
3399 spin_unlock_irqrestore(&xhci->lock, flags);
3400 ret = -ETIME;
3401 goto command_cleanup;
3402 }
3403
3404 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3405 * unless we tried to reset a slot ID that wasn't enabled,
3406 * or the device wasn't in the addressed or configured state.
3407 */
3408 ret = reset_device_cmd->status;
3409 switch (ret) {
3410 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3411 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3412 xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
3413 slot_id,
3414 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3415 xhci_info(xhci, "Not freeing device rings.\n");
3416 /* Don't treat this as an error. May change my mind later. */
3417 ret = 0;
3418 goto command_cleanup;
3419 case COMP_SUCCESS:
3420 xhci_dbg(xhci, "Successful reset device command.\n");
3421 break;
3422 default:
3423 if (xhci_is_vendor_info_code(xhci, ret))
3424 break;
3425 xhci_warn(xhci, "Unknown completion code %u for "
3426 "reset device command.\n", ret);
3427 ret = -EINVAL;
3428 goto command_cleanup;
3429 }
3430
3431 /* Free up host controller endpoint resources */
3432 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3433 spin_lock_irqsave(&xhci->lock, flags);
3434 /* Don't delete the default control endpoint resources */
3435 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3436 spin_unlock_irqrestore(&xhci->lock, flags);
3437 }
3438
3439 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3440 last_freed_endpoint = 1;
3441 for (i = 1; i < 31; ++i) {
3442 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3443
3444 if (ep->ep_state & EP_HAS_STREAMS) {
3445 xhci_free_stream_info(xhci, ep->stream_info);
3446 ep->stream_info = NULL;
3447 ep->ep_state &= ~EP_HAS_STREAMS;
3448 }
3449
3450 if (ep->ring) {
3451 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3452 last_freed_endpoint = i;
3453 }
3454 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3455 xhci_drop_ep_from_interval_table(xhci,
3456 &virt_dev->eps[i].bw_info,
3457 virt_dev->bw_table,
3458 udev,
3459 &virt_dev->eps[i],
3460 virt_dev->tt_info);
3461 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3462 }
3463 /* If necessary, update the number of active TTs on this root port */
3464 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3465
3466 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3467 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3468 ret = 0;
3469
3470 command_cleanup:
3471 xhci_free_command(xhci, reset_device_cmd);
3472 return ret;
3473 }
3474
3475 /*
3476 * At this point, the struct usb_device is about to go away, the device has
3477 * disconnected, and all traffic has been stopped and the endpoints have been
3478 * disabled. Free any HC data structures associated with that device.
3479 */
3480 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3481 {
3482 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3483 struct xhci_virt_device *virt_dev;
3484 unsigned long flags;
3485 u32 state;
3486 int i, ret;
3487
3488 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3489 /* If the host is halted due to driver unload, we still need to free the
3490 * device.
3491 */
3492 if (ret <= 0 && ret != -ENODEV)
3493 return;
3494
3495 virt_dev = xhci->devs[udev->slot_id];
3496
3497 /* Stop any wayward timer functions (which may grab the lock) */
3498 for (i = 0; i < 31; ++i) {
3499 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3500 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3501 }
3502
3503 if (udev->usb2_hw_lpm_enabled) {
3504 xhci_set_usb2_hardware_lpm(hcd, udev, 0);
3505 udev->usb2_hw_lpm_enabled = 0;
3506 }
3507
3508 spin_lock_irqsave(&xhci->lock, flags);
3509 /* Don't disable the slot if the host controller is dead. */
3510 state = xhci_readl(xhci, &xhci->op_regs->status);
3511 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3512 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3513 xhci_free_virt_device(xhci, udev->slot_id);
3514 spin_unlock_irqrestore(&xhci->lock, flags);
3515 return;
3516 }
3517
3518 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
3519 spin_unlock_irqrestore(&xhci->lock, flags);
3520 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3521 return;
3522 }
3523 xhci_ring_cmd_db(xhci);
3524 spin_unlock_irqrestore(&xhci->lock, flags);
3525 /*
3526 * Event command completion handler will free any data structures
3527 * associated with the slot. XXX Can free sleep?
3528 */
3529 }
3530
3531 /*
3532 * Checks if we have enough host controller resources for the default control
3533 * endpoint.
3534 *
3535 * Must be called with xhci->lock held.
3536 */
3537 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3538 {
3539 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3540 xhci_dbg(xhci, "Not enough ep ctxs: "
3541 "%u active, need to add 1, limit is %u.\n",
3542 xhci->num_active_eps, xhci->limit_active_eps);
3543 return -ENOMEM;
3544 }
3545 xhci->num_active_eps += 1;
3546 xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
3547 xhci->num_active_eps);
3548 return 0;
3549 }
3550
3551
3552 /*
3553 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3554 * timed out, or allocating memory failed. Returns 1 on success.
3555 */
3556 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3557 {
3558 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3559 unsigned long flags;
3560 int timeleft;
3561 int ret;
3562 union xhci_trb *cmd_trb;
3563
3564 spin_lock_irqsave(&xhci->lock, flags);
3565 cmd_trb = xhci->cmd_ring->dequeue;
3566 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
3567 if (ret) {
3568 spin_unlock_irqrestore(&xhci->lock, flags);
3569 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3570 return 0;
3571 }
3572 xhci_ring_cmd_db(xhci);
3573 spin_unlock_irqrestore(&xhci->lock, flags);
3574
3575 /* XXX: how much time for xHC slot assignment? */
3576 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3577 XHCI_CMD_DEFAULT_TIMEOUT);
3578 if (timeleft <= 0) {
3579 xhci_warn(xhci, "%s while waiting for a slot\n",
3580 timeleft == 0 ? "Timeout" : "Signal");
3581 /* cancel the enable slot request */
3582 return xhci_cancel_cmd(xhci, NULL, cmd_trb);
3583 }
3584
3585 if (!xhci->slot_id) {
3586 xhci_err(xhci, "Error while assigning device slot ID\n");
3587 return 0;
3588 }
3589
3590 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3591 spin_lock_irqsave(&xhci->lock, flags);
3592 ret = xhci_reserve_host_control_ep_resources(xhci);
3593 if (ret) {
3594 spin_unlock_irqrestore(&xhci->lock, flags);
3595 xhci_warn(xhci, "Not enough host resources, "
3596 "active endpoint contexts = %u\n",
3597 xhci->num_active_eps);
3598 goto disable_slot;
3599 }
3600 spin_unlock_irqrestore(&xhci->lock, flags);
3601 }
3602 /* Use GFP_NOIO, since this function can be called from
3603 * xhci_discover_or_reset_device(), which may be called as part of
3604 * mass storage driver error handling.
3605 */
3606 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
3607 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3608 goto disable_slot;
3609 }
3610 udev->slot_id = xhci->slot_id;
3611 /* Is this a LS or FS device under a HS hub? */
3612 /* Hub or peripherial? */
3613 return 1;
3614
3615 disable_slot:
3616 /* Disable slot, if we can do it without mem alloc */
3617 spin_lock_irqsave(&xhci->lock, flags);
3618 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
3619 xhci_ring_cmd_db(xhci);
3620 spin_unlock_irqrestore(&xhci->lock, flags);
3621 return 0;
3622 }
3623
3624 /*
3625 * Issue an Address Device command (which will issue a SetAddress request to
3626 * the device).
3627 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
3628 * we should only issue and wait on one address command at the same time.
3629 *
3630 * We add one to the device address issued by the hardware because the USB core
3631 * uses address 1 for the root hubs (even though they're not really devices).
3632 */
3633 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3634 {
3635 unsigned long flags;
3636 int timeleft;
3637 struct xhci_virt_device *virt_dev;
3638 int ret = 0;
3639 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3640 struct xhci_slot_ctx *slot_ctx;
3641 struct xhci_input_control_ctx *ctrl_ctx;
3642 u64 temp_64;
3643 union xhci_trb *cmd_trb;
3644
3645 if (!udev->slot_id) {
3646 xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
3647 return -EINVAL;
3648 }
3649
3650 virt_dev = xhci->devs[udev->slot_id];
3651
3652 if (WARN_ON(!virt_dev)) {
3653 /*
3654 * In plug/unplug torture test with an NEC controller,
3655 * a zero-dereference was observed once due to virt_dev = 0.
3656 * Print useful debug rather than crash if it is observed again!
3657 */
3658 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3659 udev->slot_id);
3660 return -EINVAL;
3661 }
3662
3663 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3664 /*
3665 * If this is the first Set Address since device plug-in or
3666 * virt_device realloaction after a resume with an xHCI power loss,
3667 * then set up the slot context.
3668 */
3669 if (!slot_ctx->dev_info)
3670 xhci_setup_addressable_virt_dev(xhci, udev);
3671 /* Otherwise, update the control endpoint ring enqueue pointer. */
3672 else
3673 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3674 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
3675 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3676 ctrl_ctx->drop_flags = 0;
3677
3678 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3679 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3680
3681 spin_lock_irqsave(&xhci->lock, flags);
3682 cmd_trb = xhci->cmd_ring->dequeue;
3683 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
3684 udev->slot_id);
3685 if (ret) {
3686 spin_unlock_irqrestore(&xhci->lock, flags);
3687 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3688 return ret;
3689 }
3690 xhci_ring_cmd_db(xhci);
3691 spin_unlock_irqrestore(&xhci->lock, flags);
3692
3693 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3694 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3695 XHCI_CMD_DEFAULT_TIMEOUT);
3696 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3697 * the SetAddress() "recovery interval" required by USB and aborting the
3698 * command on a timeout.
3699 */
3700 if (timeleft <= 0) {
3701 xhci_warn(xhci, "%s while waiting for address device command\n",
3702 timeleft == 0 ? "Timeout" : "Signal");
3703 /* cancel the address device command */
3704 ret = xhci_cancel_cmd(xhci, NULL, cmd_trb);
3705 if (ret < 0)
3706 return ret;
3707 return -ETIME;
3708 }
3709
3710 switch (virt_dev->cmd_status) {
3711 case COMP_CTX_STATE:
3712 case COMP_EBADSLT:
3713 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
3714 udev->slot_id);
3715 ret = -EINVAL;
3716 break;
3717 case COMP_TX_ERR:
3718 dev_warn(&udev->dev, "Device not responding to set address.\n");
3719 ret = -EPROTO;
3720 break;
3721 case COMP_DEV_ERR:
3722 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
3723 "device command.\n");
3724 ret = -ENODEV;
3725 break;
3726 case COMP_SUCCESS:
3727 xhci_dbg(xhci, "Successful Address Device command\n");
3728 break;
3729 default:
3730 xhci_err(xhci, "ERROR: unexpected command completion "
3731 "code 0x%x.\n", virt_dev->cmd_status);
3732 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3733 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3734 ret = -EINVAL;
3735 break;
3736 }
3737 if (ret) {
3738 return ret;
3739 }
3740 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3741 xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
3742 xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
3743 udev->slot_id,
3744 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3745 (unsigned long long)
3746 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3747 xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
3748 (unsigned long long)virt_dev->out_ctx->dma);
3749 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3750 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3751 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3752 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3753 /*
3754 * USB core uses address 1 for the roothubs, so we add one to the
3755 * address given back to us by the HC.
3756 */
3757 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3758 /* Use kernel assigned address for devices; store xHC assigned
3759 * address locally. */
3760 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
3761 + 1;
3762 /* Zero the input context control for later use */
3763 ctrl_ctx->add_flags = 0;
3764 ctrl_ctx->drop_flags = 0;
3765
3766 xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
3767
3768 return 0;
3769 }
3770
3771 #ifdef CONFIG_USB_SUSPEND
3772
3773 /* BESL to HIRD Encoding array for USB2 LPM */
3774 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
3775 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
3776
3777 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
3778 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
3779 struct usb_device *udev)
3780 {
3781 int u2del, besl, besl_host;
3782 int besl_device = 0;
3783 u32 field;
3784
3785 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
3786 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
3787
3788 if (field & USB_BESL_SUPPORT) {
3789 for (besl_host = 0; besl_host < 16; besl_host++) {
3790 if (xhci_besl_encoding[besl_host] >= u2del)
3791 break;
3792 }
3793 /* Use baseline BESL value as default */
3794 if (field & USB_BESL_BASELINE_VALID)
3795 besl_device = USB_GET_BESL_BASELINE(field);
3796 else if (field & USB_BESL_DEEP_VALID)
3797 besl_device = USB_GET_BESL_DEEP(field);
3798 } else {
3799 if (u2del <= 50)
3800 besl_host = 0;
3801 else
3802 besl_host = (u2del - 51) / 75 + 1;
3803 }
3804
3805 besl = besl_host + besl_device;
3806 if (besl > 15)
3807 besl = 15;
3808
3809 return besl;
3810 }
3811
3812 static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd,
3813 struct usb_device *udev)
3814 {
3815 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3816 struct dev_info *dev_info;
3817 __le32 __iomem **port_array;
3818 __le32 __iomem *addr, *pm_addr;
3819 u32 temp, dev_id;
3820 unsigned int port_num;
3821 unsigned long flags;
3822 int hird;
3823 int ret;
3824
3825 if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
3826 !udev->lpm_capable)
3827 return -EINVAL;
3828
3829 /* we only support lpm for non-hub device connected to root hub yet */
3830 if (!udev->parent || udev->parent->parent ||
3831 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
3832 return -EINVAL;
3833
3834 spin_lock_irqsave(&xhci->lock, flags);
3835
3836 /* Look for devices in lpm_failed_devs list */
3837 dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 |
3838 le16_to_cpu(udev->descriptor.idProduct);
3839 list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) {
3840 if (dev_info->dev_id == dev_id) {
3841 ret = -EINVAL;
3842 goto finish;
3843 }
3844 }
3845
3846 port_array = xhci->usb2_ports;
3847 port_num = udev->portnum - 1;
3848
3849 if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) {
3850 xhci_dbg(xhci, "invalid port number %d\n", udev->portnum);
3851 ret = -EINVAL;
3852 goto finish;
3853 }
3854
3855 /*
3856 * Test USB 2.0 software LPM.
3857 * FIXME: some xHCI 1.0 hosts may implement a new register to set up
3858 * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1
3859 * in the June 2011 errata release.
3860 */
3861 xhci_dbg(xhci, "test port %d software LPM\n", port_num);
3862 /*
3863 * Set L1 Device Slot and HIRD/BESL.
3864 * Check device's USB 2.0 extension descriptor to determine whether
3865 * HIRD or BESL shoule be used. See USB2.0 LPM errata.
3866 */
3867 pm_addr = port_array[port_num] + 1;
3868 hird = xhci_calculate_hird_besl(xhci, udev);
3869 temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird);
3870 xhci_writel(xhci, temp, pm_addr);
3871
3872 /* Set port link state to U2(L1) */
3873 addr = port_array[port_num];
3874 xhci_set_link_state(xhci, port_array, port_num, XDEV_U2);
3875
3876 /* wait for ACK */
3877 spin_unlock_irqrestore(&xhci->lock, flags);
3878 msleep(10);
3879 spin_lock_irqsave(&xhci->lock, flags);
3880
3881 /* Check L1 Status */
3882 ret = xhci_handshake(xhci, pm_addr,
3883 PORT_L1S_MASK, PORT_L1S_SUCCESS, 125);
3884 if (ret != -ETIMEDOUT) {
3885 /* enter L1 successfully */
3886 temp = xhci_readl(xhci, addr);
3887 xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n",
3888 port_num, temp);
3889 ret = 0;
3890 } else {
3891 temp = xhci_readl(xhci, pm_addr);
3892 xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n",
3893 port_num, temp & PORT_L1S_MASK);
3894 ret = -EINVAL;
3895 }
3896
3897 /* Resume the port */
3898 xhci_set_link_state(xhci, port_array, port_num, XDEV_U0);
3899
3900 spin_unlock_irqrestore(&xhci->lock, flags);
3901 msleep(10);
3902 spin_lock_irqsave(&xhci->lock, flags);
3903
3904 /* Clear PLC */
3905 xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC);
3906
3907 /* Check PORTSC to make sure the device is in the right state */
3908 if (!ret) {
3909 temp = xhci_readl(xhci, addr);
3910 xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp);
3911 if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) ||
3912 (temp & PORT_PLS_MASK) != XDEV_U0) {
3913 xhci_dbg(xhci, "port L1 resume fail\n");
3914 ret = -EINVAL;
3915 }
3916 }
3917
3918 if (ret) {
3919 /* Insert dev to lpm_failed_devs list */
3920 xhci_warn(xhci, "device LPM test failed, may disconnect and "
3921 "re-enumerate\n");
3922 dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC);
3923 if (!dev_info) {
3924 ret = -ENOMEM;
3925 goto finish;
3926 }
3927 dev_info->dev_id = dev_id;
3928 INIT_LIST_HEAD(&dev_info->list);
3929 list_add(&dev_info->list, &xhci->lpm_failed_devs);
3930 } else {
3931 xhci_ring_device(xhci, udev->slot_id);
3932 }
3933
3934 finish:
3935 spin_unlock_irqrestore(&xhci->lock, flags);
3936 return ret;
3937 }
3938
3939 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
3940 struct usb_device *udev, int enable)
3941 {
3942 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3943 __le32 __iomem **port_array;
3944 __le32 __iomem *pm_addr;
3945 u32 temp;
3946 unsigned int port_num;
3947 unsigned long flags;
3948 int hird;
3949
3950 if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
3951 !udev->lpm_capable)
3952 return -EPERM;
3953
3954 if (!udev->parent || udev->parent->parent ||
3955 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
3956 return -EPERM;
3957
3958 if (udev->usb2_hw_lpm_capable != 1)
3959 return -EPERM;
3960
3961 spin_lock_irqsave(&xhci->lock, flags);
3962
3963 port_array = xhci->usb2_ports;
3964 port_num = udev->portnum - 1;
3965 pm_addr = port_array[port_num] + 1;
3966 temp = xhci_readl(xhci, pm_addr);
3967
3968 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
3969 enable ? "enable" : "disable", port_num);
3970
3971 hird = xhci_calculate_hird_besl(xhci, udev);
3972
3973 if (enable) {
3974 temp &= ~PORT_HIRD_MASK;
3975 temp |= PORT_HIRD(hird) | PORT_RWE;
3976 xhci_writel(xhci, temp, pm_addr);
3977 temp = xhci_readl(xhci, pm_addr);
3978 temp |= PORT_HLE;
3979 xhci_writel(xhci, temp, pm_addr);
3980 } else {
3981 temp &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK);
3982 xhci_writel(xhci, temp, pm_addr);
3983 }
3984
3985 spin_unlock_irqrestore(&xhci->lock, flags);
3986 return 0;
3987 }
3988
3989 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
3990 {
3991 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3992 int ret;
3993
3994 ret = xhci_usb2_software_lpm_test(hcd, udev);
3995 if (!ret) {
3996 xhci_dbg(xhci, "software LPM test succeed\n");
3997 if (xhci->hw_lpm_support == 1) {
3998 udev->usb2_hw_lpm_capable = 1;
3999 ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1);
4000 if (!ret)
4001 udev->usb2_hw_lpm_enabled = 1;
4002 }
4003 }
4004
4005 return 0;
4006 }
4007
4008 #else
4009
4010 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4011 struct usb_device *udev, int enable)
4012 {
4013 return 0;
4014 }
4015
4016 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4017 {
4018 return 0;
4019 }
4020
4021 #endif /* CONFIG_USB_SUSPEND */
4022
4023 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4024
4025 #ifdef CONFIG_PM
4026 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4027 static unsigned long long xhci_service_interval_to_ns(
4028 struct usb_endpoint_descriptor *desc)
4029 {
4030 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4031 }
4032
4033 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4034 enum usb3_link_state state)
4035 {
4036 unsigned long long sel;
4037 unsigned long long pel;
4038 unsigned int max_sel_pel;
4039 char *state_name;
4040
4041 switch (state) {
4042 case USB3_LPM_U1:
4043 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4044 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4045 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4046 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4047 state_name = "U1";
4048 break;
4049 case USB3_LPM_U2:
4050 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4051 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4052 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4053 state_name = "U2";
4054 break;
4055 default:
4056 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4057 __func__);
4058 return USB3_LPM_DISABLED;
4059 }
4060
4061 if (sel <= max_sel_pel && pel <= max_sel_pel)
4062 return USB3_LPM_DEVICE_INITIATED;
4063
4064 if (sel > max_sel_pel)
4065 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4066 "due to long SEL %llu ms\n",
4067 state_name, sel);
4068 else
4069 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4070 "due to long PEL %llu\n ms",
4071 state_name, pel);
4072 return USB3_LPM_DISABLED;
4073 }
4074
4075 /* Returns the hub-encoded U1 timeout value.
4076 * The U1 timeout should be the maximum of the following values:
4077 * - For control endpoints, U1 system exit latency (SEL) * 3
4078 * - For bulk endpoints, U1 SEL * 5
4079 * - For interrupt endpoints:
4080 * - Notification EPs, U1 SEL * 3
4081 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4082 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4083 */
4084 static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev,
4085 struct usb_endpoint_descriptor *desc)
4086 {
4087 unsigned long long timeout_ns;
4088 int ep_type;
4089 int intr_type;
4090
4091 ep_type = usb_endpoint_type(desc);
4092 switch (ep_type) {
4093 case USB_ENDPOINT_XFER_CONTROL:
4094 timeout_ns = udev->u1_params.sel * 3;
4095 break;
4096 case USB_ENDPOINT_XFER_BULK:
4097 timeout_ns = udev->u1_params.sel * 5;
4098 break;
4099 case USB_ENDPOINT_XFER_INT:
4100 intr_type = usb_endpoint_interrupt_type(desc);
4101 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4102 timeout_ns = udev->u1_params.sel * 3;
4103 break;
4104 }
4105 /* Otherwise the calculation is the same as isoc eps */
4106 case USB_ENDPOINT_XFER_ISOC:
4107 timeout_ns = xhci_service_interval_to_ns(desc);
4108 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4109 if (timeout_ns < udev->u1_params.sel * 2)
4110 timeout_ns = udev->u1_params.sel * 2;
4111 break;
4112 default:
4113 return 0;
4114 }
4115
4116 /* The U1 timeout is encoded in 1us intervals. */
4117 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4118 /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */
4119 if (timeout_ns == USB3_LPM_DISABLED)
4120 timeout_ns++;
4121
4122 /* If the necessary timeout value is bigger than what we can set in the
4123 * USB 3.0 hub, we have to disable hub-initiated U1.
4124 */
4125 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4126 return timeout_ns;
4127 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4128 "due to long timeout %llu ms\n", timeout_ns);
4129 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4130 }
4131
4132 /* Returns the hub-encoded U2 timeout value.
4133 * The U2 timeout should be the maximum of:
4134 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4135 * - largest bInterval of any active periodic endpoint (to avoid going
4136 * into lower power link states between intervals).
4137 * - the U2 Exit Latency of the device
4138 */
4139 static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev,
4140 struct usb_endpoint_descriptor *desc)
4141 {
4142 unsigned long long timeout_ns;
4143 unsigned long long u2_del_ns;
4144
4145 timeout_ns = 10 * 1000 * 1000;
4146
4147 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4148 (xhci_service_interval_to_ns(desc) > timeout_ns))
4149 timeout_ns = xhci_service_interval_to_ns(desc);
4150
4151 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4152 if (u2_del_ns > timeout_ns)
4153 timeout_ns = u2_del_ns;
4154
4155 /* The U2 timeout is encoded in 256us intervals */
4156 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4157 /* If the necessary timeout value is bigger than what we can set in the
4158 * USB 3.0 hub, we have to disable hub-initiated U2.
4159 */
4160 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4161 return timeout_ns;
4162 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4163 "due to long timeout %llu ms\n", timeout_ns);
4164 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4165 }
4166
4167 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4168 struct usb_device *udev,
4169 struct usb_endpoint_descriptor *desc,
4170 enum usb3_link_state state,
4171 u16 *timeout)
4172 {
4173 if (state == USB3_LPM_U1) {
4174 if (xhci->quirks & XHCI_INTEL_HOST)
4175 return xhci_calculate_intel_u1_timeout(udev, desc);
4176 } else {
4177 if (xhci->quirks & XHCI_INTEL_HOST)
4178 return xhci_calculate_intel_u2_timeout(udev, desc);
4179 }
4180
4181 return USB3_LPM_DISABLED;
4182 }
4183
4184 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4185 struct usb_device *udev,
4186 struct usb_endpoint_descriptor *desc,
4187 enum usb3_link_state state,
4188 u16 *timeout)
4189 {
4190 u16 alt_timeout;
4191
4192 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4193 desc, state, timeout);
4194
4195 /* If we found we can't enable hub-initiated LPM, or
4196 * the U1 or U2 exit latency was too high to allow
4197 * device-initiated LPM as well, just stop searching.
4198 */
4199 if (alt_timeout == USB3_LPM_DISABLED ||
4200 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4201 *timeout = alt_timeout;
4202 return -E2BIG;
4203 }
4204 if (alt_timeout > *timeout)
4205 *timeout = alt_timeout;
4206 return 0;
4207 }
4208
4209 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4210 struct usb_device *udev,
4211 struct usb_host_interface *alt,
4212 enum usb3_link_state state,
4213 u16 *timeout)
4214 {
4215 int j;
4216
4217 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4218 if (xhci_update_timeout_for_endpoint(xhci, udev,
4219 &alt->endpoint[j].desc, state, timeout))
4220 return -E2BIG;
4221 continue;
4222 }
4223 return 0;
4224 }
4225
4226 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4227 enum usb3_link_state state)
4228 {
4229 struct usb_device *parent;
4230 unsigned int num_hubs;
4231
4232 if (state == USB3_LPM_U2)
4233 return 0;
4234
4235 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4236 for (parent = udev->parent, num_hubs = 0; parent->parent;
4237 parent = parent->parent)
4238 num_hubs++;
4239
4240 if (num_hubs < 2)
4241 return 0;
4242
4243 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4244 " below second-tier hub.\n");
4245 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4246 "to decrease power consumption.\n");
4247 return -E2BIG;
4248 }
4249
4250 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4251 struct usb_device *udev,
4252 enum usb3_link_state state)
4253 {
4254 if (xhci->quirks & XHCI_INTEL_HOST)
4255 return xhci_check_intel_tier_policy(udev, state);
4256 return -EINVAL;
4257 }
4258
4259 /* Returns the U1 or U2 timeout that should be enabled.
4260 * If the tier check or timeout setting functions return with a non-zero exit
4261 * code, that means the timeout value has been finalized and we shouldn't look
4262 * at any more endpoints.
4263 */
4264 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4265 struct usb_device *udev, enum usb3_link_state state)
4266 {
4267 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4268 struct usb_host_config *config;
4269 char *state_name;
4270 int i;
4271 u16 timeout = USB3_LPM_DISABLED;
4272
4273 if (state == USB3_LPM_U1)
4274 state_name = "U1";
4275 else if (state == USB3_LPM_U2)
4276 state_name = "U2";
4277 else {
4278 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4279 state);
4280 return timeout;
4281 }
4282
4283 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4284 return timeout;
4285
4286 /* Gather some information about the currently installed configuration
4287 * and alternate interface settings.
4288 */
4289 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4290 state, &timeout))
4291 return timeout;
4292
4293 config = udev->actconfig;
4294 if (!config)
4295 return timeout;
4296
4297 for (i = 0; i < USB_MAXINTERFACES; i++) {
4298 struct usb_driver *driver;
4299 struct usb_interface *intf = config->interface[i];
4300
4301 if (!intf)
4302 continue;
4303
4304 /* Check if any currently bound drivers want hub-initiated LPM
4305 * disabled.
4306 */
4307 if (intf->dev.driver) {
4308 driver = to_usb_driver(intf->dev.driver);
4309 if (driver && driver->disable_hub_initiated_lpm) {
4310 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4311 "at request of driver %s\n",
4312 state_name, driver->name);
4313 return xhci_get_timeout_no_hub_lpm(udev, state);
4314 }
4315 }
4316
4317 /* Not sure how this could happen... */
4318 if (!intf->cur_altsetting)
4319 continue;
4320
4321 if (xhci_update_timeout_for_interface(xhci, udev,
4322 intf->cur_altsetting,
4323 state, &timeout))
4324 return timeout;
4325 }
4326 return timeout;
4327 }
4328
4329 /*
4330 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4331 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4332 */
4333 static int xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4334 struct usb_device *udev, u16 max_exit_latency)
4335 {
4336 struct xhci_virt_device *virt_dev;
4337 struct xhci_command *command;
4338 struct xhci_input_control_ctx *ctrl_ctx;
4339 struct xhci_slot_ctx *slot_ctx;
4340 unsigned long flags;
4341 int ret;
4342
4343 spin_lock_irqsave(&xhci->lock, flags);
4344 if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) {
4345 spin_unlock_irqrestore(&xhci->lock, flags);
4346 return 0;
4347 }
4348
4349 /* Attempt to issue an Evaluate Context command to change the MEL. */
4350 virt_dev = xhci->devs[udev->slot_id];
4351 command = xhci->lpm_command;
4352 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4353 spin_unlock_irqrestore(&xhci->lock, flags);
4354
4355 ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
4356 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4357 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4358 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4359 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4360
4361 xhci_dbg(xhci, "Set up evaluate context for LPM MEL change.\n");
4362 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4363 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4364
4365 /* Issue and wait for the evaluate context command. */
4366 ret = xhci_configure_endpoint(xhci, udev, command,
4367 true, true);
4368 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4369 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4370
4371 if (!ret) {
4372 spin_lock_irqsave(&xhci->lock, flags);
4373 virt_dev->current_mel = max_exit_latency;
4374 spin_unlock_irqrestore(&xhci->lock, flags);
4375 }
4376 return ret;
4377 }
4378
4379 static int calculate_max_exit_latency(struct usb_device *udev,
4380 enum usb3_link_state state_changed,
4381 u16 hub_encoded_timeout)
4382 {
4383 unsigned long long u1_mel_us = 0;
4384 unsigned long long u2_mel_us = 0;
4385 unsigned long long mel_us = 0;
4386 bool disabling_u1;
4387 bool disabling_u2;
4388 bool enabling_u1;
4389 bool enabling_u2;
4390
4391 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4392 hub_encoded_timeout == USB3_LPM_DISABLED);
4393 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4394 hub_encoded_timeout == USB3_LPM_DISABLED);
4395
4396 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4397 hub_encoded_timeout != USB3_LPM_DISABLED);
4398 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4399 hub_encoded_timeout != USB3_LPM_DISABLED);
4400
4401 /* If U1 was already enabled and we're not disabling it,
4402 * or we're going to enable U1, account for the U1 max exit latency.
4403 */
4404 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4405 enabling_u1)
4406 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4407 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4408 enabling_u2)
4409 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4410
4411 if (u1_mel_us > u2_mel_us)
4412 mel_us = u1_mel_us;
4413 else
4414 mel_us = u2_mel_us;
4415 /* xHCI host controller max exit latency field is only 16 bits wide. */
4416 if (mel_us > MAX_EXIT) {
4417 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4418 "is too big.\n", mel_us);
4419 return -E2BIG;
4420 }
4421 return mel_us;
4422 }
4423
4424 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4425 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4426 struct usb_device *udev, enum usb3_link_state state)
4427 {
4428 struct xhci_hcd *xhci;
4429 u16 hub_encoded_timeout;
4430 int mel;
4431 int ret;
4432
4433 xhci = hcd_to_xhci(hcd);
4434 /* The LPM timeout values are pretty host-controller specific, so don't
4435 * enable hub-initiated timeouts unless the vendor has provided
4436 * information about their timeout algorithm.
4437 */
4438 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4439 !xhci->devs[udev->slot_id])
4440 return USB3_LPM_DISABLED;
4441
4442 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4443 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4444 if (mel < 0) {
4445 /* Max Exit Latency is too big, disable LPM. */
4446 hub_encoded_timeout = USB3_LPM_DISABLED;
4447 mel = 0;
4448 }
4449
4450 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4451 if (ret)
4452 return ret;
4453 return hub_encoded_timeout;
4454 }
4455
4456 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4457 struct usb_device *udev, enum usb3_link_state state)
4458 {
4459 struct xhci_hcd *xhci;
4460 u16 mel;
4461 int ret;
4462
4463 xhci = hcd_to_xhci(hcd);
4464 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4465 !xhci->devs[udev->slot_id])
4466 return 0;
4467
4468 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4469 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4470 if (ret)
4471 return ret;
4472 return 0;
4473 }
4474 #else /* CONFIG_PM */
4475
4476 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4477 struct usb_device *udev, enum usb3_link_state state)
4478 {
4479 return USB3_LPM_DISABLED;
4480 }
4481
4482 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4483 struct usb_device *udev, enum usb3_link_state state)
4484 {
4485 return 0;
4486 }
4487 #endif /* CONFIG_PM */
4488
4489 /*-------------------------------------------------------------------------*/
4490
4491 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4492 * internal data structures for the device.
4493 */
4494 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4495 struct usb_tt *tt, gfp_t mem_flags)
4496 {
4497 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4498 struct xhci_virt_device *vdev;
4499 struct xhci_command *config_cmd;
4500 struct xhci_input_control_ctx *ctrl_ctx;
4501 struct xhci_slot_ctx *slot_ctx;
4502 unsigned long flags;
4503 unsigned think_time;
4504 int ret;
4505
4506 /* Ignore root hubs */
4507 if (!hdev->parent)
4508 return 0;
4509
4510 vdev = xhci->devs[hdev->slot_id];
4511 if (!vdev) {
4512 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4513 return -EINVAL;
4514 }
4515 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4516 if (!config_cmd) {
4517 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4518 return -ENOMEM;
4519 }
4520
4521 spin_lock_irqsave(&xhci->lock, flags);
4522 if (hdev->speed == USB_SPEED_HIGH &&
4523 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4524 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4525 xhci_free_command(xhci, config_cmd);
4526 spin_unlock_irqrestore(&xhci->lock, flags);
4527 return -ENOMEM;
4528 }
4529
4530 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4531 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
4532 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4533 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4534 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4535 if (tt->multi)
4536 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4537 if (xhci->hci_version > 0x95) {
4538 xhci_dbg(xhci, "xHCI version %x needs hub "
4539 "TT think time and number of ports\n",
4540 (unsigned int) xhci->hci_version);
4541 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4542 /* Set TT think time - convert from ns to FS bit times.
4543 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4544 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4545 *
4546 * xHCI 1.0: this field shall be 0 if the device is not a
4547 * High-spped hub.
4548 */
4549 think_time = tt->think_time;
4550 if (think_time != 0)
4551 think_time = (think_time / 666) - 1;
4552 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4553 slot_ctx->tt_info |=
4554 cpu_to_le32(TT_THINK_TIME(think_time));
4555 } else {
4556 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4557 "TT think time or number of ports\n",
4558 (unsigned int) xhci->hci_version);
4559 }
4560 slot_ctx->dev_state = 0;
4561 spin_unlock_irqrestore(&xhci->lock, flags);
4562
4563 xhci_dbg(xhci, "Set up %s for hub device.\n",
4564 (xhci->hci_version > 0x95) ?
4565 "configure endpoint" : "evaluate context");
4566 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4567 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4568
4569 /* Issue and wait for the configure endpoint or
4570 * evaluate context command.
4571 */
4572 if (xhci->hci_version > 0x95)
4573 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4574 false, false);
4575 else
4576 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4577 true, false);
4578
4579 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4580 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4581
4582 xhci_free_command(xhci, config_cmd);
4583 return ret;
4584 }
4585
4586 int xhci_get_frame(struct usb_hcd *hcd)
4587 {
4588 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4589 /* EHCI mods by the periodic size. Why? */
4590 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
4591 }
4592
4593 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4594 {
4595 struct xhci_hcd *xhci;
4596 struct device *dev = hcd->self.controller;
4597 int retval;
4598 u32 temp;
4599
4600 /* Accept arbitrarily long scatter-gather lists */
4601 hcd->self.sg_tablesize = ~0;
4602 /* XHCI controllers don't stop the ep queue on short packets :| */
4603 hcd->self.no_stop_on_short = 1;
4604
4605 if (usb_hcd_is_primary_hcd(hcd)) {
4606 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
4607 if (!xhci)
4608 return -ENOMEM;
4609 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
4610 xhci->main_hcd = hcd;
4611 /* Mark the first roothub as being USB 2.0.
4612 * The xHCI driver will register the USB 3.0 roothub.
4613 */
4614 hcd->speed = HCD_USB2;
4615 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4616 /*
4617 * USB 2.0 roothub under xHCI has an integrated TT,
4618 * (rate matching hub) as opposed to having an OHCI/UHCI
4619 * companion controller.
4620 */
4621 hcd->has_tt = 1;
4622 } else {
4623 /* xHCI private pointer was set in xhci_pci_probe for the second
4624 * registered roothub.
4625 */
4626 xhci = hcd_to_xhci(hcd);
4627 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4628 if (HCC_64BIT_ADDR(temp)) {
4629 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4630 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4631 } else {
4632 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4633 }
4634 return 0;
4635 }
4636
4637 xhci->cap_regs = hcd->regs;
4638 xhci->op_regs = hcd->regs +
4639 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
4640 xhci->run_regs = hcd->regs +
4641 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4642 /* Cache read-only capability registers */
4643 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
4644 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
4645 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
4646 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
4647 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4648 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4649 xhci_print_registers(xhci);
4650
4651 get_quirks(dev, xhci);
4652
4653 /* Make sure the HC is halted. */
4654 retval = xhci_halt(xhci);
4655 if (retval)
4656 goto error;
4657
4658 xhci_dbg(xhci, "Resetting HCD\n");
4659 /* Reset the internal HC memory state and registers. */
4660 retval = xhci_reset(xhci);
4661 if (retval)
4662 goto error;
4663 xhci_dbg(xhci, "Reset complete\n");
4664
4665 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4666 if (HCC_64BIT_ADDR(temp)) {
4667 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4668 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4669 } else {
4670 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4671 }
4672
4673 xhci_dbg(xhci, "Calling HCD init\n");
4674 /* Initialize HCD and host controller data structures. */
4675 retval = xhci_init(hcd);
4676 if (retval)
4677 goto error;
4678 xhci_dbg(xhci, "Called HCD init\n");
4679 return 0;
4680 error:
4681 kfree(xhci);
4682 return retval;
4683 }
4684
4685 MODULE_DESCRIPTION(DRIVER_DESC);
4686 MODULE_AUTHOR(DRIVER_AUTHOR);
4687 MODULE_LICENSE("GPL");
4688
4689 static int __init xhci_hcd_init(void)
4690 {
4691 int retval;
4692
4693 retval = xhci_register_pci();
4694 if (retval < 0) {
4695 printk(KERN_DEBUG "Problem registering PCI driver.");
4696 return retval;
4697 }
4698 retval = xhci_register_plat();
4699 if (retval < 0) {
4700 printk(KERN_DEBUG "Problem registering platform driver.");
4701 goto unreg_pci;
4702 }
4703 /*
4704 * Check the compiler generated sizes of structures that must be laid
4705 * out in specific ways for hardware access.
4706 */
4707 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4708 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
4709 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
4710 /* xhci_device_control has eight fields, and also
4711 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
4712 */
4713 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
4714 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
4715 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
4716 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
4717 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
4718 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
4719 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
4720 return 0;
4721 unreg_pci:
4722 xhci_unregister_pci();
4723 return retval;
4724 }
4725 module_init(xhci_hcd_init);
4726
4727 static void __exit xhci_hcd_cleanup(void)
4728 {
4729 xhci_unregister_pci();
4730 xhci_unregister_plat();
4731 }
4732 module_exit(xhci_hcd_cleanup);
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