drivers/usb/host/xhci.h

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #ifndef __LINUX_XHCI_HCD_H
  24 #define __LINUX_XHCI_HCD_H
  25
  26 #include <linux/usb.h>
  27 #include <linux/timer.h>
  28 #include <linux/kernel.h>
  29 #include <linux/usb/hcd.h>
  30
  31 /* Code sharing between pci-quirks and xhci hcd */
  32 #include        "xhci-ext-caps.h"
  33 #include "pci-quirks.h"
  34
  35 /* xHCI PCI Configuration Registers */
  36 #define XHCI_SBRN_OFFSET        (0x60)
  37
  38 /* Max number of USB devices for any host controller - limit in section 6.1 */
  39 #define MAX_HC_SLOTS            256
  40 /* Section 5.3.3 - MaxPorts */
  41 #define MAX_HC_PORTS            127
  42
  43 /*
  44  * xHCI register interface.
  45  * This corresponds to the eXtensible Host Controller Interface (xHCI)
  46  * Revision 0.95 specification
  47  */
  48
  49 /**
  50  * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
  51  * @hc_capbase:         length of the capabilities register and HC version number
  52  * @hcs_params1:        HCSPARAMS1 - Structural Parameters 1
  53  * @hcs_params2:        HCSPARAMS2 - Structural Parameters 2
  54  * @hcs_params3:        HCSPARAMS3 - Structural Parameters 3
  55  * @hcc_params:         HCCPARAMS - Capability Parameters
  56  * @db_off:             DBOFF - Doorbell array offset
  57  * @run_regs_off:       RTSOFF - Runtime register space offset
  58  */
  59 struct xhci_cap_regs {
  60         __le32  hc_capbase;
  61         __le32  hcs_params1;
  62         __le32  hcs_params2;
  63         __le32  hcs_params3;
  64         __le32  hcc_params;
  65         __le32  db_off;
  66         __le32  run_regs_off;
  67         /* Reserved up to (CAPLENGTH - 0x1C) */
  68 };
  69
  70 /* hc_capbase bitmasks */
  71 /* bits 7:0 - how long is the Capabilities register */
  72 #define HC_LENGTH(p)            XHCI_HC_LENGTH(p)
  73 /* bits 31:16   */
  74 #define HC_VERSION(p)           (((p) >> 16) & 0xffff)
  75
  76 /* HCSPARAMS1 - hcs_params1 - bitmasks */
  77 /* bits 0:7, Max Device Slots */
  78 #define HCS_MAX_SLOTS(p)        (((p) >> 0) & 0xff)
  79 #define HCS_SLOTS_MASK          0xff
  80 /* bits 8:18, Max Interrupters */
  81 #define HCS_MAX_INTRS(p)        (((p) >> 8) & 0x7ff)
  82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
  83 #define HCS_MAX_PORTS(p)        (((p) >> 24) & 0x7f)
  84
  85 /* HCSPARAMS2 - hcs_params2 - bitmasks */
  86 /* bits 0:3, frames or uframes that SW needs to queue transactions
  87  * ahead of the HW to meet periodic deadlines */
  88 #define HCS_IST(p)              (((p) >> 0) & 0xf)
  89 /* bits 4:7, max number of Event Ring segments */
  90 #define HCS_ERST_MAX(p)         (((p) >> 4) & 0xf)
  91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
  92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
  93 #define HCS_MAX_SCRATCHPAD(p)   (((p) >> 27) & 0x1f)
  94
  95 /* HCSPARAMS3 - hcs_params3 - bitmasks */
  96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
  97 #define HCS_U1_LATENCY(p)       (((p) >> 0) & 0xff)
  98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
  99 #define HCS_U2_LATENCY(p)       (((p) >> 16) & 0xffff)
 100
 101 /* HCCPARAMS - hcc_params - bitmasks */
 102 /* true: HC can use 64-bit address pointers */
 103 #define HCC_64BIT_ADDR(p)       ((p) & (1 << 0))
 104 /* true: HC can do bandwidth negotiation */
 105 #define HCC_BANDWIDTH_NEG(p)    ((p) & (1 << 1))
 106 /* true: HC uses 64-byte Device Context structures
 107  * FIXME 64-byte context structures aren't supported yet.
 108  */
 109 #define HCC_64BYTE_CONTEXT(p)   ((p) & (1 << 2))
 110 /* true: HC has port power switches */
 111 #define HCC_PPC(p)              ((p) & (1 << 3))
 112 /* true: HC has port indicators */
 113 #define HCS_INDICATOR(p)        ((p) & (1 << 4))
 114 /* true: HC has Light HC Reset Capability */
 115 #define HCC_LIGHT_RESET(p)      ((p) & (1 << 5))
 116 /* true: HC supports latency tolerance messaging */
 117 #define HCC_LTC(p)              ((p) & (1 << 6))
 118 /* true: no secondary Stream ID Support */
 119 #define HCC_NSS(p)              ((p) & (1 << 7))
 120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
 121 #define HCC_MAX_PSA(p)          (1 << ((((p) >> 12) & 0xf) + 1))
 122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
 123 #define HCC_EXT_CAPS(p)         XHCI_HCC_EXT_CAPS(p)
 124
 125 /* db_off bitmask - bits 0:1 reserved */
 126 #define DBOFF_MASK      (~0x3)
 127
 128 /* run_regs_off bitmask - bits 0:4 reserved */
 129 #define RTSOFF_MASK     (~0x1f)
 130
 131
 132 /* Number of registers per port */
 133 #define NUM_PORT_REGS   4
 134
 135 #define PORTSC          0
 136 #define PORTPMSC        1
 137 #define PORTLI          2
 138 #define PORTHLPMC       3
 139
 140 /**
 141  * struct xhci_op_regs - xHCI Host Controller Operational Registers.
 142  * @command:            USBCMD - xHC command register
 143  * @status:             USBSTS - xHC status register
 144  * @page_size:          This indicates the page size that the host controller
 145  *                      supports.  If bit n is set, the HC supports a page size
 146  *                      of 2^(n+12), up to a 128MB page size.
 147  *                      4K is the minimum page size.
 148  * @cmd_ring:           CRP - 64-bit Command Ring Pointer
 149  * @dcbaa_ptr:          DCBAAP - 64-bit Device Context Base Address Array Pointer
 150  * @config_reg:         CONFIG - Configure Register
 151  * @port_status_base:   PORTSCn - base address for Port Status and Control
 152  *                      Each port has a Port Status and Control register,
 153  *                      followed by a Port Power Management Status and Control
 154  *                      register, a Port Link Info register, and a reserved
 155  *                      register.
 156  * @port_power_base:    PORTPMSCn - base address for
 157  *                      Port Power Management Status and Control
 158  * @port_link_base:     PORTLIn - base address for Port Link Info (current
 159  *                      Link PM state and control) for USB 2.1 and USB 3.0
 160  *                      devices.
 161  */
 162 struct xhci_op_regs {
 163         __le32  command;
 164         __le32  status;
 165         __le32  page_size;
 166         __le32  reserved1;
 167         __le32  reserved2;
 168         __le32  dev_notification;
 169         __le64  cmd_ring;
 170         /* rsvd: offset 0x20-2F */
 171         __le32  reserved3[4];
 172         __le64  dcbaa_ptr;
 173         __le32  config_reg;
 174         /* rsvd: offset 0x3C-3FF */
 175         __le32  reserved4[241];
 176         /* port 1 registers, which serve as a base address for other ports */
 177         __le32  port_status_base;
 178         __le32  port_power_base;
 179         __le32  port_link_base;
 180         __le32  reserved5;
 181         /* registers for ports 2-255 */
 182         __le32  reserved6[NUM_PORT_REGS*254];
 183 };
 184
 185 /* USBCMD - USB command - command bitmasks */
 186 /* start/stop HC execution - do not write unless HC is halted*/
 187 #define CMD_RUN         XHCI_CMD_RUN
 188 /* Reset HC - resets internal HC state machine and all registers (except
 189  * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
 190  * The xHCI driver must reinitialize the xHC after setting this bit.
 191  */
 192 #define CMD_RESET       (1 << 1)
 193 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
 194 #define CMD_EIE         XHCI_CMD_EIE
 195 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
 196 #define CMD_HSEIE       XHCI_CMD_HSEIE
 197 /* bits 4:6 are reserved (and should be preserved on writes). */
 198 /* light reset (port status stays unchanged) - reset completed when this is 0 */
 199 #define CMD_LRESET      (1 << 7)
 200 /* host controller save/restore state. */
 201 #define CMD_CSS         (1 << 8)
 202 #define CMD_CRS         (1 << 9)
 203 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
 204 #define CMD_EWE         XHCI_CMD_EWE
 205 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
 206  * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
 207  * '0' means the xHC can power it off if all ports are in the disconnect,
 208  * disabled, or powered-off state.
 209  */
 210 #define CMD_PM_INDEX    (1 << 11)
 211 /* bits 12:31 are reserved (and should be preserved on writes). */
 212
 213 /* IMAN - Interrupt Management Register */
 214 #define IMAN_IE         (1 << 1)
 215 #define IMAN_IP         (1 << 0)
 216
 217 /* USBSTS - USB status - status bitmasks */
 218 /* HC not running - set to 1 when run/stop bit is cleared. */
 219 #define STS_HALT        XHCI_STS_HALT
 220 /* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
 221 #define STS_FATAL       (1 << 2)
 222 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
 223 #define STS_EINT        (1 << 3)
 224 /* port change detect */
 225 #define STS_PORT        (1 << 4)
 226 /* bits 5:7 reserved and zeroed */
 227 /* save state status - '1' means xHC is saving state */
 228 #define STS_SAVE        (1 << 8)
 229 /* restore state status - '1' means xHC is restoring state */
 230 #define STS_RESTORE     (1 << 9)
 231 /* true: save or restore error */
 232 #define STS_SRE         (1 << 10)
 233 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
 234 #define STS_CNR         XHCI_STS_CNR
 235 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
 236 #define STS_HCE         (1 << 12)
 237 /* bits 13:31 reserved and should be preserved */
 238
 239 /*
 240  * DNCTRL - Device Notification Control Register - dev_notification bitmasks
 241  * Generate a device notification event when the HC sees a transaction with a
 242  * notification type that matches a bit set in this bit field.
 243  */
 244 #define DEV_NOTE_MASK           (0xffff)
 245 #define ENABLE_DEV_NOTE(x)      (1 << (x))
 246 /* Most of the device notification types should only be used for debug.
 247  * SW does need to pay attention to function wake notifications.
 248  */
 249 #define DEV_NOTE_FWAKE          ENABLE_DEV_NOTE(1)
 250
 251 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
 252 /* bit 0 is the command ring cycle state */
 253 /* stop ring operation after completion of the currently executing command */
 254 #define CMD_RING_PAUSE          (1 << 1)
 255 /* stop ring immediately - abort the currently executing command */
 256 #define CMD_RING_ABORT          (1 << 2)
 257 /* true: command ring is running */
 258 #define CMD_RING_RUNNING        (1 << 3)
 259 /* bits 4:5 reserved and should be preserved */
 260 /* Command Ring pointer - bit mask for the lower 32 bits. */
 261 #define CMD_RING_RSVD_BITS      (0x3f)
 262
 263 /* CONFIG - Configure Register - config_reg bitmasks */
 264 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
 265 #define MAX_DEVS(p)     ((p) & 0xff)
 266 /* bits 8:31 - reserved and should be preserved */
 267
 268 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
 269 /* true: device connected */
 270 #define PORT_CONNECT    (1 << 0)
 271 /* true: port enabled */
 272 #define PORT_PE         (1 << 1)
 273 /* bit 2 reserved and zeroed */
 274 /* true: port has an over-current condition */
 275 #define PORT_OC         (1 << 3)
 276 /* true: port reset signaling asserted */
 277 #define PORT_RESET      (1 << 4)
 278 /* Port Link State - bits 5:8
 279  * A read gives the current link PM state of the port,
 280  * a write with Link State Write Strobe set sets the link state.
 281  */
 282 #define PORT_PLS_MASK   (0xf << 5)
 283 #define XDEV_U0         (0x0 << 5)
 284 #define XDEV_U2         (0x2 << 5)
 285 #define XDEV_U3         (0x3 << 5)
 286 #define XDEV_RESUME     (0xf << 5)
 287 /* true: port has power (see HCC_PPC) */
 288 #define PORT_POWER      (1 << 9)
 289 /* bits 10:13 indicate device speed:
 290  * 0 - undefined speed - port hasn't be initialized by a reset yet
 291  * 1 - full speed
 292  * 2 - low speed
 293  * 3 - high speed
 294  * 4 - super speed
 295  * 5-15 reserved
 296  */
 297 #define DEV_SPEED_MASK          (0xf << 10)
 298 #define XDEV_FS                 (0x1 << 10)
 299 #define XDEV_LS                 (0x2 << 10)
 300 #define XDEV_HS                 (0x3 << 10)
 301 #define XDEV_SS                 (0x4 << 10)
 302 #define DEV_UNDEFSPEED(p)       (((p) & DEV_SPEED_MASK) == (0x0<<10))
 303 #define DEV_FULLSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_FS)
 304 #define DEV_LOWSPEED(p)         (((p) & DEV_SPEED_MASK) == XDEV_LS)
 305 #define DEV_HIGHSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_HS)
 306 #define DEV_SUPERSPEED(p)       (((p) & DEV_SPEED_MASK) == XDEV_SS)
 307 /* Bits 20:23 in the Slot Context are the speed for the device */
 308 #define SLOT_SPEED_FS           (XDEV_FS << 10)
 309 #define SLOT_SPEED_LS           (XDEV_LS << 10)
 310 #define SLOT_SPEED_HS           (XDEV_HS << 10)
 311 #define SLOT_SPEED_SS           (XDEV_SS << 10)
 312 /* Port Indicator Control */
 313 #define PORT_LED_OFF    (0 << 14)
 314 #define PORT_LED_AMBER  (1 << 14)
 315 #define PORT_LED_GREEN  (2 << 14)
 316 #define PORT_LED_MASK   (3 << 14)
 317 /* Port Link State Write Strobe - set this when changing link state */
 318 #define PORT_LINK_STROBE        (1 << 16)
 319 /* true: connect status change */
 320 #define PORT_CSC        (1 << 17)
 321 /* true: port enable change */
 322 #define PORT_PEC        (1 << 18)
 323 /* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
 324  * into an enabled state, and the device into the default state.  A "warm" reset
 325  * also resets the link, forcing the device through the link training sequence.
 326  * SW can also look at the Port Reset register to see when warm reset is done.
 327  */
 328 #define PORT_WRC        (1 << 19)
 329 /* true: over-current change */
 330 #define PORT_OCC        (1 << 20)
 331 /* true: reset change - 1 to 0 transition of PORT_RESET */
 332 #define PORT_RC         (1 << 21)
 333 /* port link status change - set on some port link state transitions:
 334  *  Transition                          Reason
 335  *  ------------------------------------------------------------------------------
 336  *  - U3 to Resume                      Wakeup signaling from a device
 337  *  - Resume to Recovery to U0          USB 3.0 device resume
 338  *  - Resume to U0                      USB 2.0 device resume
 339  *  - U3 to Recovery to U0              Software resume of USB 3.0 device complete
 340  *  - U3 to U0                          Software resume of USB 2.0 device complete
 341  *  - U2 to U0                          L1 resume of USB 2.1 device complete
 342  *  - U0 to U0 (???)                    L1 entry rejection by USB 2.1 device
 343  *  - U0 to disabled                    L1 entry error with USB 2.1 device
 344  *  - Any state to inactive             Error on USB 3.0 port
 345  */
 346 #define PORT_PLC        (1 << 22)
 347 /* port configure error change - port failed to configure its link partner */
 348 #define PORT_CEC        (1 << 23)
 349 /* Cold Attach Status - xHC can set this bit to report device attached during
 350  * Sx state. Warm port reset should be perfomed to clear this bit and move port
 351  * to connected state.
 352  */
 353 #define PORT_CAS        (1 << 24)
 354 /* wake on connect (enable) */
 355 #define PORT_WKCONN_E   (1 << 25)
 356 /* wake on disconnect (enable) */
 357 #define PORT_WKDISC_E   (1 << 26)
 358 /* wake on over-current (enable) */
 359 #define PORT_WKOC_E     (1 << 27)
 360 /* bits 28:29 reserved */
 361 /* true: device is removable - for USB 3.0 roothub emulation */
 362 #define PORT_DEV_REMOVE (1 << 30)
 363 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
 364 #define PORT_WR         (1 << 31)
 365
 366 /* We mark duplicate entries with -1 */
 367 #define DUPLICATE_ENTRY ((u8)(-1))
 368
 369 /* Port Power Management Status and Control - port_power_base bitmasks */
 370 /* Inactivity timer value for transitions into U1, in microseconds.
 371  * Timeout can be up to 127us.  0xFF means an infinite timeout.
 372  */
 373 #define PORT_U1_TIMEOUT(p)      ((p) & 0xff)
 374 #define PORT_U1_TIMEOUT_MASK    0xff
 375 /* Inactivity timer value for transitions into U2 */
 376 #define PORT_U2_TIMEOUT(p)      (((p) & 0xff) << 8)
 377 #define PORT_U2_TIMEOUT_MASK    (0xff << 8)
 378 /* Bits 24:31 for port testing */
 379
 380 /* USB2 Protocol PORTSPMSC */
 381 #define PORT_L1S_MASK           7
 382 #define PORT_L1S_SUCCESS        1
 383 #define PORT_RWE                (1 << 3)
 384 #define PORT_HIRD(p)            (((p) & 0xf) << 4)
 385 #define PORT_HIRD_MASK          (0xf << 4)
 386 #define PORT_L1DS(p)            (((p) & 0xff) << 8)
 387 #define PORT_HLE                (1 << 16)
 388
 389 /**
 390  * struct xhci_intr_reg - Interrupt Register Set
 391  * @irq_pending:        IMAN - Interrupt Management Register.  Used to enable
 392  *                      interrupts and check for pending interrupts.
 393  * @irq_control:        IMOD - Interrupt Moderation Register.
 394  *                      Used to throttle interrupts.
 395  * @erst_size:          Number of segments in the Event Ring Segment Table (ERST).
 396  * @erst_base:          ERST base address.
 397  * @erst_dequeue:       Event ring dequeue pointer.
 398  *
 399  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
 400  * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
 401  * multiple segments of the same size.  The HC places events on the ring and
 402  * "updates the Cycle bit in the TRBs to indicate to software the current
 403  * position of the Enqueue Pointer." The HCD (Linux) processes those events and
 404  * updates the dequeue pointer.
 405  */
 406 struct xhci_intr_reg {
 407         __le32  irq_pending;
 408         __le32  irq_control;
 409         __le32  erst_size;
 410         __le32  rsvd;
 411         __le64  erst_base;
 412         __le64  erst_dequeue;
 413 };
 414
 415 /* irq_pending bitmasks */
 416 #define ER_IRQ_PENDING(p)       ((p) & 0x1)
 417 /* bits 2:31 need to be preserved */
 418 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
 419 #define ER_IRQ_CLEAR(p)         ((p) & 0xfffffffe)
 420 #define ER_IRQ_ENABLE(p)        ((ER_IRQ_CLEAR(p)) | 0x2)
 421 #define ER_IRQ_DISABLE(p)       ((ER_IRQ_CLEAR(p)) & ~(0x2))
 422
 423 /* irq_control bitmasks */
 424 /* Minimum interval between interrupts (in 250ns intervals).  The interval
 425  * between interrupts will be longer if there are no events on the event ring.
 426  * Default is 4000 (1 ms).
 427  */
 428 #define ER_IRQ_INTERVAL_MASK    (0xffff)
 429 /* Counter used to count down the time to the next interrupt - HW use only */
 430 #define ER_IRQ_COUNTER_MASK     (0xffff << 16)
 431
 432 /* erst_size bitmasks */
 433 /* Preserve bits 16:31 of erst_size */
 434 #define ERST_SIZE_MASK          (0xffff << 16)
 435
 436 /* erst_dequeue bitmasks */
 437 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
 438  * where the current dequeue pointer lies.  This is an optional HW hint.
 439  */
 440 #define ERST_DESI_MASK          (0x7)
 441 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
 442  * a work queue (or delayed service routine)?
 443  */
 444 #define ERST_EHB                (1 << 3)
 445 #define ERST_PTR_MASK           (0xf)
 446
 447 /**
 448  * struct xhci_run_regs
 449  * @microframe_index:
 450  *              MFINDEX - current microframe number
 451  *
 452  * Section 5.5 Host Controller Runtime Registers:
 453  * "Software should read and write these registers using only Dword (32 bit)
 454  * or larger accesses"
 455  */
 456 struct xhci_run_regs {
 457         __le32                  microframe_index;
 458         __le32                  rsvd[7];
 459         struct xhci_intr_reg    ir_set[128];
 460 };
 461
 462 /**
 463  * struct doorbell_array
 464  *
 465  * Bits  0 -  7: Endpoint target
 466  * Bits  8 - 15: RsvdZ
 467  * Bits 16 - 31: Stream ID
 468  *
 469  * Section 5.6
 470  */
 471 struct xhci_doorbell_array {
 472         __le32  doorbell[256];
 473 };
 474
 475 #define DB_VALUE(ep, stream)    ((((ep) + 1) & 0xff) | ((stream) << 16))
 476 #define DB_VALUE_HOST           0x00000000
 477
 478 /**
 479  * struct xhci_protocol_caps
 480  * @revision:           major revision, minor revision, capability ID,
 481  *                      and next capability pointer.
 482  * @name_string:        Four ASCII characters to say which spec this xHC
 483  *                      follows, typically "USB ".
 484  * @port_info:          Port offset, count, and protocol-defined information.
 485  */
 486 struct xhci_protocol_caps {
 487         u32     revision;
 488         u32     name_string;
 489         u32     port_info;
 490 };
 491
 492 #define XHCI_EXT_PORT_MAJOR(x)  (((x) >> 24) & 0xff)
 493 #define XHCI_EXT_PORT_OFF(x)    ((x) & 0xff)
 494 #define XHCI_EXT_PORT_COUNT(x)  (((x) >> 8) & 0xff)
 495
 496 /**
 497  * struct xhci_container_ctx
 498  * @type: Type of context.  Used to calculated offsets to contained contexts.
 499  * @size: Size of the context data
 500  * @bytes: The raw context data given to HW
 501  * @dma: dma address of the bytes
 502  *
 503  * Represents either a Device or Input context.  Holds a pointer to the raw
 504  * memory used for the context (bytes) and dma address of it (dma).
 505  */
 506 struct xhci_container_ctx {
 507         unsigned type;
 508 #define XHCI_CTX_TYPE_DEVICE  0x1
 509 #define XHCI_CTX_TYPE_INPUT   0x2
 510
 511         int size;
 512
 513         u8 *bytes;
 514         dma_addr_t dma;
 515 };
 516
 517 /**
 518  * struct xhci_slot_ctx
 519  * @dev_info:   Route string, device speed, hub info, and last valid endpoint
 520  * @dev_info2:  Max exit latency for device number, root hub port number
 521  * @tt_info:    tt_info is used to construct split transaction tokens
 522  * @dev_state:  slot state and device address
 523  *
 524  * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
 525  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 526  * reserved at the end of the slot context for HC internal use.
 527  */
 528 struct xhci_slot_ctx {
 529         __le32  dev_info;
 530         __le32  dev_info2;
 531         __le32  tt_info;
 532         __le32  dev_state;
 533         /* offset 0x10 to 0x1f reserved for HC internal use */
 534         __le32  reserved[4];
 535 };
 536
 537 /* dev_info bitmasks */
 538 /* Route String - 0:19 */
 539 #define ROUTE_STRING_MASK       (0xfffff)
 540 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
 541 #define DEV_SPEED       (0xf << 20)
 542 /* bit 24 reserved */
 543 /* Is this LS/FS device connected through a HS hub? - bit 25 */
 544 #define DEV_MTT         (0x1 << 25)
 545 /* Set if the device is a hub - bit 26 */
 546 #define DEV_HUB         (0x1 << 26)
 547 /* Index of the last valid endpoint context in this device context - 27:31 */
 548 #define LAST_CTX_MASK   (0x1f << 27)
 549 #define LAST_CTX(p)     ((p) << 27)
 550 #define LAST_CTX_TO_EP_NUM(p)   (((p) >> 27) - 1)
 551 #define SLOT_FLAG       (1 << 0)
 552 #define EP0_FLAG        (1 << 1)
 553
 554 /* dev_info2 bitmasks */
 555 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
 556 #define MAX_EXIT        (0xffff)
 557 /* Root hub port number that is needed to access the USB device */
 558 #define ROOT_HUB_PORT(p)        (((p) & 0xff) << 16)
 559 #define DEVINFO_TO_ROOT_HUB_PORT(p)     (((p) >> 16) & 0xff)
 560 /* Maximum number of ports under a hub device */
 561 #define XHCI_MAX_PORTS(p)       (((p) & 0xff) << 24)
 562
 563 /* tt_info bitmasks */
 564 /*
 565  * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
 566  * The Slot ID of the hub that isolates the high speed signaling from
 567  * this low or full-speed device.  '0' if attached to root hub port.
 568  */
 569 #define TT_SLOT         (0xff)
 570 /*
 571  * The number of the downstream facing port of the high-speed hub
 572  * '0' if the device is not low or full speed.
 573  */
 574 #define TT_PORT         (0xff << 8)
 575 #define TT_THINK_TIME(p)        (((p) & 0x3) << 16)
 576
 577 /* dev_state bitmasks */
 578 /* USB device address - assigned by the HC */
 579 #define DEV_ADDR_MASK   (0xff)
 580 /* bits 8:26 reserved */
 581 /* Slot state */
 582 #define SLOT_STATE      (0x1f << 27)
 583 #define GET_SLOT_STATE(p)       (((p) & (0x1f << 27)) >> 27)
 584
 585 #define SLOT_STATE_DISABLED     0
 586 #define SLOT_STATE_ENABLED      SLOT_STATE_DISABLED
 587 #define SLOT_STATE_DEFAULT      1
 588 #define SLOT_STATE_ADDRESSED    2
 589 #define SLOT_STATE_CONFIGURED   3
 590
 591 /**
 592  * struct xhci_ep_ctx
 593  * @ep_info:    endpoint state, streams, mult, and interval information.
 594  * @ep_info2:   information on endpoint type, max packet size, max burst size,
 595  *              error count, and whether the HC will force an event for all
 596  *              transactions.
 597  * @deq:        64-bit ring dequeue pointer address.  If the endpoint only
 598  *              defines one stream, this points to the endpoint transfer ring.
 599  *              Otherwise, it points to a stream context array, which has a
 600  *              ring pointer for each flow.
 601  * @tx_info:
 602  *              Average TRB lengths for the endpoint ring and
 603  *              max payload within an Endpoint Service Interval Time (ESIT).
 604  *
 605  * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
 606  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 607  * reserved at the end of the endpoint context for HC internal use.
 608  */
 609 struct xhci_ep_ctx {
 610         __le32  ep_info;
 611         __le32  ep_info2;
 612         __le64  deq;
 613         __le32  tx_info;
 614         /* offset 0x14 - 0x1f reserved for HC internal use */
 615         __le32  reserved[3];
 616 };
 617
 618 /* ep_info bitmasks */
 619 /*
 620  * Endpoint State - bits 0:2
 621  * 0 - disabled
 622  * 1 - running
 623  * 2 - halted due to halt condition - ok to manipulate endpoint ring
 624  * 3 - stopped
 625  * 4 - TRB error
 626  * 5-7 - reserved
 627  */
 628 #define EP_STATE_MASK           (0xf)
 629 #define EP_STATE_DISABLED       0
 630 #define EP_STATE_RUNNING        1
 631 #define EP_STATE_HALTED         2
 632 #define EP_STATE_STOPPED        3
 633 #define EP_STATE_ERROR          4
 634 /* Mult - Max number of burtst within an interval, in EP companion desc. */
 635 #define EP_MULT(p)              (((p) & 0x3) << 8)
 636 #define CTX_TO_EP_MULT(p)       (((p) >> 8) & 0x3)
 637 /* bits 10:14 are Max Primary Streams */
 638 /* bit 15 is Linear Stream Array */
 639 /* Interval - period between requests to an endpoint - 125u increments. */
 640 #define EP_INTERVAL(p)          (((p) & 0xff) << 16)
 641 #define EP_INTERVAL_TO_UFRAMES(p)               (1 << (((p) >> 16) & 0xff))
 642 #define CTX_TO_EP_INTERVAL(p)   (((p) >> 16) & 0xff)
 643 #define EP_MAXPSTREAMS_MASK     (0x1f << 10)
 644 #define EP_MAXPSTREAMS(p)       (((p) << 10) & EP_MAXPSTREAMS_MASK)
 645 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
 646 #define EP_HAS_LSA              (1 << 15)
 647
 648 /* ep_info2 bitmasks */
 649 /*
 650  * Force Event - generate transfer events for all TRBs for this endpoint
 651  * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
 652  */
 653 #define FORCE_EVENT     (0x1)
 654 #define ERROR_COUNT(p)  (((p) & 0x3) << 1)
 655 #define CTX_TO_EP_TYPE(p)       (((p) >> 3) & 0x7)
 656 #define EP_TYPE(p)      ((p) << 3)
 657 #define ISOC_OUT_EP     1
 658 #define BULK_OUT_EP     2
 659 #define INT_OUT_EP      3
 660 #define CTRL_EP         4
 661 #define ISOC_IN_EP      5
 662 #define BULK_IN_EP      6
 663 #define INT_IN_EP       7
 664 /* bit 6 reserved */
 665 /* bit 7 is Host Initiate Disable - for disabling stream selection */
 666 #define MAX_BURST(p)    (((p)&0xff) << 8)
 667 #define CTX_TO_MAX_BURST(p)     (((p) >> 8) & 0xff)
 668 #define MAX_PACKET(p)   (((p)&0xffff) << 16)
 669 #define MAX_PACKET_MASK         (0xffff << 16)
 670 #define MAX_PACKET_DECODED(p)   (((p) >> 16) & 0xffff)
 671
 672 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
 673  * USB2.0 spec 9.6.6.
 674  */
 675 #define GET_MAX_PACKET(p)       ((p) & 0x7ff)
 676
 677 /* tx_info bitmasks */
 678 #define AVG_TRB_LENGTH_FOR_EP(p)        ((p) & 0xffff)
 679 #define MAX_ESIT_PAYLOAD_FOR_EP(p)      (((p) & 0xffff) << 16)
 680 #define CTX_TO_MAX_ESIT_PAYLOAD(p)      (((p) >> 16) & 0xffff)
 681
 682 /* deq bitmasks */
 683 #define EP_CTX_CYCLE_MASK               (1 << 0)
 684
 685
 686 /**
 687  * struct xhci_input_control_context
 688  * Input control context; see section 6.2.5.
 689  *
 690  * @drop_context:       set the bit of the endpoint context you want to disable
 691  * @add_context:        set the bit of the endpoint context you want to enable
 692  */
 693 struct xhci_input_control_ctx {
 694         __le32  drop_flags;
 695         __le32  add_flags;
 696         __le32  rsvd2[6];
 697 };
 698
 699 #define EP_IS_ADDED(ctrl_ctx, i) \
 700         (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
 701 #define EP_IS_DROPPED(ctrl_ctx, i)       \
 702         (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
 703
 704 /* Represents everything that is needed to issue a command on the command ring.
 705  * It's useful to pre-allocate these for commands that cannot fail due to
 706  * out-of-memory errors, like freeing streams.
 707  */
 708 struct xhci_command {
 709         /* Input context for changing device state */
 710         struct xhci_container_ctx       *in_ctx;
 711         u32                             status;
 712         /* If completion is null, no one is waiting on this command
 713          * and the structure can be freed after the command completes.
 714          */
 715         struct completion               *completion;
 716         union xhci_trb                  *command_trb;
 717         struct list_head                cmd_list;
 718 };
 719
 720 /* drop context bitmasks */
 721 #define DROP_EP(x)      (0x1 << x)
 722 /* add context bitmasks */
 723 #define ADD_EP(x)       (0x1 << x)
 724
 725 struct xhci_stream_ctx {
 726         /* 64-bit stream ring address, cycle state, and stream type */
 727         __le64  stream_ring;
 728         /* offset 0x14 - 0x1f reserved for HC internal use */
 729         __le32  reserved[2];
 730 };
 731
 732 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
 733 #define SCT_FOR_CTX(p)          (((p) << 1) & 0x7)
 734 /* Secondary stream array type, dequeue pointer is to a transfer ring */
 735 #define SCT_SEC_TR              0
 736 /* Primary stream array type, dequeue pointer is to a transfer ring */
 737 #define SCT_PRI_TR              1
 738 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
 739 #define SCT_SSA_8               2
 740 #define SCT_SSA_16              3
 741 #define SCT_SSA_32              4
 742 #define SCT_SSA_64              5
 743 #define SCT_SSA_128             6
 744 #define SCT_SSA_256             7
 745
 746 /* Assume no secondary streams for now */
 747 struct xhci_stream_info {
 748         struct xhci_ring                **stream_rings;
 749         /* Number of streams, including stream 0 (which drivers can't use) */
 750         unsigned int                    num_streams;
 751         /* The stream context array may be bigger than
 752          * the number of streams the driver asked for
 753          */
 754         struct xhci_stream_ctx          *stream_ctx_array;
 755         unsigned int                    num_stream_ctxs;
 756         dma_addr_t                      ctx_array_dma;
 757         /* For mapping physical TRB addresses to segments in stream rings */
 758         struct radix_tree_root          trb_address_map;
 759         struct xhci_command             *free_streams_command;
 760 };
 761
 762 #define SMALL_STREAM_ARRAY_SIZE         256
 763 #define MEDIUM_STREAM_ARRAY_SIZE        1024
 764
 765 /* Some Intel xHCI host controllers need software to keep track of the bus
 766  * bandwidth.  Keep track of endpoint info here.  Each root port is allocated
 767  * the full bus bandwidth.  We must also treat TTs (including each port under a
 768  * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
 769  * (DMI) also limits the total bandwidth (across all domains) that can be used.
 770  */
 771 struct xhci_bw_info {
 772         /* ep_interval is zero-based */
 773         unsigned int            ep_interval;
 774         /* mult and num_packets are one-based */
 775         unsigned int            mult;
 776         unsigned int            num_packets;
 777         unsigned int            max_packet_size;
 778         unsigned int            max_esit_payload;
 779         unsigned int            type;
 780 };
 781
 782 /* "Block" sizes in bytes the hardware uses for different device speeds.
 783  * The logic in this part of the hardware limits the number of bits the hardware
 784  * can use, so must represent bandwidth in a less precise manner to mimic what
 785  * the scheduler hardware computes.
 786  */
 787 #define FS_BLOCK        1
 788 #define HS_BLOCK        4
 789 #define SS_BLOCK        16
 790 #define DMI_BLOCK       32
 791
 792 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
 793  * with each byte transferred.  SuperSpeed devices have an initial overhead to
 794  * set up bursts.  These are in blocks, see above.  LS overhead has already been
 795  * translated into FS blocks.
 796  */
 797 #define DMI_OVERHEAD 8
 798 #define DMI_OVERHEAD_BURST 4
 799 #define SS_OVERHEAD 8
 800 #define SS_OVERHEAD_BURST 32
 801 #define HS_OVERHEAD 26
 802 #define FS_OVERHEAD 20
 803 #define LS_OVERHEAD 128
 804 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
 805  * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
 806  * of overhead associated with split transfers crossing microframe boundaries.
 807  * 31 blocks is pure protocol overhead.
 808  */
 809 #define TT_HS_OVERHEAD (31 + 94)
 810 #define TT_DMI_OVERHEAD (25 + 12)
 811
 812 /* Bandwidth limits in blocks */
 813 #define FS_BW_LIMIT             1285
 814 #define TT_BW_LIMIT             1320
 815 #define HS_BW_LIMIT             1607
 816 #define SS_BW_LIMIT_IN          3906
 817 #define DMI_BW_LIMIT_IN         3906
 818 #define SS_BW_LIMIT_OUT         3906
 819 #define DMI_BW_LIMIT_OUT        3906
 820
 821 /* Percentage of bus bandwidth reserved for non-periodic transfers */
 822 #define FS_BW_RESERVED          10
 823 #define HS_BW_RESERVED          20
 824 #define SS_BW_RESERVED          10
 825
 826 struct xhci_virt_ep {
 827         struct xhci_ring                *ring;
 828         /* Related to endpoints that are configured to use stream IDs only */
 829         struct xhci_stream_info         *stream_info;
 830         /* Temporary storage in case the configure endpoint command fails and we
 831          * have to restore the device state to the previous state
 832          */
 833         struct xhci_ring                *new_ring;
 834         unsigned int                    ep_state;
 835 #define SET_DEQ_PENDING         (1 << 0)
 836 #define EP_HALTED               (1 << 1)        /* For stall handling */
 837 #define EP_HALT_PENDING         (1 << 2)        /* For URB cancellation */
 838 /* Transitioning the endpoint to using streams, don't enqueue URBs */
 839 #define EP_GETTING_STREAMS      (1 << 3)
 840 #define EP_HAS_STREAMS          (1 << 4)
 841 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
 842 #define EP_GETTING_NO_STREAMS   (1 << 5)
 843         /* ----  Related to URB cancellation ---- */
 844         struct list_head        cancelled_td_list;
 845         /* The TRB that was last reported in a stopped endpoint ring */
 846         union xhci_trb          *stopped_trb;
 847         struct xhci_td          *stopped_td;
 848         unsigned int            stopped_stream;
 849         /* Watchdog timer for stop endpoint command to cancel URBs */
 850         struct timer_list       stop_cmd_timer;
 851         int                     stop_cmds_pending;
 852         struct xhci_hcd         *xhci;
 853         /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
 854          * command.  We'll need to update the ring's dequeue segment and dequeue
 855          * pointer after the command completes.
 856          */
 857         struct xhci_segment     *queued_deq_seg;
 858         union xhci_trb          *queued_deq_ptr;
 859         /*
 860          * Sometimes the xHC can not process isochronous endpoint ring quickly
 861          * enough, and it will miss some isoc tds on the ring and generate
 862          * a Missed Service Error Event.
 863          * Set skip flag when receive a Missed Service Error Event and
 864          * process the missed tds on the endpoint ring.
 865          */
 866         bool                    skip;
 867         /* Bandwidth checking storage */
 868         struct xhci_bw_info     bw_info;
 869         struct list_head        bw_endpoint_list;
 870 };
 871
 872 enum xhci_overhead_type {
 873         LS_OVERHEAD_TYPE = 0,
 874         FS_OVERHEAD_TYPE,
 875         HS_OVERHEAD_TYPE,
 876 };
 877
 878 struct xhci_interval_bw {
 879         unsigned int            num_packets;
 880         /* Sorted by max packet size.
 881          * Head of the list is the greatest max packet size.
 882          */
 883         struct list_head        endpoints;
 884         /* How many endpoints of each speed are present. */
 885         unsigned int            overhead[3];
 886 };
 887
 888 #define XHCI_MAX_INTERVAL       16
 889
 890 struct xhci_interval_bw_table {
 891         unsigned int            interval0_esit_payload;
 892         struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
 893         /* Includes reserved bandwidth for async endpoints */
 894         unsigned int            bw_used;
 895         unsigned int            ss_bw_in;
 896         unsigned int            ss_bw_out;
 897 };
 898
 899
 900 struct xhci_virt_device {
 901         struct usb_device               *udev;
 902         /*
 903          * Commands to the hardware are passed an "input context" that
 904          * tells the hardware what to change in its data structures.
 905          * The hardware will return changes in an "output context" that
 906          * software must allocate for the hardware.  We need to keep
 907          * track of input and output contexts separately because
 908          * these commands might fail and we don't trust the hardware.
 909          */
 910         struct xhci_container_ctx       *out_ctx;
 911         /* Used for addressing devices and configuration changes */
 912         struct xhci_container_ctx       *in_ctx;
 913         /* Rings saved to ensure old alt settings can be re-instated */
 914         struct xhci_ring                **ring_cache;
 915         int                             num_rings_cached;
 916         /* Store xHC assigned device address */
 917         int                             address;
 918 #define XHCI_MAX_RINGS_CACHED   31
 919         struct xhci_virt_ep             eps[31];
 920         struct completion               cmd_completion;
 921         /* Status of the last command issued for this device */
 922         u32                             cmd_status;
 923         struct list_head                cmd_list;
 924         u8                              fake_port;
 925         u8                              real_port;
 926         struct xhci_interval_bw_table   *bw_table;
 927         struct xhci_tt_bw_info          *tt_info;
 928         /* The current max exit latency for the enabled USB3 link states. */
 929         u16                             current_mel;
 930 };
 931
 932 /*
 933  * For each roothub, keep track of the bandwidth information for each periodic
 934  * interval.
 935  *
 936  * If a high speed hub is attached to the roothub, each TT associated with that
 937  * hub is a separate bandwidth domain.  The interval information for the
 938  * endpoints on the devices under that TT will appear in the TT structure.
 939  */
 940 struct xhci_root_port_bw_info {
 941         struct list_head                tts;
 942         unsigned int                    num_active_tts;
 943         struct xhci_interval_bw_table   bw_table;
 944 };
 945
 946 struct xhci_tt_bw_info {
 947         struct list_head                tt_list;
 948         int                             slot_id;
 949         int                             ttport;
 950         struct xhci_interval_bw_table   bw_table;
 951         int                             active_eps;
 952 };
 953
 954
 955 /**
 956  * struct xhci_device_context_array
 957  * @dev_context_ptr     array of 64-bit DMA addresses for device contexts
 958  */
 959 struct xhci_device_context_array {
 960         /* 64-bit device addresses; we only write 32-bit addresses */
 961         __le64                  dev_context_ptrs[MAX_HC_SLOTS];
 962         /* private xHCD pointers */
 963         dma_addr_t      dma;
 964 };
 965 /* TODO: write function to set the 64-bit device DMA address */
 966 /*
 967  * TODO: change this to be dynamically sized at HC mem init time since the HC
 968  * might not be able to handle the maximum number of devices possible.
 969  */
 970
 971
 972 struct xhci_transfer_event {
 973         /* 64-bit buffer address, or immediate data */
 974         __le64  buffer;
 975         __le32  transfer_len;
 976         /* This field is interpreted differently based on the type of TRB */
 977         __le32  flags;
 978 };
 979
 980 /* Transfer event TRB length bit mask */
 981 /* bits 0:23 */
 982 #define EVENT_TRB_LEN(p)                ((p) & 0xffffff)
 983
 984 /** Transfer Event bit fields **/
 985 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
 986
 987 /* Completion Code - only applicable for some types of TRBs */
 988 #define COMP_CODE_MASK          (0xff << 24)
 989 #define GET_COMP_CODE(p)        (((p) & COMP_CODE_MASK) >> 24)
 990 #define COMP_SUCCESS    1
 991 /* Data Buffer Error */
 992 #define COMP_DB_ERR     2
 993 /* Babble Detected Error */
 994 #define COMP_BABBLE     3
 995 /* USB Transaction Error */
 996 #define COMP_TX_ERR     4
 997 /* TRB Error - some TRB field is invalid */
 998 #define COMP_TRB_ERR    5
 999 /* Stall Error - USB device is stalled */
1000 #define COMP_STALL      6
1001 /* Resource Error - HC doesn't have memory for that device configuration */
1002 #define COMP_ENOMEM     7
1003 /* Bandwidth Error - not enough room in schedule for this dev config */
1004 #define COMP_BW_ERR     8
1005 /* No Slots Available Error - HC ran out of device slots */
1006 #define COMP_ENOSLOTS   9
1007 /* Invalid Stream Type Error */
1008 #define COMP_STREAM_ERR 10
1009 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1010 #define COMP_EBADSLT    11
1011 /* Endpoint Not Enabled Error */
1012 #define COMP_EBADEP     12
1013 /* Short Packet */
1014 #define COMP_SHORT_TX   13
1015 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1016 #define COMP_UNDERRUN   14
1017 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1018 #define COMP_OVERRUN    15
1019 /* Virtual Function Event Ring Full Error */
1020 #define COMP_VF_FULL    16
1021 /* Parameter Error - Context parameter is invalid */
1022 #define COMP_EINVAL     17
1023 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1024 #define COMP_BW_OVER    18
1025 /* Context State Error - illegal context state transition requested */
1026 #define COMP_CTX_STATE  19
1027 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1028 #define COMP_PING_ERR   20
1029 /* Event Ring is full */
1030 #define COMP_ER_FULL    21
1031 /* Incompatible Device Error */
1032 #define COMP_DEV_ERR    22
1033 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1034 #define COMP_MISSED_INT 23
1035 /* Successfully stopped command ring */
1036 #define COMP_CMD_STOP   24
1037 /* Successfully aborted current command and stopped command ring */
1038 #define COMP_CMD_ABORT  25
1039 /* Stopped - transfer was terminated by a stop endpoint command */
1040 #define COMP_STOP       26
1041 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1042 #define COMP_STOP_INVAL 27
1043 /* Control Abort Error - Debug Capability - control pipe aborted */
1044 #define COMP_DBG_ABORT  28
1045 /* Max Exit Latency Too Large Error */
1046 #define COMP_MEL_ERR    29
1047 /* TRB type 30 reserved */
1048 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1049 #define COMP_BUFF_OVER  31
1050 /* Event Lost Error - xHC has an "internal event overrun condition" */
1051 #define COMP_ISSUES     32
1052 /* Undefined Error - reported when other error codes don't apply */
1053 #define COMP_UNKNOWN    33
1054 /* Invalid Stream ID Error */
1055 #define COMP_STRID_ERR  34
1056 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1057 #define COMP_2ND_BW_ERR 35
1058 /* Split Transaction Error */
1059 #define COMP_SPLIT_ERR  36
1060
1061 struct xhci_link_trb {
1062         /* 64-bit segment pointer*/
1063         __le64 segment_ptr;
1064         __le32 intr_target;
1065         __le32 control;
1066 };
1067
1068 /* control bitfields */
1069 #define LINK_TOGGLE     (0x1<<1)
1070
1071 /* Command completion event TRB */
1072 struct xhci_event_cmd {
1073         /* Pointer to command TRB, or the value passed by the event data trb */
1074         __le64 cmd_trb;
1075         __le32 status;
1076         __le32 flags;
1077 };
1078
1079 /* flags bitmasks */
1080 /* bits 16:23 are the virtual function ID */
1081 /* bits 24:31 are the slot ID */
1082 #define TRB_TO_SLOT_ID(p)       (((p) & (0xff<<24)) >> 24)
1083 #define SLOT_ID_FOR_TRB(p)      (((p) & 0xff) << 24)
1084
1085 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1086 #define TRB_TO_EP_INDEX(p)              ((((p) & (0x1f << 16)) >> 16) - 1)
1087 #define EP_ID_FOR_TRB(p)                ((((p) + 1) & 0x1f) << 16)
1088
1089 #define SUSPEND_PORT_FOR_TRB(p)         (((p) & 1) << 23)
1090 #define TRB_TO_SUSPEND_PORT(p)          (((p) & (1 << 23)) >> 23)
1091 #define LAST_EP_INDEX                   30
1092
1093 /* Set TR Dequeue Pointer command TRB fields */
1094 #define TRB_TO_STREAM_ID(p)             ((((p) & (0xffff << 16)) >> 16))
1095 #define STREAM_ID_FOR_TRB(p)            ((((p)) & 0xffff) << 16)
1096
1097
1098 /* Port Status Change Event TRB fields */
1099 /* Port ID - bits 31:24 */
1100 #define GET_PORT_ID(p)          (((p) & (0xff << 24)) >> 24)
1101
1102 /* Normal TRB fields */
1103 /* transfer_len bitmasks - bits 0:16 */
1104 #define TRB_LEN(p)              ((p) & 0x1ffff)
1105 /* Interrupter Target - which MSI-X vector to target the completion event at */
1106 #define TRB_INTR_TARGET(p)      (((p) & 0x3ff) << 22)
1107 #define GET_INTR_TARGET(p)      (((p) >> 22) & 0x3ff)
1108 #define TRB_TBC(p)              (((p) & 0x3) << 7)
1109 #define TRB_TLBPC(p)            (((p) & 0xf) << 16)
1110
1111 /* Cycle bit - indicates TRB ownership by HC or HCD */
1112 #define TRB_CYCLE               (1<<0)
1113 /*
1114  * Force next event data TRB to be evaluated before task switch.
1115  * Used to pass OS data back after a TD completes.
1116  */
1117 #define TRB_ENT                 (1<<1)
1118 /* Interrupt on short packet */
1119 #define TRB_ISP                 (1<<2)
1120 /* Set PCIe no snoop attribute */
1121 #define TRB_NO_SNOOP            (1<<3)
1122 /* Chain multiple TRBs into a TD */
1123 #define TRB_CHAIN               (1<<4)
1124 /* Interrupt on completion */
1125 #define TRB_IOC                 (1<<5)
1126 /* The buffer pointer contains immediate data */
1127 #define TRB_IDT                 (1<<6)
1128
1129 /* Block Event Interrupt */
1130 #define TRB_BEI                 (1<<9)
1131
1132 /* Control transfer TRB specific fields */
1133 #define TRB_DIR_IN              (1<<16)
1134 #define TRB_TX_TYPE(p)          ((p) << 16)
1135 #define TRB_DATA_OUT            2
1136 #define TRB_DATA_IN             3
1137
1138 /* Isochronous TRB specific fields */
1139 #define TRB_SIA                 (1<<31)
1140
1141 struct xhci_generic_trb {
1142         __le32 field[4];
1143 };
1144
1145 union xhci_trb {
1146         struct xhci_link_trb            link;
1147         struct xhci_transfer_event      trans_event;
1148         struct xhci_event_cmd           event_cmd;
1149         struct xhci_generic_trb         generic;
1150 };
1151
1152 /* TRB bit mask */
1153 #define TRB_TYPE_BITMASK        (0xfc00)
1154 #define TRB_TYPE(p)             ((p) << 10)
1155 #define TRB_FIELD_TO_TYPE(p)    (((p) & TRB_TYPE_BITMASK) >> 10)
1156 /* TRB type IDs */
1157 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1158 #define TRB_NORMAL              1
1159 /* setup stage for control transfers */
1160 #define TRB_SETUP               2
1161 /* data stage for control transfers */
1162 #define TRB_DATA                3
1163 /* status stage for control transfers */
1164 #define TRB_STATUS              4
1165 /* isoc transfers */
1166 #define TRB_ISOC                5
1167 /* TRB for linking ring segments */
1168 #define TRB_LINK                6
1169 #define TRB_EVENT_DATA          7
1170 /* Transfer Ring No-op (not for the command ring) */
1171 #define TRB_TR_NOOP             8
1172 /* Command TRBs */
1173 /* Enable Slot Command */
1174 #define TRB_ENABLE_SLOT         9
1175 /* Disable Slot Command */
1176 #define TRB_DISABLE_SLOT        10
1177 /* Address Device Command */
1178 #define TRB_ADDR_DEV            11
1179 /* Configure Endpoint Command */
1180 #define TRB_CONFIG_EP           12
1181 /* Evaluate Context Command */
1182 #define TRB_EVAL_CONTEXT        13
1183 /* Reset Endpoint Command */
1184 #define TRB_RESET_EP            14
1185 /* Stop Transfer Ring Command */
1186 #define TRB_STOP_RING           15
1187 /* Set Transfer Ring Dequeue Pointer Command */
1188 #define TRB_SET_DEQ             16
1189 /* Reset Device Command */
1190 #define TRB_RESET_DEV           17
1191 /* Force Event Command (opt) */
1192 #define TRB_FORCE_EVENT         18
1193 /* Negotiate Bandwidth Command (opt) */
1194 #define TRB_NEG_BANDWIDTH       19
1195 /* Set Latency Tolerance Value Command (opt) */
1196 #define TRB_SET_LT              20
1197 /* Get port bandwidth Command */
1198 #define TRB_GET_BW              21
1199 /* Force Header Command - generate a transaction or link management packet */
1200 #define TRB_FORCE_HEADER        22
1201 /* No-op Command - not for transfer rings */
1202 #define TRB_CMD_NOOP            23
1203 /* TRB IDs 24-31 reserved */
1204 /* Event TRBS */
1205 /* Transfer Event */
1206 #define TRB_TRANSFER            32
1207 /* Command Completion Event */
1208 #define TRB_COMPLETION          33
1209 /* Port Status Change Event */
1210 #define TRB_PORT_STATUS         34
1211 /* Bandwidth Request Event (opt) */
1212 #define TRB_BANDWIDTH_EVENT     35
1213 /* Doorbell Event (opt) */
1214 #define TRB_DOORBELL            36
1215 /* Host Controller Event */
1216 #define TRB_HC_EVENT            37
1217 /* Device Notification Event - device sent function wake notification */
1218 #define TRB_DEV_NOTE            38
1219 /* MFINDEX Wrap Event - microframe counter wrapped */
1220 #define TRB_MFINDEX_WRAP        39
1221 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1222
1223 /* Nec vendor-specific command completion event. */
1224 #define TRB_NEC_CMD_COMP        48
1225 /* Get NEC firmware revision. */
1226 #define TRB_NEC_GET_FW          49
1227
1228 #define TRB_TYPE_LINK(x)        (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1229 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1230 #define TRB_TYPE_LINK_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1231                                  cpu_to_le32(TRB_TYPE(TRB_LINK)))
1232 #define TRB_TYPE_NOOP_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1233                                  cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1234
1235 #define NEC_FW_MINOR(p)         (((p) >> 0) & 0xff)
1236 #define NEC_FW_MAJOR(p)         (((p) >> 8) & 0xff)
1237
1238 /*
1239  * TRBS_PER_SEGMENT must be a multiple of 4,
1240  * since the command ring is 64-byte aligned.
1241  * It must also be greater than 16.
1242  */
1243 #define TRBS_PER_SEGMENT        64
1244 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1245 #define MAX_RSVD_CMD_TRBS       (TRBS_PER_SEGMENT - 3)
1246 #define TRB_SEGMENT_SIZE        (TRBS_PER_SEGMENT*16)
1247 #define TRB_SEGMENT_SHIFT       (ilog2(TRB_SEGMENT_SIZE))
1248 /* TRB buffer pointers can't cross 64KB boundaries */
1249 #define TRB_MAX_BUFF_SHIFT              16
1250 #define TRB_MAX_BUFF_SIZE       (1 << TRB_MAX_BUFF_SHIFT)
1251
1252 struct xhci_segment {
1253         union xhci_trb          *trbs;
1254         /* private to HCD */
1255         struct xhci_segment     *next;
1256         dma_addr_t              dma;
1257 };
1258
1259 struct xhci_td {
1260         struct list_head        td_list;
1261         struct list_head        cancelled_td_list;
1262         struct urb              *urb;
1263         struct xhci_segment     *start_seg;
1264         union xhci_trb          *first_trb;
1265         union xhci_trb          *last_trb;
1266 };
1267
1268 /* xHCI command default timeout value */
1269 #define XHCI_CMD_DEFAULT_TIMEOUT        (5 * HZ)
1270
1271 /* command descriptor */
1272 struct xhci_cd {
1273         struct list_head        cancel_cmd_list;
1274         struct xhci_command     *command;
1275         union xhci_trb          *cmd_trb;
1276 };
1277
1278 struct xhci_dequeue_state {
1279         struct xhci_segment *new_deq_seg;
1280         union xhci_trb *new_deq_ptr;
1281         int new_cycle_state;
1282 };
1283
1284 enum xhci_ring_type {
1285         TYPE_CTRL = 0,
1286         TYPE_ISOC,
1287         TYPE_BULK,
1288         TYPE_INTR,
1289         TYPE_STREAM,
1290         TYPE_COMMAND,
1291         TYPE_EVENT,
1292 };
1293
1294 struct xhci_ring {
1295         struct xhci_segment     *first_seg;
1296         struct xhci_segment     *last_seg;
1297         union  xhci_trb         *enqueue;
1298         struct xhci_segment     *enq_seg;
1299         unsigned int            enq_updates;
1300         union  xhci_trb         *dequeue;
1301         struct xhci_segment     *deq_seg;
1302         unsigned int            deq_updates;
1303         struct list_head        td_list;
1304         /*
1305          * Write the cycle state into the TRB cycle field to give ownership of
1306          * the TRB to the host controller (if we are the producer), or to check
1307          * if we own the TRB (if we are the consumer).  See section 4.9.1.
1308          */
1309         u32                     cycle_state;
1310         unsigned int            stream_id;
1311         unsigned int            num_segs;
1312         unsigned int            num_trbs_free;
1313         unsigned int            num_trbs_free_temp;
1314         enum xhci_ring_type     type;
1315         bool                    last_td_was_short;
1316 };
1317
1318 struct xhci_erst_entry {
1319         /* 64-bit event ring segment address */
1320         __le64  seg_addr;
1321         __le32  seg_size;
1322         /* Set to zero */
1323         __le32  rsvd;
1324 };
1325
1326 struct xhci_erst {
1327         struct xhci_erst_entry  *entries;
1328         unsigned int            num_entries;
1329         /* xhci->event_ring keeps track of segment dma addresses */
1330         dma_addr_t              erst_dma_addr;
1331         /* Num entries the ERST can contain */
1332         unsigned int            erst_size;
1333 };
1334
1335 struct xhci_scratchpad {
1336         u64 *sp_array;
1337         dma_addr_t sp_dma;
1338         void **sp_buffers;
1339         dma_addr_t *sp_dma_buffers;
1340 };
1341
1342 struct urb_priv {
1343         int     length;
1344         int     td_cnt;
1345         struct  xhci_td *td[0];
1346 };
1347
1348 /*
1349  * Each segment table entry is 4*32bits long.  1K seems like an ok size:
1350  * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1351  * meaning 64 ring segments.
1352  * Initial allocated size of the ERST, in number of entries */
1353 #define ERST_NUM_SEGS   1
1354 /* Initial allocated size of the ERST, in number of entries */
1355 #define ERST_SIZE       64
1356 /* Initial number of event segment rings allocated */
1357 #define ERST_ENTRIES    1
1358 /* Poll every 60 seconds */
1359 #define POLL_TIMEOUT    60
1360 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1361 #define XHCI_STOP_EP_CMD_TIMEOUT        5
1362 /* XXX: Make these module parameters */
1363
1364 struct s3_save {
1365         u32     command;
1366         u32     dev_nt;
1367         u64     dcbaa_ptr;
1368         u32     config_reg;
1369         u32     irq_pending;
1370         u32     irq_control;
1371         u32     erst_size;
1372         u64     erst_base;
1373         u64     erst_dequeue;
1374 };
1375
1376 /* Use for lpm */
1377 struct dev_info {
1378         u32                     dev_id;
1379         struct  list_head       list;
1380 };
1381
1382 struct xhci_bus_state {
1383         unsigned long           bus_suspended;
1384         unsigned long           next_statechange;
1385
1386         /* Port suspend arrays are indexed by the portnum of the fake roothub */
1387         /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1388         u32                     port_c_suspend;
1389         u32                     suspended_ports;
1390         u32                     port_remote_wakeup;
1391         unsigned long           resume_done[USB_MAXCHILDREN];
1392         /* which ports have started to resume */
1393         unsigned long           resuming_ports;
1394 };
1395
1396 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1397 {
1398         if (hcd->speed == HCD_USB3)
1399                 return 0;
1400         else
1401                 return 1;
1402 }
1403
1404 /* There is one xhci_hcd structure per controller */
1405 struct xhci_hcd {
1406         struct usb_hcd *main_hcd;
1407         struct usb_hcd *shared_hcd;
1408         /* glue to PCI and HCD framework */
1409         struct xhci_cap_regs __iomem *cap_regs;
1410         struct xhci_op_regs __iomem *op_regs;
1411         struct xhci_run_regs __iomem *run_regs;
1412         struct xhci_doorbell_array __iomem *dba;
1413         /* Our HCD's current interrupter register set */
1414         struct  xhci_intr_reg __iomem *ir_set;
1415
1416         /* Cached register copies of read-only HC data */
1417         __u32           hcs_params1;
1418         __u32           hcs_params2;
1419         __u32           hcs_params3;
1420         __u32           hcc_params;
1421
1422         spinlock_t      lock;
1423
1424         /* packed release number */
1425         u8              sbrn;
1426         u16             hci_version;
1427         u8              max_slots;
1428         u8              max_interrupters;
1429         u8              max_ports;
1430         u8              isoc_threshold;
1431         int             event_ring_max;
1432         int             addr_64;
1433         /* 4KB min, 128MB max */
1434         int             page_size;
1435         /* Valid values are 12 to 20, inclusive */
1436         int             page_shift;
1437         /* msi-x vectors */
1438         int             msix_count;
1439         struct msix_entry       *msix_entries;
1440         /* data structures */
1441         struct xhci_device_context_array *dcbaa;
1442         struct xhci_ring        *cmd_ring;
1443         unsigned int            cmd_ring_state;
1444 #define CMD_RING_STATE_RUNNING         (1 << 0)
1445 #define CMD_RING_STATE_ABORTED         (1 << 1)
1446 #define CMD_RING_STATE_STOPPED         (1 << 2)
1447         struct list_head        cancel_cmd_list;
1448         unsigned int            cmd_ring_reserved_trbs;
1449         struct xhci_ring        *event_ring;
1450         struct xhci_erst        erst;
1451         /* Scratchpad */
1452         struct xhci_scratchpad  *scratchpad;
1453         /* Store LPM test failed devices' information */
1454         struct list_head        lpm_failed_devs;
1455
1456         /* slot enabling and address device helpers */
1457         struct completion       addr_dev;
1458         int slot_id;
1459         /* For USB 3.0 LPM enable/disable. */
1460         struct xhci_command             *lpm_command;
1461         /* Internal mirror of the HW's dcbaa */
1462         struct xhci_virt_device *devs[MAX_HC_SLOTS];
1463         /* For keeping track of bandwidth domains per roothub. */
1464         struct xhci_root_port_bw_info   *rh_bw;
1465
1466         /* DMA pools */
1467         struct dma_pool *device_pool;
1468         struct dma_pool *segment_pool;
1469         struct dma_pool *small_streams_pool;
1470         struct dma_pool *medium_streams_pool;
1471
1472 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1473         /* Poll the rings - for debugging */
1474         struct timer_list       event_ring_timer;
1475         int                     zombie;
1476 #endif
1477         /* Host controller watchdog timer structures */
1478         unsigned int            xhc_state;
1479
1480         u32                     command;
1481         struct s3_save          s3;
1482 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1483  *
1484  * xHC interrupts have been disabled and a watchdog timer will (or has already)
1485  * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1486  * that sees this status (other than the timer that set it) should stop touching
1487  * hardware immediately.  Interrupt handlers should return immediately when
1488  * they see this status (any time they drop and re-acquire xhci->lock).
1489  * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1490  * putting the TD on the canceled list, etc.
1491  *
1492  * There are no reports of xHCI host controllers that display this issue.
1493  */
1494 #define XHCI_STATE_DYING        (1 << 0)
1495 #define XHCI_STATE_HALTED       (1 << 1)
1496         /* Statistics */
1497         int                     error_bitmask;
1498         unsigned int            quirks;
1499 #define XHCI_LINK_TRB_QUIRK     (1 << 0)
1500 #define XHCI_RESET_EP_QUIRK     (1 << 1)
1501 #define XHCI_NEC_HOST           (1 << 2)
1502 #define XHCI_AMD_PLL_FIX        (1 << 3)
1503 #define XHCI_SPURIOUS_SUCCESS   (1 << 4)
1504 /*
1505  * Certain Intel host controllers have a limit to the number of endpoint
1506  * contexts they can handle.  Ideally, they would signal that they can't handle
1507  * anymore endpoint contexts by returning a Resource Error for the Configure
1508  * Endpoint command, but they don't.  Instead they expect software to keep track
1509  * of the number of active endpoints for them, across configure endpoint
1510  * commands, reset device commands, disable slot commands, and address device
1511  * commands.
1512  */
1513 #define XHCI_EP_LIMIT_QUIRK     (1 << 5)
1514 #define XHCI_BROKEN_MSI         (1 << 6)
1515 #define XHCI_RESET_ON_RESUME    (1 << 7)
1516 #define XHCI_SW_BW_CHECKING     (1 << 8)
1517 #define XHCI_AMD_0x96_HOST      (1 << 9)
1518 #define XHCI_TRUST_TX_LENGTH    (1 << 10)
1519 #define XHCI_LPM_SUPPORT        (1 << 11)
1520 #define XHCI_INTEL_HOST         (1 << 12)
1521 #define XHCI_SPURIOUS_REBOOT    (1 << 13)
1522 #define XHCI_COMP_MODE_QUIRK    (1 << 14)
1523 #define XHCI_AVOID_BEI          (1 << 15)
1524         unsigned int            num_active_eps;
1525         unsigned int            limit_active_eps;
1526         /* There are two roothubs to keep track of bus suspend info for */
1527         struct xhci_bus_state   bus_state[2];
1528         /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1529         u8                      *port_array;
1530         /* Array of pointers to USB 3.0 PORTSC registers */
1531         __le32 __iomem          **usb3_ports;
1532         unsigned int            num_usb3_ports;
1533         /* Array of pointers to USB 2.0 PORTSC registers */
1534         __le32 __iomem          **usb2_ports;
1535         unsigned int            num_usb2_ports;
1536         /* support xHCI 0.96 spec USB2 software LPM */
1537         unsigned                sw_lpm_support:1;
1538         /* support xHCI 1.0 spec USB2 hardware LPM */
1539         unsigned                hw_lpm_support:1;
1540         /* cached usb2 extened protocol capabilites */
1541         u32                     *ext_caps;
1542         unsigned int            num_ext_caps;
1543         /* Compliance Mode Recovery Data */
1544         struct timer_list       comp_mode_recovery_timer;
1545         u32                     port_status_u0;
1546 /* Compliance Mode Timer Triggered every 2 seconds */
1547 #define COMP_MODE_RCVRY_MSECS 2000
1548 };
1549
1550 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1551 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1552 {
1553         return *((struct xhci_hcd **) (hcd->hcd_priv));
1554 }
1555
1556 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1557 {
1558         return xhci->main_hcd;
1559 }
1560
1561 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1562 #define XHCI_DEBUG      1
1563 #else
1564 #define XHCI_DEBUG      0
1565 #endif
1566
1567 #define xhci_dbg(xhci, fmt, args...) \
1568         do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1569 #define xhci_info(xhci, fmt, args...) \
1570         do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1571 #define xhci_err(xhci, fmt, args...) \
1572         dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1573 #define xhci_warn(xhci, fmt, args...) \
1574         dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1575 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1576         dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1577
1578 /* TODO: copied from ehci.h - can be refactored? */
1579 /* xHCI spec says all registers are little endian */
1580 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1581                 __le32 __iomem *regs)
1582 {
1583         return readl(regs);
1584 }
1585 static inline void xhci_writel(struct xhci_hcd *xhci,
1586                 const unsigned int val, __le32 __iomem *regs)
1587 {
1588         writel(val, regs);
1589 }
1590
1591 /*
1592  * Registers should always be accessed with double word or quad word accesses.
1593  *
1594  * Some xHCI implementations may support 64-bit address pointers.  Registers
1595  * with 64-bit address pointers should be written to with dword accesses by
1596  * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1597  * xHCI implementations that do not support 64-bit address pointers will ignore
1598  * the high dword, and write order is irrelevant.
1599  */
1600 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1601                 __le64 __iomem *regs)
1602 {
1603         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1604         u64 val_lo = readl(ptr);
1605         u64 val_hi = readl(ptr + 1);
1606         return val_lo + (val_hi << 32);
1607 }
1608 static inline void xhci_write_64(struct xhci_hcd *xhci,
1609                                  const u64 val, __le64 __iomem *regs)
1610 {
1611         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1612         u32 val_lo = lower_32_bits(val);
1613         u32 val_hi = upper_32_bits(val);
1614
1615         writel(val_lo, ptr);
1616         writel(val_hi, ptr + 1);
1617 }
1618
1619 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1620 {
1621         return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1622 }
1623
1624 /* xHCI debugging */
1625 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1626 void xhci_print_registers(struct xhci_hcd *xhci);
1627 void xhci_dbg_regs(struct xhci_hcd *xhci);
1628 void xhci_print_run_regs(struct xhci_hcd *xhci);
1629 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1630 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1631 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1632 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1633 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1634 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1635 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1636 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1637 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1638                 struct xhci_container_ctx *ctx);
1639 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1640                 unsigned int slot_id, unsigned int ep_index,
1641                 struct xhci_virt_ep *ep);
1642
1643 /* xHCI memory management */
1644 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1645 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1646 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1647 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1648 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1649 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1650                 struct usb_device *udev);
1651 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1652 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1653 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1654 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1655 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1656 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1657 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1658                 struct xhci_bw_info *ep_bw,
1659                 struct xhci_interval_bw_table *bw_table,
1660                 struct usb_device *udev,
1661                 struct xhci_virt_ep *virt_ep,
1662                 struct xhci_tt_bw_info *tt_info);
1663 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1664                 struct xhci_virt_device *virt_dev,
1665                 int old_active_eps);
1666 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1667 void xhci_update_bw_info(struct xhci_hcd *xhci,
1668                 struct xhci_container_ctx *in_ctx,
1669                 struct xhci_input_control_ctx *ctrl_ctx,
1670                 struct xhci_virt_device *virt_dev);
1671 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1672                 struct xhci_container_ctx *in_ctx,
1673                 struct xhci_container_ctx *out_ctx,
1674                 unsigned int ep_index);
1675 void xhci_slot_copy(struct xhci_hcd *xhci,
1676                 struct xhci_container_ctx *in_ctx,
1677                 struct xhci_container_ctx *out_ctx);
1678 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1679                 struct usb_device *udev, struct usb_host_endpoint *ep,
1680                 gfp_t mem_flags);
1681 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1682 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1683                                 unsigned int num_trbs, gfp_t flags);
1684 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1685                 struct xhci_virt_device *virt_dev,
1686                 unsigned int ep_index);
1687 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1688                 unsigned int num_stream_ctxs,
1689                 unsigned int num_streams, gfp_t flags);
1690 void xhci_free_stream_info(struct xhci_hcd *xhci,
1691                 struct xhci_stream_info *stream_info);
1692 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1693                 struct xhci_ep_ctx *ep_ctx,
1694                 struct xhci_stream_info *stream_info);
1695 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1696                 struct xhci_ep_ctx *ep_ctx,
1697                 struct xhci_virt_ep *ep);
1698 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1699         struct xhci_virt_device *virt_dev, bool drop_control_ep);
1700 struct xhci_ring *xhci_dma_to_transfer_ring(
1701                 struct xhci_virt_ep *ep,
1702                 u64 address);
1703 struct xhci_ring *xhci_stream_id_to_ring(
1704                 struct xhci_virt_device *dev,
1705                 unsigned int ep_index,
1706                 unsigned int stream_id);
1707 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1708                 bool allocate_in_ctx, bool allocate_completion,
1709                 gfp_t mem_flags);
1710 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1711 void xhci_free_command(struct xhci_hcd *xhci,
1712                 struct xhci_command *command);
1713
1714 #ifdef CONFIG_PCI
1715 /* xHCI PCI glue */
1716 int xhci_register_pci(void);
1717 void xhci_unregister_pci(void);
1718 #else
1719 static inline int xhci_register_pci(void) { return 0; }
1720 static inline void xhci_unregister_pci(void) {}
1721 #endif
1722
1723 #if defined(CONFIG_USB_XHCI_PLATFORM) \
1724         || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1725 int xhci_register_plat(void);
1726 void xhci_unregister_plat(void);
1727 #else
1728 static inline int xhci_register_plat(void)
1729 { return 0; }
1730 static inline void xhci_unregister_plat(void)
1731 {  }
1732 #endif
1733
1734 /* xHCI host controller glue */
1735 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1736 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1737                 u32 mask, u32 done, int usec);
1738 void xhci_quiesce(struct xhci_hcd *xhci);
1739 int xhci_halt(struct xhci_hcd *xhci);
1740 int xhci_reset(struct xhci_hcd *xhci);
1741 int xhci_init(struct usb_hcd *hcd);
1742 int xhci_run(struct usb_hcd *hcd);
1743 void xhci_stop(struct usb_hcd *hcd);
1744 void xhci_shutdown(struct usb_hcd *hcd);
1745 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1746
1747 #ifdef  CONFIG_PM
1748 int xhci_suspend(struct xhci_hcd *xhci);
1749 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1750 #else
1751 #define xhci_suspend    NULL
1752 #define xhci_resume     NULL
1753 #endif
1754
1755 int xhci_get_frame(struct usb_hcd *hcd);
1756 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1757 irqreturn_t xhci_msi_irq(int irq, void *hcd);
1758 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1759 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1760 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1761                 struct xhci_virt_device *virt_dev,
1762                 struct usb_device *hdev,
1763                 struct usb_tt *tt, gfp_t mem_flags);
1764 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1765                 struct usb_host_endpoint **eps, unsigned int num_eps,
1766                 unsigned int num_streams, gfp_t mem_flags);
1767 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1768                 struct usb_host_endpoint **eps, unsigned int num_eps,
1769                 gfp_t mem_flags);
1770 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1771 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1772 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1773                                 struct usb_device *udev, int enable);
1774 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1775                         struct usb_tt *tt, gfp_t mem_flags);
1776 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1777 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1778 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1779 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1780 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1781 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1782 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1783 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1784
1785 /* xHCI ring, segment, TRB, and TD functions */
1786 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1787 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1788                 union xhci_trb *start_trb, union xhci_trb *end_trb,
1789                 dma_addr_t suspect_dma);
1790 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1791 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1792 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1793 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1794                 u32 slot_id);
1795 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1796                 u32 field1, u32 field2, u32 field3, u32 field4);
1797 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1798                 unsigned int ep_index, int suspend);
1799 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1800                 int slot_id, unsigned int ep_index);
1801 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1802                 int slot_id, unsigned int ep_index);
1803 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1804                 int slot_id, unsigned int ep_index);
1805 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1806                 struct urb *urb, int slot_id, unsigned int ep_index);
1807 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1808                 u32 slot_id, bool command_must_succeed);
1809 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1810                 u32 slot_id, bool command_must_succeed);
1811 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1812                 unsigned int ep_index);
1813 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1814 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1815                 unsigned int slot_id, unsigned int ep_index,
1816                 unsigned int stream_id, struct xhci_td *cur_td,
1817                 struct xhci_dequeue_state *state);
1818 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1819                 unsigned int slot_id, unsigned int ep_index,
1820                 unsigned int stream_id,
1821                 struct xhci_dequeue_state *deq_state);
1822 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1823                 struct usb_device *udev, unsigned int ep_index);
1824 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1825                 unsigned int slot_id, unsigned int ep_index,
1826                 struct xhci_dequeue_state *deq_state);
1827 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1828 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
1829                 union xhci_trb *cmd_trb);
1830 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1831                 unsigned int ep_index, unsigned int stream_id);
1832
1833 /* xHCI roothub code */
1834 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1835                                 int port_id, u32 link_state);
1836 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1837                         struct usb_device *udev, enum usb3_link_state state);
1838 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1839                         struct usb_device *udev, enum usb3_link_state state);
1840 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1841                                 int port_id, u32 port_bit);
1842 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1843                 char *buf, u16 wLength);
1844 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1845 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1846
1847 #ifdef CONFIG_PM
1848 int xhci_bus_suspend(struct usb_hcd *hcd);
1849 int xhci_bus_resume(struct usb_hcd *hcd);
1850 #else
1851 #define xhci_bus_suspend        NULL
1852 #define xhci_bus_resume         NULL
1853 #endif  /* CONFIG_PM */
1854
1855 u32 xhci_port_state_to_neutral(u32 state);
1856 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1857                 u16 port);
1858 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1859
1860 /* xHCI contexts */
1861 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1862 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1863 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1864
1865 #endif /* __LINUX_XHCI_HCD_H */