2 * MUSB OTG controller driver for Blackfin Processors
4 * Copyright 2006-2008 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/init.h>
15 #include <linux/list.h>
16 #include <linux/gpio.h>
19 #include <asm/cacheflush.h>
21 #include "musb_core.h"
25 * Load an endpoint's FIFO
27 void musb_write_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, const u8
*src
)
29 void __iomem
*fifo
= hw_ep
->fifo
;
30 void __iomem
*epio
= hw_ep
->regs
;
31 u8 epnum
= hw_ep
->epnum
;
35 musb_writew(epio
, MUSB_TXCOUNT
, len
);
37 DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
38 hw_ep
->epnum
, fifo
, len
, src
, epio
);
40 dump_fifo_data(src
, len
);
42 if (!ANOMALY_05000380
&& epnum
!= 0) {
45 flush_dcache_range((unsigned long)src
,
46 (unsigned long)(src
+ len
));
48 /* Setup DMA address register */
50 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_ADDR_LOW
), dma_reg
);
53 dma_reg
= (u32
)src
>> 16;
54 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_ADDR_HIGH
), dma_reg
);
57 /* Setup DMA count register */
58 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_COUNT_LOW
), len
);
59 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_COUNT_HIGH
), 0);
63 dma_reg
= (epnum
<< 4) | DMA_ENA
| INT_ENA
| DIRECTION
;
64 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_CTRL
), dma_reg
);
67 /* Wait for compelete */
68 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum
)))
71 /* acknowledge dma interrupt */
72 bfin_write_USB_DMA_INTERRUPT(1 << epnum
);
76 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_CTRL
), 0);
81 if (unlikely((unsigned long)src
& 0x01))
82 outsw_8((unsigned long)fifo
, src
, (len
+ 1) >> 1);
84 outsw((unsigned long)fifo
, src
, (len
+ 1) >> 1);
88 * Unload an endpoint's FIFO
90 void musb_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
92 void __iomem
*fifo
= hw_ep
->fifo
;
93 u8 epnum
= hw_ep
->epnum
;
95 if (ANOMALY_05000467
&& epnum
!= 0) {
98 invalidate_dcache_range((unsigned long)dst
,
99 (unsigned long)(dst
+ len
));
101 /* Setup DMA address register */
103 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_ADDR_LOW
), dma_reg
);
106 dma_reg
= (u32
)dst
>> 16;
107 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_ADDR_HIGH
), dma_reg
);
110 /* Setup DMA count register */
111 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_COUNT_LOW
), len
);
112 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_COUNT_HIGH
), 0);
116 dma_reg
= (epnum
<< 4) | DMA_ENA
| INT_ENA
;
117 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_CTRL
), dma_reg
);
120 /* Wait for compelete */
121 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum
)))
124 /* acknowledge dma interrupt */
125 bfin_write_USB_DMA_INTERRUPT(1 << epnum
);
129 bfin_write16(USB_DMA_REG(epnum
, USB_DMAx_CTRL
), 0);
133 /* Read the last byte of packet with odd size from address fifo + 4
134 * to trigger 1 byte access to EP0 FIFO.
137 *dst
= (u8
)inw((unsigned long)fifo
+ 4);
139 if (unlikely((unsigned long)dst
& 0x01))
140 insw_8((unsigned long)fifo
, dst
, len
>> 1);
142 insw((unsigned long)fifo
, dst
, len
>> 1);
145 *(dst
+ len
- 1) = (u8
)inw((unsigned long)fifo
+ 4);
148 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
149 'R', hw_ep
->epnum
, fifo
, len
, dst
);
151 dump_fifo_data(dst
, len
);
154 static irqreturn_t
blackfin_interrupt(int irq
, void *__hci
)
157 irqreturn_t retval
= IRQ_NONE
;
158 struct musb
*musb
= __hci
;
160 spin_lock_irqsave(&musb
->lock
, flags
);
162 musb
->int_usb
= musb_readb(musb
->mregs
, MUSB_INTRUSB
);
163 musb
->int_tx
= musb_readw(musb
->mregs
, MUSB_INTRTX
);
164 musb
->int_rx
= musb_readw(musb
->mregs
, MUSB_INTRRX
);
166 if (musb
->int_usb
|| musb
->int_tx
|| musb
->int_rx
) {
167 musb_writeb(musb
->mregs
, MUSB_INTRUSB
, musb
->int_usb
);
168 musb_writew(musb
->mregs
, MUSB_INTRTX
, musb
->int_tx
);
169 musb_writew(musb
->mregs
, MUSB_INTRRX
, musb
->int_rx
);
170 retval
= musb_interrupt(musb
);
173 /* Start sampling ID pin, when plug is removed from MUSB */
174 if ((is_otg_enabled(musb
) && (musb
->xceiv
->state
== OTG_STATE_B_IDLE
175 || musb
->xceiv
->state
== OTG_STATE_A_WAIT_BCON
)) ||
176 (musb
->int_usb
& MUSB_INTR_DISCONNECT
&& is_host_active(musb
))) {
177 mod_timer(&musb_conn_timer
, jiffies
+ TIMER_DELAY
);
178 musb
->a_wait_bcon
= TIMER_DELAY
;
181 spin_unlock_irqrestore(&musb
->lock
, flags
);
186 static void musb_conn_timer_handler(unsigned long _musb
)
188 struct musb
*musb
= (void *)_musb
;
193 spin_lock_irqsave(&musb
->lock
, flags
);
194 switch (musb
->xceiv
->state
) {
195 case OTG_STATE_A_IDLE
:
196 case OTG_STATE_A_WAIT_BCON
:
197 /* Start a new session */
198 val
= musb_readw(musb
->mregs
, MUSB_DEVCTL
);
199 val
&= ~MUSB_DEVCTL_SESSION
;
200 musb_writew(musb
->mregs
, MUSB_DEVCTL
, val
);
201 val
|= MUSB_DEVCTL_SESSION
;
202 musb_writew(musb
->mregs
, MUSB_DEVCTL
, val
);
203 /* Check if musb is host or peripheral. */
204 val
= musb_readw(musb
->mregs
, MUSB_DEVCTL
);
206 if (!(val
& MUSB_DEVCTL_BDEVICE
)) {
207 gpio_set_value(musb
->config
->gpio_vrsel
, 1);
208 musb
->xceiv
->state
= OTG_STATE_A_WAIT_BCON
;
210 gpio_set_value(musb
->config
->gpio_vrsel
, 0);
211 /* Ignore VBUSERROR and SUSPEND IRQ */
212 val
= musb_readb(musb
->mregs
, MUSB_INTRUSBE
);
213 val
&= ~MUSB_INTR_VBUSERROR
;
214 musb_writeb(musb
->mregs
, MUSB_INTRUSBE
, val
);
216 val
= MUSB_INTR_SUSPEND
| MUSB_INTR_VBUSERROR
;
217 musb_writeb(musb
->mregs
, MUSB_INTRUSB
, val
);
218 if (is_otg_enabled(musb
))
219 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
221 musb_writeb(musb
->mregs
, MUSB_POWER
, MUSB_POWER_HSENAB
);
223 mod_timer(&musb_conn_timer
, jiffies
+ TIMER_DELAY
);
225 case OTG_STATE_B_IDLE
:
227 if (!is_peripheral_enabled(musb
))
229 /* Start a new session. It seems that MUSB needs taking
230 * some time to recognize the type of the plug inserted?
232 val
= musb_readw(musb
->mregs
, MUSB_DEVCTL
);
233 val
|= MUSB_DEVCTL_SESSION
;
234 musb_writew(musb
->mregs
, MUSB_DEVCTL
, val
);
235 val
= musb_readw(musb
->mregs
, MUSB_DEVCTL
);
237 if (!(val
& MUSB_DEVCTL_BDEVICE
)) {
238 gpio_set_value(musb
->config
->gpio_vrsel
, 1);
239 musb
->xceiv
->state
= OTG_STATE_A_WAIT_BCON
;
241 gpio_set_value(musb
->config
->gpio_vrsel
, 0);
243 /* Ignore VBUSERROR and SUSPEND IRQ */
244 val
= musb_readb(musb
->mregs
, MUSB_INTRUSBE
);
245 val
&= ~MUSB_INTR_VBUSERROR
;
246 musb_writeb(musb
->mregs
, MUSB_INTRUSBE
, val
);
248 val
= MUSB_INTR_SUSPEND
| MUSB_INTR_VBUSERROR
;
249 musb_writeb(musb
->mregs
, MUSB_INTRUSB
, val
);
251 /* Toggle the Soft Conn bit, so that we can response to
252 * the inserting of either A-plug or B-plug.
255 val
= musb_readb(musb
->mregs
, MUSB_POWER
);
256 val
&= ~MUSB_POWER_SOFTCONN
;
257 musb_writeb(musb
->mregs
, MUSB_POWER
, val
);
260 val
= musb_readb(musb
->mregs
, MUSB_POWER
);
261 val
|= MUSB_POWER_SOFTCONN
;
262 musb_writeb(musb
->mregs
, MUSB_POWER
, val
);
265 /* The delay time is set to 1/4 second by default,
266 * shortening it, if accelerating A-plug detection
267 * is needed in OTG mode.
269 mod_timer(&musb_conn_timer
, jiffies
+ TIMER_DELAY
/ 4);
273 DBG(1, "%s state not handled\n", otg_state_string(musb
));
276 spin_unlock_irqrestore(&musb
->lock
, flags
);
278 DBG(4, "state is %s\n", otg_state_string(musb
));
281 void musb_platform_enable(struct musb
*musb
)
283 if (!is_otg_enabled(musb
) && is_host_enabled(musb
)) {
284 mod_timer(&musb_conn_timer
, jiffies
+ TIMER_DELAY
);
285 musb
->a_wait_bcon
= TIMER_DELAY
;
289 void musb_platform_disable(struct musb
*musb
)
293 static void bfin_set_vbus(struct musb
*musb
, int is_on
)
295 int value
= musb
->config
->gpio_vrsel_active
;
298 gpio_set_value(musb
->config
->gpio_vrsel
, value
);
300 DBG(1, "VBUS %s, devctl %02x "
301 /* otg %3x conf %08x prcm %08x */ "\n",
302 otg_state_string(musb
),
303 musb_readb(musb
->mregs
, MUSB_DEVCTL
));
306 static int bfin_set_power(struct otg_transceiver
*x
, unsigned mA
)
311 void musb_platform_try_idle(struct musb
*musb
, unsigned long timeout
)
313 if (!is_otg_enabled(musb
) && is_host_enabled(musb
))
314 mod_timer(&musb_conn_timer
, jiffies
+ TIMER_DELAY
);
317 int musb_platform_get_vbus_status(struct musb
*musb
)
322 int musb_platform_set_mode(struct musb
*musb
, u8 musb_mode
)
327 int __init
musb_platform_init(struct musb
*musb
, void *board_data
)
331 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
332 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
333 * be low for DEVICE mode and high for HOST mode. We set it high
334 * here because we are in host mode
337 if (gpio_request(musb
->config
->gpio_vrsel
, "USB_VRSEL")) {
338 printk(KERN_ERR
"Failed ro request USB_VRSEL GPIO_%d \n",
339 musb
->config
->gpio_vrsel
);
342 gpio_direction_output(musb
->config
->gpio_vrsel
, 0);
344 usb_nop_xceiv_register();
345 musb
->xceiv
= otg_get_transceiver();
347 gpio_free(musb
->config
->gpio_vrsel
);
351 if (ANOMALY_05000346
) {
352 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value
);
356 if (ANOMALY_05000347
) {
357 bfin_write_USB_APHY_CNTRL(0x0);
361 /* Configure PLL oscillator register */
362 bfin_write_USB_PLLOSC_CTRL(0x3080 |
363 ((480/musb
->config
->clkin
) << 1));
366 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
369 bfin_write_USB_EP_NI0_RXMAXP(64);
372 bfin_write_USB_EP_NI0_TXMAXP(64);
375 /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
376 bfin_write_USB_GLOBINTR(0x7);
379 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA
| EP1_TX_ENA
| EP2_TX_ENA
|
380 EP3_TX_ENA
| EP4_TX_ENA
| EP5_TX_ENA
|
381 EP6_TX_ENA
| EP7_TX_ENA
| EP1_RX_ENA
|
382 EP2_RX_ENA
| EP3_RX_ENA
| EP4_RX_ENA
|
383 EP5_RX_ENA
| EP6_RX_ENA
| EP7_RX_ENA
);
386 if (is_host_enabled(musb
)) {
387 musb
->board_set_vbus
= bfin_set_vbus
;
388 setup_timer(&musb_conn_timer
,
389 musb_conn_timer_handler
, (unsigned long) musb
);
391 if (is_peripheral_enabled(musb
))
392 musb
->xceiv
->set_power
= bfin_set_power
;
394 musb
->isr
= blackfin_interrupt
;
399 int musb_platform_exit(struct musb
*musb
)
401 gpio_free(musb
->config
->gpio_vrsel
);
403 otg_put_transceiver(musb
->xceiv
);
404 usb_nop_xceiv_unregister();
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