projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
usb: musb: drop a gigantic amount of ifdeferry
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
102
103 #include "musb_core.h"
104
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111 #define MUSB_VERSION "6.0"
112
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124 /*-------------------------------------------------------------------------*/
125
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128 return dev_get_drvdata(dev);
129 }
130
131 /*-------------------------------------------------------------------------*/
132
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
135 {
136 void __iomem *addr = otg->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140
141 /* Make sure the transceiver is not in low power mode */
142 power = musb_readb(addr, MUSB_POWER);
143 power &= ~MUSB_POWER_SUSPENDM;
144 musb_writeb(addr, MUSB_POWER, power);
145
146 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
147 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
148 */
149
150 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
151 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
152 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
153
154 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
155 & MUSB_ULPI_REG_CMPLT)) {
156 i++;
157 if (i == 10000)
158 return -ETIMEDOUT;
159
160 }
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
164
165 return musb_readb(addr, MUSB_ULPI_REG_DATA);
166 }
167
168 static int musb_ulpi_write(struct otg_transceiver *otg,
169 u32 offset, u32 data)
170 {
171 void __iomem *addr = otg->io_priv;
172 int i = 0;
173 u8 r = 0;
174 u8 power;
175
176 /* Make sure the transceiver is not in low power mode */
177 power = musb_readb(addr, MUSB_POWER);
178 power &= ~MUSB_POWER_SUSPENDM;
179 musb_writeb(addr, MUSB_POWER, power);
180
181 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
182 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
184
185 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
186 & MUSB_ULPI_REG_CMPLT)) {
187 i++;
188 if (i == 10000)
189 return -ETIMEDOUT;
190 }
191
192 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
193 r &= ~MUSB_ULPI_REG_CMPLT;
194 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
195
196 return 0;
197 }
198 #else
199 #define musb_ulpi_read NULL
200 #define musb_ulpi_write NULL
201 #endif
202
203 static struct otg_io_access_ops musb_ulpi_access = {
204 .read = musb_ulpi_read,
205 .write = musb_ulpi_write,
206 };
207
208 /*-------------------------------------------------------------------------*/
209
210 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
211
212 /*
213 * Load an endpoint's FIFO
214 */
215 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
216 {
217 struct musb *musb = hw_ep->musb;
218 void __iomem *fifo = hw_ep->fifo;
219
220 prefetch((u8 *)src);
221
222 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
223 'T', hw_ep->epnum, fifo, len, src);
224
225 /* we can't assume unaligned reads work */
226 if (likely((0x01 & (unsigned long) src) == 0)) {
227 u16 index = 0;
228
229 /* best case is 32bit-aligned source address */
230 if ((0x02 & (unsigned long) src) == 0) {
231 if (len >= 4) {
232 writesl(fifo, src + index, len >> 2);
233 index += len & ~0x03;
234 }
235 if (len & 0x02) {
236 musb_writew(fifo, 0, *(u16 *)&src[index]);
237 index += 2;
238 }
239 } else {
240 if (len >= 2) {
241 writesw(fifo, src + index, len >> 1);
242 index += len & ~0x01;
243 }
244 }
245 if (len & 0x01)
246 musb_writeb(fifo, 0, src[index]);
247 } else {
248 /* byte aligned */
249 writesb(fifo, src, len);
250 }
251 }
252
253 #if !defined(CONFIG_USB_MUSB_AM35X)
254 /*
255 * Unload an endpoint's FIFO
256 */
257 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
258 {
259 struct musb *musb = hw_ep->musb;
260 void __iomem *fifo = hw_ep->fifo;
261
262 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
263 'R', hw_ep->epnum, fifo, len, dst);
264
265 /* we can't assume unaligned writes work */
266 if (likely((0x01 & (unsigned long) dst) == 0)) {
267 u16 index = 0;
268
269 /* best case is 32bit-aligned destination address */
270 if ((0x02 & (unsigned long) dst) == 0) {
271 if (len >= 4) {
272 readsl(fifo, dst, len >> 2);
273 index = len & ~0x03;
274 }
275 if (len & 0x02) {
276 *(u16 *)&dst[index] = musb_readw(fifo, 0);
277 index += 2;
278 }
279 } else {
280 if (len >= 2) {
281 readsw(fifo, dst, len >> 1);
282 index = len & ~0x01;
283 }
284 }
285 if (len & 0x01)
286 dst[index] = musb_readb(fifo, 0);
287 } else {
288 /* byte aligned */
289 readsb(fifo, dst, len);
290 }
291 }
292 #endif
293
294 #endif /* normal PIO */
295
296
297 /*-------------------------------------------------------------------------*/
298
299 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
300 static const u8 musb_test_packet[53] = {
301 /* implicit SYNC then DATA0 to start */
302
303 /* JKJKJKJK x9 */
304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
305 /* JJKKJJKK x8 */
306 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
307 /* JJJJKKKK x8 */
308 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
309 /* JJJJJJJKKKKKKK x8 */
310 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
311 /* JJJJJJJK x8 */
312 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
313 /* JKKKKKKK x10, JK */
314 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
315
316 /* implicit CRC16 then EOP to end */
317 };
318
319 void musb_load_testpacket(struct musb *musb)
320 {
321 void __iomem *regs = musb->endpoints[0].regs;
322
323 musb_ep_select(musb->mregs, 0);
324 musb_write_fifo(musb->control_ep,
325 sizeof(musb_test_packet), musb_test_packet);
326 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
327 }
328
329 /*-------------------------------------------------------------------------*/
330
331 /*
332 * Handles OTG hnp timeouts, such as b_ase0_brst
333 */
334 void musb_otg_timer_func(unsigned long data)
335 {
336 struct musb *musb = (struct musb *)data;
337 unsigned long flags;
338
339 spin_lock_irqsave(&musb->lock, flags);
340 switch (musb->xceiv->state) {
341 case OTG_STATE_B_WAIT_ACON:
342 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
343 musb_g_disconnect(musb);
344 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
345 musb->is_active = 0;
346 break;
347 case OTG_STATE_A_SUSPEND:
348 case OTG_STATE_A_WAIT_BCON:
349 dev_dbg(musb->controller, "HNP: %s timeout\n",
350 otg_state_string(musb->xceiv->state));
351 musb_platform_set_vbus(musb, 0);
352 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
353 break;
354 default:
355 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
356 otg_state_string(musb->xceiv->state));
357 }
358 musb->ignore_disconnect = 0;
359 spin_unlock_irqrestore(&musb->lock, flags);
360 }
361
362 /*
363 * Stops the HNP transition. Caller must take care of locking.
364 */
365 void musb_hnp_stop(struct musb *musb)
366 {
367 struct usb_hcd *hcd = musb_to_hcd(musb);
368 void __iomem *mbase = musb->mregs;
369 u8 reg;
370
371 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
372
373 switch (musb->xceiv->state) {
374 case OTG_STATE_A_PERIPHERAL:
375 musb_g_disconnect(musb);
376 dev_dbg(musb->controller, "HNP: back to %s\n",
377 otg_state_string(musb->xceiv->state));
378 break;
379 case OTG_STATE_B_HOST:
380 dev_dbg(musb->controller, "HNP: Disabling HR\n");
381 hcd->self.is_b_host = 0;
382 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
383 MUSB_DEV_MODE(musb);
384 reg = musb_readb(mbase, MUSB_POWER);
385 reg |= MUSB_POWER_SUSPENDM;
386 musb_writeb(mbase, MUSB_POWER, reg);
387 /* REVISIT: Start SESSION_REQUEST here? */
388 break;
389 default:
390 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
391 otg_state_string(musb->xceiv->state));
392 }
393
394 /*
395 * When returning to A state after HNP, avoid hub_port_rebounce(),
396 * which cause occasional OPT A "Did not receive reset after connect"
397 * errors.
398 */
399 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
400 }
401
402 /*
403 * Interrupt Service Routine to record USB "global" interrupts.
404 * Since these do not happen often and signify things of
405 * paramount importance, it seems OK to check them individually;
406 * the order of the tests is specified in the manual
407 *
408 * @param musb instance pointer
409 * @param int_usb register contents
410 * @param devctl
411 * @param power
412 */
413
414 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
415 u8 devctl, u8 power)
416 {
417 irqreturn_t handled = IRQ_NONE;
418
419 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
420 int_usb);
421
422 /* in host mode, the peripheral may issue remote wakeup.
423 * in peripheral mode, the host may resume the link.
424 * spurious RESUME irqs happen too, paired with SUSPEND.
425 */
426 if (int_usb & MUSB_INTR_RESUME) {
427 handled = IRQ_HANDLED;
428 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
429
430 if (devctl & MUSB_DEVCTL_HM) {
431 void __iomem *mbase = musb->mregs;
432
433 switch (musb->xceiv->state) {
434 case OTG_STATE_A_SUSPEND:
435 /* remote wakeup? later, GetPortStatus
436 * will stop RESUME signaling
437 */
438
439 if (power & MUSB_POWER_SUSPENDM) {
440 /* spurious */
441 musb->int_usb &= ~MUSB_INTR_SUSPEND;
442 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
443 break;
444 }
445
446 power &= ~MUSB_POWER_SUSPENDM;
447 musb_writeb(mbase, MUSB_POWER,
448 power | MUSB_POWER_RESUME);
449
450 musb->port1_status |=
451 (USB_PORT_STAT_C_SUSPEND << 16)
452 | MUSB_PORT_STAT_RESUME;
453 musb->rh_timer = jiffies
454 + msecs_to_jiffies(20);
455
456 musb->xceiv->state = OTG_STATE_A_HOST;
457 musb->is_active = 1;
458 usb_hcd_resume_root_hub(musb_to_hcd(musb));
459 break;
460 case OTG_STATE_B_WAIT_ACON:
461 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
462 musb->is_active = 1;
463 MUSB_DEV_MODE(musb);
464 break;
465 default:
466 WARNING("bogus %s RESUME (%s)\n",
467 "host",
468 otg_state_string(musb->xceiv->state));
469 }
470 } else {
471 switch (musb->xceiv->state) {
472 case OTG_STATE_A_SUSPEND:
473 /* possibly DISCONNECT is upcoming */
474 musb->xceiv->state = OTG_STATE_A_HOST;
475 usb_hcd_resume_root_hub(musb_to_hcd(musb));
476 break;
477 case OTG_STATE_B_WAIT_ACON:
478 case OTG_STATE_B_PERIPHERAL:
479 /* disconnect while suspended? we may
480 * not get a disconnect irq...
481 */
482 if ((devctl & MUSB_DEVCTL_VBUS)
483 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
484 ) {
485 musb->int_usb |= MUSB_INTR_DISCONNECT;
486 musb->int_usb &= ~MUSB_INTR_SUSPEND;
487 break;
488 }
489 musb_g_resume(musb);
490 break;
491 case OTG_STATE_B_IDLE:
492 musb->int_usb &= ~MUSB_INTR_SUSPEND;
493 break;
494 default:
495 WARNING("bogus %s RESUME (%s)\n",
496 "peripheral",
497 otg_state_string(musb->xceiv->state));
498 }
499 }
500 }
501
502 /* see manual for the order of the tests */
503 if (int_usb & MUSB_INTR_SESSREQ) {
504 void __iomem *mbase = musb->mregs;
505
506 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
507 && (devctl & MUSB_DEVCTL_BDEVICE)) {
508 dev_dbg(musb->controller, "SessReq while on B state\n");
509 return IRQ_HANDLED;
510 }
511
512 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
513 otg_state_string(musb->xceiv->state));
514
515 /* IRQ arrives from ID pin sense or (later, if VBUS power
516 * is removed) SRP. responses are time critical:
517 * - turn on VBUS (with silicon-specific mechanism)
518 * - go through A_WAIT_VRISE
519 * - ... to A_WAIT_BCON.
520 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
521 */
522 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
523 musb->ep0_stage = MUSB_EP0_START;
524 musb->xceiv->state = OTG_STATE_A_IDLE;
525 MUSB_HST_MODE(musb);
526 musb_platform_set_vbus(musb, 1);
527
528 handled = IRQ_HANDLED;
529 }
530
531 if (int_usb & MUSB_INTR_VBUSERROR) {
532 int ignore = 0;
533
534 /* During connection as an A-Device, we may see a short
535 * current spikes causing voltage drop, because of cable
536 * and peripheral capacitance combined with vbus draw.
537 * (So: less common with truly self-powered devices, where
538 * vbus doesn't act like a power supply.)
539 *
540 * Such spikes are short; usually less than ~500 usec, max
541 * of ~2 msec. That is, they're not sustained overcurrent
542 * errors, though they're reported using VBUSERROR irqs.
543 *
544 * Workarounds: (a) hardware: use self powered devices.
545 * (b) software: ignore non-repeated VBUS errors.
546 *
547 * REVISIT: do delays from lots of DEBUG_KERNEL checks
548 * make trouble here, keeping VBUS < 4.4V ?
549 */
550 switch (musb->xceiv->state) {
551 case OTG_STATE_A_HOST:
552 /* recovery is dicey once we've gotten past the
553 * initial stages of enumeration, but if VBUS
554 * stayed ok at the other end of the link, and
555 * another reset is due (at least for high speed,
556 * to redo the chirp etc), it might work OK...
557 */
558 case OTG_STATE_A_WAIT_BCON:
559 case OTG_STATE_A_WAIT_VRISE:
560 if (musb->vbuserr_retry) {
561 void __iomem *mbase = musb->mregs;
562
563 musb->vbuserr_retry--;
564 ignore = 1;
565 devctl |= MUSB_DEVCTL_SESSION;
566 musb_writeb(mbase, MUSB_DEVCTL, devctl);
567 } else {
568 musb->port1_status |=
569 USB_PORT_STAT_OVERCURRENT
570 | (USB_PORT_STAT_C_OVERCURRENT << 16);
571 }
572 break;
573 default:
574 break;
575 }
576
577 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
578 otg_state_string(musb->xceiv->state),
579 devctl,
580 ({ char *s;
581 switch (devctl & MUSB_DEVCTL_VBUS) {
582 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
583 s = "<SessEnd"; break;
584 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
585 s = "<AValid"; break;
586 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
587 s = "<VBusValid"; break;
588 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
589 default:
590 s = "VALID"; break;
591 }; s; }),
592 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
593 musb->port1_status);
594
595 /* go through A_WAIT_VFALL then start a new session */
596 if (!ignore)
597 musb_platform_set_vbus(musb, 0);
598 handled = IRQ_HANDLED;
599 }
600
601 if (int_usb & MUSB_INTR_SUSPEND) {
602 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
603 otg_state_string(musb->xceiv->state), devctl, power);
604 handled = IRQ_HANDLED;
605
606 switch (musb->xceiv->state) {
607 case OTG_STATE_A_PERIPHERAL:
608 /* We also come here if the cable is removed, since
609 * this silicon doesn't report ID-no-longer-grounded.
610 *
611 * We depend on T(a_wait_bcon) to shut us down, and
612 * hope users don't do anything dicey during this
613 * undesired detour through A_WAIT_BCON.
614 */
615 musb_hnp_stop(musb);
616 usb_hcd_resume_root_hub(musb_to_hcd(musb));
617 musb_root_disconnect(musb);
618 musb_platform_try_idle(musb, jiffies
619 + msecs_to_jiffies(musb->a_wait_bcon
620 ? : OTG_TIME_A_WAIT_BCON));
621
622 break;
623 case OTG_STATE_B_IDLE:
624 if (!musb->is_active)
625 break;
626 case OTG_STATE_B_PERIPHERAL:
627 musb_g_suspend(musb);
628 musb->is_active = is_otg_enabled(musb)
629 && musb->xceiv->gadget->b_hnp_enable;
630 if (musb->is_active) {
631 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
632 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
633 mod_timer(&musb->otg_timer, jiffies
634 + msecs_to_jiffies(
635 OTG_TIME_B_ASE0_BRST));
636 }
637 break;
638 case OTG_STATE_A_WAIT_BCON:
639 if (musb->a_wait_bcon != 0)
640 musb_platform_try_idle(musb, jiffies
641 + msecs_to_jiffies(musb->a_wait_bcon));
642 break;
643 case OTG_STATE_A_HOST:
644 musb->xceiv->state = OTG_STATE_A_SUSPEND;
645 musb->is_active = is_otg_enabled(musb)
646 && musb->xceiv->host->b_hnp_enable;
647 break;
648 case OTG_STATE_B_HOST:
649 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
650 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
651 break;
652 default:
653 /* "should not happen" */
654 musb->is_active = 0;
655 break;
656 }
657 }
658
659 if (int_usb & MUSB_INTR_CONNECT) {
660 struct usb_hcd *hcd = musb_to_hcd(musb);
661
662 handled = IRQ_HANDLED;
663 musb->is_active = 1;
664 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
665
666 musb->ep0_stage = MUSB_EP0_START;
667
668 /* flush endpoints when transitioning from Device Mode */
669 if (is_peripheral_active(musb)) {
670 /* REVISIT HNP; just force disconnect */
671 }
672 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
673 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
674 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
675 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
676 |USB_PORT_STAT_HIGH_SPEED
677 |USB_PORT_STAT_ENABLE
678 );
679 musb->port1_status |= USB_PORT_STAT_CONNECTION
680 |(USB_PORT_STAT_C_CONNECTION << 16);
681
682 /* high vs full speed is just a guess until after reset */
683 if (devctl & MUSB_DEVCTL_LSDEV)
684 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
685
686 /* indicate new connection to OTG machine */
687 switch (musb->xceiv->state) {
688 case OTG_STATE_B_PERIPHERAL:
689 if (int_usb & MUSB_INTR_SUSPEND) {
690 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
691 int_usb &= ~MUSB_INTR_SUSPEND;
692 goto b_host;
693 } else
694 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
695 break;
696 case OTG_STATE_B_WAIT_ACON:
697 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
698 b_host:
699 musb->xceiv->state = OTG_STATE_B_HOST;
700 hcd->self.is_b_host = 1;
701 musb->ignore_disconnect = 0;
702 del_timer(&musb->otg_timer);
703 break;
704 default:
705 if ((devctl & MUSB_DEVCTL_VBUS)
706 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
707 musb->xceiv->state = OTG_STATE_A_HOST;
708 hcd->self.is_b_host = 0;
709 }
710 break;
711 }
712
713 /* poke the root hub */
714 MUSB_HST_MODE(musb);
715 if (hcd->status_urb)
716 usb_hcd_poll_rh_status(hcd);
717 else
718 usb_hcd_resume_root_hub(hcd);
719
720 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
721 otg_state_string(musb->xceiv->state), devctl);
722 }
723
724 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
725 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
726 otg_state_string(musb->xceiv->state),
727 MUSB_MODE(musb), devctl);
728 handled = IRQ_HANDLED;
729
730 switch (musb->xceiv->state) {
731 case OTG_STATE_A_HOST:
732 case OTG_STATE_A_SUSPEND:
733 usb_hcd_resume_root_hub(musb_to_hcd(musb));
734 musb_root_disconnect(musb);
735 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
736 musb_platform_try_idle(musb, jiffies
737 + msecs_to_jiffies(musb->a_wait_bcon));
738 break;
739 case OTG_STATE_B_HOST:
740 /* REVISIT this behaves for "real disconnect"
741 * cases; make sure the other transitions from
742 * from B_HOST act right too. The B_HOST code
743 * in hnp_stop() is currently not used...
744 */
745 musb_root_disconnect(musb);
746 musb_to_hcd(musb)->self.is_b_host = 0;
747 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
748 MUSB_DEV_MODE(musb);
749 musb_g_disconnect(musb);
750 break;
751 case OTG_STATE_A_PERIPHERAL:
752 musb_hnp_stop(musb);
753 musb_root_disconnect(musb);
754 /* FALLTHROUGH */
755 case OTG_STATE_B_WAIT_ACON:
756 /* FALLTHROUGH */
757 case OTG_STATE_B_PERIPHERAL:
758 case OTG_STATE_B_IDLE:
759 musb_g_disconnect(musb);
760 break;
761 default:
762 WARNING("unhandled DISCONNECT transition (%s)\n",
763 otg_state_string(musb->xceiv->state));
764 break;
765 }
766 }
767
768 /* mentor saves a bit: bus reset and babble share the same irq.
769 * only host sees babble; only peripheral sees bus reset.
770 */
771 if (int_usb & MUSB_INTR_RESET) {
772 handled = IRQ_HANDLED;
773 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
774 /*
775 * Looks like non-HS BABBLE can be ignored, but
776 * HS BABBLE is an error condition. For HS the solution
777 * is to avoid babble in the first place and fix what
778 * caused BABBLE. When HS BABBLE happens we can only
779 * stop the session.
780 */
781 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
782 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
783 else {
784 ERR("Stopping host session -- babble\n");
785 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
786 }
787 } else if (is_peripheral_capable()) {
788 dev_dbg(musb->controller, "BUS RESET as %s\n",
789 otg_state_string(musb->xceiv->state));
790 switch (musb->xceiv->state) {
791 case OTG_STATE_A_SUSPEND:
792 /* We need to ignore disconnect on suspend
793 * otherwise tusb 2.0 won't reconnect after a
794 * power cycle, which breaks otg compliance.
795 */
796 musb->ignore_disconnect = 1;
797 musb_g_reset(musb);
798 /* FALLTHROUGH */
799 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
800 /* never use invalid T(a_wait_bcon) */
801 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
802 otg_state_string(musb->xceiv->state),
803 TA_WAIT_BCON(musb));
804 mod_timer(&musb->otg_timer, jiffies
805 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
806 break;
807 case OTG_STATE_A_PERIPHERAL:
808 musb->ignore_disconnect = 0;
809 del_timer(&musb->otg_timer);
810 musb_g_reset(musb);
811 break;
812 case OTG_STATE_B_WAIT_ACON:
813 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
814 otg_state_string(musb->xceiv->state));
815 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
816 musb_g_reset(musb);
817 break;
818 case OTG_STATE_B_IDLE:
819 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
820 /* FALLTHROUGH */
821 case OTG_STATE_B_PERIPHERAL:
822 musb_g_reset(musb);
823 break;
824 default:
825 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
826 otg_state_string(musb->xceiv->state));
827 }
828 }
829 }
830
831 #if 0
832 /* REVISIT ... this would be for multiplexing periodic endpoints, or
833 * supporting transfer phasing to prevent exceeding ISO bandwidth
834 * limits of a given frame or microframe.
835 *
836 * It's not needed for peripheral side, which dedicates endpoints;
837 * though it _might_ use SOF irqs for other purposes.
838 *
839 * And it's not currently needed for host side, which also dedicates
840 * endpoints, relies on TX/RX interval registers, and isn't claimed
841 * to support ISO transfers yet.
842 */
843 if (int_usb & MUSB_INTR_SOF) {
844 void __iomem *mbase = musb->mregs;
845 struct musb_hw_ep *ep;
846 u8 epnum;
847 u16 frame;
848
849 dev_dbg(musb->controller, "START_OF_FRAME\n");
850 handled = IRQ_HANDLED;
851
852 /* start any periodic Tx transfers waiting for current frame */
853 frame = musb_readw(mbase, MUSB_FRAME);
854 ep = musb->endpoints;
855 for (epnum = 1; (epnum < musb->nr_endpoints)
856 && (musb->epmask >= (1 << epnum));
857 epnum++, ep++) {
858 /*
859 * FIXME handle framecounter wraps (12 bits)
860 * eliminate duplicated StartUrb logic
861 */
862 if (ep->dwWaitFrame >= frame) {
863 ep->dwWaitFrame = 0;
864 pr_debug("SOF --> periodic TX%s on %d\n",
865 ep->tx_channel ? " DMA" : "",
866 epnum);
867 if (!ep->tx_channel)
868 musb_h_tx_start(musb, epnum);
869 else
870 cppi_hostdma_start(musb, epnum);
871 }
872 } /* end of for loop */
873 }
874 #endif
875
876 schedule_work(&musb->irq_work);
877
878 return handled;
879 }
880
881 /*-------------------------------------------------------------------------*/
882
883 /*
884 * Program the HDRC to start (enable interrupts, dma, etc.).
885 */
886 void musb_start(struct musb *musb)
887 {
888 void __iomem *regs = musb->mregs;
889 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
890
891 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
892
893 /* Set INT enable registers, enable interrupts */
894 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
895 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
896 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
897
898 musb_writeb(regs, MUSB_TESTMODE, 0);
899
900 /* put into basic highspeed mode and start session */
901 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
902 | MUSB_POWER_SOFTCONN
903 | MUSB_POWER_HSENAB
904 /* ENSUSPEND wedges tusb */
905 /* | MUSB_POWER_ENSUSPEND */
906 );
907
908 musb->is_active = 0;
909 devctl = musb_readb(regs, MUSB_DEVCTL);
910 devctl &= ~MUSB_DEVCTL_SESSION;
911
912 if (is_otg_enabled(musb)) {
913 /* session started after:
914 * (a) ID-grounded irq, host mode;
915 * (b) vbus present/connect IRQ, peripheral mode;
916 * (c) peripheral initiates, using SRP
917 */
918 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
919 musb->is_active = 1;
920 else
921 devctl |= MUSB_DEVCTL_SESSION;
922
923 } else if (is_host_enabled(musb)) {
924 /* assume ID pin is hard-wired to ground */
925 devctl |= MUSB_DEVCTL_SESSION;
926
927 } else /* peripheral is enabled */ {
928 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
929 musb->is_active = 1;
930 }
931 musb_platform_enable(musb);
932 musb_writeb(regs, MUSB_DEVCTL, devctl);
933 }
934
935
936 static void musb_generic_disable(struct musb *musb)
937 {
938 void __iomem *mbase = musb->mregs;
939 u16 temp;
940
941 /* disable interrupts */
942 musb_writeb(mbase, MUSB_INTRUSBE, 0);
943 musb_writew(mbase, MUSB_INTRTXE, 0);
944 musb_writew(mbase, MUSB_INTRRXE, 0);
945
946 /* off */
947 musb_writeb(mbase, MUSB_DEVCTL, 0);
948
949 /* flush pending interrupts */
950 temp = musb_readb(mbase, MUSB_INTRUSB);
951 temp = musb_readw(mbase, MUSB_INTRTX);
952 temp = musb_readw(mbase, MUSB_INTRRX);
953
954 }
955
956 /*
957 * Make the HDRC stop (disable interrupts, etc.);
958 * reversible by musb_start
959 * called on gadget driver unregister
960 * with controller locked, irqs blocked
961 * acts as a NOP unless some role activated the hardware
962 */
963 void musb_stop(struct musb *musb)
964 {
965 /* stop IRQs, timers, ... */
966 musb_platform_disable(musb);
967 musb_generic_disable(musb);
968 dev_dbg(musb->controller, "HDRC disabled\n");
969
970 /* FIXME
971 * - mark host and/or peripheral drivers unusable/inactive
972 * - disable DMA (and enable it in HdrcStart)
973 * - make sure we can musb_start() after musb_stop(); with
974 * OTG mode, gadget driver module rmmod/modprobe cycles that
975 * - ...
976 */
977 musb_platform_try_idle(musb, 0);
978 }
979
980 static void musb_shutdown(struct platform_device *pdev)
981 {
982 struct musb *musb = dev_to_musb(&pdev->dev);
983 unsigned long flags;
984
985 pm_runtime_get_sync(musb->controller);
986 spin_lock_irqsave(&musb->lock, flags);
987 musb_platform_disable(musb);
988 musb_generic_disable(musb);
989 spin_unlock_irqrestore(&musb->lock, flags);
990
991 if (!is_otg_enabled(musb) && is_host_enabled(musb))
992 usb_remove_hcd(musb_to_hcd(musb));
993 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
994 musb_platform_exit(musb);
995
996 pm_runtime_put(musb->controller);
997 /* FIXME power down */
998 }
999
1000
1001 /*-------------------------------------------------------------------------*/
1002
1003 /*
1004 * The silicon either has hard-wired endpoint configurations, or else
1005 * "dynamic fifo" sizing. The driver has support for both, though at this
1006 * writing only the dynamic sizing is very well tested. Since we switched
1007 * away from compile-time hardware parameters, we can no longer rely on
1008 * dead code elimination to leave only the relevant one in the object file.
1009 *
1010 * We don't currently use dynamic fifo setup capability to do anything
1011 * more than selecting one of a bunch of predefined configurations.
1012 */
1013 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1014 || defined(CONFIG_USB_MUSB_AM35X)
1015 static ushort __initdata fifo_mode = 4;
1016 #elif defined(CONFIG_USB_MUSB_UX500)
1017 static ushort __initdata fifo_mode = 5;
1018 #else
1019 static ushort __initdata fifo_mode = 2;
1020 #endif
1021
1022 /* "modprobe ... fifo_mode=1" etc */
1023 module_param(fifo_mode, ushort, 0);
1024 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1025
1026 /*
1027 * tables defining fifo_mode values. define more if you like.
1028 * for host side, make sure both halves of ep1 are set up.
1029 */
1030
1031 /* mode 0 - fits in 2KB */
1032 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1033 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1034 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1035 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1036 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1037 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1038 };
1039
1040 /* mode 1 - fits in 4KB */
1041 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1042 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1043 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1044 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1045 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1046 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1047 };
1048
1049 /* mode 2 - fits in 4KB */
1050 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1051 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1052 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1053 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1054 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1055 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1056 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1057 };
1058
1059 /* mode 3 - fits in 4KB */
1060 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1061 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1062 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1063 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1064 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1065 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1066 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1067 };
1068
1069 /* mode 4 - fits in 16KB */
1070 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1071 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1072 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1073 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1074 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1075 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1076 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1077 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1078 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1079 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1080 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1081 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1082 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1083 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1084 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1085 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1086 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1087 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1088 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1089 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1090 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1091 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1092 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1093 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1094 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1095 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1096 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1097 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1098 };
1099
1100 /* mode 5 - fits in 8KB */
1101 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1102 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1107 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1108 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1109 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1110 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1111 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1112 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1113 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1114 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1115 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1116 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1117 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1118 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1119 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1120 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1121 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1122 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1123 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1124 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1125 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1126 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1127 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1128 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1129 };
1130
1131 /*
1132 * configure a fifo; for non-shared endpoints, this may be called
1133 * once for a tx fifo and once for an rx fifo.
1134 *
1135 * returns negative errno or offset for next fifo.
1136 */
1137 static int __init
1138 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1139 const struct musb_fifo_cfg *cfg, u16 offset)
1140 {
1141 void __iomem *mbase = musb->mregs;
1142 int size = 0;
1143 u16 maxpacket = cfg->maxpacket;
1144 u16 c_off = offset >> 3;
1145 u8 c_size;
1146
1147 /* expect hw_ep has already been zero-initialized */
1148
1149 size = ffs(max(maxpacket, (u16) 8)) - 1;
1150 maxpacket = 1 << size;
1151
1152 c_size = size - 3;
1153 if (cfg->mode == BUF_DOUBLE) {
1154 if ((offset + (maxpacket << 1)) >
1155 (1 << (musb->config->ram_bits + 2)))
1156 return -EMSGSIZE;
1157 c_size |= MUSB_FIFOSZ_DPB;
1158 } else {
1159 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1160 return -EMSGSIZE;
1161 }
1162
1163 /* configure the FIFO */
1164 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1165
1166 /* EP0 reserved endpoint for control, bidirectional;
1167 * EP1 reserved for bulk, two unidirection halves.
1168 */
1169 if (hw_ep->epnum == 1)
1170 musb->bulk_ep = hw_ep;
1171 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1172 switch (cfg->style) {
1173 case FIFO_TX:
1174 musb_write_txfifosz(mbase, c_size);
1175 musb_write_txfifoadd(mbase, c_off);
1176 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1177 hw_ep->max_packet_sz_tx = maxpacket;
1178 break;
1179 case FIFO_RX:
1180 musb_write_rxfifosz(mbase, c_size);
1181 musb_write_rxfifoadd(mbase, c_off);
1182 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1183 hw_ep->max_packet_sz_rx = maxpacket;
1184 break;
1185 case FIFO_RXTX:
1186 musb_write_txfifosz(mbase, c_size);
1187 musb_write_txfifoadd(mbase, c_off);
1188 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1189 hw_ep->max_packet_sz_rx = maxpacket;
1190
1191 musb_write_rxfifosz(mbase, c_size);
1192 musb_write_rxfifoadd(mbase, c_off);
1193 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1194 hw_ep->max_packet_sz_tx = maxpacket;
1195
1196 hw_ep->is_shared_fifo = true;
1197 break;
1198 }
1199
1200 /* NOTE rx and tx endpoint irqs aren't managed separately,
1201 * which happens to be ok
1202 */
1203 musb->epmask |= (1 << hw_ep->epnum);
1204
1205 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1206 }
1207
1208 static struct musb_fifo_cfg __initdata ep0_cfg = {
1209 .style = FIFO_RXTX, .maxpacket = 64,
1210 };
1211
1212 static int __init ep_config_from_table(struct musb *musb)
1213 {
1214 const struct musb_fifo_cfg *cfg;
1215 unsigned i, n;
1216 int offset;
1217 struct musb_hw_ep *hw_ep = musb->endpoints;
1218
1219 if (musb->config->fifo_cfg) {
1220 cfg = musb->config->fifo_cfg;
1221 n = musb->config->fifo_cfg_size;
1222 goto done;
1223 }
1224
1225 switch (fifo_mode) {
1226 default:
1227 fifo_mode = 0;
1228 /* FALLTHROUGH */
1229 case 0:
1230 cfg = mode_0_cfg;
1231 n = ARRAY_SIZE(mode_0_cfg);
1232 break;
1233 case 1:
1234 cfg = mode_1_cfg;
1235 n = ARRAY_SIZE(mode_1_cfg);
1236 break;
1237 case 2:
1238 cfg = mode_2_cfg;
1239 n = ARRAY_SIZE(mode_2_cfg);
1240 break;
1241 case 3:
1242 cfg = mode_3_cfg;
1243 n = ARRAY_SIZE(mode_3_cfg);
1244 break;
1245 case 4:
1246 cfg = mode_4_cfg;
1247 n = ARRAY_SIZE(mode_4_cfg);
1248 break;
1249 case 5:
1250 cfg = mode_5_cfg;
1251 n = ARRAY_SIZE(mode_5_cfg);
1252 break;
1253 }
1254
1255 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1256 musb_driver_name, fifo_mode);
1257
1258
1259 done:
1260 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1261 /* assert(offset > 0) */
1262
1263 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1264 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1265 */
1266
1267 for (i = 0; i < n; i++) {
1268 u8 epn = cfg->hw_ep_num;
1269
1270 if (epn >= musb->config->num_eps) {
1271 pr_debug("%s: invalid ep %d\n",
1272 musb_driver_name, epn);
1273 return -EINVAL;
1274 }
1275 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1276 if (offset < 0) {
1277 pr_debug("%s: mem overrun, ep %d\n",
1278 musb_driver_name, epn);
1279 return -EINVAL;
1280 }
1281 epn++;
1282 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1283 }
1284
1285 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1286 musb_driver_name,
1287 n + 1, musb->config->num_eps * 2 - 1,
1288 offset, (1 << (musb->config->ram_bits + 2)));
1289
1290 if (!musb->bulk_ep) {
1291 pr_debug("%s: missing bulk\n", musb_driver_name);
1292 return -EINVAL;
1293 }
1294
1295 return 0;
1296 }
1297
1298
1299 /*
1300 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1301 * @param musb the controller
1302 */
1303 static int __init ep_config_from_hw(struct musb *musb)
1304 {
1305 u8 epnum = 0;
1306 struct musb_hw_ep *hw_ep;
1307 void *mbase = musb->mregs;
1308 int ret = 0;
1309
1310 dev_dbg(musb->controller, "<== static silicon ep config\n");
1311
1312 /* FIXME pick up ep0 maxpacket size */
1313
1314 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1315 musb_ep_select(mbase, epnum);
1316 hw_ep = musb->endpoints + epnum;
1317
1318 ret = musb_read_fifosize(musb, hw_ep, epnum);
1319 if (ret < 0)
1320 break;
1321
1322 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1323
1324 /* pick an RX/TX endpoint for bulk */
1325 if (hw_ep->max_packet_sz_tx < 512
1326 || hw_ep->max_packet_sz_rx < 512)
1327 continue;
1328
1329 /* REVISIT: this algorithm is lazy, we should at least
1330 * try to pick a double buffered endpoint.
1331 */
1332 if (musb->bulk_ep)
1333 continue;
1334 musb->bulk_ep = hw_ep;
1335 }
1336
1337 if (!musb->bulk_ep) {
1338 pr_debug("%s: missing bulk\n", musb_driver_name);
1339 return -EINVAL;
1340 }
1341
1342 return 0;
1343 }
1344
1345 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1346
1347 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1348 * configure endpoints, or take their config from silicon
1349 */
1350 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1351 {
1352 u8 reg;
1353 char *type;
1354 char aInfo[90], aRevision[32], aDate[12];
1355 void __iomem *mbase = musb->mregs;
1356 int status = 0;
1357 int i;
1358
1359 /* log core options (read using indexed model) */
1360 reg = musb_read_configdata(mbase);
1361
1362 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1363 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1364 strcat(aInfo, ", dyn FIFOs");
1365 musb->dyn_fifo = true;
1366 }
1367 if (reg & MUSB_CONFIGDATA_MPRXE) {
1368 strcat(aInfo, ", bulk combine");
1369 musb->bulk_combine = true;
1370 }
1371 if (reg & MUSB_CONFIGDATA_MPTXE) {
1372 strcat(aInfo, ", bulk split");
1373 musb->bulk_split = true;
1374 }
1375 if (reg & MUSB_CONFIGDATA_HBRXE) {
1376 strcat(aInfo, ", HB-ISO Rx");
1377 musb->hb_iso_rx = true;
1378 }
1379 if (reg & MUSB_CONFIGDATA_HBTXE) {
1380 strcat(aInfo, ", HB-ISO Tx");
1381 musb->hb_iso_tx = true;
1382 }
1383 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1384 strcat(aInfo, ", SoftConn");
1385
1386 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1387 musb_driver_name, reg, aInfo);
1388
1389 aDate[0] = 0;
1390 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1391 musb->is_multipoint = 1;
1392 type = "M";
1393 } else {
1394 musb->is_multipoint = 0;
1395 type = "";
1396 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1397 printk(KERN_ERR
1398 "%s: kernel must blacklist external hubs\n",
1399 musb_driver_name);
1400 #endif
1401 }
1402
1403 /* log release info */
1404 musb->hwvers = musb_read_hwvers(mbase);
1405 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1406 MUSB_HWVERS_MINOR(musb->hwvers),
1407 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1408 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1409 musb_driver_name, type, aRevision, aDate);
1410
1411 /* configure ep0 */
1412 musb_configure_ep0(musb);
1413
1414 /* discover endpoint configuration */
1415 musb->nr_endpoints = 1;
1416 musb->epmask = 1;
1417
1418 if (musb->dyn_fifo)
1419 status = ep_config_from_table(musb);
1420 else
1421 status = ep_config_from_hw(musb);
1422
1423 if (status < 0)
1424 return status;
1425
1426 /* finish init, and print endpoint config */
1427 for (i = 0; i < musb->nr_endpoints; i++) {
1428 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1429
1430 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1431 #ifdef CONFIG_USB_MUSB_TUSB6010
1432 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1433 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1434 hw_ep->fifo_sync_va =
1435 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1436
1437 if (i == 0)
1438 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1439 else
1440 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1441 #endif
1442
1443 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1444 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1445 hw_ep->rx_reinit = 1;
1446 hw_ep->tx_reinit = 1;
1447
1448 if (hw_ep->max_packet_sz_tx) {
1449 dev_dbg(musb->controller,
1450 "%s: hw_ep %d%s, %smax %d\n",
1451 musb_driver_name, i,
1452 hw_ep->is_shared_fifo ? "shared" : "tx",
1453 hw_ep->tx_double_buffered
1454 ? "doublebuffer, " : "",
1455 hw_ep->max_packet_sz_tx);
1456 }
1457 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1458 dev_dbg(musb->controller,
1459 "%s: hw_ep %d%s, %smax %d\n",
1460 musb_driver_name, i,
1461 "rx",
1462 hw_ep->rx_double_buffered
1463 ? "doublebuffer, " : "",
1464 hw_ep->max_packet_sz_rx);
1465 }
1466 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1467 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1468 }
1469
1470 return 0;
1471 }
1472
1473 /*-------------------------------------------------------------------------*/
1474
1475 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1476 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \
1477 defined(CONFIG_ARCH_U5500)
1478
1479 static irqreturn_t generic_interrupt(int irq, void *__hci)
1480 {
1481 unsigned long flags;
1482 irqreturn_t retval = IRQ_NONE;
1483 struct musb *musb = __hci;
1484
1485 spin_lock_irqsave(&musb->lock, flags);
1486
1487 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1488 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1489 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1490
1491 if (musb->int_usb || musb->int_tx || musb->int_rx)
1492 retval = musb_interrupt(musb);
1493
1494 spin_unlock_irqrestore(&musb->lock, flags);
1495
1496 return retval;
1497 }
1498
1499 #else
1500 #define generic_interrupt NULL
1501 #endif
1502
1503 /*
1504 * handle all the irqs defined by the HDRC core. for now we expect: other
1505 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1506 * will be assigned, and the irq will already have been acked.
1507 *
1508 * called in irq context with spinlock held, irqs blocked
1509 */
1510 irqreturn_t musb_interrupt(struct musb *musb)
1511 {
1512 irqreturn_t retval = IRQ_NONE;
1513 u8 devctl, power;
1514 int ep_num;
1515 u32 reg;
1516
1517 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1518 power = musb_readb(musb->mregs, MUSB_POWER);
1519
1520 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1521 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1522 musb->int_usb, musb->int_tx, musb->int_rx);
1523
1524 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1525 if (!musb->gadget_driver) {
1526 dev_dbg(musb->controller, "No gadget driver loaded\n");
1527 return IRQ_HANDLED;
1528 }
1529
1530 /* the core can interrupt us for multiple reasons; docs have
1531 * a generic interrupt flowchart to follow
1532 */
1533 if (musb->int_usb)
1534 retval |= musb_stage0_irq(musb, musb->int_usb,
1535 devctl, power);
1536
1537 /* "stage 1" is handling endpoint irqs */
1538
1539 /* handle endpoint 0 first */
1540 if (musb->int_tx & 1) {
1541 if (devctl & MUSB_DEVCTL_HM)
1542 retval |= musb_h_ep0_irq(musb);
1543 else
1544 retval |= musb_g_ep0_irq(musb);
1545 }
1546
1547 /* RX on endpoints 1-15 */
1548 reg = musb->int_rx >> 1;
1549 ep_num = 1;
1550 while (reg) {
1551 if (reg & 1) {
1552 /* musb_ep_select(musb->mregs, ep_num); */
1553 /* REVISIT just retval = ep->rx_irq(...) */
1554 retval = IRQ_HANDLED;
1555 if (devctl & MUSB_DEVCTL_HM) {
1556 if (is_host_capable())
1557 musb_host_rx(musb, ep_num);
1558 } else {
1559 if (is_peripheral_capable())
1560 musb_g_rx(musb, ep_num);
1561 }
1562 }
1563
1564 reg >>= 1;
1565 ep_num++;
1566 }
1567
1568 /* TX on endpoints 1-15 */
1569 reg = musb->int_tx >> 1;
1570 ep_num = 1;
1571 while (reg) {
1572 if (reg & 1) {
1573 /* musb_ep_select(musb->mregs, ep_num); */
1574 /* REVISIT just retval |= ep->tx_irq(...) */
1575 retval = IRQ_HANDLED;
1576 if (devctl & MUSB_DEVCTL_HM) {
1577 if (is_host_capable())
1578 musb_host_tx(musb, ep_num);
1579 } else {
1580 if (is_peripheral_capable())
1581 musb_g_tx(musb, ep_num);
1582 }
1583 }
1584 reg >>= 1;
1585 ep_num++;
1586 }
1587
1588 return retval;
1589 }
1590 EXPORT_SYMBOL_GPL(musb_interrupt);
1591
1592 #ifndef CONFIG_MUSB_PIO_ONLY
1593 static int __initdata use_dma = 1;
1594
1595 /* "modprobe ... use_dma=0" etc */
1596 module_param(use_dma, bool, 0);
1597 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1598
1599 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1600 {
1601 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1602
1603 /* called with controller lock already held */
1604
1605 if (!epnum) {
1606 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1607 if (!is_cppi_enabled()) {
1608 /* endpoint 0 */
1609 if (devctl & MUSB_DEVCTL_HM)
1610 musb_h_ep0_irq(musb);
1611 else
1612 musb_g_ep0_irq(musb);
1613 }
1614 #endif
1615 } else {
1616 /* endpoints 1..15 */
1617 if (transmit) {
1618 if (devctl & MUSB_DEVCTL_HM) {
1619 if (is_host_capable())
1620 musb_host_tx(musb, epnum);
1621 } else {
1622 if (is_peripheral_capable())
1623 musb_g_tx(musb, epnum);
1624 }
1625 } else {
1626 /* receive */
1627 if (devctl & MUSB_DEVCTL_HM) {
1628 if (is_host_capable())
1629 musb_host_rx(musb, epnum);
1630 } else {
1631 if (is_peripheral_capable())
1632 musb_g_rx(musb, epnum);
1633 }
1634 }
1635 }
1636 }
1637
1638 #else
1639 #define use_dma 0
1640 #endif
1641
1642 /*-------------------------------------------------------------------------*/
1643
1644 #ifdef CONFIG_SYSFS
1645
1646 static ssize_t
1647 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1648 {
1649 struct musb *musb = dev_to_musb(dev);
1650 unsigned long flags;
1651 int ret = -EINVAL;
1652
1653 spin_lock_irqsave(&musb->lock, flags);
1654 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1655 spin_unlock_irqrestore(&musb->lock, flags);
1656
1657 return ret;
1658 }
1659
1660 static ssize_t
1661 musb_mode_store(struct device *dev, struct device_attribute *attr,
1662 const char *buf, size_t n)
1663 {
1664 struct musb *musb = dev_to_musb(dev);
1665 unsigned long flags;
1666 int status;
1667
1668 spin_lock_irqsave(&musb->lock, flags);
1669 if (sysfs_streq(buf, "host"))
1670 status = musb_platform_set_mode(musb, MUSB_HOST);
1671 else if (sysfs_streq(buf, "peripheral"))
1672 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1673 else if (sysfs_streq(buf, "otg"))
1674 status = musb_platform_set_mode(musb, MUSB_OTG);
1675 else
1676 status = -EINVAL;
1677 spin_unlock_irqrestore(&musb->lock, flags);
1678
1679 return (status == 0) ? n : status;
1680 }
1681 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1682
1683 static ssize_t
1684 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1685 const char *buf, size_t n)
1686 {
1687 struct musb *musb = dev_to_musb(dev);
1688 unsigned long flags;
1689 unsigned long val;
1690
1691 if (sscanf(buf, "%lu", &val) < 1) {
1692 dev_err(dev, "Invalid VBUS timeout ms value\n");
1693 return -EINVAL;
1694 }
1695
1696 spin_lock_irqsave(&musb->lock, flags);
1697 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1698 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1699 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1700 musb->is_active = 0;
1701 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1702 spin_unlock_irqrestore(&musb->lock, flags);
1703
1704 return n;
1705 }
1706
1707 static ssize_t
1708 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1709 {
1710 struct musb *musb = dev_to_musb(dev);
1711 unsigned long flags;
1712 unsigned long val;
1713 int vbus;
1714
1715 spin_lock_irqsave(&musb->lock, flags);
1716 val = musb->a_wait_bcon;
1717 /* FIXME get_vbus_status() is normally #defined as false...
1718 * and is effectively TUSB-specific.
1719 */
1720 vbus = musb_platform_get_vbus_status(musb);
1721 spin_unlock_irqrestore(&musb->lock, flags);
1722
1723 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1724 vbus ? "on" : "off", val);
1725 }
1726 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1727
1728 /* Gadget drivers can't know that a host is connected so they might want
1729 * to start SRP, but users can. This allows userspace to trigger SRP.
1730 */
1731 static ssize_t
1732 musb_srp_store(struct device *dev, struct device_attribute *attr,
1733 const char *buf, size_t n)
1734 {
1735 struct musb *musb = dev_to_musb(dev);
1736 unsigned short srp;
1737
1738 if (sscanf(buf, "%hu", &srp) != 1
1739 || (srp != 1)) {
1740 dev_err(dev, "SRP: Value must be 1\n");
1741 return -EINVAL;
1742 }
1743
1744 if (srp == 1)
1745 musb_g_wakeup(musb);
1746
1747 return n;
1748 }
1749 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1750
1751 static struct attribute *musb_attributes[] = {
1752 &dev_attr_mode.attr,
1753 &dev_attr_vbus.attr,
1754 &dev_attr_srp.attr,
1755 NULL
1756 };
1757
1758 static const struct attribute_group musb_attr_group = {
1759 .attrs = musb_attributes,
1760 };
1761
1762 #endif /* sysfs */
1763
1764 /* Only used to provide driver mode change events */
1765 static void musb_irq_work(struct work_struct *data)
1766 {
1767 struct musb *musb = container_of(data, struct musb, irq_work);
1768 static int old_state;
1769
1770 if (musb->xceiv->state != old_state) {
1771 old_state = musb->xceiv->state;
1772 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1773 }
1774 }
1775
1776 /* --------------------------------------------------------------------------
1777 * Init support
1778 */
1779
1780 static struct musb *__init
1781 allocate_instance(struct device *dev,
1782 struct musb_hdrc_config *config, void __iomem *mbase)
1783 {
1784 struct musb *musb;
1785 struct musb_hw_ep *ep;
1786 int epnum;
1787 struct usb_hcd *hcd;
1788
1789 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1790 if (!hcd)
1791 return NULL;
1792 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1793
1794 musb = hcd_to_musb(hcd);
1795 INIT_LIST_HEAD(&musb->control);
1796 INIT_LIST_HEAD(&musb->in_bulk);
1797 INIT_LIST_HEAD(&musb->out_bulk);
1798
1799 hcd->uses_new_polling = 1;
1800 hcd->has_tt = 1;
1801
1802 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1803 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1804 dev_set_drvdata(dev, musb);
1805 musb->mregs = mbase;
1806 musb->ctrl_base = mbase;
1807 musb->nIrq = -ENODEV;
1808 musb->config = config;
1809 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1810 for (epnum = 0, ep = musb->endpoints;
1811 epnum < musb->config->num_eps;
1812 epnum++, ep++) {
1813 ep->musb = musb;
1814 ep->epnum = epnum;
1815 }
1816
1817 musb->controller = dev;
1818
1819 return musb;
1820 }
1821
1822 static void musb_free(struct musb *musb)
1823 {
1824 /* this has multiple entry modes. it handles fault cleanup after
1825 * probe(), where things may be partially set up, as well as rmmod
1826 * cleanup after everything's been de-activated.
1827 */
1828
1829 #ifdef CONFIG_SYSFS
1830 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1831 #endif
1832
1833 musb_gadget_cleanup(musb);
1834
1835 if (musb->nIrq >= 0) {
1836 if (musb->irq_wake)
1837 disable_irq_wake(musb->nIrq);
1838 free_irq(musb->nIrq, musb);
1839 }
1840 if (is_dma_capable() && musb->dma_controller) {
1841 struct dma_controller *c = musb->dma_controller;
1842
1843 (void) c->stop(c);
1844 dma_controller_destroy(c);
1845 }
1846
1847 kfree(musb);
1848 }
1849
1850 /*
1851 * Perform generic per-controller initialization.
1852 *
1853 * @pDevice: the controller (already clocked, etc)
1854 * @nIrq: irq
1855 * @mregs: virtual address of controller registers,
1856 * not yet corrected for platform-specific offsets
1857 */
1858 static int __init
1859 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1860 {
1861 int status;
1862 struct musb *musb;
1863 struct musb_hdrc_platform_data *plat = dev->platform_data;
1864
1865 /* The driver might handle more features than the board; OK.
1866 * Fail when the board needs a feature that's not enabled.
1867 */
1868 if (!plat) {
1869 dev_dbg(dev, "no platform_data?\n");
1870 status = -ENODEV;
1871 goto fail0;
1872 }
1873
1874 /* allocate */
1875 musb = allocate_instance(dev, plat->config, ctrl);
1876 if (!musb) {
1877 status = -ENOMEM;
1878 goto fail0;
1879 }
1880
1881 pm_runtime_use_autosuspend(musb->controller);
1882 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1883 pm_runtime_enable(musb->controller);
1884
1885 spin_lock_init(&musb->lock);
1886 musb->board_mode = plat->mode;
1887 musb->board_set_power = plat->set_power;
1888 musb->min_power = plat->min_power;
1889 musb->ops = plat->platform_ops;
1890
1891 /* The musb_platform_init() call:
1892 * - adjusts musb->mregs and musb->isr if needed,
1893 * - may initialize an integrated tranceiver
1894 * - initializes musb->xceiv, usually by otg_get_transceiver()
1895 * - stops powering VBUS
1896 *
1897 * There are various transciever configurations. Blackfin,
1898 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1899 * external/discrete ones in various flavors (twl4030 family,
1900 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1901 */
1902 musb->isr = generic_interrupt;
1903 status = musb_platform_init(musb);
1904 if (status < 0)
1905 goto fail1;
1906
1907 if (!musb->isr) {
1908 status = -ENODEV;
1909 goto fail3;
1910 }
1911
1912 if (!musb->xceiv->io_ops) {
1913 musb->xceiv->io_priv = musb->mregs;
1914 musb->xceiv->io_ops = &musb_ulpi_access;
1915 }
1916
1917 #ifndef CONFIG_MUSB_PIO_ONLY
1918 if (use_dma && dev->dma_mask) {
1919 struct dma_controller *c;
1920
1921 c = dma_controller_create(musb, musb->mregs);
1922 musb->dma_controller = c;
1923 if (c)
1924 (void) c->start(c);
1925 }
1926 #endif
1927 /* ideally this would be abstracted in platform setup */
1928 if (!is_dma_capable() || !musb->dma_controller)
1929 dev->dma_mask = NULL;
1930
1931 /* be sure interrupts are disabled before connecting ISR */
1932 musb_platform_disable(musb);
1933 musb_generic_disable(musb);
1934
1935 /* setup musb parts of the core (especially endpoints) */
1936 status = musb_core_init(plat->config->multipoint
1937 ? MUSB_CONTROLLER_MHDRC
1938 : MUSB_CONTROLLER_HDRC, musb);
1939 if (status < 0)
1940 goto fail3;
1941
1942 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1943
1944 /* Init IRQ workqueue before request_irq */
1945 INIT_WORK(&musb->irq_work, musb_irq_work);
1946
1947 /* attach to the IRQ */
1948 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1949 dev_err(dev, "request_irq %d failed!\n", nIrq);
1950 status = -ENODEV;
1951 goto fail3;
1952 }
1953 musb->nIrq = nIrq;
1954 /* FIXME this handles wakeup irqs wrong */
1955 if (enable_irq_wake(nIrq) == 0) {
1956 musb->irq_wake = 1;
1957 device_init_wakeup(dev, 1);
1958 } else {
1959 musb->irq_wake = 0;
1960 }
1961
1962 /* host side needs more setup */
1963 if (is_host_enabled(musb)) {
1964 struct usb_hcd *hcd = musb_to_hcd(musb);
1965
1966 otg_set_host(musb->xceiv, &hcd->self);
1967
1968 if (is_otg_enabled(musb))
1969 hcd->self.otg_port = 1;
1970 musb->xceiv->host = &hcd->self;
1971 hcd->power_budget = 2 * (plat->power ? : 250);
1972
1973 /* program PHY to use external vBus if required */
1974 if (plat->extvbus) {
1975 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1976 busctl |= MUSB_ULPI_USE_EXTVBUS;
1977 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1978 }
1979 }
1980
1981 /* For the host-only role, we can activate right away.
1982 * (We expect the ID pin to be forcibly grounded!!)
1983 * Otherwise, wait till the gadget driver hooks up.
1984 */
1985 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
1986 struct usb_hcd *hcd = musb_to_hcd(musb);
1987
1988 MUSB_HST_MODE(musb);
1989 musb->xceiv->default_a = 1;
1990 musb->xceiv->state = OTG_STATE_A_IDLE;
1991
1992 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1993
1994 hcd->self.uses_pio_for_control = 1;
1995 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
1996 "HOST", status,
1997 musb_readb(musb->mregs, MUSB_DEVCTL),
1998 (musb_readb(musb->mregs, MUSB_DEVCTL)
1999 & MUSB_DEVCTL_BDEVICE
2000 ? 'B' : 'A'));
2001
2002 } else /* peripheral is enabled */ {
2003 MUSB_DEV_MODE(musb);
2004 musb->xceiv->default_a = 0;
2005 musb->xceiv->state = OTG_STATE_B_IDLE;
2006
2007 status = musb_gadget_setup(musb);
2008
2009 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2010 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2011 status,
2012 musb_readb(musb->mregs, MUSB_DEVCTL));
2013
2014 }
2015 if (status < 0)
2016 goto fail3;
2017
2018 pm_runtime_put(musb->controller);
2019
2020 status = musb_init_debugfs(musb);
2021 if (status < 0)
2022 goto fail4;
2023
2024 #ifdef CONFIG_SYSFS
2025 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2026 if (status)
2027 goto fail5;
2028 #endif
2029
2030 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2031 ({char *s;
2032 switch (musb->board_mode) {
2033 case MUSB_HOST: s = "Host"; break;
2034 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2035 default: s = "OTG"; break;
2036 }; s; }),
2037 ctrl,
2038 (is_dma_capable() && musb->dma_controller)
2039 ? "DMA" : "PIO",
2040 musb->nIrq);
2041
2042 return 0;
2043
2044 fail5:
2045 musb_exit_debugfs(musb);
2046
2047 fail4:
2048 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2049 usb_remove_hcd(musb_to_hcd(musb));
2050 else
2051 musb_gadget_cleanup(musb);
2052
2053 fail3:
2054 if (musb->irq_wake)
2055 device_init_wakeup(dev, 0);
2056 musb_platform_exit(musb);
2057
2058 fail1:
2059 dev_err(musb->controller,
2060 "musb_init_controller failed with status %d\n", status);
2061
2062 musb_free(musb);
2063
2064 fail0:
2065
2066 return status;
2067
2068 }
2069
2070 /*-------------------------------------------------------------------------*/
2071
2072 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2073 * bridge to a platform device; this driver then suffices.
2074 */
2075
2076 #ifndef CONFIG_MUSB_PIO_ONLY
2077 static u64 *orig_dma_mask;
2078 #endif
2079
2080 static int __init musb_probe(struct platform_device *pdev)
2081 {
2082 struct device *dev = &pdev->dev;
2083 int irq = platform_get_irq_byname(pdev, "mc");
2084 int status;
2085 struct resource *iomem;
2086 void __iomem *base;
2087
2088 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2089 if (!iomem || irq <= 0)
2090 return -ENODEV;
2091
2092 base = ioremap(iomem->start, resource_size(iomem));
2093 if (!base) {
2094 dev_err(dev, "ioremap failed\n");
2095 return -ENOMEM;
2096 }
2097
2098 #ifndef CONFIG_MUSB_PIO_ONLY
2099 /* clobbered by use_dma=n */
2100 orig_dma_mask = dev->dma_mask;
2101 #endif
2102 status = musb_init_controller(dev, irq, base);
2103 if (status < 0)
2104 iounmap(base);
2105
2106 return status;
2107 }
2108
2109 static int __exit musb_remove(struct platform_device *pdev)
2110 {
2111 struct musb *musb = dev_to_musb(&pdev->dev);
2112 void __iomem *ctrl_base = musb->ctrl_base;
2113
2114 /* this gets called on rmmod.
2115 * - Host mode: host may still be active
2116 * - Peripheral mode: peripheral is deactivated (or never-activated)
2117 * - OTG mode: both roles are deactivated (or never-activated)
2118 */
2119 pm_runtime_get_sync(musb->controller);
2120 musb_exit_debugfs(musb);
2121 musb_shutdown(pdev);
2122
2123 pm_runtime_put(musb->controller);
2124 musb_free(musb);
2125 iounmap(ctrl_base);
2126 device_init_wakeup(&pdev->dev, 0);
2127 #ifndef CONFIG_MUSB_PIO_ONLY
2128 pdev->dev.dma_mask = orig_dma_mask;
2129 #endif
2130 return 0;
2131 }
2132
2133 #ifdef CONFIG_PM
2134
2135 static void musb_save_context(struct musb *musb)
2136 {
2137 int i;
2138 void __iomem *musb_base = musb->mregs;
2139 void __iomem *epio;
2140
2141 if (is_host_enabled(musb)) {
2142 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2143 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2144 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2145 }
2146 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2147 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2148 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2149 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2150 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2151 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2152
2153 for (i = 0; i < musb->config->num_eps; ++i) {
2154 struct musb_hw_ep *hw_ep;
2155
2156 hw_ep = &musb->endpoints[i];
2157 if (!hw_ep)
2158 continue;
2159
2160 epio = hw_ep->regs;
2161 if (!epio)
2162 continue;
2163
2164 musb->context.index_regs[i].txmaxp =
2165 musb_readw(epio, MUSB_TXMAXP);
2166 musb->context.index_regs[i].txcsr =
2167 musb_readw(epio, MUSB_TXCSR);
2168 musb->context.index_regs[i].rxmaxp =
2169 musb_readw(epio, MUSB_RXMAXP);
2170 musb->context.index_regs[i].rxcsr =
2171 musb_readw(epio, MUSB_RXCSR);
2172
2173 if (musb->dyn_fifo) {
2174 musb->context.index_regs[i].txfifoadd =
2175 musb_read_txfifoadd(musb_base);
2176 musb->context.index_regs[i].rxfifoadd =
2177 musb_read_rxfifoadd(musb_base);
2178 musb->context.index_regs[i].txfifosz =
2179 musb_read_txfifosz(musb_base);
2180 musb->context.index_regs[i].rxfifosz =
2181 musb_read_rxfifosz(musb_base);
2182 }
2183 if (is_host_enabled(musb)) {
2184 musb->context.index_regs[i].txtype =
2185 musb_readb(epio, MUSB_TXTYPE);
2186 musb->context.index_regs[i].txinterval =
2187 musb_readb(epio, MUSB_TXINTERVAL);
2188 musb->context.index_regs[i].rxtype =
2189 musb_readb(epio, MUSB_RXTYPE);
2190 musb->context.index_regs[i].rxinterval =
2191 musb_readb(epio, MUSB_RXINTERVAL);
2192
2193 musb->context.index_regs[i].txfunaddr =
2194 musb_read_txfunaddr(musb_base, i);
2195 musb->context.index_regs[i].txhubaddr =
2196 musb_read_txhubaddr(musb_base, i);
2197 musb->context.index_regs[i].txhubport =
2198 musb_read_txhubport(musb_base, i);
2199
2200 musb->context.index_regs[i].rxfunaddr =
2201 musb_read_rxfunaddr(musb_base, i);
2202 musb->context.index_regs[i].rxhubaddr =
2203 musb_read_rxhubaddr(musb_base, i);
2204 musb->context.index_regs[i].rxhubport =
2205 musb_read_rxhubport(musb_base, i);
2206 }
2207 }
2208 }
2209
2210 static void musb_restore_context(struct musb *musb)
2211 {
2212 int i;
2213 void __iomem *musb_base = musb->mregs;
2214 void __iomem *ep_target_regs;
2215 void __iomem *epio;
2216
2217 if (is_host_enabled(musb)) {
2218 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2219 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2220 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2221 }
2222 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2223 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2224 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2225 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2226 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2227
2228 for (i = 0; i < musb->config->num_eps; ++i) {
2229 struct musb_hw_ep *hw_ep;
2230
2231 hw_ep = &musb->endpoints[i];
2232 if (!hw_ep)
2233 continue;
2234
2235 epio = hw_ep->regs;
2236 if (!epio)
2237 continue;
2238
2239 musb_writew(epio, MUSB_TXMAXP,
2240 musb->context.index_regs[i].txmaxp);
2241 musb_writew(epio, MUSB_TXCSR,
2242 musb->context.index_regs[i].txcsr);
2243 musb_writew(epio, MUSB_RXMAXP,
2244 musb->context.index_regs[i].rxmaxp);
2245 musb_writew(epio, MUSB_RXCSR,
2246 musb->context.index_regs[i].rxcsr);
2247
2248 if (musb->dyn_fifo) {
2249 musb_write_txfifosz(musb_base,
2250 musb->context.index_regs[i].txfifosz);
2251 musb_write_rxfifosz(musb_base,
2252 musb->context.index_regs[i].rxfifosz);
2253 musb_write_txfifoadd(musb_base,
2254 musb->context.index_regs[i].txfifoadd);
2255 musb_write_rxfifoadd(musb_base,
2256 musb->context.index_regs[i].rxfifoadd);
2257 }
2258
2259 if (is_host_enabled(musb)) {
2260 musb_writeb(epio, MUSB_TXTYPE,
2261 musb->context.index_regs[i].txtype);
2262 musb_writeb(epio, MUSB_TXINTERVAL,
2263 musb->context.index_regs[i].txinterval);
2264 musb_writeb(epio, MUSB_RXTYPE,
2265 musb->context.index_regs[i].rxtype);
2266 musb_writeb(epio, MUSB_RXINTERVAL,
2267
2268 musb->context.index_regs[i].rxinterval);
2269 musb_write_txfunaddr(musb_base, i,
2270 musb->context.index_regs[i].txfunaddr);
2271 musb_write_txhubaddr(musb_base, i,
2272 musb->context.index_regs[i].txhubaddr);
2273 musb_write_txhubport(musb_base, i,
2274 musb->context.index_regs[i].txhubport);
2275
2276 ep_target_regs =
2277 musb_read_target_reg_base(i, musb_base);
2278
2279 musb_write_rxfunaddr(ep_target_regs,
2280 musb->context.index_regs[i].rxfunaddr);
2281 musb_write_rxhubaddr(ep_target_regs,
2282 musb->context.index_regs[i].rxhubaddr);
2283 musb_write_rxhubport(ep_target_regs,
2284 musb->context.index_regs[i].rxhubport);
2285 }
2286 }
2287 }
2288
2289 static int musb_suspend(struct device *dev)
2290 {
2291 struct platform_device *pdev = to_platform_device(dev);
2292 unsigned long flags;
2293 struct musb *musb = dev_to_musb(&pdev->dev);
2294
2295 spin_lock_irqsave(&musb->lock, flags);
2296
2297 if (is_peripheral_active(musb)) {
2298 /* FIXME force disconnect unless we know USB will wake
2299 * the system up quickly enough to respond ...
2300 */
2301 } else if (is_host_active(musb)) {
2302 /* we know all the children are suspended; sometimes
2303 * they will even be wakeup-enabled.
2304 */
2305 }
2306
2307 musb_save_context(musb);
2308
2309 spin_unlock_irqrestore(&musb->lock, flags);
2310 return 0;
2311 }
2312
2313 static int musb_resume_noirq(struct device *dev)
2314 {
2315 struct platform_device *pdev = to_platform_device(dev);
2316 struct musb *musb = dev_to_musb(&pdev->dev);
2317
2318 musb_restore_context(musb);
2319
2320 /* for static cmos like DaVinci, register values were preserved
2321 * unless for some reason the whole soc powered down or the USB
2322 * module got reset through the PSC (vs just being disabled).
2323 */
2324 return 0;
2325 }
2326
2327 static int musb_runtime_suspend(struct device *dev)
2328 {
2329 struct musb *musb = dev_to_musb(dev);
2330
2331 musb_save_context(musb);
2332
2333 return 0;
2334 }
2335
2336 static int musb_runtime_resume(struct device *dev)
2337 {
2338 struct musb *musb = dev_to_musb(dev);
2339 static int first = 1;
2340
2341 /*
2342 * When pm_runtime_get_sync called for the first time in driver
2343 * init, some of the structure is still not initialized which is
2344 * used in restore function. But clock needs to be
2345 * enabled before any register access, so
2346 * pm_runtime_get_sync has to be called.
2347 * Also context restore without save does not make
2348 * any sense
2349 */
2350 if (!first)
2351 musb_restore_context(musb);
2352 first = 0;
2353
2354 return 0;
2355 }
2356
2357 static const struct dev_pm_ops musb_dev_pm_ops = {
2358 .suspend = musb_suspend,
2359 .resume_noirq = musb_resume_noirq,
2360 .runtime_suspend = musb_runtime_suspend,
2361 .runtime_resume = musb_runtime_resume,
2362 };
2363
2364 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2365 #else
2366 #define MUSB_DEV_PM_OPS NULL
2367 #endif
2368
2369 static struct platform_driver musb_driver = {
2370 .driver = {
2371 .name = (char *)musb_driver_name,
2372 .bus = &platform_bus_type,
2373 .owner = THIS_MODULE,
2374 .pm = MUSB_DEV_PM_OPS,
2375 },
2376 .remove = __exit_p(musb_remove),
2377 .shutdown = musb_shutdown,
2378 };
2379
2380 /*-------------------------------------------------------------------------*/
2381
2382 static int __init musb_init(void)
2383 {
2384 if (usb_disabled())
2385 return 0;
2386
2387 pr_info("%s: version " MUSB_VERSION ", "
2388 "?dma?"
2389 ", "
2390 "otg (peripheral+host)",
2391 musb_driver_name);
2392 return platform_driver_probe(&musb_driver, musb_probe);
2393 }
2394
2395 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2396 * and before usb gadget and host-side drivers start to register
2397 */
2398 fs_initcall(musb_init);
2399
2400 static void __exit musb_cleanup(void)
2401 {
2402 platform_driver_unregister(&musb_driver);
2403 }
2404 module_exit(musb_cleanup);
Linux kernel - Deliverables
This page took 0.10881 seconds and 5 git commands to generate.