2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
102 #include <linux/idr.h>
103 #include <linux/dma-mapping.h>
105 #include "musb_core.h"
107 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
110 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113 #define MUSB_VERSION "6.0"
115 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
117 #define MUSB_DRIVER_NAME "musb-hdrc"
118 const char musb_driver_name
[] = MUSB_DRIVER_NAME
;
120 MODULE_DESCRIPTION(DRIVER_INFO
);
121 MODULE_AUTHOR(DRIVER_AUTHOR
);
122 MODULE_LICENSE("GPL");
123 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME
);
126 /*-------------------------------------------------------------------------*/
128 static inline struct musb
*dev_to_musb(struct device
*dev
)
130 return dev_get_drvdata(dev
);
133 /*-------------------------------------------------------------------------*/
135 #ifndef CONFIG_BLACKFIN
136 static int musb_ulpi_read(struct usb_phy
*phy
, u32 offset
)
138 void __iomem
*addr
= phy
->io_priv
;
144 pm_runtime_get_sync(phy
->io_dev
);
146 /* Make sure the transceiver is not in low power mode */
147 power
= musb_readb(addr
, MUSB_POWER
);
148 power
&= ~MUSB_POWER_SUSPENDM
;
149 musb_writeb(addr
, MUSB_POWER
, power
);
151 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
152 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
155 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
156 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
,
157 MUSB_ULPI_REG_REQ
| MUSB_ULPI_RDN_WR
);
159 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
160 & MUSB_ULPI_REG_CMPLT
)) {
168 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
169 r
&= ~MUSB_ULPI_REG_CMPLT
;
170 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
172 ret
= musb_readb(addr
, MUSB_ULPI_REG_DATA
);
175 pm_runtime_put(phy
->io_dev
);
180 static int musb_ulpi_write(struct usb_phy
*phy
, u32 offset
, u32 data
)
182 void __iomem
*addr
= phy
->io_priv
;
188 pm_runtime_get_sync(phy
->io_dev
);
190 /* Make sure the transceiver is not in low power mode */
191 power
= musb_readb(addr
, MUSB_POWER
);
192 power
&= ~MUSB_POWER_SUSPENDM
;
193 musb_writeb(addr
, MUSB_POWER
, power
);
195 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
196 musb_writeb(addr
, MUSB_ULPI_REG_DATA
, (u8
)data
);
197 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, MUSB_ULPI_REG_REQ
);
199 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
200 & MUSB_ULPI_REG_CMPLT
)) {
208 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
209 r
&= ~MUSB_ULPI_REG_CMPLT
;
210 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
213 pm_runtime_put(phy
->io_dev
);
218 #define musb_ulpi_read NULL
219 #define musb_ulpi_write NULL
222 static struct usb_phy_io_ops musb_ulpi_access
= {
223 .read
= musb_ulpi_read
,
224 .write
= musb_ulpi_write
,
227 /*-------------------------------------------------------------------------*/
229 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
232 * Load an endpoint's FIFO
234 void musb_write_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, const u8
*src
)
236 struct musb
*musb
= hw_ep
->musb
;
237 void __iomem
*fifo
= hw_ep
->fifo
;
239 if (unlikely(len
== 0))
244 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep
->epnum
, fifo
, len
, src
);
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src
) == 0)) {
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src
) == 0) {
254 iowrite32_rep(fifo
, src
+ index
, len
>> 2);
255 index
+= len
& ~0x03;
258 musb_writew(fifo
, 0, *(u16
*)&src
[index
]);
263 iowrite16_rep(fifo
, src
+ index
, len
>> 1);
264 index
+= len
& ~0x01;
268 musb_writeb(fifo
, 0, src
[index
]);
271 iowrite8_rep(fifo
, src
, len
);
275 #if !defined(CONFIG_USB_MUSB_AM35X)
277 * Unload an endpoint's FIFO
279 void musb_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
281 struct musb
*musb
= hw_ep
->musb
;
282 void __iomem
*fifo
= hw_ep
->fifo
;
284 if (unlikely(len
== 0))
287 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
288 'R', hw_ep
->epnum
, fifo
, len
, dst
);
290 /* we can't assume unaligned writes work */
291 if (likely((0x01 & (unsigned long) dst
) == 0)) {
294 /* best case is 32bit-aligned destination address */
295 if ((0x02 & (unsigned long) dst
) == 0) {
297 ioread32_rep(fifo
, dst
, len
>> 2);
301 *(u16
*)&dst
[index
] = musb_readw(fifo
, 0);
306 ioread16_rep(fifo
, dst
, len
>> 1);
311 dst
[index
] = musb_readb(fifo
, 0);
314 ioread8_rep(fifo
, dst
, len
);
319 #endif /* normal PIO */
322 /*-------------------------------------------------------------------------*/
324 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
325 static const u8 musb_test_packet
[53] = {
326 /* implicit SYNC then DATA0 to start */
329 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
331 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
333 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
334 /* JJJJJJJKKKKKKK x8 */
335 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
337 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
338 /* JKKKKKKK x10, JK */
339 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
341 /* implicit CRC16 then EOP to end */
344 void musb_load_testpacket(struct musb
*musb
)
346 void __iomem
*regs
= musb
->endpoints
[0].regs
;
348 musb_ep_select(musb
->mregs
, 0);
349 musb_write_fifo(musb
->control_ep
,
350 sizeof(musb_test_packet
), musb_test_packet
);
351 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_TXPKTRDY
);
354 /*-------------------------------------------------------------------------*/
357 * Handles OTG hnp timeouts, such as b_ase0_brst
359 static void musb_otg_timer_func(unsigned long data
)
361 struct musb
*musb
= (struct musb
*)data
;
364 spin_lock_irqsave(&musb
->lock
, flags
);
365 switch (musb
->xceiv
->state
) {
366 case OTG_STATE_B_WAIT_ACON
:
367 dev_dbg(musb
->controller
, "HNP: b_wait_acon timeout; back to b_peripheral\n");
368 musb_g_disconnect(musb
);
369 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
372 case OTG_STATE_A_SUSPEND
:
373 case OTG_STATE_A_WAIT_BCON
:
374 dev_dbg(musb
->controller
, "HNP: %s timeout\n",
375 usb_otg_state_string(musb
->xceiv
->state
));
376 musb_platform_set_vbus(musb
, 0);
377 musb
->xceiv
->state
= OTG_STATE_A_WAIT_VFALL
;
380 dev_dbg(musb
->controller
, "HNP: Unhandled mode %s\n",
381 usb_otg_state_string(musb
->xceiv
->state
));
383 spin_unlock_irqrestore(&musb
->lock
, flags
);
387 * Stops the HNP transition. Caller must take care of locking.
389 void musb_hnp_stop(struct musb
*musb
)
391 struct usb_hcd
*hcd
= musb
->hcd
;
392 void __iomem
*mbase
= musb
->mregs
;
395 dev_dbg(musb
->controller
, "HNP: stop from %s\n",
396 usb_otg_state_string(musb
->xceiv
->state
));
398 switch (musb
->xceiv
->state
) {
399 case OTG_STATE_A_PERIPHERAL
:
400 musb_g_disconnect(musb
);
401 dev_dbg(musb
->controller
, "HNP: back to %s\n",
402 usb_otg_state_string(musb
->xceiv
->state
));
404 case OTG_STATE_B_HOST
:
405 dev_dbg(musb
->controller
, "HNP: Disabling HR\n");
407 hcd
->self
.is_b_host
= 0;
408 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
410 reg
= musb_readb(mbase
, MUSB_POWER
);
411 reg
|= MUSB_POWER_SUSPENDM
;
412 musb_writeb(mbase
, MUSB_POWER
, reg
);
413 /* REVISIT: Start SESSION_REQUEST here? */
416 dev_dbg(musb
->controller
, "HNP: Stopping in unknown state %s\n",
417 usb_otg_state_string(musb
->xceiv
->state
));
421 * When returning to A state after HNP, avoid hub_port_rebounce(),
422 * which cause occasional OPT A "Did not receive reset after connect"
425 musb
->port1_status
&= ~(USB_PORT_STAT_C_CONNECTION
<< 16);
429 * Interrupt Service Routine to record USB "global" interrupts.
430 * Since these do not happen often and signify things of
431 * paramount importance, it seems OK to check them individually;
432 * the order of the tests is specified in the manual
434 * @param musb instance pointer
435 * @param int_usb register contents
440 static irqreturn_t
musb_stage0_irq(struct musb
*musb
, u8 int_usb
,
443 struct usb_otg
*otg
= musb
->xceiv
->otg
;
444 irqreturn_t handled
= IRQ_NONE
;
446 dev_dbg(musb
->controller
, "<== DevCtl=%02x, int_usb=0x%x\n", devctl
,
449 /* in host mode, the peripheral may issue remote wakeup.
450 * in peripheral mode, the host may resume the link.
451 * spurious RESUME irqs happen too, paired with SUSPEND.
453 if (int_usb
& MUSB_INTR_RESUME
) {
454 handled
= IRQ_HANDLED
;
455 dev_dbg(musb
->controller
, "RESUME (%s)\n", usb_otg_state_string(musb
->xceiv
->state
));
457 if (devctl
& MUSB_DEVCTL_HM
) {
458 void __iomem
*mbase
= musb
->mregs
;
461 switch (musb
->xceiv
->state
) {
462 case OTG_STATE_A_SUSPEND
:
463 /* remote wakeup? later, GetPortStatus
464 * will stop RESUME signaling
467 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
468 if (power
& MUSB_POWER_SUSPENDM
) {
470 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
471 dev_dbg(musb
->controller
, "Spurious SUSPENDM\n");
475 power
&= ~MUSB_POWER_SUSPENDM
;
476 musb_writeb(mbase
, MUSB_POWER
,
477 power
| MUSB_POWER_RESUME
);
479 musb
->port1_status
|=
480 (USB_PORT_STAT_C_SUSPEND
<< 16)
481 | MUSB_PORT_STAT_RESUME
;
482 musb
->rh_timer
= jiffies
483 + msecs_to_jiffies(20);
485 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
487 musb_host_resume_root_hub(musb
);
489 case OTG_STATE_B_WAIT_ACON
:
490 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
495 WARNING("bogus %s RESUME (%s)\n",
497 usb_otg_state_string(musb
->xceiv
->state
));
500 switch (musb
->xceiv
->state
) {
501 case OTG_STATE_A_SUSPEND
:
502 /* possibly DISCONNECT is upcoming */
503 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
504 musb_host_resume_root_hub(musb
);
506 case OTG_STATE_B_WAIT_ACON
:
507 case OTG_STATE_B_PERIPHERAL
:
508 /* disconnect while suspended? we may
509 * not get a disconnect irq...
511 if ((devctl
& MUSB_DEVCTL_VBUS
)
512 != (3 << MUSB_DEVCTL_VBUS_SHIFT
)
514 musb
->int_usb
|= MUSB_INTR_DISCONNECT
;
515 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
520 case OTG_STATE_B_IDLE
:
521 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
524 WARNING("bogus %s RESUME (%s)\n",
526 usb_otg_state_string(musb
->xceiv
->state
));
531 /* see manual for the order of the tests */
532 if (int_usb
& MUSB_INTR_SESSREQ
) {
533 void __iomem
*mbase
= musb
->mregs
;
535 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
536 && (devctl
& MUSB_DEVCTL_BDEVICE
)) {
537 dev_dbg(musb
->controller
, "SessReq while on B state\n");
541 dev_dbg(musb
->controller
, "SESSION_REQUEST (%s)\n",
542 usb_otg_state_string(musb
->xceiv
->state
));
544 /* IRQ arrives from ID pin sense or (later, if VBUS power
545 * is removed) SRP. responses are time critical:
546 * - turn on VBUS (with silicon-specific mechanism)
547 * - go through A_WAIT_VRISE
548 * - ... to A_WAIT_BCON.
549 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
551 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
552 musb
->ep0_stage
= MUSB_EP0_START
;
553 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
555 musb_platform_set_vbus(musb
, 1);
557 handled
= IRQ_HANDLED
;
560 if (int_usb
& MUSB_INTR_VBUSERROR
) {
563 /* During connection as an A-Device, we may see a short
564 * current spikes causing voltage drop, because of cable
565 * and peripheral capacitance combined with vbus draw.
566 * (So: less common with truly self-powered devices, where
567 * vbus doesn't act like a power supply.)
569 * Such spikes are short; usually less than ~500 usec, max
570 * of ~2 msec. That is, they're not sustained overcurrent
571 * errors, though they're reported using VBUSERROR irqs.
573 * Workarounds: (a) hardware: use self powered devices.
574 * (b) software: ignore non-repeated VBUS errors.
576 * REVISIT: do delays from lots of DEBUG_KERNEL checks
577 * make trouble here, keeping VBUS < 4.4V ?
579 switch (musb
->xceiv
->state
) {
580 case OTG_STATE_A_HOST
:
581 /* recovery is dicey once we've gotten past the
582 * initial stages of enumeration, but if VBUS
583 * stayed ok at the other end of the link, and
584 * another reset is due (at least for high speed,
585 * to redo the chirp etc), it might work OK...
587 case OTG_STATE_A_WAIT_BCON
:
588 case OTG_STATE_A_WAIT_VRISE
:
589 if (musb
->vbuserr_retry
) {
590 void __iomem
*mbase
= musb
->mregs
;
592 musb
->vbuserr_retry
--;
594 devctl
|= MUSB_DEVCTL_SESSION
;
595 musb_writeb(mbase
, MUSB_DEVCTL
, devctl
);
597 musb
->port1_status
|=
598 USB_PORT_STAT_OVERCURRENT
599 | (USB_PORT_STAT_C_OVERCURRENT
<< 16);
606 dev_printk(ignore
? KERN_DEBUG
: KERN_ERR
, musb
->controller
,
607 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
608 usb_otg_state_string(musb
->xceiv
->state
),
611 switch (devctl
& MUSB_DEVCTL_VBUS
) {
612 case 0 << MUSB_DEVCTL_VBUS_SHIFT
:
613 s
= "<SessEnd"; break;
614 case 1 << MUSB_DEVCTL_VBUS_SHIFT
:
615 s
= "<AValid"; break;
616 case 2 << MUSB_DEVCTL_VBUS_SHIFT
:
617 s
= "<VBusValid"; break;
618 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
622 VBUSERR_RETRY_COUNT
- musb
->vbuserr_retry
,
625 /* go through A_WAIT_VFALL then start a new session */
627 musb_platform_set_vbus(musb
, 0);
628 handled
= IRQ_HANDLED
;
631 if (int_usb
& MUSB_INTR_SUSPEND
) {
632 dev_dbg(musb
->controller
, "SUSPEND (%s) devctl %02x\n",
633 usb_otg_state_string(musb
->xceiv
->state
), devctl
);
634 handled
= IRQ_HANDLED
;
636 switch (musb
->xceiv
->state
) {
637 case OTG_STATE_A_PERIPHERAL
:
638 /* We also come here if the cable is removed, since
639 * this silicon doesn't report ID-no-longer-grounded.
641 * We depend on T(a_wait_bcon) to shut us down, and
642 * hope users don't do anything dicey during this
643 * undesired detour through A_WAIT_BCON.
646 musb_host_resume_root_hub(musb
);
647 musb_root_disconnect(musb
);
648 musb_platform_try_idle(musb
, jiffies
649 + msecs_to_jiffies(musb
->a_wait_bcon
650 ? : OTG_TIME_A_WAIT_BCON
));
653 case OTG_STATE_B_IDLE
:
654 if (!musb
->is_active
)
656 case OTG_STATE_B_PERIPHERAL
:
657 musb_g_suspend(musb
);
658 musb
->is_active
= otg
->gadget
->b_hnp_enable
;
659 if (musb
->is_active
) {
660 musb
->xceiv
->state
= OTG_STATE_B_WAIT_ACON
;
661 dev_dbg(musb
->controller
, "HNP: Setting timer for b_ase0_brst\n");
662 mod_timer(&musb
->otg_timer
, jiffies
664 OTG_TIME_B_ASE0_BRST
));
667 case OTG_STATE_A_WAIT_BCON
:
668 if (musb
->a_wait_bcon
!= 0)
669 musb_platform_try_idle(musb
, jiffies
670 + msecs_to_jiffies(musb
->a_wait_bcon
));
672 case OTG_STATE_A_HOST
:
673 musb
->xceiv
->state
= OTG_STATE_A_SUSPEND
;
674 musb
->is_active
= otg
->host
->b_hnp_enable
;
676 case OTG_STATE_B_HOST
:
677 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
678 dev_dbg(musb
->controller
, "REVISIT: SUSPEND as B_HOST\n");
681 /* "should not happen" */
687 if (int_usb
& MUSB_INTR_CONNECT
) {
688 struct usb_hcd
*hcd
= musb
->hcd
;
690 handled
= IRQ_HANDLED
;
693 musb
->ep0_stage
= MUSB_EP0_START
;
695 /* flush endpoints when transitioning from Device Mode */
696 if (is_peripheral_active(musb
)) {
697 /* REVISIT HNP; just force disconnect */
699 musb
->intrtxe
= musb
->epmask
;
700 musb_writew(musb
->mregs
, MUSB_INTRTXE
, musb
->intrtxe
);
701 musb
->intrrxe
= musb
->epmask
& 0xfffe;
702 musb_writew(musb
->mregs
, MUSB_INTRRXE
, musb
->intrrxe
);
703 musb_writeb(musb
->mregs
, MUSB_INTRUSBE
, 0xf7);
704 musb
->port1_status
&= ~(USB_PORT_STAT_LOW_SPEED
705 |USB_PORT_STAT_HIGH_SPEED
706 |USB_PORT_STAT_ENABLE
708 musb
->port1_status
|= USB_PORT_STAT_CONNECTION
709 |(USB_PORT_STAT_C_CONNECTION
<< 16);
711 /* high vs full speed is just a guess until after reset */
712 if (devctl
& MUSB_DEVCTL_LSDEV
)
713 musb
->port1_status
|= USB_PORT_STAT_LOW_SPEED
;
715 /* indicate new connection to OTG machine */
716 switch (musb
->xceiv
->state
) {
717 case OTG_STATE_B_PERIPHERAL
:
718 if (int_usb
& MUSB_INTR_SUSPEND
) {
719 dev_dbg(musb
->controller
, "HNP: SUSPEND+CONNECT, now b_host\n");
720 int_usb
&= ~MUSB_INTR_SUSPEND
;
723 dev_dbg(musb
->controller
, "CONNECT as b_peripheral???\n");
725 case OTG_STATE_B_WAIT_ACON
:
726 dev_dbg(musb
->controller
, "HNP: CONNECT, now b_host\n");
728 musb
->xceiv
->state
= OTG_STATE_B_HOST
;
730 musb
->hcd
->self
.is_b_host
= 1;
731 del_timer(&musb
->otg_timer
);
734 if ((devctl
& MUSB_DEVCTL_VBUS
)
735 == (3 << MUSB_DEVCTL_VBUS_SHIFT
)) {
736 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
738 hcd
->self
.is_b_host
= 0;
743 musb_host_poke_root_hub(musb
);
745 dev_dbg(musb
->controller
, "CONNECT (%s) devctl %02x\n",
746 usb_otg_state_string(musb
->xceiv
->state
), devctl
);
749 if (int_usb
& MUSB_INTR_DISCONNECT
) {
750 dev_dbg(musb
->controller
, "DISCONNECT (%s) as %s, devctl %02x\n",
751 usb_otg_state_string(musb
->xceiv
->state
),
752 MUSB_MODE(musb
), devctl
);
753 handled
= IRQ_HANDLED
;
755 switch (musb
->xceiv
->state
) {
756 case OTG_STATE_A_HOST
:
757 case OTG_STATE_A_SUSPEND
:
758 musb_host_resume_root_hub(musb
);
759 musb_root_disconnect(musb
);
760 if (musb
->a_wait_bcon
!= 0)
761 musb_platform_try_idle(musb
, jiffies
762 + msecs_to_jiffies(musb
->a_wait_bcon
));
764 case OTG_STATE_B_HOST
:
765 /* REVISIT this behaves for "real disconnect"
766 * cases; make sure the other transitions from
767 * from B_HOST act right too. The B_HOST code
768 * in hnp_stop() is currently not used...
770 musb_root_disconnect(musb
);
772 musb
->hcd
->self
.is_b_host
= 0;
773 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
775 musb_g_disconnect(musb
);
777 case OTG_STATE_A_PERIPHERAL
:
779 musb_root_disconnect(musb
);
781 case OTG_STATE_B_WAIT_ACON
:
783 case OTG_STATE_B_PERIPHERAL
:
784 case OTG_STATE_B_IDLE
:
785 musb_g_disconnect(musb
);
788 WARNING("unhandled DISCONNECT transition (%s)\n",
789 usb_otg_state_string(musb
->xceiv
->state
));
794 /* mentor saves a bit: bus reset and babble share the same irq.
795 * only host sees babble; only peripheral sees bus reset.
797 if (int_usb
& MUSB_INTR_RESET
) {
798 handled
= IRQ_HANDLED
;
799 if ((devctl
& MUSB_DEVCTL_HM
) != 0) {
801 * Looks like non-HS BABBLE can be ignored, but
802 * HS BABBLE is an error condition. For HS the solution
803 * is to avoid babble in the first place and fix what
804 * caused BABBLE. When HS BABBLE happens we can only
807 if (devctl
& (MUSB_DEVCTL_FSDEV
| MUSB_DEVCTL_LSDEV
))
808 dev_dbg(musb
->controller
, "BABBLE devctl: %02x\n", devctl
);
810 ERR("Stopping host session -- babble\n");
811 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
814 dev_dbg(musb
->controller
, "BUS RESET as %s\n",
815 usb_otg_state_string(musb
->xceiv
->state
));
816 switch (musb
->xceiv
->state
) {
817 case OTG_STATE_A_SUSPEND
:
820 case OTG_STATE_A_WAIT_BCON
: /* OPT TD.4.7-900ms */
821 /* never use invalid T(a_wait_bcon) */
822 dev_dbg(musb
->controller
, "HNP: in %s, %d msec timeout\n",
823 usb_otg_state_string(musb
->xceiv
->state
),
825 mod_timer(&musb
->otg_timer
, jiffies
826 + msecs_to_jiffies(TA_WAIT_BCON(musb
)));
828 case OTG_STATE_A_PERIPHERAL
:
829 del_timer(&musb
->otg_timer
);
832 case OTG_STATE_B_WAIT_ACON
:
833 dev_dbg(musb
->controller
, "HNP: RESET (%s), to b_peripheral\n",
834 usb_otg_state_string(musb
->xceiv
->state
));
835 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
838 case OTG_STATE_B_IDLE
:
839 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
841 case OTG_STATE_B_PERIPHERAL
:
845 dev_dbg(musb
->controller
, "Unhandled BUS RESET as %s\n",
846 usb_otg_state_string(musb
->xceiv
->state
));
852 /* REVISIT ... this would be for multiplexing periodic endpoints, or
853 * supporting transfer phasing to prevent exceeding ISO bandwidth
854 * limits of a given frame or microframe.
856 * It's not needed for peripheral side, which dedicates endpoints;
857 * though it _might_ use SOF irqs for other purposes.
859 * And it's not currently needed for host side, which also dedicates
860 * endpoints, relies on TX/RX interval registers, and isn't claimed
861 * to support ISO transfers yet.
863 if (int_usb
& MUSB_INTR_SOF
) {
864 void __iomem
*mbase
= musb
->mregs
;
865 struct musb_hw_ep
*ep
;
869 dev_dbg(musb
->controller
, "START_OF_FRAME\n");
870 handled
= IRQ_HANDLED
;
872 /* start any periodic Tx transfers waiting for current frame */
873 frame
= musb_readw(mbase
, MUSB_FRAME
);
874 ep
= musb
->endpoints
;
875 for (epnum
= 1; (epnum
< musb
->nr_endpoints
)
876 && (musb
->epmask
>= (1 << epnum
));
879 * FIXME handle framecounter wraps (12 bits)
880 * eliminate duplicated StartUrb logic
882 if (ep
->dwWaitFrame
>= frame
) {
884 pr_debug("SOF --> periodic TX%s on %d\n",
885 ep
->tx_channel
? " DMA" : "",
888 musb_h_tx_start(musb
, epnum
);
890 cppi_hostdma_start(musb
, epnum
);
892 } /* end of for loop */
896 schedule_work(&musb
->irq_work
);
901 /*-------------------------------------------------------------------------*/
903 static void musb_generic_disable(struct musb
*musb
)
905 void __iomem
*mbase
= musb
->mregs
;
908 /* disable interrupts */
909 musb_writeb(mbase
, MUSB_INTRUSBE
, 0);
911 musb_writew(mbase
, MUSB_INTRTXE
, 0);
913 musb_writew(mbase
, MUSB_INTRRXE
, 0);
916 musb_writeb(mbase
, MUSB_DEVCTL
, 0);
918 /* flush pending interrupts */
919 temp
= musb_readb(mbase
, MUSB_INTRUSB
);
920 temp
= musb_readw(mbase
, MUSB_INTRTX
);
921 temp
= musb_readw(mbase
, MUSB_INTRRX
);
926 * Make the HDRC stop (disable interrupts, etc.);
927 * reversible by musb_start
928 * called on gadget driver unregister
929 * with controller locked, irqs blocked
930 * acts as a NOP unless some role activated the hardware
932 void musb_stop(struct musb
*musb
)
934 /* stop IRQs, timers, ... */
935 musb_platform_disable(musb
);
936 musb_generic_disable(musb
);
937 dev_dbg(musb
->controller
, "HDRC disabled\n");
940 * - mark host and/or peripheral drivers unusable/inactive
941 * - disable DMA (and enable it in HdrcStart)
942 * - make sure we can musb_start() after musb_stop(); with
943 * OTG mode, gadget driver module rmmod/modprobe cycles that
946 musb_platform_try_idle(musb
, 0);
949 static void musb_shutdown(struct platform_device
*pdev
)
951 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
954 pm_runtime_get_sync(musb
->controller
);
956 musb_host_cleanup(musb
);
957 musb_gadget_cleanup(musb
);
959 spin_lock_irqsave(&musb
->lock
, flags
);
960 musb_platform_disable(musb
);
961 musb_generic_disable(musb
);
962 spin_unlock_irqrestore(&musb
->lock
, flags
);
964 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
965 musb_platform_exit(musb
);
967 pm_runtime_put(musb
->controller
);
968 /* FIXME power down */
972 /*-------------------------------------------------------------------------*/
975 * The silicon either has hard-wired endpoint configurations, or else
976 * "dynamic fifo" sizing. The driver has support for both, though at this
977 * writing only the dynamic sizing is very well tested. Since we switched
978 * away from compile-time hardware parameters, we can no longer rely on
979 * dead code elimination to leave only the relevant one in the object file.
981 * We don't currently use dynamic fifo setup capability to do anything
982 * more than selecting one of a bunch of predefined configurations.
984 #if defined(CONFIG_USB_MUSB_TUSB6010) \
985 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
986 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
987 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
988 || defined(CONFIG_USB_MUSB_AM35X) \
989 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
990 || defined(CONFIG_USB_MUSB_DSPS) \
991 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
992 static ushort fifo_mode
= 4;
993 #elif defined(CONFIG_USB_MUSB_UX500) \
994 || defined(CONFIG_USB_MUSB_UX500_MODULE)
995 static ushort fifo_mode
= 5;
997 static ushort fifo_mode
= 2;
1000 /* "modprobe ... fifo_mode=1" etc */
1001 module_param(fifo_mode
, ushort
, 0);
1002 MODULE_PARM_DESC(fifo_mode
, "initial endpoint configuration");
1005 * tables defining fifo_mode values. define more if you like.
1006 * for host side, make sure both halves of ep1 are set up.
1009 /* mode 0 - fits in 2KB */
1010 static struct musb_fifo_cfg mode_0_cfg
[] = {
1011 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1012 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1013 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1014 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1015 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1018 /* mode 1 - fits in 4KB */
1019 static struct musb_fifo_cfg mode_1_cfg
[] = {
1020 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1021 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1022 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1023 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1024 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1027 /* mode 2 - fits in 4KB */
1028 static struct musb_fifo_cfg mode_2_cfg
[] = {
1029 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1030 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1031 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1032 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1033 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1034 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1037 /* mode 3 - fits in 4KB */
1038 static struct musb_fifo_cfg mode_3_cfg
[] = {
1039 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1040 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1041 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1042 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1043 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1044 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1047 /* mode 4 - fits in 16KB */
1048 static struct musb_fifo_cfg mode_4_cfg
[] = {
1049 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1050 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1051 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1052 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1053 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1054 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1055 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1056 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1057 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1058 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1059 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 512, },
1060 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 512, },
1061 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 512, },
1062 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 512, },
1063 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 512, },
1064 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 512, },
1065 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 512, },
1066 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 512, },
1067 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 256, },
1068 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 64, },
1069 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 256, },
1070 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 64, },
1071 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 256, },
1072 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 64, },
1073 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 4096, },
1074 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1075 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1078 /* mode 5 - fits in 8KB */
1079 static struct musb_fifo_cfg mode_5_cfg
[] = {
1080 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1081 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1082 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1083 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1084 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1085 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1086 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1087 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1088 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1089 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1090 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 32, },
1091 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 32, },
1092 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 32, },
1093 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 32, },
1094 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 32, },
1095 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 32, },
1096 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 32, },
1097 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 32, },
1098 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 32, },
1099 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 32, },
1100 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 32, },
1101 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 32, },
1102 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 32, },
1103 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 32, },
1104 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1105 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1106 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1110 * configure a fifo; for non-shared endpoints, this may be called
1111 * once for a tx fifo and once for an rx fifo.
1113 * returns negative errno or offset for next fifo.
1116 fifo_setup(struct musb
*musb
, struct musb_hw_ep
*hw_ep
,
1117 const struct musb_fifo_cfg
*cfg
, u16 offset
)
1119 void __iomem
*mbase
= musb
->mregs
;
1121 u16 maxpacket
= cfg
->maxpacket
;
1122 u16 c_off
= offset
>> 3;
1125 /* expect hw_ep has already been zero-initialized */
1127 size
= ffs(max(maxpacket
, (u16
) 8)) - 1;
1128 maxpacket
= 1 << size
;
1131 if (cfg
->mode
== BUF_DOUBLE
) {
1132 if ((offset
+ (maxpacket
<< 1)) >
1133 (1 << (musb
->config
->ram_bits
+ 2)))
1135 c_size
|= MUSB_FIFOSZ_DPB
;
1137 if ((offset
+ maxpacket
) > (1 << (musb
->config
->ram_bits
+ 2)))
1141 /* configure the FIFO */
1142 musb_writeb(mbase
, MUSB_INDEX
, hw_ep
->epnum
);
1144 /* EP0 reserved endpoint for control, bidirectional;
1145 * EP1 reserved for bulk, two unidirection halves.
1147 if (hw_ep
->epnum
== 1)
1148 musb
->bulk_ep
= hw_ep
;
1149 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1150 switch (cfg
->style
) {
1152 musb_write_txfifosz(mbase
, c_size
);
1153 musb_write_txfifoadd(mbase
, c_off
);
1154 hw_ep
->tx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1155 hw_ep
->max_packet_sz_tx
= maxpacket
;
1158 musb_write_rxfifosz(mbase
, c_size
);
1159 musb_write_rxfifoadd(mbase
, c_off
);
1160 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1161 hw_ep
->max_packet_sz_rx
= maxpacket
;
1164 musb_write_txfifosz(mbase
, c_size
);
1165 musb_write_txfifoadd(mbase
, c_off
);
1166 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1167 hw_ep
->max_packet_sz_rx
= maxpacket
;
1169 musb_write_rxfifosz(mbase
, c_size
);
1170 musb_write_rxfifoadd(mbase
, c_off
);
1171 hw_ep
->tx_double_buffered
= hw_ep
->rx_double_buffered
;
1172 hw_ep
->max_packet_sz_tx
= maxpacket
;
1174 hw_ep
->is_shared_fifo
= true;
1178 /* NOTE rx and tx endpoint irqs aren't managed separately,
1179 * which happens to be ok
1181 musb
->epmask
|= (1 << hw_ep
->epnum
);
1183 return offset
+ (maxpacket
<< ((c_size
& MUSB_FIFOSZ_DPB
) ? 1 : 0));
1186 static struct musb_fifo_cfg ep0_cfg
= {
1187 .style
= FIFO_RXTX
, .maxpacket
= 64,
1190 static int ep_config_from_table(struct musb
*musb
)
1192 const struct musb_fifo_cfg
*cfg
;
1195 struct musb_hw_ep
*hw_ep
= musb
->endpoints
;
1197 if (musb
->config
->fifo_cfg
) {
1198 cfg
= musb
->config
->fifo_cfg
;
1199 n
= musb
->config
->fifo_cfg_size
;
1203 switch (fifo_mode
) {
1209 n
= ARRAY_SIZE(mode_0_cfg
);
1213 n
= ARRAY_SIZE(mode_1_cfg
);
1217 n
= ARRAY_SIZE(mode_2_cfg
);
1221 n
= ARRAY_SIZE(mode_3_cfg
);
1225 n
= ARRAY_SIZE(mode_4_cfg
);
1229 n
= ARRAY_SIZE(mode_5_cfg
);
1233 printk(KERN_DEBUG
"%s: setup fifo_mode %d\n",
1234 musb_driver_name
, fifo_mode
);
1238 offset
= fifo_setup(musb
, hw_ep
, &ep0_cfg
, 0);
1239 /* assert(offset > 0) */
1241 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1242 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1245 for (i
= 0; i
< n
; i
++) {
1246 u8 epn
= cfg
->hw_ep_num
;
1248 if (epn
>= musb
->config
->num_eps
) {
1249 pr_debug("%s: invalid ep %d\n",
1250 musb_driver_name
, epn
);
1253 offset
= fifo_setup(musb
, hw_ep
+ epn
, cfg
++, offset
);
1255 pr_debug("%s: mem overrun, ep %d\n",
1256 musb_driver_name
, epn
);
1260 musb
->nr_endpoints
= max(epn
, musb
->nr_endpoints
);
1263 printk(KERN_DEBUG
"%s: %d/%d max ep, %d/%d memory\n",
1265 n
+ 1, musb
->config
->num_eps
* 2 - 1,
1266 offset
, (1 << (musb
->config
->ram_bits
+ 2)));
1268 if (!musb
->bulk_ep
) {
1269 pr_debug("%s: missing bulk\n", musb_driver_name
);
1278 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1279 * @param musb the controller
1281 static int ep_config_from_hw(struct musb
*musb
)
1284 struct musb_hw_ep
*hw_ep
;
1285 void __iomem
*mbase
= musb
->mregs
;
1288 dev_dbg(musb
->controller
, "<== static silicon ep config\n");
1290 /* FIXME pick up ep0 maxpacket size */
1292 for (epnum
= 1; epnum
< musb
->config
->num_eps
; epnum
++) {
1293 musb_ep_select(mbase
, epnum
);
1294 hw_ep
= musb
->endpoints
+ epnum
;
1296 ret
= musb_read_fifosize(musb
, hw_ep
, epnum
);
1300 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1302 /* pick an RX/TX endpoint for bulk */
1303 if (hw_ep
->max_packet_sz_tx
< 512
1304 || hw_ep
->max_packet_sz_rx
< 512)
1307 /* REVISIT: this algorithm is lazy, we should at least
1308 * try to pick a double buffered endpoint.
1312 musb
->bulk_ep
= hw_ep
;
1315 if (!musb
->bulk_ep
) {
1316 pr_debug("%s: missing bulk\n", musb_driver_name
);
1323 enum { MUSB_CONTROLLER_MHDRC
, MUSB_CONTROLLER_HDRC
, };
1325 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1326 * configure endpoints, or take their config from silicon
1328 static int musb_core_init(u16 musb_type
, struct musb
*musb
)
1332 char aInfo
[90], aRevision
[32], aDate
[12];
1333 void __iomem
*mbase
= musb
->mregs
;
1337 /* log core options (read using indexed model) */
1338 reg
= musb_read_configdata(mbase
);
1340 strcpy(aInfo
, (reg
& MUSB_CONFIGDATA_UTMIDW
) ? "UTMI-16" : "UTMI-8");
1341 if (reg
& MUSB_CONFIGDATA_DYNFIFO
) {
1342 strcat(aInfo
, ", dyn FIFOs");
1343 musb
->dyn_fifo
= true;
1345 if (reg
& MUSB_CONFIGDATA_MPRXE
) {
1346 strcat(aInfo
, ", bulk combine");
1347 musb
->bulk_combine
= true;
1349 if (reg
& MUSB_CONFIGDATA_MPTXE
) {
1350 strcat(aInfo
, ", bulk split");
1351 musb
->bulk_split
= true;
1353 if (reg
& MUSB_CONFIGDATA_HBRXE
) {
1354 strcat(aInfo
, ", HB-ISO Rx");
1355 musb
->hb_iso_rx
= true;
1357 if (reg
& MUSB_CONFIGDATA_HBTXE
) {
1358 strcat(aInfo
, ", HB-ISO Tx");
1359 musb
->hb_iso_tx
= true;
1361 if (reg
& MUSB_CONFIGDATA_SOFTCONE
)
1362 strcat(aInfo
, ", SoftConn");
1364 printk(KERN_DEBUG
"%s: ConfigData=0x%02x (%s)\n",
1365 musb_driver_name
, reg
, aInfo
);
1368 if (MUSB_CONTROLLER_MHDRC
== musb_type
) {
1369 musb
->is_multipoint
= 1;
1372 musb
->is_multipoint
= 0;
1374 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1376 "%s: kernel must blacklist external hubs\n",
1381 /* log release info */
1382 musb
->hwvers
= musb_read_hwvers(mbase
);
1383 snprintf(aRevision
, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb
->hwvers
),
1384 MUSB_HWVERS_MINOR(musb
->hwvers
),
1385 (musb
->hwvers
& MUSB_HWVERS_RC
) ? "RC" : "");
1386 printk(KERN_DEBUG
"%s: %sHDRC RTL version %s %s\n",
1387 musb_driver_name
, type
, aRevision
, aDate
);
1390 musb_configure_ep0(musb
);
1392 /* discover endpoint configuration */
1393 musb
->nr_endpoints
= 1;
1397 status
= ep_config_from_table(musb
);
1399 status
= ep_config_from_hw(musb
);
1404 /* finish init, and print endpoint config */
1405 for (i
= 0; i
< musb
->nr_endpoints
; i
++) {
1406 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ i
;
1408 hw_ep
->fifo
= MUSB_FIFO_OFFSET(i
) + mbase
;
1409 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1410 hw_ep
->fifo_async
= musb
->async
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1411 hw_ep
->fifo_sync
= musb
->sync
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1412 hw_ep
->fifo_sync_va
=
1413 musb
->sync_va
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1416 hw_ep
->conf
= mbase
- 0x400 + TUSB_EP0_CONF
;
1418 hw_ep
->conf
= mbase
+ 0x400 + (((i
- 1) & 0xf) << 2);
1421 hw_ep
->regs
= MUSB_EP_OFFSET(i
, 0) + mbase
;
1422 hw_ep
->target_regs
= musb_read_target_reg_base(i
, mbase
);
1423 hw_ep
->rx_reinit
= 1;
1424 hw_ep
->tx_reinit
= 1;
1426 if (hw_ep
->max_packet_sz_tx
) {
1427 dev_dbg(musb
->controller
,
1428 "%s: hw_ep %d%s, %smax %d\n",
1429 musb_driver_name
, i
,
1430 hw_ep
->is_shared_fifo
? "shared" : "tx",
1431 hw_ep
->tx_double_buffered
1432 ? "doublebuffer, " : "",
1433 hw_ep
->max_packet_sz_tx
);
1435 if (hw_ep
->max_packet_sz_rx
&& !hw_ep
->is_shared_fifo
) {
1436 dev_dbg(musb
->controller
,
1437 "%s: hw_ep %d%s, %smax %d\n",
1438 musb_driver_name
, i
,
1440 hw_ep
->rx_double_buffered
1441 ? "doublebuffer, " : "",
1442 hw_ep
->max_packet_sz_rx
);
1444 if (!(hw_ep
->max_packet_sz_tx
|| hw_ep
->max_packet_sz_rx
))
1445 dev_dbg(musb
->controller
, "hw_ep %d not configured\n", i
);
1451 /*-------------------------------------------------------------------------*/
1454 * handle all the irqs defined by the HDRC core. for now we expect: other
1455 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1456 * will be assigned, and the irq will already have been acked.
1458 * called in irq context with spinlock held, irqs blocked
1460 irqreturn_t
musb_interrupt(struct musb
*musb
)
1462 irqreturn_t retval
= IRQ_NONE
;
1467 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1469 dev_dbg(musb
->controller
, "** IRQ %s usb%04x tx%04x rx%04x\n",
1470 (devctl
& MUSB_DEVCTL_HM
) ? "host" : "peripheral",
1471 musb
->int_usb
, musb
->int_tx
, musb
->int_rx
);
1473 /* the core can interrupt us for multiple reasons; docs have
1474 * a generic interrupt flowchart to follow
1477 retval
|= musb_stage0_irq(musb
, musb
->int_usb
,
1480 /* "stage 1" is handling endpoint irqs */
1482 /* handle endpoint 0 first */
1483 if (musb
->int_tx
& 1) {
1484 if (devctl
& MUSB_DEVCTL_HM
)
1485 retval
|= musb_h_ep0_irq(musb
);
1487 retval
|= musb_g_ep0_irq(musb
);
1490 /* RX on endpoints 1-15 */
1491 reg
= musb
->int_rx
>> 1;
1495 /* musb_ep_select(musb->mregs, ep_num); */
1496 /* REVISIT just retval = ep->rx_irq(...) */
1497 retval
= IRQ_HANDLED
;
1498 if (devctl
& MUSB_DEVCTL_HM
)
1499 musb_host_rx(musb
, ep_num
);
1501 musb_g_rx(musb
, ep_num
);
1508 /* TX on endpoints 1-15 */
1509 reg
= musb
->int_tx
>> 1;
1513 /* musb_ep_select(musb->mregs, ep_num); */
1514 /* REVISIT just retval |= ep->tx_irq(...) */
1515 retval
= IRQ_HANDLED
;
1516 if (devctl
& MUSB_DEVCTL_HM
)
1517 musb_host_tx(musb
, ep_num
);
1519 musb_g_tx(musb
, ep_num
);
1527 EXPORT_SYMBOL_GPL(musb_interrupt
);
1529 #ifndef CONFIG_MUSB_PIO_ONLY
1530 static bool use_dma
= 1;
1532 /* "modprobe ... use_dma=0" etc */
1533 module_param(use_dma
, bool, 0);
1534 MODULE_PARM_DESC(use_dma
, "enable/disable use of DMA");
1536 void musb_dma_completion(struct musb
*musb
, u8 epnum
, u8 transmit
)
1538 u8 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1540 /* called with controller lock already held */
1543 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1544 if (!is_cppi_enabled()) {
1546 if (devctl
& MUSB_DEVCTL_HM
)
1547 musb_h_ep0_irq(musb
);
1549 musb_g_ep0_irq(musb
);
1553 /* endpoints 1..15 */
1555 if (devctl
& MUSB_DEVCTL_HM
)
1556 musb_host_tx(musb
, epnum
);
1558 musb_g_tx(musb
, epnum
);
1561 if (devctl
& MUSB_DEVCTL_HM
)
1562 musb_host_rx(musb
, epnum
);
1564 musb_g_rx(musb
, epnum
);
1568 EXPORT_SYMBOL_GPL(musb_dma_completion
);
1574 /*-------------------------------------------------------------------------*/
1577 musb_mode_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1579 struct musb
*musb
= dev_to_musb(dev
);
1580 unsigned long flags
;
1583 spin_lock_irqsave(&musb
->lock
, flags
);
1584 ret
= sprintf(buf
, "%s\n", usb_otg_state_string(musb
->xceiv
->state
));
1585 spin_unlock_irqrestore(&musb
->lock
, flags
);
1591 musb_mode_store(struct device
*dev
, struct device_attribute
*attr
,
1592 const char *buf
, size_t n
)
1594 struct musb
*musb
= dev_to_musb(dev
);
1595 unsigned long flags
;
1598 spin_lock_irqsave(&musb
->lock
, flags
);
1599 if (sysfs_streq(buf
, "host"))
1600 status
= musb_platform_set_mode(musb
, MUSB_HOST
);
1601 else if (sysfs_streq(buf
, "peripheral"))
1602 status
= musb_platform_set_mode(musb
, MUSB_PERIPHERAL
);
1603 else if (sysfs_streq(buf
, "otg"))
1604 status
= musb_platform_set_mode(musb
, MUSB_OTG
);
1607 spin_unlock_irqrestore(&musb
->lock
, flags
);
1609 return (status
== 0) ? n
: status
;
1611 static DEVICE_ATTR(mode
, 0644, musb_mode_show
, musb_mode_store
);
1614 musb_vbus_store(struct device
*dev
, struct device_attribute
*attr
,
1615 const char *buf
, size_t n
)
1617 struct musb
*musb
= dev_to_musb(dev
);
1618 unsigned long flags
;
1621 if (sscanf(buf
, "%lu", &val
) < 1) {
1622 dev_err(dev
, "Invalid VBUS timeout ms value\n");
1626 spin_lock_irqsave(&musb
->lock
, flags
);
1627 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1628 musb
->a_wait_bcon
= val
? max_t(int, val
, OTG_TIME_A_WAIT_BCON
) : 0 ;
1629 if (musb
->xceiv
->state
== OTG_STATE_A_WAIT_BCON
)
1630 musb
->is_active
= 0;
1631 musb_platform_try_idle(musb
, jiffies
+ msecs_to_jiffies(val
));
1632 spin_unlock_irqrestore(&musb
->lock
, flags
);
1638 musb_vbus_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1640 struct musb
*musb
= dev_to_musb(dev
);
1641 unsigned long flags
;
1645 spin_lock_irqsave(&musb
->lock
, flags
);
1646 val
= musb
->a_wait_bcon
;
1647 /* FIXME get_vbus_status() is normally #defined as false...
1648 * and is effectively TUSB-specific.
1650 vbus
= musb_platform_get_vbus_status(musb
);
1651 spin_unlock_irqrestore(&musb
->lock
, flags
);
1653 return sprintf(buf
, "Vbus %s, timeout %lu msec\n",
1654 vbus
? "on" : "off", val
);
1656 static DEVICE_ATTR(vbus
, 0644, musb_vbus_show
, musb_vbus_store
);
1658 /* Gadget drivers can't know that a host is connected so they might want
1659 * to start SRP, but users can. This allows userspace to trigger SRP.
1662 musb_srp_store(struct device
*dev
, struct device_attribute
*attr
,
1663 const char *buf
, size_t n
)
1665 struct musb
*musb
= dev_to_musb(dev
);
1668 if (sscanf(buf
, "%hu", &srp
) != 1
1670 dev_err(dev
, "SRP: Value must be 1\n");
1675 musb_g_wakeup(musb
);
1679 static DEVICE_ATTR(srp
, 0644, NULL
, musb_srp_store
);
1681 static struct attribute
*musb_attributes
[] = {
1682 &dev_attr_mode
.attr
,
1683 &dev_attr_vbus
.attr
,
1688 static const struct attribute_group musb_attr_group
= {
1689 .attrs
= musb_attributes
,
1692 /* Only used to provide driver mode change events */
1693 static void musb_irq_work(struct work_struct
*data
)
1695 struct musb
*musb
= container_of(data
, struct musb
, irq_work
);
1697 if (musb
->xceiv
->state
!= musb
->xceiv_old_state
) {
1698 musb
->xceiv_old_state
= musb
->xceiv
->state
;
1699 sysfs_notify(&musb
->controller
->kobj
, NULL
, "mode");
1703 /* --------------------------------------------------------------------------
1707 static struct musb
*allocate_instance(struct device
*dev
,
1708 struct musb_hdrc_config
*config
, void __iomem
*mbase
)
1711 struct musb_hw_ep
*ep
;
1715 musb
= devm_kzalloc(dev
, sizeof(*musb
), GFP_KERNEL
);
1719 INIT_LIST_HEAD(&musb
->control
);
1720 INIT_LIST_HEAD(&musb
->in_bulk
);
1721 INIT_LIST_HEAD(&musb
->out_bulk
);
1723 musb
->vbuserr_retry
= VBUSERR_RETRY_COUNT
;
1724 musb
->a_wait_bcon
= OTG_TIME_A_WAIT_BCON
;
1725 musb
->mregs
= mbase
;
1726 musb
->ctrl_base
= mbase
;
1727 musb
->nIrq
= -ENODEV
;
1728 musb
->config
= config
;
1729 BUG_ON(musb
->config
->num_eps
> MUSB_C_NUM_EPS
);
1730 for (epnum
= 0, ep
= musb
->endpoints
;
1731 epnum
< musb
->config
->num_eps
;
1737 musb
->controller
= dev
;
1739 ret
= musb_host_alloc(musb
);
1743 dev_set_drvdata(dev
, musb
);
1751 static void musb_free(struct musb
*musb
)
1753 /* this has multiple entry modes. it handles fault cleanup after
1754 * probe(), where things may be partially set up, as well as rmmod
1755 * cleanup after everything's been de-activated.
1759 sysfs_remove_group(&musb
->controller
->kobj
, &musb_attr_group
);
1762 if (musb
->nIrq
>= 0) {
1764 disable_irq_wake(musb
->nIrq
);
1765 free_irq(musb
->nIrq
, musb
);
1767 if (musb
->dma_controller
)
1768 dma_controller_destroy(musb
->dma_controller
);
1770 musb_host_free(musb
);
1774 * Perform generic per-controller initialization.
1776 * @dev: the controller (already clocked, etc)
1778 * @ctrl: virtual address of controller registers,
1779 * not yet corrected for platform-specific offsets
1782 musb_init_controller(struct device
*dev
, int nIrq
, void __iomem
*ctrl
)
1786 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
1788 /* The driver might handle more features than the board; OK.
1789 * Fail when the board needs a feature that's not enabled.
1792 dev_dbg(dev
, "no platform_data?\n");
1798 musb
= allocate_instance(dev
, plat
->config
, ctrl
);
1804 pm_runtime_use_autosuspend(musb
->controller
);
1805 pm_runtime_set_autosuspend_delay(musb
->controller
, 200);
1806 pm_runtime_enable(musb
->controller
);
1808 spin_lock_init(&musb
->lock
);
1809 musb
->board_set_power
= plat
->set_power
;
1810 musb
->min_power
= plat
->min_power
;
1811 musb
->ops
= plat
->platform_ops
;
1812 musb
->port_mode
= plat
->mode
;
1814 /* The musb_platform_init() call:
1815 * - adjusts musb->mregs
1816 * - sets the musb->isr
1817 * - may initialize an integrated tranceiver
1818 * - initializes musb->xceiv, usually by otg_get_phy()
1819 * - stops powering VBUS
1821 * There are various transceiver configurations. Blackfin,
1822 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1823 * external/discrete ones in various flavors (twl4030 family,
1824 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1826 status
= musb_platform_init(musb
);
1835 if (!musb
->xceiv
->io_ops
) {
1836 musb
->xceiv
->io_dev
= musb
->controller
;
1837 musb
->xceiv
->io_priv
= musb
->mregs
;
1838 musb
->xceiv
->io_ops
= &musb_ulpi_access
;
1841 pm_runtime_get_sync(musb
->controller
);
1843 if (use_dma
&& dev
->dma_mask
)
1844 musb
->dma_controller
= dma_controller_create(musb
, musb
->mregs
);
1846 /* ideally this would be abstracted in platform setup */
1847 if (!musb
->dma_controller
)
1848 dev
->dma_mask
= NULL
;
1850 /* be sure interrupts are disabled before connecting ISR */
1851 musb_platform_disable(musb
);
1852 musb_generic_disable(musb
);
1854 /* setup musb parts of the core (especially endpoints) */
1855 status
= musb_core_init(plat
->config
->multipoint
1856 ? MUSB_CONTROLLER_MHDRC
1857 : MUSB_CONTROLLER_HDRC
, musb
);
1861 setup_timer(&musb
->otg_timer
, musb_otg_timer_func
, (unsigned long) musb
);
1863 /* Init IRQ workqueue before request_irq */
1864 INIT_WORK(&musb
->irq_work
, musb_irq_work
);
1866 /* attach to the IRQ */
1867 if (request_irq(nIrq
, musb
->isr
, 0, dev_name(dev
), musb
)) {
1868 dev_err(dev
, "request_irq %d failed!\n", nIrq
);
1873 /* FIXME this handles wakeup irqs wrong */
1874 if (enable_irq_wake(nIrq
) == 0) {
1876 device_init_wakeup(dev
, 1);
1881 /* program PHY to use external vBus if required */
1882 if (plat
->extvbus
) {
1883 u8 busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
1884 busctl
|= MUSB_ULPI_USE_EXTVBUS
;
1885 musb_write_ulpi_buscontrol(musb
->mregs
, busctl
);
1888 if (musb
->xceiv
->otg
->default_a
) {
1889 MUSB_HST_MODE(musb
);
1890 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
1892 MUSB_DEV_MODE(musb
);
1893 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1896 switch (musb
->port_mode
) {
1897 case MUSB_PORT_MODE_HOST
:
1898 status
= musb_host_setup(musb
, plat
->power
);
1900 case MUSB_PORT_MODE_GADGET
:
1901 status
= musb_gadget_setup(musb
);
1903 case MUSB_PORT_MODE_DUAL_ROLE
:
1904 status
= musb_host_setup(musb
, plat
->power
);
1907 status
= musb_gadget_setup(musb
);
1910 dev_err(dev
, "unsupported port mode %d\n", musb
->port_mode
);
1917 status
= musb_init_debugfs(musb
);
1921 status
= sysfs_create_group(&musb
->controller
->kobj
, &musb_attr_group
);
1925 pm_runtime_put(musb
->controller
);
1930 musb_exit_debugfs(musb
);
1933 musb_gadget_cleanup(musb
);
1936 pm_runtime_put_sync(musb
->controller
);
1940 device_init_wakeup(dev
, 0);
1941 musb_platform_exit(musb
);
1944 pm_runtime_disable(musb
->controller
);
1945 dev_err(musb
->controller
,
1946 "musb_init_controller failed with status %d\n", status
);
1956 /*-------------------------------------------------------------------------*/
1958 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
1959 * bridge to a platform device; this driver then suffices.
1961 static int musb_probe(struct platform_device
*pdev
)
1963 struct device
*dev
= &pdev
->dev
;
1964 int irq
= platform_get_irq_byname(pdev
, "mc");
1965 struct resource
*iomem
;
1968 iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1969 if (!iomem
|| irq
<= 0)
1972 base
= devm_ioremap_resource(dev
, iomem
);
1974 return PTR_ERR(base
);
1976 return musb_init_controller(dev
, irq
, base
);
1979 static int musb_remove(struct platform_device
*pdev
)
1981 struct device
*dev
= &pdev
->dev
;
1982 struct musb
*musb
= dev_to_musb(dev
);
1984 /* this gets called on rmmod.
1985 * - Host mode: host may still be active
1986 * - Peripheral mode: peripheral is deactivated (or never-activated)
1987 * - OTG mode: both roles are deactivated (or never-activated)
1989 musb_exit_debugfs(musb
);
1990 musb_shutdown(pdev
);
1993 device_init_wakeup(dev
, 0);
1994 #ifndef CONFIG_MUSB_PIO_ONLY
1995 dma_set_mask(dev
, *dev
->parent
->dma_mask
);
2002 static void musb_save_context(struct musb
*musb
)
2005 void __iomem
*musb_base
= musb
->mregs
;
2008 musb
->context
.frame
= musb_readw(musb_base
, MUSB_FRAME
);
2009 musb
->context
.testmode
= musb_readb(musb_base
, MUSB_TESTMODE
);
2010 musb
->context
.busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
2011 musb
->context
.power
= musb_readb(musb_base
, MUSB_POWER
);
2012 musb
->context
.intrusbe
= musb_readb(musb_base
, MUSB_INTRUSBE
);
2013 musb
->context
.index
= musb_readb(musb_base
, MUSB_INDEX
);
2014 musb
->context
.devctl
= musb_readb(musb_base
, MUSB_DEVCTL
);
2016 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2017 struct musb_hw_ep
*hw_ep
;
2019 hw_ep
= &musb
->endpoints
[i
];
2027 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2028 musb
->context
.index_regs
[i
].txmaxp
=
2029 musb_readw(epio
, MUSB_TXMAXP
);
2030 musb
->context
.index_regs
[i
].txcsr
=
2031 musb_readw(epio
, MUSB_TXCSR
);
2032 musb
->context
.index_regs
[i
].rxmaxp
=
2033 musb_readw(epio
, MUSB_RXMAXP
);
2034 musb
->context
.index_regs
[i
].rxcsr
=
2035 musb_readw(epio
, MUSB_RXCSR
);
2037 if (musb
->dyn_fifo
) {
2038 musb
->context
.index_regs
[i
].txfifoadd
=
2039 musb_read_txfifoadd(musb_base
);
2040 musb
->context
.index_regs
[i
].rxfifoadd
=
2041 musb_read_rxfifoadd(musb_base
);
2042 musb
->context
.index_regs
[i
].txfifosz
=
2043 musb_read_txfifosz(musb_base
);
2044 musb
->context
.index_regs
[i
].rxfifosz
=
2045 musb_read_rxfifosz(musb_base
);
2048 musb
->context
.index_regs
[i
].txtype
=
2049 musb_readb(epio
, MUSB_TXTYPE
);
2050 musb
->context
.index_regs
[i
].txinterval
=
2051 musb_readb(epio
, MUSB_TXINTERVAL
);
2052 musb
->context
.index_regs
[i
].rxtype
=
2053 musb_readb(epio
, MUSB_RXTYPE
);
2054 musb
->context
.index_regs
[i
].rxinterval
=
2055 musb_readb(epio
, MUSB_RXINTERVAL
);
2057 musb
->context
.index_regs
[i
].txfunaddr
=
2058 musb_read_txfunaddr(musb_base
, i
);
2059 musb
->context
.index_regs
[i
].txhubaddr
=
2060 musb_read_txhubaddr(musb_base
, i
);
2061 musb
->context
.index_regs
[i
].txhubport
=
2062 musb_read_txhubport(musb_base
, i
);
2064 musb
->context
.index_regs
[i
].rxfunaddr
=
2065 musb_read_rxfunaddr(musb_base
, i
);
2066 musb
->context
.index_regs
[i
].rxhubaddr
=
2067 musb_read_rxhubaddr(musb_base
, i
);
2068 musb
->context
.index_regs
[i
].rxhubport
=
2069 musb_read_rxhubport(musb_base
, i
);
2073 static void musb_restore_context(struct musb
*musb
)
2076 void __iomem
*musb_base
= musb
->mregs
;
2077 void __iomem
*ep_target_regs
;
2080 musb_writew(musb_base
, MUSB_FRAME
, musb
->context
.frame
);
2081 musb_writeb(musb_base
, MUSB_TESTMODE
, musb
->context
.testmode
);
2082 musb_write_ulpi_buscontrol(musb
->mregs
, musb
->context
.busctl
);
2083 musb_writeb(musb_base
, MUSB_POWER
, musb
->context
.power
);
2084 musb_writew(musb_base
, MUSB_INTRTXE
, musb
->intrtxe
);
2085 musb_writew(musb_base
, MUSB_INTRRXE
, musb
->intrrxe
);
2086 musb_writeb(musb_base
, MUSB_INTRUSBE
, musb
->context
.intrusbe
);
2087 musb_writeb(musb_base
, MUSB_DEVCTL
, musb
->context
.devctl
);
2089 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2090 struct musb_hw_ep
*hw_ep
;
2092 hw_ep
= &musb
->endpoints
[i
];
2100 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2101 musb_writew(epio
, MUSB_TXMAXP
,
2102 musb
->context
.index_regs
[i
].txmaxp
);
2103 musb_writew(epio
, MUSB_TXCSR
,
2104 musb
->context
.index_regs
[i
].txcsr
);
2105 musb_writew(epio
, MUSB_RXMAXP
,
2106 musb
->context
.index_regs
[i
].rxmaxp
);
2107 musb_writew(epio
, MUSB_RXCSR
,
2108 musb
->context
.index_regs
[i
].rxcsr
);
2110 if (musb
->dyn_fifo
) {
2111 musb_write_txfifosz(musb_base
,
2112 musb
->context
.index_regs
[i
].txfifosz
);
2113 musb_write_rxfifosz(musb_base
,
2114 musb
->context
.index_regs
[i
].rxfifosz
);
2115 musb_write_txfifoadd(musb_base
,
2116 musb
->context
.index_regs
[i
].txfifoadd
);
2117 musb_write_rxfifoadd(musb_base
,
2118 musb
->context
.index_regs
[i
].rxfifoadd
);
2121 musb_writeb(epio
, MUSB_TXTYPE
,
2122 musb
->context
.index_regs
[i
].txtype
);
2123 musb_writeb(epio
, MUSB_TXINTERVAL
,
2124 musb
->context
.index_regs
[i
].txinterval
);
2125 musb_writeb(epio
, MUSB_RXTYPE
,
2126 musb
->context
.index_regs
[i
].rxtype
);
2127 musb_writeb(epio
, MUSB_RXINTERVAL
,
2129 musb
->context
.index_regs
[i
].rxinterval
);
2130 musb_write_txfunaddr(musb_base
, i
,
2131 musb
->context
.index_regs
[i
].txfunaddr
);
2132 musb_write_txhubaddr(musb_base
, i
,
2133 musb
->context
.index_regs
[i
].txhubaddr
);
2134 musb_write_txhubport(musb_base
, i
,
2135 musb
->context
.index_regs
[i
].txhubport
);
2138 musb_read_target_reg_base(i
, musb_base
);
2140 musb_write_rxfunaddr(ep_target_regs
,
2141 musb
->context
.index_regs
[i
].rxfunaddr
);
2142 musb_write_rxhubaddr(ep_target_regs
,
2143 musb
->context
.index_regs
[i
].rxhubaddr
);
2144 musb_write_rxhubport(ep_target_regs
,
2145 musb
->context
.index_regs
[i
].rxhubport
);
2147 musb_writeb(musb_base
, MUSB_INDEX
, musb
->context
.index
);
2150 static int musb_suspend(struct device
*dev
)
2152 struct musb
*musb
= dev_to_musb(dev
);
2153 unsigned long flags
;
2155 spin_lock_irqsave(&musb
->lock
, flags
);
2157 if (is_peripheral_active(musb
)) {
2158 /* FIXME force disconnect unless we know USB will wake
2159 * the system up quickly enough to respond ...
2161 } else if (is_host_active(musb
)) {
2162 /* we know all the children are suspended; sometimes
2163 * they will even be wakeup-enabled.
2167 spin_unlock_irqrestore(&musb
->lock
, flags
);
2171 static int musb_resume_noirq(struct device
*dev
)
2173 /* for static cmos like DaVinci, register values were preserved
2174 * unless for some reason the whole soc powered down or the USB
2175 * module got reset through the PSC (vs just being disabled).
2180 static int musb_runtime_suspend(struct device
*dev
)
2182 struct musb
*musb
= dev_to_musb(dev
);
2184 musb_save_context(musb
);
2189 static int musb_runtime_resume(struct device
*dev
)
2191 struct musb
*musb
= dev_to_musb(dev
);
2192 static int first
= 1;
2195 * When pm_runtime_get_sync called for the first time in driver
2196 * init, some of the structure is still not initialized which is
2197 * used in restore function. But clock needs to be
2198 * enabled before any register access, so
2199 * pm_runtime_get_sync has to be called.
2200 * Also context restore without save does not make
2204 musb_restore_context(musb
);
2210 static const struct dev_pm_ops musb_dev_pm_ops
= {
2211 .suspend
= musb_suspend
,
2212 .resume_noirq
= musb_resume_noirq
,
2213 .runtime_suspend
= musb_runtime_suspend
,
2214 .runtime_resume
= musb_runtime_resume
,
2217 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2219 #define MUSB_DEV_PM_OPS NULL
2222 static struct platform_driver musb_driver
= {
2224 .name
= (char *)musb_driver_name
,
2225 .bus
= &platform_bus_type
,
2226 .owner
= THIS_MODULE
,
2227 .pm
= MUSB_DEV_PM_OPS
,
2229 .probe
= musb_probe
,
2230 .remove
= musb_remove
,
2231 .shutdown
= musb_shutdown
,
2234 /*-------------------------------------------------------------------------*/
2236 static int __init
musb_init(void)
2241 return platform_driver_register(&musb_driver
);
2243 module_init(musb_init
);
2245 static void __exit
musb_cleanup(void)
2247 platform_driver_unregister(&musb_driver
);
2249 module_exit(musb_cleanup
);