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usb: musb: use dev_get_platdata()
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
102 #include <linux/idr.h>
103 #include <linux/dma-mapping.h>
104
105 #include "musb_core.h"
106
107 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108
109
110 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112
113 #define MUSB_VERSION "6.0"
114
115 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116
117 #define MUSB_DRIVER_NAME "musb-hdrc"
118 const char musb_driver_name[] = MUSB_DRIVER_NAME;
119
120 MODULE_DESCRIPTION(DRIVER_INFO);
121 MODULE_AUTHOR(DRIVER_AUTHOR);
122 MODULE_LICENSE("GPL");
123 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124
125
126 /*-------------------------------------------------------------------------*/
127
128 static inline struct musb *dev_to_musb(struct device *dev)
129 {
130 return dev_get_drvdata(dev);
131 }
132
133 /*-------------------------------------------------------------------------*/
134
135 #ifndef CONFIG_BLACKFIN
136 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
137 {
138 void __iomem *addr = phy->io_priv;
139 int i = 0;
140 u8 r;
141 u8 power;
142 int ret;
143
144 pm_runtime_get_sync(phy->io_dev);
145
146 /* Make sure the transceiver is not in low power mode */
147 power = musb_readb(addr, MUSB_POWER);
148 power &= ~MUSB_POWER_SUSPENDM;
149 musb_writeb(addr, MUSB_POWER, power);
150
151 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
152 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 */
154
155 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
156 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
157 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
158
159 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
160 & MUSB_ULPI_REG_CMPLT)) {
161 i++;
162 if (i == 10000) {
163 ret = -ETIMEDOUT;
164 goto out;
165 }
166
167 }
168 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
169 r &= ~MUSB_ULPI_REG_CMPLT;
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
171
172 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173
174 out:
175 pm_runtime_put(phy->io_dev);
176
177 return ret;
178 }
179
180 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
181 {
182 void __iomem *addr = phy->io_priv;
183 int i = 0;
184 u8 r = 0;
185 u8 power;
186 int ret = 0;
187
188 pm_runtime_get_sync(phy->io_dev);
189
190 /* Make sure the transceiver is not in low power mode */
191 power = musb_readb(addr, MUSB_POWER);
192 power &= ~MUSB_POWER_SUSPENDM;
193 musb_writeb(addr, MUSB_POWER, power);
194
195 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
196 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
197 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198
199 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
200 & MUSB_ULPI_REG_CMPLT)) {
201 i++;
202 if (i == 10000) {
203 ret = -ETIMEDOUT;
204 goto out;
205 }
206 }
207
208 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
209 r &= ~MUSB_ULPI_REG_CMPLT;
210 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
211
212 out:
213 pm_runtime_put(phy->io_dev);
214
215 return ret;
216 }
217 #else
218 #define musb_ulpi_read NULL
219 #define musb_ulpi_write NULL
220 #endif
221
222 static struct usb_phy_io_ops musb_ulpi_access = {
223 .read = musb_ulpi_read,
224 .write = musb_ulpi_write,
225 };
226
227 /*-------------------------------------------------------------------------*/
228
229 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
230
231 /*
232 * Load an endpoint's FIFO
233 */
234 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
235 {
236 struct musb *musb = hw_ep->musb;
237 void __iomem *fifo = hw_ep->fifo;
238
239 if (unlikely(len == 0))
240 return;
241
242 prefetch((u8 *)src);
243
244 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
246
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
249 u16 index = 0;
250
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
253 if (len >= 4) {
254 iowrite32_rep(fifo, src + index, len >> 2);
255 index += len & ~0x03;
256 }
257 if (len & 0x02) {
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 index += 2;
260 }
261 } else {
262 if (len >= 2) {
263 iowrite16_rep(fifo, src + index, len >> 1);
264 index += len & ~0x01;
265 }
266 }
267 if (len & 0x01)
268 musb_writeb(fifo, 0, src[index]);
269 } else {
270 /* byte aligned */
271 iowrite8_rep(fifo, src, len);
272 }
273 }
274
275 #if !defined(CONFIG_USB_MUSB_AM35X)
276 /*
277 * Unload an endpoint's FIFO
278 */
279 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
280 {
281 struct musb *musb = hw_ep->musb;
282 void __iomem *fifo = hw_ep->fifo;
283
284 if (unlikely(len == 0))
285 return;
286
287 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
288 'R', hw_ep->epnum, fifo, len, dst);
289
290 /* we can't assume unaligned writes work */
291 if (likely((0x01 & (unsigned long) dst) == 0)) {
292 u16 index = 0;
293
294 /* best case is 32bit-aligned destination address */
295 if ((0x02 & (unsigned long) dst) == 0) {
296 if (len >= 4) {
297 ioread32_rep(fifo, dst, len >> 2);
298 index = len & ~0x03;
299 }
300 if (len & 0x02) {
301 *(u16 *)&dst[index] = musb_readw(fifo, 0);
302 index += 2;
303 }
304 } else {
305 if (len >= 2) {
306 ioread16_rep(fifo, dst, len >> 1);
307 index = len & ~0x01;
308 }
309 }
310 if (len & 0x01)
311 dst[index] = musb_readb(fifo, 0);
312 } else {
313 /* byte aligned */
314 ioread8_rep(fifo, dst, len);
315 }
316 }
317 #endif
318
319 #endif /* normal PIO */
320
321
322 /*-------------------------------------------------------------------------*/
323
324 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
325 static const u8 musb_test_packet[53] = {
326 /* implicit SYNC then DATA0 to start */
327
328 /* JKJKJKJK x9 */
329 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
330 /* JJKKJJKK x8 */
331 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
332 /* JJJJKKKK x8 */
333 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
334 /* JJJJJJJKKKKKKK x8 */
335 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
336 /* JJJJJJJK x8 */
337 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
338 /* JKKKKKKK x10, JK */
339 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
340
341 /* implicit CRC16 then EOP to end */
342 };
343
344 void musb_load_testpacket(struct musb *musb)
345 {
346 void __iomem *regs = musb->endpoints[0].regs;
347
348 musb_ep_select(musb->mregs, 0);
349 musb_write_fifo(musb->control_ep,
350 sizeof(musb_test_packet), musb_test_packet);
351 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
352 }
353
354 /*-------------------------------------------------------------------------*/
355
356 /*
357 * Handles OTG hnp timeouts, such as b_ase0_brst
358 */
359 static void musb_otg_timer_func(unsigned long data)
360 {
361 struct musb *musb = (struct musb *)data;
362 unsigned long flags;
363
364 spin_lock_irqsave(&musb->lock, flags);
365 switch (musb->xceiv->state) {
366 case OTG_STATE_B_WAIT_ACON:
367 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
368 musb_g_disconnect(musb);
369 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
370 musb->is_active = 0;
371 break;
372 case OTG_STATE_A_SUSPEND:
373 case OTG_STATE_A_WAIT_BCON:
374 dev_dbg(musb->controller, "HNP: %s timeout\n",
375 usb_otg_state_string(musb->xceiv->state));
376 musb_platform_set_vbus(musb, 0);
377 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
378 break;
379 default:
380 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
381 usb_otg_state_string(musb->xceiv->state));
382 }
383 spin_unlock_irqrestore(&musb->lock, flags);
384 }
385
386 /*
387 * Stops the HNP transition. Caller must take care of locking.
388 */
389 void musb_hnp_stop(struct musb *musb)
390 {
391 struct usb_hcd *hcd = musb->hcd;
392 void __iomem *mbase = musb->mregs;
393 u8 reg;
394
395 dev_dbg(musb->controller, "HNP: stop from %s\n",
396 usb_otg_state_string(musb->xceiv->state));
397
398 switch (musb->xceiv->state) {
399 case OTG_STATE_A_PERIPHERAL:
400 musb_g_disconnect(musb);
401 dev_dbg(musb->controller, "HNP: back to %s\n",
402 usb_otg_state_string(musb->xceiv->state));
403 break;
404 case OTG_STATE_B_HOST:
405 dev_dbg(musb->controller, "HNP: Disabling HR\n");
406 if (hcd)
407 hcd->self.is_b_host = 0;
408 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
409 MUSB_DEV_MODE(musb);
410 reg = musb_readb(mbase, MUSB_POWER);
411 reg |= MUSB_POWER_SUSPENDM;
412 musb_writeb(mbase, MUSB_POWER, reg);
413 /* REVISIT: Start SESSION_REQUEST here? */
414 break;
415 default:
416 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
417 usb_otg_state_string(musb->xceiv->state));
418 }
419
420 /*
421 * When returning to A state after HNP, avoid hub_port_rebounce(),
422 * which cause occasional OPT A "Did not receive reset after connect"
423 * errors.
424 */
425 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
426 }
427
428 /*
429 * Interrupt Service Routine to record USB "global" interrupts.
430 * Since these do not happen often and signify things of
431 * paramount importance, it seems OK to check them individually;
432 * the order of the tests is specified in the manual
433 *
434 * @param musb instance pointer
435 * @param int_usb register contents
436 * @param devctl
437 * @param power
438 */
439
440 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
441 u8 devctl)
442 {
443 struct usb_otg *otg = musb->xceiv->otg;
444 irqreturn_t handled = IRQ_NONE;
445
446 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
447 int_usb);
448
449 /* in host mode, the peripheral may issue remote wakeup.
450 * in peripheral mode, the host may resume the link.
451 * spurious RESUME irqs happen too, paired with SUSPEND.
452 */
453 if (int_usb & MUSB_INTR_RESUME) {
454 handled = IRQ_HANDLED;
455 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state));
456
457 if (devctl & MUSB_DEVCTL_HM) {
458 void __iomem *mbase = musb->mregs;
459 u8 power;
460
461 switch (musb->xceiv->state) {
462 case OTG_STATE_A_SUSPEND:
463 /* remote wakeup? later, GetPortStatus
464 * will stop RESUME signaling
465 */
466
467 power = musb_readb(musb->mregs, MUSB_POWER);
468 if (power & MUSB_POWER_SUSPENDM) {
469 /* spurious */
470 musb->int_usb &= ~MUSB_INTR_SUSPEND;
471 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
472 break;
473 }
474
475 power &= ~MUSB_POWER_SUSPENDM;
476 musb_writeb(mbase, MUSB_POWER,
477 power | MUSB_POWER_RESUME);
478
479 musb->port1_status |=
480 (USB_PORT_STAT_C_SUSPEND << 16)
481 | MUSB_PORT_STAT_RESUME;
482 musb->rh_timer = jiffies
483 + msecs_to_jiffies(20);
484
485 musb->xceiv->state = OTG_STATE_A_HOST;
486 musb->is_active = 1;
487 musb_host_resume_root_hub(musb);
488 break;
489 case OTG_STATE_B_WAIT_ACON:
490 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
491 musb->is_active = 1;
492 MUSB_DEV_MODE(musb);
493 break;
494 default:
495 WARNING("bogus %s RESUME (%s)\n",
496 "host",
497 usb_otg_state_string(musb->xceiv->state));
498 }
499 } else {
500 switch (musb->xceiv->state) {
501 case OTG_STATE_A_SUSPEND:
502 /* possibly DISCONNECT is upcoming */
503 musb->xceiv->state = OTG_STATE_A_HOST;
504 musb_host_resume_root_hub(musb);
505 break;
506 case OTG_STATE_B_WAIT_ACON:
507 case OTG_STATE_B_PERIPHERAL:
508 /* disconnect while suspended? we may
509 * not get a disconnect irq...
510 */
511 if ((devctl & MUSB_DEVCTL_VBUS)
512 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
513 ) {
514 musb->int_usb |= MUSB_INTR_DISCONNECT;
515 musb->int_usb &= ~MUSB_INTR_SUSPEND;
516 break;
517 }
518 musb_g_resume(musb);
519 break;
520 case OTG_STATE_B_IDLE:
521 musb->int_usb &= ~MUSB_INTR_SUSPEND;
522 break;
523 default:
524 WARNING("bogus %s RESUME (%s)\n",
525 "peripheral",
526 usb_otg_state_string(musb->xceiv->state));
527 }
528 }
529 }
530
531 /* see manual for the order of the tests */
532 if (int_usb & MUSB_INTR_SESSREQ) {
533 void __iomem *mbase = musb->mregs;
534
535 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
536 && (devctl & MUSB_DEVCTL_BDEVICE)) {
537 dev_dbg(musb->controller, "SessReq while on B state\n");
538 return IRQ_HANDLED;
539 }
540
541 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
542 usb_otg_state_string(musb->xceiv->state));
543
544 /* IRQ arrives from ID pin sense or (later, if VBUS power
545 * is removed) SRP. responses are time critical:
546 * - turn on VBUS (with silicon-specific mechanism)
547 * - go through A_WAIT_VRISE
548 * - ... to A_WAIT_BCON.
549 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
550 */
551 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
552 musb->ep0_stage = MUSB_EP0_START;
553 musb->xceiv->state = OTG_STATE_A_IDLE;
554 MUSB_HST_MODE(musb);
555 musb_platform_set_vbus(musb, 1);
556
557 handled = IRQ_HANDLED;
558 }
559
560 if (int_usb & MUSB_INTR_VBUSERROR) {
561 int ignore = 0;
562
563 /* During connection as an A-Device, we may see a short
564 * current spikes causing voltage drop, because of cable
565 * and peripheral capacitance combined with vbus draw.
566 * (So: less common with truly self-powered devices, where
567 * vbus doesn't act like a power supply.)
568 *
569 * Such spikes are short; usually less than ~500 usec, max
570 * of ~2 msec. That is, they're not sustained overcurrent
571 * errors, though they're reported using VBUSERROR irqs.
572 *
573 * Workarounds: (a) hardware: use self powered devices.
574 * (b) software: ignore non-repeated VBUS errors.
575 *
576 * REVISIT: do delays from lots of DEBUG_KERNEL checks
577 * make trouble here, keeping VBUS < 4.4V ?
578 */
579 switch (musb->xceiv->state) {
580 case OTG_STATE_A_HOST:
581 /* recovery is dicey once we've gotten past the
582 * initial stages of enumeration, but if VBUS
583 * stayed ok at the other end of the link, and
584 * another reset is due (at least for high speed,
585 * to redo the chirp etc), it might work OK...
586 */
587 case OTG_STATE_A_WAIT_BCON:
588 case OTG_STATE_A_WAIT_VRISE:
589 if (musb->vbuserr_retry) {
590 void __iomem *mbase = musb->mregs;
591
592 musb->vbuserr_retry--;
593 ignore = 1;
594 devctl |= MUSB_DEVCTL_SESSION;
595 musb_writeb(mbase, MUSB_DEVCTL, devctl);
596 } else {
597 musb->port1_status |=
598 USB_PORT_STAT_OVERCURRENT
599 | (USB_PORT_STAT_C_OVERCURRENT << 16);
600 }
601 break;
602 default:
603 break;
604 }
605
606 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
607 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
608 usb_otg_state_string(musb->xceiv->state),
609 devctl,
610 ({ char *s;
611 switch (devctl & MUSB_DEVCTL_VBUS) {
612 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
613 s = "<SessEnd"; break;
614 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
615 s = "<AValid"; break;
616 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
617 s = "<VBusValid"; break;
618 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
619 default:
620 s = "VALID"; break;
621 }; s; }),
622 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
623 musb->port1_status);
624
625 /* go through A_WAIT_VFALL then start a new session */
626 if (!ignore)
627 musb_platform_set_vbus(musb, 0);
628 handled = IRQ_HANDLED;
629 }
630
631 if (int_usb & MUSB_INTR_SUSPEND) {
632 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
633 usb_otg_state_string(musb->xceiv->state), devctl);
634 handled = IRQ_HANDLED;
635
636 switch (musb->xceiv->state) {
637 case OTG_STATE_A_PERIPHERAL:
638 /* We also come here if the cable is removed, since
639 * this silicon doesn't report ID-no-longer-grounded.
640 *
641 * We depend on T(a_wait_bcon) to shut us down, and
642 * hope users don't do anything dicey during this
643 * undesired detour through A_WAIT_BCON.
644 */
645 musb_hnp_stop(musb);
646 musb_host_resume_root_hub(musb);
647 musb_root_disconnect(musb);
648 musb_platform_try_idle(musb, jiffies
649 + msecs_to_jiffies(musb->a_wait_bcon
650 ? : OTG_TIME_A_WAIT_BCON));
651
652 break;
653 case OTG_STATE_B_IDLE:
654 if (!musb->is_active)
655 break;
656 case OTG_STATE_B_PERIPHERAL:
657 musb_g_suspend(musb);
658 musb->is_active = otg->gadget->b_hnp_enable;
659 if (musb->is_active) {
660 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
661 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
662 mod_timer(&musb->otg_timer, jiffies
663 + msecs_to_jiffies(
664 OTG_TIME_B_ASE0_BRST));
665 }
666 break;
667 case OTG_STATE_A_WAIT_BCON:
668 if (musb->a_wait_bcon != 0)
669 musb_platform_try_idle(musb, jiffies
670 + msecs_to_jiffies(musb->a_wait_bcon));
671 break;
672 case OTG_STATE_A_HOST:
673 musb->xceiv->state = OTG_STATE_A_SUSPEND;
674 musb->is_active = otg->host->b_hnp_enable;
675 break;
676 case OTG_STATE_B_HOST:
677 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
678 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
679 break;
680 default:
681 /* "should not happen" */
682 musb->is_active = 0;
683 break;
684 }
685 }
686
687 if (int_usb & MUSB_INTR_CONNECT) {
688 struct usb_hcd *hcd = musb->hcd;
689
690 handled = IRQ_HANDLED;
691 musb->is_active = 1;
692
693 musb->ep0_stage = MUSB_EP0_START;
694
695 /* flush endpoints when transitioning from Device Mode */
696 if (is_peripheral_active(musb)) {
697 /* REVISIT HNP; just force disconnect */
698 }
699 musb->intrtxe = musb->epmask;
700 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
701 musb->intrrxe = musb->epmask & 0xfffe;
702 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
703 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
704 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
705 |USB_PORT_STAT_HIGH_SPEED
706 |USB_PORT_STAT_ENABLE
707 );
708 musb->port1_status |= USB_PORT_STAT_CONNECTION
709 |(USB_PORT_STAT_C_CONNECTION << 16);
710
711 /* high vs full speed is just a guess until after reset */
712 if (devctl & MUSB_DEVCTL_LSDEV)
713 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
714
715 /* indicate new connection to OTG machine */
716 switch (musb->xceiv->state) {
717 case OTG_STATE_B_PERIPHERAL:
718 if (int_usb & MUSB_INTR_SUSPEND) {
719 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
720 int_usb &= ~MUSB_INTR_SUSPEND;
721 goto b_host;
722 } else
723 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
724 break;
725 case OTG_STATE_B_WAIT_ACON:
726 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
727 b_host:
728 musb->xceiv->state = OTG_STATE_B_HOST;
729 if (musb->hcd)
730 musb->hcd->self.is_b_host = 1;
731 del_timer(&musb->otg_timer);
732 break;
733 default:
734 if ((devctl & MUSB_DEVCTL_VBUS)
735 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
736 musb->xceiv->state = OTG_STATE_A_HOST;
737 if (hcd)
738 hcd->self.is_b_host = 0;
739 }
740 break;
741 }
742
743 musb_host_poke_root_hub(musb);
744
745 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
746 usb_otg_state_string(musb->xceiv->state), devctl);
747 }
748
749 if (int_usb & MUSB_INTR_DISCONNECT) {
750 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
751 usb_otg_state_string(musb->xceiv->state),
752 MUSB_MODE(musb), devctl);
753 handled = IRQ_HANDLED;
754
755 switch (musb->xceiv->state) {
756 case OTG_STATE_A_HOST:
757 case OTG_STATE_A_SUSPEND:
758 musb_host_resume_root_hub(musb);
759 musb_root_disconnect(musb);
760 if (musb->a_wait_bcon != 0)
761 musb_platform_try_idle(musb, jiffies
762 + msecs_to_jiffies(musb->a_wait_bcon));
763 break;
764 case OTG_STATE_B_HOST:
765 /* REVISIT this behaves for "real disconnect"
766 * cases; make sure the other transitions from
767 * from B_HOST act right too. The B_HOST code
768 * in hnp_stop() is currently not used...
769 */
770 musb_root_disconnect(musb);
771 if (musb->hcd)
772 musb->hcd->self.is_b_host = 0;
773 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
774 MUSB_DEV_MODE(musb);
775 musb_g_disconnect(musb);
776 break;
777 case OTG_STATE_A_PERIPHERAL:
778 musb_hnp_stop(musb);
779 musb_root_disconnect(musb);
780 /* FALLTHROUGH */
781 case OTG_STATE_B_WAIT_ACON:
782 /* FALLTHROUGH */
783 case OTG_STATE_B_PERIPHERAL:
784 case OTG_STATE_B_IDLE:
785 musb_g_disconnect(musb);
786 break;
787 default:
788 WARNING("unhandled DISCONNECT transition (%s)\n",
789 usb_otg_state_string(musb->xceiv->state));
790 break;
791 }
792 }
793
794 /* mentor saves a bit: bus reset and babble share the same irq.
795 * only host sees babble; only peripheral sees bus reset.
796 */
797 if (int_usb & MUSB_INTR_RESET) {
798 handled = IRQ_HANDLED;
799 if ((devctl & MUSB_DEVCTL_HM) != 0) {
800 /*
801 * Looks like non-HS BABBLE can be ignored, but
802 * HS BABBLE is an error condition. For HS the solution
803 * is to avoid babble in the first place and fix what
804 * caused BABBLE. When HS BABBLE happens we can only
805 * stop the session.
806 */
807 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
808 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
809 else {
810 ERR("Stopping host session -- babble\n");
811 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
812 }
813 } else {
814 dev_dbg(musb->controller, "BUS RESET as %s\n",
815 usb_otg_state_string(musb->xceiv->state));
816 switch (musb->xceiv->state) {
817 case OTG_STATE_A_SUSPEND:
818 musb_g_reset(musb);
819 /* FALLTHROUGH */
820 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
821 /* never use invalid T(a_wait_bcon) */
822 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
823 usb_otg_state_string(musb->xceiv->state),
824 TA_WAIT_BCON(musb));
825 mod_timer(&musb->otg_timer, jiffies
826 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
827 break;
828 case OTG_STATE_A_PERIPHERAL:
829 del_timer(&musb->otg_timer);
830 musb_g_reset(musb);
831 break;
832 case OTG_STATE_B_WAIT_ACON:
833 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
834 usb_otg_state_string(musb->xceiv->state));
835 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
836 musb_g_reset(musb);
837 break;
838 case OTG_STATE_B_IDLE:
839 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
840 /* FALLTHROUGH */
841 case OTG_STATE_B_PERIPHERAL:
842 musb_g_reset(musb);
843 break;
844 default:
845 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
846 usb_otg_state_string(musb->xceiv->state));
847 }
848 }
849 }
850
851 #if 0
852 /* REVISIT ... this would be for multiplexing periodic endpoints, or
853 * supporting transfer phasing to prevent exceeding ISO bandwidth
854 * limits of a given frame or microframe.
855 *
856 * It's not needed for peripheral side, which dedicates endpoints;
857 * though it _might_ use SOF irqs for other purposes.
858 *
859 * And it's not currently needed for host side, which also dedicates
860 * endpoints, relies on TX/RX interval registers, and isn't claimed
861 * to support ISO transfers yet.
862 */
863 if (int_usb & MUSB_INTR_SOF) {
864 void __iomem *mbase = musb->mregs;
865 struct musb_hw_ep *ep;
866 u8 epnum;
867 u16 frame;
868
869 dev_dbg(musb->controller, "START_OF_FRAME\n");
870 handled = IRQ_HANDLED;
871
872 /* start any periodic Tx transfers waiting for current frame */
873 frame = musb_readw(mbase, MUSB_FRAME);
874 ep = musb->endpoints;
875 for (epnum = 1; (epnum < musb->nr_endpoints)
876 && (musb->epmask >= (1 << epnum));
877 epnum++, ep++) {
878 /*
879 * FIXME handle framecounter wraps (12 bits)
880 * eliminate duplicated StartUrb logic
881 */
882 if (ep->dwWaitFrame >= frame) {
883 ep->dwWaitFrame = 0;
884 pr_debug("SOF --> periodic TX%s on %d\n",
885 ep->tx_channel ? " DMA" : "",
886 epnum);
887 if (!ep->tx_channel)
888 musb_h_tx_start(musb, epnum);
889 else
890 cppi_hostdma_start(musb, epnum);
891 }
892 } /* end of for loop */
893 }
894 #endif
895
896 schedule_work(&musb->irq_work);
897
898 return handled;
899 }
900
901 /*-------------------------------------------------------------------------*/
902
903 static void musb_generic_disable(struct musb *musb)
904 {
905 void __iomem *mbase = musb->mregs;
906 u16 temp;
907
908 /* disable interrupts */
909 musb_writeb(mbase, MUSB_INTRUSBE, 0);
910 musb->intrtxe = 0;
911 musb_writew(mbase, MUSB_INTRTXE, 0);
912 musb->intrrxe = 0;
913 musb_writew(mbase, MUSB_INTRRXE, 0);
914
915 /* off */
916 musb_writeb(mbase, MUSB_DEVCTL, 0);
917
918 /* flush pending interrupts */
919 temp = musb_readb(mbase, MUSB_INTRUSB);
920 temp = musb_readw(mbase, MUSB_INTRTX);
921 temp = musb_readw(mbase, MUSB_INTRRX);
922
923 }
924
925 /*
926 * Make the HDRC stop (disable interrupts, etc.);
927 * reversible by musb_start
928 * called on gadget driver unregister
929 * with controller locked, irqs blocked
930 * acts as a NOP unless some role activated the hardware
931 */
932 void musb_stop(struct musb *musb)
933 {
934 /* stop IRQs, timers, ... */
935 musb_platform_disable(musb);
936 musb_generic_disable(musb);
937 dev_dbg(musb->controller, "HDRC disabled\n");
938
939 /* FIXME
940 * - mark host and/or peripheral drivers unusable/inactive
941 * - disable DMA (and enable it in HdrcStart)
942 * - make sure we can musb_start() after musb_stop(); with
943 * OTG mode, gadget driver module rmmod/modprobe cycles that
944 * - ...
945 */
946 musb_platform_try_idle(musb, 0);
947 }
948
949 static void musb_shutdown(struct platform_device *pdev)
950 {
951 struct musb *musb = dev_to_musb(&pdev->dev);
952 unsigned long flags;
953
954 pm_runtime_get_sync(musb->controller);
955
956 musb_host_cleanup(musb);
957 musb_gadget_cleanup(musb);
958
959 spin_lock_irqsave(&musb->lock, flags);
960 musb_platform_disable(musb);
961 musb_generic_disable(musb);
962 spin_unlock_irqrestore(&musb->lock, flags);
963
964 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
965 musb_platform_exit(musb);
966
967 pm_runtime_put(musb->controller);
968 /* FIXME power down */
969 }
970
971
972 /*-------------------------------------------------------------------------*/
973
974 /*
975 * The silicon either has hard-wired endpoint configurations, or else
976 * "dynamic fifo" sizing. The driver has support for both, though at this
977 * writing only the dynamic sizing is very well tested. Since we switched
978 * away from compile-time hardware parameters, we can no longer rely on
979 * dead code elimination to leave only the relevant one in the object file.
980 *
981 * We don't currently use dynamic fifo setup capability to do anything
982 * more than selecting one of a bunch of predefined configurations.
983 */
984 #if defined(CONFIG_USB_MUSB_TUSB6010) \
985 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
986 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
987 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
988 || defined(CONFIG_USB_MUSB_AM35X) \
989 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
990 || defined(CONFIG_USB_MUSB_DSPS) \
991 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
992 static ushort fifo_mode = 4;
993 #elif defined(CONFIG_USB_MUSB_UX500) \
994 || defined(CONFIG_USB_MUSB_UX500_MODULE)
995 static ushort fifo_mode = 5;
996 #else
997 static ushort fifo_mode = 2;
998 #endif
999
1000 /* "modprobe ... fifo_mode=1" etc */
1001 module_param(fifo_mode, ushort, 0);
1002 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1003
1004 /*
1005 * tables defining fifo_mode values. define more if you like.
1006 * for host side, make sure both halves of ep1 are set up.
1007 */
1008
1009 /* mode 0 - fits in 2KB */
1010 static struct musb_fifo_cfg mode_0_cfg[] = {
1011 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1012 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1013 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1014 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1015 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1016 };
1017
1018 /* mode 1 - fits in 4KB */
1019 static struct musb_fifo_cfg mode_1_cfg[] = {
1020 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1021 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1022 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1023 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1024 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1025 };
1026
1027 /* mode 2 - fits in 4KB */
1028 static struct musb_fifo_cfg mode_2_cfg[] = {
1029 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1030 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1031 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1032 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1033 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1034 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1035 };
1036
1037 /* mode 3 - fits in 4KB */
1038 static struct musb_fifo_cfg mode_3_cfg[] = {
1039 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1040 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1041 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1042 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1043 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1044 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1045 };
1046
1047 /* mode 4 - fits in 16KB */
1048 static struct musb_fifo_cfg mode_4_cfg[] = {
1049 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1050 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1051 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1052 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1053 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1054 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1055 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1056 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1057 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1058 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1059 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1060 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1061 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1062 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1063 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1064 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1065 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1066 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1067 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1068 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1069 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1070 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1071 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1072 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1073 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1074 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1075 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1076 };
1077
1078 /* mode 5 - fits in 8KB */
1079 static struct musb_fifo_cfg mode_5_cfg[] = {
1080 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1087 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1088 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1089 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1090 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1091 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1092 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1093 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1094 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1095 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1096 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1097 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1098 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1099 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1100 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1101 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1102 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1103 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1104 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1105 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1106 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1107 };
1108
1109 /*
1110 * configure a fifo; for non-shared endpoints, this may be called
1111 * once for a tx fifo and once for an rx fifo.
1112 *
1113 * returns negative errno or offset for next fifo.
1114 */
1115 static int
1116 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1117 const struct musb_fifo_cfg *cfg, u16 offset)
1118 {
1119 void __iomem *mbase = musb->mregs;
1120 int size = 0;
1121 u16 maxpacket = cfg->maxpacket;
1122 u16 c_off = offset >> 3;
1123 u8 c_size;
1124
1125 /* expect hw_ep has already been zero-initialized */
1126
1127 size = ffs(max(maxpacket, (u16) 8)) - 1;
1128 maxpacket = 1 << size;
1129
1130 c_size = size - 3;
1131 if (cfg->mode == BUF_DOUBLE) {
1132 if ((offset + (maxpacket << 1)) >
1133 (1 << (musb->config->ram_bits + 2)))
1134 return -EMSGSIZE;
1135 c_size |= MUSB_FIFOSZ_DPB;
1136 } else {
1137 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1138 return -EMSGSIZE;
1139 }
1140
1141 /* configure the FIFO */
1142 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1143
1144 /* EP0 reserved endpoint for control, bidirectional;
1145 * EP1 reserved for bulk, two unidirection halves.
1146 */
1147 if (hw_ep->epnum == 1)
1148 musb->bulk_ep = hw_ep;
1149 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1150 switch (cfg->style) {
1151 case FIFO_TX:
1152 musb_write_txfifosz(mbase, c_size);
1153 musb_write_txfifoadd(mbase, c_off);
1154 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1155 hw_ep->max_packet_sz_tx = maxpacket;
1156 break;
1157 case FIFO_RX:
1158 musb_write_rxfifosz(mbase, c_size);
1159 musb_write_rxfifoadd(mbase, c_off);
1160 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1161 hw_ep->max_packet_sz_rx = maxpacket;
1162 break;
1163 case FIFO_RXTX:
1164 musb_write_txfifosz(mbase, c_size);
1165 musb_write_txfifoadd(mbase, c_off);
1166 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1167 hw_ep->max_packet_sz_rx = maxpacket;
1168
1169 musb_write_rxfifosz(mbase, c_size);
1170 musb_write_rxfifoadd(mbase, c_off);
1171 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1172 hw_ep->max_packet_sz_tx = maxpacket;
1173
1174 hw_ep->is_shared_fifo = true;
1175 break;
1176 }
1177
1178 /* NOTE rx and tx endpoint irqs aren't managed separately,
1179 * which happens to be ok
1180 */
1181 musb->epmask |= (1 << hw_ep->epnum);
1182
1183 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1184 }
1185
1186 static struct musb_fifo_cfg ep0_cfg = {
1187 .style = FIFO_RXTX, .maxpacket = 64,
1188 };
1189
1190 static int ep_config_from_table(struct musb *musb)
1191 {
1192 const struct musb_fifo_cfg *cfg;
1193 unsigned i, n;
1194 int offset;
1195 struct musb_hw_ep *hw_ep = musb->endpoints;
1196
1197 if (musb->config->fifo_cfg) {
1198 cfg = musb->config->fifo_cfg;
1199 n = musb->config->fifo_cfg_size;
1200 goto done;
1201 }
1202
1203 switch (fifo_mode) {
1204 default:
1205 fifo_mode = 0;
1206 /* FALLTHROUGH */
1207 case 0:
1208 cfg = mode_0_cfg;
1209 n = ARRAY_SIZE(mode_0_cfg);
1210 break;
1211 case 1:
1212 cfg = mode_1_cfg;
1213 n = ARRAY_SIZE(mode_1_cfg);
1214 break;
1215 case 2:
1216 cfg = mode_2_cfg;
1217 n = ARRAY_SIZE(mode_2_cfg);
1218 break;
1219 case 3:
1220 cfg = mode_3_cfg;
1221 n = ARRAY_SIZE(mode_3_cfg);
1222 break;
1223 case 4:
1224 cfg = mode_4_cfg;
1225 n = ARRAY_SIZE(mode_4_cfg);
1226 break;
1227 case 5:
1228 cfg = mode_5_cfg;
1229 n = ARRAY_SIZE(mode_5_cfg);
1230 break;
1231 }
1232
1233 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1234 musb_driver_name, fifo_mode);
1235
1236
1237 done:
1238 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1239 /* assert(offset > 0) */
1240
1241 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1242 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1243 */
1244
1245 for (i = 0; i < n; i++) {
1246 u8 epn = cfg->hw_ep_num;
1247
1248 if (epn >= musb->config->num_eps) {
1249 pr_debug("%s: invalid ep %d\n",
1250 musb_driver_name, epn);
1251 return -EINVAL;
1252 }
1253 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1254 if (offset < 0) {
1255 pr_debug("%s: mem overrun, ep %d\n",
1256 musb_driver_name, epn);
1257 return offset;
1258 }
1259 epn++;
1260 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1261 }
1262
1263 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1264 musb_driver_name,
1265 n + 1, musb->config->num_eps * 2 - 1,
1266 offset, (1 << (musb->config->ram_bits + 2)));
1267
1268 if (!musb->bulk_ep) {
1269 pr_debug("%s: missing bulk\n", musb_driver_name);
1270 return -EINVAL;
1271 }
1272
1273 return 0;
1274 }
1275
1276
1277 /*
1278 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1279 * @param musb the controller
1280 */
1281 static int ep_config_from_hw(struct musb *musb)
1282 {
1283 u8 epnum = 0;
1284 struct musb_hw_ep *hw_ep;
1285 void __iomem *mbase = musb->mregs;
1286 int ret = 0;
1287
1288 dev_dbg(musb->controller, "<== static silicon ep config\n");
1289
1290 /* FIXME pick up ep0 maxpacket size */
1291
1292 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1293 musb_ep_select(mbase, epnum);
1294 hw_ep = musb->endpoints + epnum;
1295
1296 ret = musb_read_fifosize(musb, hw_ep, epnum);
1297 if (ret < 0)
1298 break;
1299
1300 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1301
1302 /* pick an RX/TX endpoint for bulk */
1303 if (hw_ep->max_packet_sz_tx < 512
1304 || hw_ep->max_packet_sz_rx < 512)
1305 continue;
1306
1307 /* REVISIT: this algorithm is lazy, we should at least
1308 * try to pick a double buffered endpoint.
1309 */
1310 if (musb->bulk_ep)
1311 continue;
1312 musb->bulk_ep = hw_ep;
1313 }
1314
1315 if (!musb->bulk_ep) {
1316 pr_debug("%s: missing bulk\n", musb_driver_name);
1317 return -EINVAL;
1318 }
1319
1320 return 0;
1321 }
1322
1323 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1324
1325 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1326 * configure endpoints, or take their config from silicon
1327 */
1328 static int musb_core_init(u16 musb_type, struct musb *musb)
1329 {
1330 u8 reg;
1331 char *type;
1332 char aInfo[90], aRevision[32], aDate[12];
1333 void __iomem *mbase = musb->mregs;
1334 int status = 0;
1335 int i;
1336
1337 /* log core options (read using indexed model) */
1338 reg = musb_read_configdata(mbase);
1339
1340 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1341 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1342 strcat(aInfo, ", dyn FIFOs");
1343 musb->dyn_fifo = true;
1344 }
1345 if (reg & MUSB_CONFIGDATA_MPRXE) {
1346 strcat(aInfo, ", bulk combine");
1347 musb->bulk_combine = true;
1348 }
1349 if (reg & MUSB_CONFIGDATA_MPTXE) {
1350 strcat(aInfo, ", bulk split");
1351 musb->bulk_split = true;
1352 }
1353 if (reg & MUSB_CONFIGDATA_HBRXE) {
1354 strcat(aInfo, ", HB-ISO Rx");
1355 musb->hb_iso_rx = true;
1356 }
1357 if (reg & MUSB_CONFIGDATA_HBTXE) {
1358 strcat(aInfo, ", HB-ISO Tx");
1359 musb->hb_iso_tx = true;
1360 }
1361 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1362 strcat(aInfo, ", SoftConn");
1363
1364 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1365 musb_driver_name, reg, aInfo);
1366
1367 aDate[0] = 0;
1368 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1369 musb->is_multipoint = 1;
1370 type = "M";
1371 } else {
1372 musb->is_multipoint = 0;
1373 type = "";
1374 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1375 printk(KERN_ERR
1376 "%s: kernel must blacklist external hubs\n",
1377 musb_driver_name);
1378 #endif
1379 }
1380
1381 /* log release info */
1382 musb->hwvers = musb_read_hwvers(mbase);
1383 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1384 MUSB_HWVERS_MINOR(musb->hwvers),
1385 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1386 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1387 musb_driver_name, type, aRevision, aDate);
1388
1389 /* configure ep0 */
1390 musb_configure_ep0(musb);
1391
1392 /* discover endpoint configuration */
1393 musb->nr_endpoints = 1;
1394 musb->epmask = 1;
1395
1396 if (musb->dyn_fifo)
1397 status = ep_config_from_table(musb);
1398 else
1399 status = ep_config_from_hw(musb);
1400
1401 if (status < 0)
1402 return status;
1403
1404 /* finish init, and print endpoint config */
1405 for (i = 0; i < musb->nr_endpoints; i++) {
1406 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1407
1408 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1409 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1410 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1411 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1412 hw_ep->fifo_sync_va =
1413 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1414
1415 if (i == 0)
1416 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1417 else
1418 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1419 #endif
1420
1421 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1422 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1423 hw_ep->rx_reinit = 1;
1424 hw_ep->tx_reinit = 1;
1425
1426 if (hw_ep->max_packet_sz_tx) {
1427 dev_dbg(musb->controller,
1428 "%s: hw_ep %d%s, %smax %d\n",
1429 musb_driver_name, i,
1430 hw_ep->is_shared_fifo ? "shared" : "tx",
1431 hw_ep->tx_double_buffered
1432 ? "doublebuffer, " : "",
1433 hw_ep->max_packet_sz_tx);
1434 }
1435 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1436 dev_dbg(musb->controller,
1437 "%s: hw_ep %d%s, %smax %d\n",
1438 musb_driver_name, i,
1439 "rx",
1440 hw_ep->rx_double_buffered
1441 ? "doublebuffer, " : "",
1442 hw_ep->max_packet_sz_rx);
1443 }
1444 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1445 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1446 }
1447
1448 return 0;
1449 }
1450
1451 /*-------------------------------------------------------------------------*/
1452
1453 /*
1454 * handle all the irqs defined by the HDRC core. for now we expect: other
1455 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1456 * will be assigned, and the irq will already have been acked.
1457 *
1458 * called in irq context with spinlock held, irqs blocked
1459 */
1460 irqreturn_t musb_interrupt(struct musb *musb)
1461 {
1462 irqreturn_t retval = IRQ_NONE;
1463 u8 devctl;
1464 int ep_num;
1465 u32 reg;
1466
1467 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1468
1469 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1470 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1471 musb->int_usb, musb->int_tx, musb->int_rx);
1472
1473 /* the core can interrupt us for multiple reasons; docs have
1474 * a generic interrupt flowchart to follow
1475 */
1476 if (musb->int_usb)
1477 retval |= musb_stage0_irq(musb, musb->int_usb,
1478 devctl);
1479
1480 /* "stage 1" is handling endpoint irqs */
1481
1482 /* handle endpoint 0 first */
1483 if (musb->int_tx & 1) {
1484 if (devctl & MUSB_DEVCTL_HM)
1485 retval |= musb_h_ep0_irq(musb);
1486 else
1487 retval |= musb_g_ep0_irq(musb);
1488 }
1489
1490 /* RX on endpoints 1-15 */
1491 reg = musb->int_rx >> 1;
1492 ep_num = 1;
1493 while (reg) {
1494 if (reg & 1) {
1495 /* musb_ep_select(musb->mregs, ep_num); */
1496 /* REVISIT just retval = ep->rx_irq(...) */
1497 retval = IRQ_HANDLED;
1498 if (devctl & MUSB_DEVCTL_HM)
1499 musb_host_rx(musb, ep_num);
1500 else
1501 musb_g_rx(musb, ep_num);
1502 }
1503
1504 reg >>= 1;
1505 ep_num++;
1506 }
1507
1508 /* TX on endpoints 1-15 */
1509 reg = musb->int_tx >> 1;
1510 ep_num = 1;
1511 while (reg) {
1512 if (reg & 1) {
1513 /* musb_ep_select(musb->mregs, ep_num); */
1514 /* REVISIT just retval |= ep->tx_irq(...) */
1515 retval = IRQ_HANDLED;
1516 if (devctl & MUSB_DEVCTL_HM)
1517 musb_host_tx(musb, ep_num);
1518 else
1519 musb_g_tx(musb, ep_num);
1520 }
1521 reg >>= 1;
1522 ep_num++;
1523 }
1524
1525 return retval;
1526 }
1527 EXPORT_SYMBOL_GPL(musb_interrupt);
1528
1529 #ifndef CONFIG_MUSB_PIO_ONLY
1530 static bool use_dma = 1;
1531
1532 /* "modprobe ... use_dma=0" etc */
1533 module_param(use_dma, bool, 0);
1534 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1535
1536 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1537 {
1538 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1539
1540 /* called with controller lock already held */
1541
1542 if (!epnum) {
1543 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1544 if (!is_cppi_enabled()) {
1545 /* endpoint 0 */
1546 if (devctl & MUSB_DEVCTL_HM)
1547 musb_h_ep0_irq(musb);
1548 else
1549 musb_g_ep0_irq(musb);
1550 }
1551 #endif
1552 } else {
1553 /* endpoints 1..15 */
1554 if (transmit) {
1555 if (devctl & MUSB_DEVCTL_HM)
1556 musb_host_tx(musb, epnum);
1557 else
1558 musb_g_tx(musb, epnum);
1559 } else {
1560 /* receive */
1561 if (devctl & MUSB_DEVCTL_HM)
1562 musb_host_rx(musb, epnum);
1563 else
1564 musb_g_rx(musb, epnum);
1565 }
1566 }
1567 }
1568 EXPORT_SYMBOL_GPL(musb_dma_completion);
1569
1570 #else
1571 #define use_dma 0
1572 #endif
1573
1574 /*-------------------------------------------------------------------------*/
1575
1576 static ssize_t
1577 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1578 {
1579 struct musb *musb = dev_to_musb(dev);
1580 unsigned long flags;
1581 int ret = -EINVAL;
1582
1583 spin_lock_irqsave(&musb->lock, flags);
1584 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state));
1585 spin_unlock_irqrestore(&musb->lock, flags);
1586
1587 return ret;
1588 }
1589
1590 static ssize_t
1591 musb_mode_store(struct device *dev, struct device_attribute *attr,
1592 const char *buf, size_t n)
1593 {
1594 struct musb *musb = dev_to_musb(dev);
1595 unsigned long flags;
1596 int status;
1597
1598 spin_lock_irqsave(&musb->lock, flags);
1599 if (sysfs_streq(buf, "host"))
1600 status = musb_platform_set_mode(musb, MUSB_HOST);
1601 else if (sysfs_streq(buf, "peripheral"))
1602 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1603 else if (sysfs_streq(buf, "otg"))
1604 status = musb_platform_set_mode(musb, MUSB_OTG);
1605 else
1606 status = -EINVAL;
1607 spin_unlock_irqrestore(&musb->lock, flags);
1608
1609 return (status == 0) ? n : status;
1610 }
1611 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1612
1613 static ssize_t
1614 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1615 const char *buf, size_t n)
1616 {
1617 struct musb *musb = dev_to_musb(dev);
1618 unsigned long flags;
1619 unsigned long val;
1620
1621 if (sscanf(buf, "%lu", &val) < 1) {
1622 dev_err(dev, "Invalid VBUS timeout ms value\n");
1623 return -EINVAL;
1624 }
1625
1626 spin_lock_irqsave(&musb->lock, flags);
1627 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1628 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1629 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1630 musb->is_active = 0;
1631 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1632 spin_unlock_irqrestore(&musb->lock, flags);
1633
1634 return n;
1635 }
1636
1637 static ssize_t
1638 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1639 {
1640 struct musb *musb = dev_to_musb(dev);
1641 unsigned long flags;
1642 unsigned long val;
1643 int vbus;
1644
1645 spin_lock_irqsave(&musb->lock, flags);
1646 val = musb->a_wait_bcon;
1647 /* FIXME get_vbus_status() is normally #defined as false...
1648 * and is effectively TUSB-specific.
1649 */
1650 vbus = musb_platform_get_vbus_status(musb);
1651 spin_unlock_irqrestore(&musb->lock, flags);
1652
1653 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1654 vbus ? "on" : "off", val);
1655 }
1656 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1657
1658 /* Gadget drivers can't know that a host is connected so they might want
1659 * to start SRP, but users can. This allows userspace to trigger SRP.
1660 */
1661 static ssize_t
1662 musb_srp_store(struct device *dev, struct device_attribute *attr,
1663 const char *buf, size_t n)
1664 {
1665 struct musb *musb = dev_to_musb(dev);
1666 unsigned short srp;
1667
1668 if (sscanf(buf, "%hu", &srp) != 1
1669 || (srp != 1)) {
1670 dev_err(dev, "SRP: Value must be 1\n");
1671 return -EINVAL;
1672 }
1673
1674 if (srp == 1)
1675 musb_g_wakeup(musb);
1676
1677 return n;
1678 }
1679 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1680
1681 static struct attribute *musb_attributes[] = {
1682 &dev_attr_mode.attr,
1683 &dev_attr_vbus.attr,
1684 &dev_attr_srp.attr,
1685 NULL
1686 };
1687
1688 static const struct attribute_group musb_attr_group = {
1689 .attrs = musb_attributes,
1690 };
1691
1692 /* Only used to provide driver mode change events */
1693 static void musb_irq_work(struct work_struct *data)
1694 {
1695 struct musb *musb = container_of(data, struct musb, irq_work);
1696
1697 if (musb->xceiv->state != musb->xceiv_old_state) {
1698 musb->xceiv_old_state = musb->xceiv->state;
1699 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1700 }
1701 }
1702
1703 /* --------------------------------------------------------------------------
1704 * Init support
1705 */
1706
1707 static struct musb *allocate_instance(struct device *dev,
1708 struct musb_hdrc_config *config, void __iomem *mbase)
1709 {
1710 struct musb *musb;
1711 struct musb_hw_ep *ep;
1712 int epnum;
1713 int ret;
1714
1715 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1716 if (!musb)
1717 return NULL;
1718
1719 INIT_LIST_HEAD(&musb->control);
1720 INIT_LIST_HEAD(&musb->in_bulk);
1721 INIT_LIST_HEAD(&musb->out_bulk);
1722
1723 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1724 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1725 musb->mregs = mbase;
1726 musb->ctrl_base = mbase;
1727 musb->nIrq = -ENODEV;
1728 musb->config = config;
1729 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1730 for (epnum = 0, ep = musb->endpoints;
1731 epnum < musb->config->num_eps;
1732 epnum++, ep++) {
1733 ep->musb = musb;
1734 ep->epnum = epnum;
1735 }
1736
1737 musb->controller = dev;
1738
1739 ret = musb_host_alloc(musb);
1740 if (ret < 0)
1741 goto err_free;
1742
1743 dev_set_drvdata(dev, musb);
1744
1745 return musb;
1746
1747 err_free:
1748 return NULL;
1749 }
1750
1751 static void musb_free(struct musb *musb)
1752 {
1753 /* this has multiple entry modes. it handles fault cleanup after
1754 * probe(), where things may be partially set up, as well as rmmod
1755 * cleanup after everything's been de-activated.
1756 */
1757
1758 #ifdef CONFIG_SYSFS
1759 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1760 #endif
1761
1762 if (musb->nIrq >= 0) {
1763 if (musb->irq_wake)
1764 disable_irq_wake(musb->nIrq);
1765 free_irq(musb->nIrq, musb);
1766 }
1767 if (musb->dma_controller)
1768 dma_controller_destroy(musb->dma_controller);
1769
1770 musb_host_free(musb);
1771 }
1772
1773 /*
1774 * Perform generic per-controller initialization.
1775 *
1776 * @dev: the controller (already clocked, etc)
1777 * @nIrq: IRQ number
1778 * @ctrl: virtual address of controller registers,
1779 * not yet corrected for platform-specific offsets
1780 */
1781 static int
1782 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1783 {
1784 int status;
1785 struct musb *musb;
1786 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1787
1788 /* The driver might handle more features than the board; OK.
1789 * Fail when the board needs a feature that's not enabled.
1790 */
1791 if (!plat) {
1792 dev_dbg(dev, "no platform_data?\n");
1793 status = -ENODEV;
1794 goto fail0;
1795 }
1796
1797 /* allocate */
1798 musb = allocate_instance(dev, plat->config, ctrl);
1799 if (!musb) {
1800 status = -ENOMEM;
1801 goto fail0;
1802 }
1803
1804 pm_runtime_use_autosuspend(musb->controller);
1805 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1806 pm_runtime_enable(musb->controller);
1807
1808 spin_lock_init(&musb->lock);
1809 musb->board_set_power = plat->set_power;
1810 musb->min_power = plat->min_power;
1811 musb->ops = plat->platform_ops;
1812 musb->port_mode = plat->mode;
1813
1814 /* The musb_platform_init() call:
1815 * - adjusts musb->mregs
1816 * - sets the musb->isr
1817 * - may initialize an integrated tranceiver
1818 * - initializes musb->xceiv, usually by otg_get_phy()
1819 * - stops powering VBUS
1820 *
1821 * There are various transceiver configurations. Blackfin,
1822 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1823 * external/discrete ones in various flavors (twl4030 family,
1824 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1825 */
1826 status = musb_platform_init(musb);
1827 if (status < 0)
1828 goto fail1;
1829
1830 if (!musb->isr) {
1831 status = -ENODEV;
1832 goto fail2;
1833 }
1834
1835 if (!musb->xceiv->io_ops) {
1836 musb->xceiv->io_dev = musb->controller;
1837 musb->xceiv->io_priv = musb->mregs;
1838 musb->xceiv->io_ops = &musb_ulpi_access;
1839 }
1840
1841 pm_runtime_get_sync(musb->controller);
1842
1843 if (use_dma && dev->dma_mask)
1844 musb->dma_controller = dma_controller_create(musb, musb->mregs);
1845
1846 /* be sure interrupts are disabled before connecting ISR */
1847 musb_platform_disable(musb);
1848 musb_generic_disable(musb);
1849
1850 /* setup musb parts of the core (especially endpoints) */
1851 status = musb_core_init(plat->config->multipoint
1852 ? MUSB_CONTROLLER_MHDRC
1853 : MUSB_CONTROLLER_HDRC, musb);
1854 if (status < 0)
1855 goto fail3;
1856
1857 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1858
1859 /* Init IRQ workqueue before request_irq */
1860 INIT_WORK(&musb->irq_work, musb_irq_work);
1861
1862 /* attach to the IRQ */
1863 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1864 dev_err(dev, "request_irq %d failed!\n", nIrq);
1865 status = -ENODEV;
1866 goto fail3;
1867 }
1868 musb->nIrq = nIrq;
1869 /* FIXME this handles wakeup irqs wrong */
1870 if (enable_irq_wake(nIrq) == 0) {
1871 musb->irq_wake = 1;
1872 device_init_wakeup(dev, 1);
1873 } else {
1874 musb->irq_wake = 0;
1875 }
1876
1877 /* program PHY to use external vBus if required */
1878 if (plat->extvbus) {
1879 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1880 busctl |= MUSB_ULPI_USE_EXTVBUS;
1881 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1882 }
1883
1884 if (musb->xceiv->otg->default_a) {
1885 MUSB_HST_MODE(musb);
1886 musb->xceiv->state = OTG_STATE_A_IDLE;
1887 } else {
1888 MUSB_DEV_MODE(musb);
1889 musb->xceiv->state = OTG_STATE_B_IDLE;
1890 }
1891
1892 switch (musb->port_mode) {
1893 case MUSB_PORT_MODE_HOST:
1894 status = musb_host_setup(musb, plat->power);
1895 break;
1896 case MUSB_PORT_MODE_GADGET:
1897 status = musb_gadget_setup(musb);
1898 break;
1899 case MUSB_PORT_MODE_DUAL_ROLE:
1900 status = musb_host_setup(musb, plat->power);
1901 if (status < 0)
1902 goto fail3;
1903 status = musb_gadget_setup(musb);
1904 break;
1905 default:
1906 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
1907 break;
1908 }
1909
1910 if (status < 0)
1911 goto fail3;
1912
1913 status = musb_init_debugfs(musb);
1914 if (status < 0)
1915 goto fail4;
1916
1917 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
1918 if (status)
1919 goto fail5;
1920
1921 pm_runtime_put(musb->controller);
1922
1923 return 0;
1924
1925 fail5:
1926 musb_exit_debugfs(musb);
1927
1928 fail4:
1929 musb_gadget_cleanup(musb);
1930
1931 fail3:
1932 if (musb->dma_controller)
1933 dma_controller_destroy(musb->dma_controller);
1934 pm_runtime_put_sync(musb->controller);
1935
1936 fail2:
1937 if (musb->irq_wake)
1938 device_init_wakeup(dev, 0);
1939 musb_platform_exit(musb);
1940
1941 fail1:
1942 pm_runtime_disable(musb->controller);
1943 dev_err(musb->controller,
1944 "musb_init_controller failed with status %d\n", status);
1945
1946 musb_free(musb);
1947
1948 fail0:
1949
1950 return status;
1951
1952 }
1953
1954 /*-------------------------------------------------------------------------*/
1955
1956 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
1957 * bridge to a platform device; this driver then suffices.
1958 */
1959 static int musb_probe(struct platform_device *pdev)
1960 {
1961 struct device *dev = &pdev->dev;
1962 int irq = platform_get_irq_byname(pdev, "mc");
1963 struct resource *iomem;
1964 void __iomem *base;
1965
1966 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1967 if (!iomem || irq <= 0)
1968 return -ENODEV;
1969
1970 base = devm_ioremap_resource(dev, iomem);
1971 if (IS_ERR(base))
1972 return PTR_ERR(base);
1973
1974 return musb_init_controller(dev, irq, base);
1975 }
1976
1977 static int musb_remove(struct platform_device *pdev)
1978 {
1979 struct device *dev = &pdev->dev;
1980 struct musb *musb = dev_to_musb(dev);
1981
1982 /* this gets called on rmmod.
1983 * - Host mode: host may still be active
1984 * - Peripheral mode: peripheral is deactivated (or never-activated)
1985 * - OTG mode: both roles are deactivated (or never-activated)
1986 */
1987 musb_exit_debugfs(musb);
1988 musb_shutdown(pdev);
1989
1990 musb_free(musb);
1991 device_init_wakeup(dev, 0);
1992 return 0;
1993 }
1994
1995 #ifdef CONFIG_PM
1996
1997 static void musb_save_context(struct musb *musb)
1998 {
1999 int i;
2000 void __iomem *musb_base = musb->mregs;
2001 void __iomem *epio;
2002
2003 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2004 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2005 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2006 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2007 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2008 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2009 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2010
2011 for (i = 0; i < musb->config->num_eps; ++i) {
2012 struct musb_hw_ep *hw_ep;
2013
2014 hw_ep = &musb->endpoints[i];
2015 if (!hw_ep)
2016 continue;
2017
2018 epio = hw_ep->regs;
2019 if (!epio)
2020 continue;
2021
2022 musb_writeb(musb_base, MUSB_INDEX, i);
2023 musb->context.index_regs[i].txmaxp =
2024 musb_readw(epio, MUSB_TXMAXP);
2025 musb->context.index_regs[i].txcsr =
2026 musb_readw(epio, MUSB_TXCSR);
2027 musb->context.index_regs[i].rxmaxp =
2028 musb_readw(epio, MUSB_RXMAXP);
2029 musb->context.index_regs[i].rxcsr =
2030 musb_readw(epio, MUSB_RXCSR);
2031
2032 if (musb->dyn_fifo) {
2033 musb->context.index_regs[i].txfifoadd =
2034 musb_read_txfifoadd(musb_base);
2035 musb->context.index_regs[i].rxfifoadd =
2036 musb_read_rxfifoadd(musb_base);
2037 musb->context.index_regs[i].txfifosz =
2038 musb_read_txfifosz(musb_base);
2039 musb->context.index_regs[i].rxfifosz =
2040 musb_read_rxfifosz(musb_base);
2041 }
2042
2043 musb->context.index_regs[i].txtype =
2044 musb_readb(epio, MUSB_TXTYPE);
2045 musb->context.index_regs[i].txinterval =
2046 musb_readb(epio, MUSB_TXINTERVAL);
2047 musb->context.index_regs[i].rxtype =
2048 musb_readb(epio, MUSB_RXTYPE);
2049 musb->context.index_regs[i].rxinterval =
2050 musb_readb(epio, MUSB_RXINTERVAL);
2051
2052 musb->context.index_regs[i].txfunaddr =
2053 musb_read_txfunaddr(musb_base, i);
2054 musb->context.index_regs[i].txhubaddr =
2055 musb_read_txhubaddr(musb_base, i);
2056 musb->context.index_regs[i].txhubport =
2057 musb_read_txhubport(musb_base, i);
2058
2059 musb->context.index_regs[i].rxfunaddr =
2060 musb_read_rxfunaddr(musb_base, i);
2061 musb->context.index_regs[i].rxhubaddr =
2062 musb_read_rxhubaddr(musb_base, i);
2063 musb->context.index_regs[i].rxhubport =
2064 musb_read_rxhubport(musb_base, i);
2065 }
2066 }
2067
2068 static void musb_restore_context(struct musb *musb)
2069 {
2070 int i;
2071 void __iomem *musb_base = musb->mregs;
2072 void __iomem *ep_target_regs;
2073 void __iomem *epio;
2074
2075 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2076 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2077 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2078 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2079 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2080 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2081 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2082 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2083
2084 for (i = 0; i < musb->config->num_eps; ++i) {
2085 struct musb_hw_ep *hw_ep;
2086
2087 hw_ep = &musb->endpoints[i];
2088 if (!hw_ep)
2089 continue;
2090
2091 epio = hw_ep->regs;
2092 if (!epio)
2093 continue;
2094
2095 musb_writeb(musb_base, MUSB_INDEX, i);
2096 musb_writew(epio, MUSB_TXMAXP,
2097 musb->context.index_regs[i].txmaxp);
2098 musb_writew(epio, MUSB_TXCSR,
2099 musb->context.index_regs[i].txcsr);
2100 musb_writew(epio, MUSB_RXMAXP,
2101 musb->context.index_regs[i].rxmaxp);
2102 musb_writew(epio, MUSB_RXCSR,
2103 musb->context.index_regs[i].rxcsr);
2104
2105 if (musb->dyn_fifo) {
2106 musb_write_txfifosz(musb_base,
2107 musb->context.index_regs[i].txfifosz);
2108 musb_write_rxfifosz(musb_base,
2109 musb->context.index_regs[i].rxfifosz);
2110 musb_write_txfifoadd(musb_base,
2111 musb->context.index_regs[i].txfifoadd);
2112 musb_write_rxfifoadd(musb_base,
2113 musb->context.index_regs[i].rxfifoadd);
2114 }
2115
2116 musb_writeb(epio, MUSB_TXTYPE,
2117 musb->context.index_regs[i].txtype);
2118 musb_writeb(epio, MUSB_TXINTERVAL,
2119 musb->context.index_regs[i].txinterval);
2120 musb_writeb(epio, MUSB_RXTYPE,
2121 musb->context.index_regs[i].rxtype);
2122 musb_writeb(epio, MUSB_RXINTERVAL,
2123
2124 musb->context.index_regs[i].rxinterval);
2125 musb_write_txfunaddr(musb_base, i,
2126 musb->context.index_regs[i].txfunaddr);
2127 musb_write_txhubaddr(musb_base, i,
2128 musb->context.index_regs[i].txhubaddr);
2129 musb_write_txhubport(musb_base, i,
2130 musb->context.index_regs[i].txhubport);
2131
2132 ep_target_regs =
2133 musb_read_target_reg_base(i, musb_base);
2134
2135 musb_write_rxfunaddr(ep_target_regs,
2136 musb->context.index_regs[i].rxfunaddr);
2137 musb_write_rxhubaddr(ep_target_regs,
2138 musb->context.index_regs[i].rxhubaddr);
2139 musb_write_rxhubport(ep_target_regs,
2140 musb->context.index_regs[i].rxhubport);
2141 }
2142 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2143 }
2144
2145 static int musb_suspend(struct device *dev)
2146 {
2147 struct musb *musb = dev_to_musb(dev);
2148 unsigned long flags;
2149
2150 spin_lock_irqsave(&musb->lock, flags);
2151
2152 if (is_peripheral_active(musb)) {
2153 /* FIXME force disconnect unless we know USB will wake
2154 * the system up quickly enough to respond ...
2155 */
2156 } else if (is_host_active(musb)) {
2157 /* we know all the children are suspended; sometimes
2158 * they will even be wakeup-enabled.
2159 */
2160 }
2161
2162 spin_unlock_irqrestore(&musb->lock, flags);
2163 return 0;
2164 }
2165
2166 static int musb_resume_noirq(struct device *dev)
2167 {
2168 /* for static cmos like DaVinci, register values were preserved
2169 * unless for some reason the whole soc powered down or the USB
2170 * module got reset through the PSC (vs just being disabled).
2171 */
2172 return 0;
2173 }
2174
2175 static int musb_runtime_suspend(struct device *dev)
2176 {
2177 struct musb *musb = dev_to_musb(dev);
2178
2179 musb_save_context(musb);
2180
2181 return 0;
2182 }
2183
2184 static int musb_runtime_resume(struct device *dev)
2185 {
2186 struct musb *musb = dev_to_musb(dev);
2187 static int first = 1;
2188
2189 /*
2190 * When pm_runtime_get_sync called for the first time in driver
2191 * init, some of the structure is still not initialized which is
2192 * used in restore function. But clock needs to be
2193 * enabled before any register access, so
2194 * pm_runtime_get_sync has to be called.
2195 * Also context restore without save does not make
2196 * any sense
2197 */
2198 if (!first)
2199 musb_restore_context(musb);
2200 first = 0;
2201
2202 return 0;
2203 }
2204
2205 static const struct dev_pm_ops musb_dev_pm_ops = {
2206 .suspend = musb_suspend,
2207 .resume_noirq = musb_resume_noirq,
2208 .runtime_suspend = musb_runtime_suspend,
2209 .runtime_resume = musb_runtime_resume,
2210 };
2211
2212 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2213 #else
2214 #define MUSB_DEV_PM_OPS NULL
2215 #endif
2216
2217 static struct platform_driver musb_driver = {
2218 .driver = {
2219 .name = (char *)musb_driver_name,
2220 .bus = &platform_bus_type,
2221 .owner = THIS_MODULE,
2222 .pm = MUSB_DEV_PM_OPS,
2223 },
2224 .probe = musb_probe,
2225 .remove = musb_remove,
2226 .shutdown = musb_shutdown,
2227 };
2228
2229 /*-------------------------------------------------------------------------*/
2230
2231 static int __init musb_init(void)
2232 {
2233 if (usb_disabled())
2234 return 0;
2235
2236 return platform_driver_register(&musb_driver);
2237 }
2238 module_init(musb_init);
2239
2240 static void __exit musb_cleanup(void)
2241 {
2242 platform_driver_unregister(&musb_driver);
2243 }
2244 module_exit(musb_cleanup);
Linux kernel - Deliverables
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