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usb: musb: core: break long line
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102
103 #include "musb_core.h"
104
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111 #define MUSB_VERSION "6.0"
112
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124 /*-------------------------------------------------------------------------*/
125
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128 return dev_get_drvdata(dev);
129 }
130
131 /*-------------------------------------------------------------------------*/
132
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136 void __iomem *addr = phy->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172 out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
176 }
177
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180 void __iomem *addr = phy->io_priv;
181 int i = 0;
182 u8 r = 0;
183 u8 power;
184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
210 out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
214 }
215 #else
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
218 #endif
219
220 static struct usb_phy_io_ops musb_ulpi_access = {
221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223 };
224
225 /*-------------------------------------------------------------------------*/
226
227 static u32 musb_default_fifo_offset(u8 epnum)
228 {
229 return 0x20 + (epnum * 4);
230 }
231
232 /* "flat" mapping: each endpoint has its own i/o address */
233 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
234 {
235 }
236
237 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
238 {
239 return 0x100 + (0x10 * epnum) + offset;
240 }
241
242 /* "indexed" mapping: INDEX register controls register bank select */
243 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
244 {
245 musb_writeb(mbase, MUSB_INDEX, epnum);
246 }
247
248 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
249 {
250 return 0x10 + offset;
251 }
252
253 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
254 {
255 return __raw_readb(addr + offset);
256 }
257
258 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
259 {
260 __raw_writeb(data, addr + offset);
261 }
262
263 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264 {
265 return __raw_readw(addr + offset);
266 }
267
268 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
269 {
270 __raw_writew(data, addr + offset);
271 }
272
273 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
274 {
275 return __raw_readl(addr + offset);
276 }
277
278 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
279 {
280 __raw_writel(data, addr + offset);
281 }
282
283 /*
284 * Load an endpoint's FIFO
285 */
286 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
287 const u8 *src)
288 {
289 struct musb *musb = hw_ep->musb;
290 void __iomem *fifo = hw_ep->fifo;
291
292 if (unlikely(len == 0))
293 return;
294
295 prefetch((u8 *)src);
296
297 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
298 'T', hw_ep->epnum, fifo, len, src);
299
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src) == 0)) {
302 u16 index = 0;
303
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src) == 0) {
306 if (len >= 4) {
307 iowrite32_rep(fifo, src + index, len >> 2);
308 index += len & ~0x03;
309 }
310 if (len & 0x02) {
311 musb_writew(fifo, 0, *(u16 *)&src[index]);
312 index += 2;
313 }
314 } else {
315 if (len >= 2) {
316 iowrite16_rep(fifo, src + index, len >> 1);
317 index += len & ~0x01;
318 }
319 }
320 if (len & 0x01)
321 musb_writeb(fifo, 0, src[index]);
322 } else {
323 /* byte aligned */
324 iowrite8_rep(fifo, src, len);
325 }
326 }
327
328 /*
329 * Unload an endpoint's FIFO
330 */
331 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
332 {
333 struct musb *musb = hw_ep->musb;
334 void __iomem *fifo = hw_ep->fifo;
335
336 if (unlikely(len == 0))
337 return;
338
339 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
340 'R', hw_ep->epnum, fifo, len, dst);
341
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst) == 0)) {
344 u16 index = 0;
345
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst) == 0) {
348 if (len >= 4) {
349 ioread32_rep(fifo, dst, len >> 2);
350 index = len & ~0x03;
351 }
352 if (len & 0x02) {
353 *(u16 *)&dst[index] = musb_readw(fifo, 0);
354 index += 2;
355 }
356 } else {
357 if (len >= 2) {
358 ioread16_rep(fifo, dst, len >> 1);
359 index = len & ~0x01;
360 }
361 }
362 if (len & 0x01)
363 dst[index] = musb_readb(fifo, 0);
364 } else {
365 /* byte aligned */
366 ioread8_rep(fifo, dst, len);
367 }
368 }
369
370 /*
371 * Old style IO functions
372 */
373 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374 EXPORT_SYMBOL_GPL(musb_readb);
375
376 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377 EXPORT_SYMBOL_GPL(musb_writeb);
378
379 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readw);
381
382 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383 EXPORT_SYMBOL_GPL(musb_writew);
384
385 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readl);
387
388 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389 EXPORT_SYMBOL_GPL(musb_writel);
390
391 /*
392 * New style IO functions
393 */
394 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
395 {
396 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
397 }
398
399 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
400 {
401 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
402 }
403
404 /*-------------------------------------------------------------------------*/
405
406 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
407 static const u8 musb_test_packet[53] = {
408 /* implicit SYNC then DATA0 to start */
409
410 /* JKJKJKJK x9 */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
412 /* JJKKJJKK x8 */
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
414 /* JJJJKKKK x8 */
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
418 /* JJJJJJJK x8 */
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
422
423 /* implicit CRC16 then EOP to end */
424 };
425
426 void musb_load_testpacket(struct musb *musb)
427 {
428 void __iomem *regs = musb->endpoints[0].regs;
429
430 musb_ep_select(musb->mregs, 0);
431 musb_write_fifo(musb->control_ep,
432 sizeof(musb_test_packet), musb_test_packet);
433 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
434 }
435
436 /*-------------------------------------------------------------------------*/
437
438 /*
439 * Handles OTG hnp timeouts, such as b_ase0_brst
440 */
441 static void musb_otg_timer_func(unsigned long data)
442 {
443 struct musb *musb = (struct musb *)data;
444 unsigned long flags;
445
446 spin_lock_irqsave(&musb->lock, flags);
447 switch (musb->xceiv->otg->state) {
448 case OTG_STATE_B_WAIT_ACON:
449 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
450 musb_g_disconnect(musb);
451 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
452 musb->is_active = 0;
453 break;
454 case OTG_STATE_A_SUSPEND:
455 case OTG_STATE_A_WAIT_BCON:
456 dev_dbg(musb->controller, "HNP: %s timeout\n",
457 usb_otg_state_string(musb->xceiv->otg->state));
458 musb_platform_set_vbus(musb, 0);
459 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
460 break;
461 default:
462 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
463 usb_otg_state_string(musb->xceiv->otg->state));
464 }
465 spin_unlock_irqrestore(&musb->lock, flags);
466 }
467
468 /*
469 * Stops the HNP transition. Caller must take care of locking.
470 */
471 void musb_hnp_stop(struct musb *musb)
472 {
473 struct usb_hcd *hcd = musb->hcd;
474 void __iomem *mbase = musb->mregs;
475 u8 reg;
476
477 dev_dbg(musb->controller, "HNP: stop from %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479
480 switch (musb->xceiv->otg->state) {
481 case OTG_STATE_A_PERIPHERAL:
482 musb_g_disconnect(musb);
483 dev_dbg(musb->controller, "HNP: back to %s\n",
484 usb_otg_state_string(musb->xceiv->otg->state));
485 break;
486 case OTG_STATE_B_HOST:
487 dev_dbg(musb->controller, "HNP: Disabling HR\n");
488 if (hcd)
489 hcd->self.is_b_host = 0;
490 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
491 MUSB_DEV_MODE(musb);
492 reg = musb_readb(mbase, MUSB_POWER);
493 reg |= MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER, reg);
495 /* REVISIT: Start SESSION_REQUEST here? */
496 break;
497 default:
498 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 }
501
502 /*
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
505 * errors.
506 */
507 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
508 }
509
510 static void musb_generic_disable(struct musb *musb);
511 /*
512 * Interrupt Service Routine to record USB "global" interrupts.
513 * Since these do not happen often and signify things of
514 * paramount importance, it seems OK to check them individually;
515 * the order of the tests is specified in the manual
516 *
517 * @param musb instance pointer
518 * @param int_usb register contents
519 * @param devctl
520 * @param power
521 */
522
523 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
524 u8 devctl)
525 {
526 irqreturn_t handled = IRQ_NONE;
527
528 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
529 int_usb);
530
531 /* in host mode, the peripheral may issue remote wakeup.
532 * in peripheral mode, the host may resume the link.
533 * spurious RESUME irqs happen too, paired with SUSPEND.
534 */
535 if (int_usb & MUSB_INTR_RESUME) {
536 handled = IRQ_HANDLED;
537 dev_dbg(musb->controller, "RESUME (%s)\n",
538 usb_otg_state_string(musb->xceiv->otg->state));
539
540 if (devctl & MUSB_DEVCTL_HM) {
541 void __iomem *mbase = musb->mregs;
542 u8 power;
543
544 switch (musb->xceiv->otg->state) {
545 case OTG_STATE_A_SUSPEND:
546 /* remote wakeup? later, GetPortStatus
547 * will stop RESUME signaling
548 */
549
550 power = musb_readb(musb->mregs, MUSB_POWER);
551 if (power & MUSB_POWER_SUSPENDM) {
552 /* spurious */
553 musb->int_usb &= ~MUSB_INTR_SUSPEND;
554 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
555 break;
556 }
557
558 power &= ~MUSB_POWER_SUSPENDM;
559 musb_writeb(mbase, MUSB_POWER,
560 power | MUSB_POWER_RESUME);
561
562 musb->port1_status |=
563 (USB_PORT_STAT_C_SUSPEND << 16)
564 | MUSB_PORT_STAT_RESUME;
565 musb->rh_timer = jiffies
566 + msecs_to_jiffies(20);
567 musb->need_finish_resume = 1;
568
569 musb->xceiv->otg->state = OTG_STATE_A_HOST;
570 musb->is_active = 1;
571 musb_host_resume_root_hub(musb);
572 break;
573 case OTG_STATE_B_WAIT_ACON:
574 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
575 musb->is_active = 1;
576 MUSB_DEV_MODE(musb);
577 break;
578 default:
579 WARNING("bogus %s RESUME (%s)\n",
580 "host",
581 usb_otg_state_string(musb->xceiv->otg->state));
582 }
583 } else {
584 switch (musb->xceiv->otg->state) {
585 case OTG_STATE_A_SUSPEND:
586 /* possibly DISCONNECT is upcoming */
587 musb->xceiv->otg->state = OTG_STATE_A_HOST;
588 musb_host_resume_root_hub(musb);
589 break;
590 case OTG_STATE_B_WAIT_ACON:
591 case OTG_STATE_B_PERIPHERAL:
592 /* disconnect while suspended? we may
593 * not get a disconnect irq...
594 */
595 if ((devctl & MUSB_DEVCTL_VBUS)
596 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
597 ) {
598 musb->int_usb |= MUSB_INTR_DISCONNECT;
599 musb->int_usb &= ~MUSB_INTR_SUSPEND;
600 break;
601 }
602 musb_g_resume(musb);
603 break;
604 case OTG_STATE_B_IDLE:
605 musb->int_usb &= ~MUSB_INTR_SUSPEND;
606 break;
607 default:
608 WARNING("bogus %s RESUME (%s)\n",
609 "peripheral",
610 usb_otg_state_string(musb->xceiv->otg->state));
611 }
612 }
613 }
614
615 /* see manual for the order of the tests */
616 if (int_usb & MUSB_INTR_SESSREQ) {
617 void __iomem *mbase = musb->mregs;
618
619 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
620 && (devctl & MUSB_DEVCTL_BDEVICE)) {
621 dev_dbg(musb->controller, "SessReq while on B state\n");
622 return IRQ_HANDLED;
623 }
624
625 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
626 usb_otg_state_string(musb->xceiv->otg->state));
627
628 /* IRQ arrives from ID pin sense or (later, if VBUS power
629 * is removed) SRP. responses are time critical:
630 * - turn on VBUS (with silicon-specific mechanism)
631 * - go through A_WAIT_VRISE
632 * - ... to A_WAIT_BCON.
633 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
634 */
635 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
636 musb->ep0_stage = MUSB_EP0_START;
637 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
638 MUSB_HST_MODE(musb);
639 musb_platform_set_vbus(musb, 1);
640
641 handled = IRQ_HANDLED;
642 }
643
644 if (int_usb & MUSB_INTR_VBUSERROR) {
645 int ignore = 0;
646
647 /* During connection as an A-Device, we may see a short
648 * current spikes causing voltage drop, because of cable
649 * and peripheral capacitance combined with vbus draw.
650 * (So: less common with truly self-powered devices, where
651 * vbus doesn't act like a power supply.)
652 *
653 * Such spikes are short; usually less than ~500 usec, max
654 * of ~2 msec. That is, they're not sustained overcurrent
655 * errors, though they're reported using VBUSERROR irqs.
656 *
657 * Workarounds: (a) hardware: use self powered devices.
658 * (b) software: ignore non-repeated VBUS errors.
659 *
660 * REVISIT: do delays from lots of DEBUG_KERNEL checks
661 * make trouble here, keeping VBUS < 4.4V ?
662 */
663 switch (musb->xceiv->otg->state) {
664 case OTG_STATE_A_HOST:
665 /* recovery is dicey once we've gotten past the
666 * initial stages of enumeration, but if VBUS
667 * stayed ok at the other end of the link, and
668 * another reset is due (at least for high speed,
669 * to redo the chirp etc), it might work OK...
670 */
671 case OTG_STATE_A_WAIT_BCON:
672 case OTG_STATE_A_WAIT_VRISE:
673 if (musb->vbuserr_retry) {
674 void __iomem *mbase = musb->mregs;
675
676 musb->vbuserr_retry--;
677 ignore = 1;
678 devctl |= MUSB_DEVCTL_SESSION;
679 musb_writeb(mbase, MUSB_DEVCTL, devctl);
680 } else {
681 musb->port1_status |=
682 USB_PORT_STAT_OVERCURRENT
683 | (USB_PORT_STAT_C_OVERCURRENT << 16);
684 }
685 break;
686 default:
687 break;
688 }
689
690 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
691 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
692 usb_otg_state_string(musb->xceiv->otg->state),
693 devctl,
694 ({ char *s;
695 switch (devctl & MUSB_DEVCTL_VBUS) {
696 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
697 s = "<SessEnd"; break;
698 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
699 s = "<AValid"; break;
700 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
701 s = "<VBusValid"; break;
702 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
703 default:
704 s = "VALID"; break;
705 } s; }),
706 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
707 musb->port1_status);
708
709 /* go through A_WAIT_VFALL then start a new session */
710 if (!ignore)
711 musb_platform_set_vbus(musb, 0);
712 handled = IRQ_HANDLED;
713 }
714
715 if (int_usb & MUSB_INTR_SUSPEND) {
716 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
717 usb_otg_state_string(musb->xceiv->otg->state), devctl);
718 handled = IRQ_HANDLED;
719
720 switch (musb->xceiv->otg->state) {
721 case OTG_STATE_A_PERIPHERAL:
722 /* We also come here if the cable is removed, since
723 * this silicon doesn't report ID-no-longer-grounded.
724 *
725 * We depend on T(a_wait_bcon) to shut us down, and
726 * hope users don't do anything dicey during this
727 * undesired detour through A_WAIT_BCON.
728 */
729 musb_hnp_stop(musb);
730 musb_host_resume_root_hub(musb);
731 musb_root_disconnect(musb);
732 musb_platform_try_idle(musb, jiffies
733 + msecs_to_jiffies(musb->a_wait_bcon
734 ? : OTG_TIME_A_WAIT_BCON));
735
736 break;
737 case OTG_STATE_B_IDLE:
738 if (!musb->is_active)
739 break;
740 case OTG_STATE_B_PERIPHERAL:
741 musb_g_suspend(musb);
742 musb->is_active = musb->g.b_hnp_enable;
743 if (musb->is_active) {
744 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
745 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
746 mod_timer(&musb->otg_timer, jiffies
747 + msecs_to_jiffies(
748 OTG_TIME_B_ASE0_BRST));
749 }
750 break;
751 case OTG_STATE_A_WAIT_BCON:
752 if (musb->a_wait_bcon != 0)
753 musb_platform_try_idle(musb, jiffies
754 + msecs_to_jiffies(musb->a_wait_bcon));
755 break;
756 case OTG_STATE_A_HOST:
757 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
758 musb->is_active = musb->hcd->self.b_hnp_enable;
759 break;
760 case OTG_STATE_B_HOST:
761 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
762 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
763 break;
764 default:
765 /* "should not happen" */
766 musb->is_active = 0;
767 break;
768 }
769 }
770
771 if (int_usb & MUSB_INTR_CONNECT) {
772 struct usb_hcd *hcd = musb->hcd;
773
774 handled = IRQ_HANDLED;
775 musb->is_active = 1;
776
777 musb->ep0_stage = MUSB_EP0_START;
778
779 /* flush endpoints when transitioning from Device Mode */
780 if (is_peripheral_active(musb)) {
781 /* REVISIT HNP; just force disconnect */
782 }
783 musb->intrtxe = musb->epmask;
784 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
785 musb->intrrxe = musb->epmask & 0xfffe;
786 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
787 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
788 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
789 |USB_PORT_STAT_HIGH_SPEED
790 |USB_PORT_STAT_ENABLE
791 );
792 musb->port1_status |= USB_PORT_STAT_CONNECTION
793 |(USB_PORT_STAT_C_CONNECTION << 16);
794
795 /* high vs full speed is just a guess until after reset */
796 if (devctl & MUSB_DEVCTL_LSDEV)
797 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
798
799 /* indicate new connection to OTG machine */
800 switch (musb->xceiv->otg->state) {
801 case OTG_STATE_B_PERIPHERAL:
802 if (int_usb & MUSB_INTR_SUSPEND) {
803 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
804 int_usb &= ~MUSB_INTR_SUSPEND;
805 goto b_host;
806 } else
807 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
808 break;
809 case OTG_STATE_B_WAIT_ACON:
810 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
811 b_host:
812 musb->xceiv->otg->state = OTG_STATE_B_HOST;
813 if (musb->hcd)
814 musb->hcd->self.is_b_host = 1;
815 del_timer(&musb->otg_timer);
816 break;
817 default:
818 if ((devctl & MUSB_DEVCTL_VBUS)
819 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
820 musb->xceiv->otg->state = OTG_STATE_A_HOST;
821 if (hcd)
822 hcd->self.is_b_host = 0;
823 }
824 break;
825 }
826
827 musb_host_poke_root_hub(musb);
828
829 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
830 usb_otg_state_string(musb->xceiv->otg->state), devctl);
831 }
832
833 if (int_usb & MUSB_INTR_DISCONNECT) {
834 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
835 usb_otg_state_string(musb->xceiv->otg->state),
836 MUSB_MODE(musb), devctl);
837 handled = IRQ_HANDLED;
838
839 switch (musb->xceiv->otg->state) {
840 case OTG_STATE_A_HOST:
841 case OTG_STATE_A_SUSPEND:
842 musb_host_resume_root_hub(musb);
843 musb_root_disconnect(musb);
844 if (musb->a_wait_bcon != 0)
845 musb_platform_try_idle(musb, jiffies
846 + msecs_to_jiffies(musb->a_wait_bcon));
847 break;
848 case OTG_STATE_B_HOST:
849 /* REVISIT this behaves for "real disconnect"
850 * cases; make sure the other transitions from
851 * from B_HOST act right too. The B_HOST code
852 * in hnp_stop() is currently not used...
853 */
854 musb_root_disconnect(musb);
855 if (musb->hcd)
856 musb->hcd->self.is_b_host = 0;
857 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
858 MUSB_DEV_MODE(musb);
859 musb_g_disconnect(musb);
860 break;
861 case OTG_STATE_A_PERIPHERAL:
862 musb_hnp_stop(musb);
863 musb_root_disconnect(musb);
864 /* FALLTHROUGH */
865 case OTG_STATE_B_WAIT_ACON:
866 /* FALLTHROUGH */
867 case OTG_STATE_B_PERIPHERAL:
868 case OTG_STATE_B_IDLE:
869 musb_g_disconnect(musb);
870 break;
871 default:
872 WARNING("unhandled DISCONNECT transition (%s)\n",
873 usb_otg_state_string(musb->xceiv->otg->state));
874 break;
875 }
876 }
877
878 /* mentor saves a bit: bus reset and babble share the same irq.
879 * only host sees babble; only peripheral sees bus reset.
880 */
881 if (int_usb & MUSB_INTR_RESET) {
882 handled = IRQ_HANDLED;
883 if (devctl & MUSB_DEVCTL_HM) {
884 u8 power = musb_readl(musb->mregs, MUSB_POWER);
885
886 /*
887 * Looks like non-HS BABBLE can be ignored, but
888 * HS BABBLE is an error condition.
889 *
890 * For HS the solution is to avoid babble in the first
891 * place and fix what caused BABBLE.
892 *
893 * When HS BABBLE happens what we can depends on which
894 * platform MUSB is running, because some platforms
895 * implemented proprietary means for 'recovering' from
896 * Babble conditions. One such platform is AM335x. In
897 * most cases, however, the only thing we can do is drop
898 * the session.
899 */
900 if (power & MUSB_POWER_HSMODE) {
901 ERR("Stopping host session -- babble\n");
902 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
903
904 if (is_host_active(musb)) {
905 musb_generic_disable(musb);
906 schedule_delayed_work(&musb->recover_work,
907 msecs_to_jiffies(100));
908 }
909 }
910 } else {
911 dev_dbg(musb->controller, "BUS RESET as %s\n",
912 usb_otg_state_string(musb->xceiv->otg->state));
913 switch (musb->xceiv->otg->state) {
914 case OTG_STATE_A_SUSPEND:
915 musb_g_reset(musb);
916 /* FALLTHROUGH */
917 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
918 /* never use invalid T(a_wait_bcon) */
919 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
920 usb_otg_state_string(musb->xceiv->otg->state),
921 TA_WAIT_BCON(musb));
922 mod_timer(&musb->otg_timer, jiffies
923 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
924 break;
925 case OTG_STATE_A_PERIPHERAL:
926 del_timer(&musb->otg_timer);
927 musb_g_reset(musb);
928 break;
929 case OTG_STATE_B_WAIT_ACON:
930 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
931 usb_otg_state_string(musb->xceiv->otg->state));
932 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
933 musb_g_reset(musb);
934 break;
935 case OTG_STATE_B_IDLE:
936 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
937 /* FALLTHROUGH */
938 case OTG_STATE_B_PERIPHERAL:
939 musb_g_reset(musb);
940 break;
941 default:
942 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
943 usb_otg_state_string(musb->xceiv->otg->state));
944 }
945 }
946 }
947
948 #if 0
949 /* REVISIT ... this would be for multiplexing periodic endpoints, or
950 * supporting transfer phasing to prevent exceeding ISO bandwidth
951 * limits of a given frame or microframe.
952 *
953 * It's not needed for peripheral side, which dedicates endpoints;
954 * though it _might_ use SOF irqs for other purposes.
955 *
956 * And it's not currently needed for host side, which also dedicates
957 * endpoints, relies on TX/RX interval registers, and isn't claimed
958 * to support ISO transfers yet.
959 */
960 if (int_usb & MUSB_INTR_SOF) {
961 void __iomem *mbase = musb->mregs;
962 struct musb_hw_ep *ep;
963 u8 epnum;
964 u16 frame;
965
966 dev_dbg(musb->controller, "START_OF_FRAME\n");
967 handled = IRQ_HANDLED;
968
969 /* start any periodic Tx transfers waiting for current frame */
970 frame = musb_readw(mbase, MUSB_FRAME);
971 ep = musb->endpoints;
972 for (epnum = 1; (epnum < musb->nr_endpoints)
973 && (musb->epmask >= (1 << epnum));
974 epnum++, ep++) {
975 /*
976 * FIXME handle framecounter wraps (12 bits)
977 * eliminate duplicated StartUrb logic
978 */
979 if (ep->dwWaitFrame >= frame) {
980 ep->dwWaitFrame = 0;
981 pr_debug("SOF --> periodic TX%s on %d\n",
982 ep->tx_channel ? " DMA" : "",
983 epnum);
984 if (!ep->tx_channel)
985 musb_h_tx_start(musb, epnum);
986 else
987 cppi_hostdma_start(musb, epnum);
988 }
989 } /* end of for loop */
990 }
991 #endif
992
993 schedule_work(&musb->irq_work);
994
995 return handled;
996 }
997
998 /*-------------------------------------------------------------------------*/
999
1000 static void musb_generic_disable(struct musb *musb)
1001 {
1002 void __iomem *mbase = musb->mregs;
1003 u16 temp;
1004
1005 /* disable interrupts */
1006 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1007 musb->intrtxe = 0;
1008 musb_writew(mbase, MUSB_INTRTXE, 0);
1009 musb->intrrxe = 0;
1010 musb_writew(mbase, MUSB_INTRRXE, 0);
1011
1012 /* off */
1013 musb_writeb(mbase, MUSB_DEVCTL, 0);
1014
1015 /* flush pending interrupts */
1016 temp = musb_readb(mbase, MUSB_INTRUSB);
1017 temp = musb_readw(mbase, MUSB_INTRTX);
1018 temp = musb_readw(mbase, MUSB_INTRRX);
1019
1020 }
1021
1022 /*
1023 * Program the HDRC to start (enable interrupts, dma, etc.).
1024 */
1025 void musb_start(struct musb *musb)
1026 {
1027 void __iomem *regs = musb->mregs;
1028 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1029
1030 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1031
1032 /* Set INT enable registers, enable interrupts */
1033 musb->intrtxe = musb->epmask;
1034 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1035 musb->intrrxe = musb->epmask & 0xfffe;
1036 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1037 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1038
1039 musb_writeb(regs, MUSB_TESTMODE, 0);
1040
1041 /* put into basic highspeed mode and start session */
1042 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1043 | MUSB_POWER_HSENAB
1044 /* ENSUSPEND wedges tusb */
1045 /* | MUSB_POWER_ENSUSPEND */
1046 );
1047
1048 musb->is_active = 0;
1049 devctl = musb_readb(regs, MUSB_DEVCTL);
1050 devctl &= ~MUSB_DEVCTL_SESSION;
1051
1052 /* session started after:
1053 * (a) ID-grounded irq, host mode;
1054 * (b) vbus present/connect IRQ, peripheral mode;
1055 * (c) peripheral initiates, using SRP
1056 */
1057 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1058 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1059 musb->is_active = 1;
1060 } else {
1061 devctl |= MUSB_DEVCTL_SESSION;
1062 }
1063
1064 musb_platform_enable(musb);
1065 musb_writeb(regs, MUSB_DEVCTL, devctl);
1066 }
1067
1068 /*
1069 * Make the HDRC stop (disable interrupts, etc.);
1070 * reversible by musb_start
1071 * called on gadget driver unregister
1072 * with controller locked, irqs blocked
1073 * acts as a NOP unless some role activated the hardware
1074 */
1075 void musb_stop(struct musb *musb)
1076 {
1077 /* stop IRQs, timers, ... */
1078 musb_platform_disable(musb);
1079 musb_generic_disable(musb);
1080 dev_dbg(musb->controller, "HDRC disabled\n");
1081
1082 /* FIXME
1083 * - mark host and/or peripheral drivers unusable/inactive
1084 * - disable DMA (and enable it in HdrcStart)
1085 * - make sure we can musb_start() after musb_stop(); with
1086 * OTG mode, gadget driver module rmmod/modprobe cycles that
1087 * - ...
1088 */
1089 musb_platform_try_idle(musb, 0);
1090 }
1091
1092 static void musb_shutdown(struct platform_device *pdev)
1093 {
1094 struct musb *musb = dev_to_musb(&pdev->dev);
1095 unsigned long flags;
1096
1097 pm_runtime_get_sync(musb->controller);
1098
1099 musb_host_cleanup(musb);
1100 musb_gadget_cleanup(musb);
1101
1102 spin_lock_irqsave(&musb->lock, flags);
1103 musb_platform_disable(musb);
1104 musb_generic_disable(musb);
1105 spin_unlock_irqrestore(&musb->lock, flags);
1106
1107 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1108 musb_platform_exit(musb);
1109
1110 pm_runtime_put(musb->controller);
1111 /* FIXME power down */
1112 }
1113
1114
1115 /*-------------------------------------------------------------------------*/
1116
1117 /*
1118 * The silicon either has hard-wired endpoint configurations, or else
1119 * "dynamic fifo" sizing. The driver has support for both, though at this
1120 * writing only the dynamic sizing is very well tested. Since we switched
1121 * away from compile-time hardware parameters, we can no longer rely on
1122 * dead code elimination to leave only the relevant one in the object file.
1123 *
1124 * We don't currently use dynamic fifo setup capability to do anything
1125 * more than selecting one of a bunch of predefined configurations.
1126 */
1127 static ushort fifo_mode;
1128
1129 /* "modprobe ... fifo_mode=1" etc */
1130 module_param(fifo_mode, ushort, 0);
1131 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1132
1133 /*
1134 * tables defining fifo_mode values. define more if you like.
1135 * for host side, make sure both halves of ep1 are set up.
1136 */
1137
1138 /* mode 0 - fits in 2KB */
1139 static struct musb_fifo_cfg mode_0_cfg[] = {
1140 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1141 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1142 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1143 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1144 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1145 };
1146
1147 /* mode 1 - fits in 4KB */
1148 static struct musb_fifo_cfg mode_1_cfg[] = {
1149 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1150 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1153 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1154 };
1155
1156 /* mode 2 - fits in 4KB */
1157 static struct musb_fifo_cfg mode_2_cfg[] = {
1158 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1159 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1160 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1161 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1162 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1163 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1164 };
1165
1166 /* mode 3 - fits in 4KB */
1167 static struct musb_fifo_cfg mode_3_cfg[] = {
1168 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1169 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1170 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1171 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1172 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1173 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1174 };
1175
1176 /* mode 4 - fits in 16KB */
1177 static struct musb_fifo_cfg mode_4_cfg[] = {
1178 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1179 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1180 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1181 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1182 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1183 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1184 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1185 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1186 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1187 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1188 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1189 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1190 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1191 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1192 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1193 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1194 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1195 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1196 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1197 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1198 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1199 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1200 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1201 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1202 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1203 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1204 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1205 };
1206
1207 /* mode 5 - fits in 8KB */
1208 static struct musb_fifo_cfg mode_5_cfg[] = {
1209 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1210 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1211 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1212 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1213 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1214 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1215 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1216 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1217 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1218 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1219 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1220 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1221 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1222 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1223 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1224 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1225 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1226 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1227 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1228 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1229 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1230 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1231 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1232 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1233 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1234 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1235 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1236 };
1237
1238 /*
1239 * configure a fifo; for non-shared endpoints, this may be called
1240 * once for a tx fifo and once for an rx fifo.
1241 *
1242 * returns negative errno or offset for next fifo.
1243 */
1244 static int
1245 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1246 const struct musb_fifo_cfg *cfg, u16 offset)
1247 {
1248 void __iomem *mbase = musb->mregs;
1249 int size = 0;
1250 u16 maxpacket = cfg->maxpacket;
1251 u16 c_off = offset >> 3;
1252 u8 c_size;
1253
1254 /* expect hw_ep has already been zero-initialized */
1255
1256 size = ffs(max(maxpacket, (u16) 8)) - 1;
1257 maxpacket = 1 << size;
1258
1259 c_size = size - 3;
1260 if (cfg->mode == BUF_DOUBLE) {
1261 if ((offset + (maxpacket << 1)) >
1262 (1 << (musb->config->ram_bits + 2)))
1263 return -EMSGSIZE;
1264 c_size |= MUSB_FIFOSZ_DPB;
1265 } else {
1266 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1267 return -EMSGSIZE;
1268 }
1269
1270 /* configure the FIFO */
1271 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1272
1273 /* EP0 reserved endpoint for control, bidirectional;
1274 * EP1 reserved for bulk, two unidirectional halves.
1275 */
1276 if (hw_ep->epnum == 1)
1277 musb->bulk_ep = hw_ep;
1278 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1279 switch (cfg->style) {
1280 case FIFO_TX:
1281 musb_write_txfifosz(mbase, c_size);
1282 musb_write_txfifoadd(mbase, c_off);
1283 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1284 hw_ep->max_packet_sz_tx = maxpacket;
1285 break;
1286 case FIFO_RX:
1287 musb_write_rxfifosz(mbase, c_size);
1288 musb_write_rxfifoadd(mbase, c_off);
1289 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1290 hw_ep->max_packet_sz_rx = maxpacket;
1291 break;
1292 case FIFO_RXTX:
1293 musb_write_txfifosz(mbase, c_size);
1294 musb_write_txfifoadd(mbase, c_off);
1295 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1296 hw_ep->max_packet_sz_rx = maxpacket;
1297
1298 musb_write_rxfifosz(mbase, c_size);
1299 musb_write_rxfifoadd(mbase, c_off);
1300 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1301 hw_ep->max_packet_sz_tx = maxpacket;
1302
1303 hw_ep->is_shared_fifo = true;
1304 break;
1305 }
1306
1307 /* NOTE rx and tx endpoint irqs aren't managed separately,
1308 * which happens to be ok
1309 */
1310 musb->epmask |= (1 << hw_ep->epnum);
1311
1312 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1313 }
1314
1315 static struct musb_fifo_cfg ep0_cfg = {
1316 .style = FIFO_RXTX, .maxpacket = 64,
1317 };
1318
1319 static int ep_config_from_table(struct musb *musb)
1320 {
1321 const struct musb_fifo_cfg *cfg;
1322 unsigned i, n;
1323 int offset;
1324 struct musb_hw_ep *hw_ep = musb->endpoints;
1325
1326 if (musb->config->fifo_cfg) {
1327 cfg = musb->config->fifo_cfg;
1328 n = musb->config->fifo_cfg_size;
1329 goto done;
1330 }
1331
1332 switch (fifo_mode) {
1333 default:
1334 fifo_mode = 0;
1335 /* FALLTHROUGH */
1336 case 0:
1337 cfg = mode_0_cfg;
1338 n = ARRAY_SIZE(mode_0_cfg);
1339 break;
1340 case 1:
1341 cfg = mode_1_cfg;
1342 n = ARRAY_SIZE(mode_1_cfg);
1343 break;
1344 case 2:
1345 cfg = mode_2_cfg;
1346 n = ARRAY_SIZE(mode_2_cfg);
1347 break;
1348 case 3:
1349 cfg = mode_3_cfg;
1350 n = ARRAY_SIZE(mode_3_cfg);
1351 break;
1352 case 4:
1353 cfg = mode_4_cfg;
1354 n = ARRAY_SIZE(mode_4_cfg);
1355 break;
1356 case 5:
1357 cfg = mode_5_cfg;
1358 n = ARRAY_SIZE(mode_5_cfg);
1359 break;
1360 }
1361
1362 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1363 musb_driver_name, fifo_mode);
1364
1365
1366 done:
1367 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1368 /* assert(offset > 0) */
1369
1370 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1371 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1372 */
1373
1374 for (i = 0; i < n; i++) {
1375 u8 epn = cfg->hw_ep_num;
1376
1377 if (epn >= musb->config->num_eps) {
1378 pr_debug("%s: invalid ep %d\n",
1379 musb_driver_name, epn);
1380 return -EINVAL;
1381 }
1382 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1383 if (offset < 0) {
1384 pr_debug("%s: mem overrun, ep %d\n",
1385 musb_driver_name, epn);
1386 return offset;
1387 }
1388 epn++;
1389 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1390 }
1391
1392 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1393 musb_driver_name,
1394 n + 1, musb->config->num_eps * 2 - 1,
1395 offset, (1 << (musb->config->ram_bits + 2)));
1396
1397 if (!musb->bulk_ep) {
1398 pr_debug("%s: missing bulk\n", musb_driver_name);
1399 return -EINVAL;
1400 }
1401
1402 return 0;
1403 }
1404
1405
1406 /*
1407 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1408 * @param musb the controller
1409 */
1410 static int ep_config_from_hw(struct musb *musb)
1411 {
1412 u8 epnum = 0;
1413 struct musb_hw_ep *hw_ep;
1414 void __iomem *mbase = musb->mregs;
1415 int ret = 0;
1416
1417 dev_dbg(musb->controller, "<== static silicon ep config\n");
1418
1419 /* FIXME pick up ep0 maxpacket size */
1420
1421 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1422 musb_ep_select(mbase, epnum);
1423 hw_ep = musb->endpoints + epnum;
1424
1425 ret = musb_read_fifosize(musb, hw_ep, epnum);
1426 if (ret < 0)
1427 break;
1428
1429 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1430
1431 /* pick an RX/TX endpoint for bulk */
1432 if (hw_ep->max_packet_sz_tx < 512
1433 || hw_ep->max_packet_sz_rx < 512)
1434 continue;
1435
1436 /* REVISIT: this algorithm is lazy, we should at least
1437 * try to pick a double buffered endpoint.
1438 */
1439 if (musb->bulk_ep)
1440 continue;
1441 musb->bulk_ep = hw_ep;
1442 }
1443
1444 if (!musb->bulk_ep) {
1445 pr_debug("%s: missing bulk\n", musb_driver_name);
1446 return -EINVAL;
1447 }
1448
1449 return 0;
1450 }
1451
1452 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1453
1454 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1455 * configure endpoints, or take their config from silicon
1456 */
1457 static int musb_core_init(u16 musb_type, struct musb *musb)
1458 {
1459 u8 reg;
1460 char *type;
1461 char aInfo[90], aRevision[32], aDate[12];
1462 void __iomem *mbase = musb->mregs;
1463 int status = 0;
1464 int i;
1465
1466 /* log core options (read using indexed model) */
1467 reg = musb_read_configdata(mbase);
1468
1469 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1470 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1471 strcat(aInfo, ", dyn FIFOs");
1472 musb->dyn_fifo = true;
1473 }
1474 if (reg & MUSB_CONFIGDATA_MPRXE) {
1475 strcat(aInfo, ", bulk combine");
1476 musb->bulk_combine = true;
1477 }
1478 if (reg & MUSB_CONFIGDATA_MPTXE) {
1479 strcat(aInfo, ", bulk split");
1480 musb->bulk_split = true;
1481 }
1482 if (reg & MUSB_CONFIGDATA_HBRXE) {
1483 strcat(aInfo, ", HB-ISO Rx");
1484 musb->hb_iso_rx = true;
1485 }
1486 if (reg & MUSB_CONFIGDATA_HBTXE) {
1487 strcat(aInfo, ", HB-ISO Tx");
1488 musb->hb_iso_tx = true;
1489 }
1490 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1491 strcat(aInfo, ", SoftConn");
1492
1493 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1494 musb_driver_name, reg, aInfo);
1495
1496 aDate[0] = 0;
1497 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1498 musb->is_multipoint = 1;
1499 type = "M";
1500 } else {
1501 musb->is_multipoint = 0;
1502 type = "";
1503 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1504 printk(KERN_ERR
1505 "%s: kernel must blacklist external hubs\n",
1506 musb_driver_name);
1507 #endif
1508 }
1509
1510 /* log release info */
1511 musb->hwvers = musb_read_hwvers(mbase);
1512 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1513 MUSB_HWVERS_MINOR(musb->hwvers),
1514 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1515 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1516 musb_driver_name, type, aRevision, aDate);
1517
1518 /* configure ep0 */
1519 musb_configure_ep0(musb);
1520
1521 /* discover endpoint configuration */
1522 musb->nr_endpoints = 1;
1523 musb->epmask = 1;
1524
1525 if (musb->dyn_fifo)
1526 status = ep_config_from_table(musb);
1527 else
1528 status = ep_config_from_hw(musb);
1529
1530 if (status < 0)
1531 return status;
1532
1533 /* finish init, and print endpoint config */
1534 for (i = 0; i < musb->nr_endpoints; i++) {
1535 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1536
1537 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1538 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1539 if (musb->io.quirks & MUSB_IN_TUSB) {
1540 hw_ep->fifo_async = musb->async + 0x400 +
1541 musb->io.fifo_offset(i);
1542 hw_ep->fifo_sync = musb->sync + 0x400 +
1543 musb->io.fifo_offset(i);
1544 hw_ep->fifo_sync_va =
1545 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1546
1547 if (i == 0)
1548 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1549 else
1550 hw_ep->conf = mbase + 0x400 +
1551 (((i - 1) & 0xf) << 2);
1552 }
1553 #endif
1554
1555 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1556 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1557 hw_ep->rx_reinit = 1;
1558 hw_ep->tx_reinit = 1;
1559
1560 if (hw_ep->max_packet_sz_tx) {
1561 dev_dbg(musb->controller,
1562 "%s: hw_ep %d%s, %smax %d\n",
1563 musb_driver_name, i,
1564 hw_ep->is_shared_fifo ? "shared" : "tx",
1565 hw_ep->tx_double_buffered
1566 ? "doublebuffer, " : "",
1567 hw_ep->max_packet_sz_tx);
1568 }
1569 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1570 dev_dbg(musb->controller,
1571 "%s: hw_ep %d%s, %smax %d\n",
1572 musb_driver_name, i,
1573 "rx",
1574 hw_ep->rx_double_buffered
1575 ? "doublebuffer, " : "",
1576 hw_ep->max_packet_sz_rx);
1577 }
1578 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1579 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1580 }
1581
1582 return 0;
1583 }
1584
1585 /*-------------------------------------------------------------------------*/
1586
1587 /*
1588 * handle all the irqs defined by the HDRC core. for now we expect: other
1589 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1590 * will be assigned, and the irq will already have been acked.
1591 *
1592 * called in irq context with spinlock held, irqs blocked
1593 */
1594 irqreturn_t musb_interrupt(struct musb *musb)
1595 {
1596 irqreturn_t retval = IRQ_NONE;
1597 unsigned long status;
1598 unsigned long epnum;
1599 u8 devctl;
1600
1601 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1602 return IRQ_NONE;
1603
1604 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1605
1606 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1607 is_host_active(musb) ? "host" : "peripheral",
1608 musb->int_usb, musb->int_tx, musb->int_rx);
1609
1610 /**
1611 * According to Mentor Graphics' documentation, flowchart on page 98,
1612 * IRQ should be handled as follows:
1613 *
1614 * . Resume IRQ
1615 * . Session Request IRQ
1616 * . VBUS Error IRQ
1617 * . Suspend IRQ
1618 * . Connect IRQ
1619 * . Disconnect IRQ
1620 * . Reset/Babble IRQ
1621 * . SOF IRQ (we're not using this one)
1622 * . Endpoint 0 IRQ
1623 * . TX Endpoints
1624 * . RX Endpoints
1625 *
1626 * We will be following that flowchart in order to avoid any problems
1627 * that might arise with internal Finite State Machine.
1628 */
1629
1630 if (musb->int_usb)
1631 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1632
1633 if (musb->int_tx & 1) {
1634 if (is_host_active(musb))
1635 retval |= musb_h_ep0_irq(musb);
1636 else
1637 retval |= musb_g_ep0_irq(musb);
1638
1639 /* we have just handled endpoint 0 IRQ, clear it */
1640 musb->int_tx &= ~BIT(0);
1641 }
1642
1643 status = musb->int_tx;
1644
1645 for_each_set_bit(epnum, &status, 16) {
1646 retval = IRQ_HANDLED;
1647 if (is_host_active(musb))
1648 musb_host_tx(musb, epnum);
1649 else
1650 musb_g_tx(musb, epnum);
1651 }
1652
1653 status = musb->int_rx;
1654
1655 for_each_set_bit(epnum, &status, 16) {
1656 retval = IRQ_HANDLED;
1657 if (is_host_active(musb))
1658 musb_host_rx(musb, epnum);
1659 else
1660 musb_g_rx(musb, epnum);
1661 }
1662
1663 return retval;
1664 }
1665 EXPORT_SYMBOL_GPL(musb_interrupt);
1666
1667 #ifndef CONFIG_MUSB_PIO_ONLY
1668 static bool use_dma = 1;
1669
1670 /* "modprobe ... use_dma=0" etc */
1671 module_param(use_dma, bool, 0);
1672 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1673
1674 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1675 {
1676 /* called with controller lock already held */
1677
1678 if (!epnum) {
1679 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1680 if (!is_cppi_enabled()) {
1681 /* endpoint 0 */
1682 if (is_host_active(musb))
1683 musb_h_ep0_irq(musb);
1684 else
1685 musb_g_ep0_irq(musb);
1686 }
1687 #endif
1688 } else {
1689 /* endpoints 1..15 */
1690 if (transmit) {
1691 if (is_host_active(musb))
1692 musb_host_tx(musb, epnum);
1693 else
1694 musb_g_tx(musb, epnum);
1695 } else {
1696 /* receive */
1697 if (is_host_active(musb))
1698 musb_host_rx(musb, epnum);
1699 else
1700 musb_g_rx(musb, epnum);
1701 }
1702 }
1703 }
1704 EXPORT_SYMBOL_GPL(musb_dma_completion);
1705
1706 #else
1707 #define use_dma 0
1708 #endif
1709
1710 /*-------------------------------------------------------------------------*/
1711
1712 static ssize_t
1713 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1714 {
1715 struct musb *musb = dev_to_musb(dev);
1716 unsigned long flags;
1717 int ret = -EINVAL;
1718
1719 spin_lock_irqsave(&musb->lock, flags);
1720 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1721 spin_unlock_irqrestore(&musb->lock, flags);
1722
1723 return ret;
1724 }
1725
1726 static ssize_t
1727 musb_mode_store(struct device *dev, struct device_attribute *attr,
1728 const char *buf, size_t n)
1729 {
1730 struct musb *musb = dev_to_musb(dev);
1731 unsigned long flags;
1732 int status;
1733
1734 spin_lock_irqsave(&musb->lock, flags);
1735 if (sysfs_streq(buf, "host"))
1736 status = musb_platform_set_mode(musb, MUSB_HOST);
1737 else if (sysfs_streq(buf, "peripheral"))
1738 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1739 else if (sysfs_streq(buf, "otg"))
1740 status = musb_platform_set_mode(musb, MUSB_OTG);
1741 else
1742 status = -EINVAL;
1743 spin_unlock_irqrestore(&musb->lock, flags);
1744
1745 return (status == 0) ? n : status;
1746 }
1747 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1748
1749 static ssize_t
1750 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1751 const char *buf, size_t n)
1752 {
1753 struct musb *musb = dev_to_musb(dev);
1754 unsigned long flags;
1755 unsigned long val;
1756
1757 if (sscanf(buf, "%lu", &val) < 1) {
1758 dev_err(dev, "Invalid VBUS timeout ms value\n");
1759 return -EINVAL;
1760 }
1761
1762 spin_lock_irqsave(&musb->lock, flags);
1763 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1764 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1765 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1766 musb->is_active = 0;
1767 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1768 spin_unlock_irqrestore(&musb->lock, flags);
1769
1770 return n;
1771 }
1772
1773 static ssize_t
1774 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1775 {
1776 struct musb *musb = dev_to_musb(dev);
1777 unsigned long flags;
1778 unsigned long val;
1779 int vbus;
1780
1781 spin_lock_irqsave(&musb->lock, flags);
1782 val = musb->a_wait_bcon;
1783 /* FIXME get_vbus_status() is normally #defined as false...
1784 * and is effectively TUSB-specific.
1785 */
1786 vbus = musb_platform_get_vbus_status(musb);
1787 spin_unlock_irqrestore(&musb->lock, flags);
1788
1789 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1790 vbus ? "on" : "off", val);
1791 }
1792 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1793
1794 /* Gadget drivers can't know that a host is connected so they might want
1795 * to start SRP, but users can. This allows userspace to trigger SRP.
1796 */
1797 static ssize_t
1798 musb_srp_store(struct device *dev, struct device_attribute *attr,
1799 const char *buf, size_t n)
1800 {
1801 struct musb *musb = dev_to_musb(dev);
1802 unsigned short srp;
1803
1804 if (sscanf(buf, "%hu", &srp) != 1
1805 || (srp != 1)) {
1806 dev_err(dev, "SRP: Value must be 1\n");
1807 return -EINVAL;
1808 }
1809
1810 if (srp == 1)
1811 musb_g_wakeup(musb);
1812
1813 return n;
1814 }
1815 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1816
1817 static struct attribute *musb_attributes[] = {
1818 &dev_attr_mode.attr,
1819 &dev_attr_vbus.attr,
1820 &dev_attr_srp.attr,
1821 NULL
1822 };
1823
1824 static const struct attribute_group musb_attr_group = {
1825 .attrs = musb_attributes,
1826 };
1827
1828 /* Only used to provide driver mode change events */
1829 static void musb_irq_work(struct work_struct *data)
1830 {
1831 struct musb *musb = container_of(data, struct musb, irq_work);
1832
1833 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1834 musb->xceiv_old_state = musb->xceiv->otg->state;
1835 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1836 }
1837 }
1838
1839 /* Recover from babble interrupt conditions */
1840 static void musb_recover_work(struct work_struct *data)
1841 {
1842 struct musb *musb = container_of(data, struct musb, recover_work.work);
1843 int status, ret;
1844
1845 ret = musb_platform_reset(musb);
1846 if (ret)
1847 return;
1848
1849 usb_phy_vbus_off(musb->xceiv);
1850 usleep_range(100, 200);
1851
1852 usb_phy_vbus_on(musb->xceiv);
1853 usleep_range(100, 200);
1854
1855 /*
1856 * When a babble condition occurs, the musb controller
1857 * removes the session bit and the endpoint config is lost.
1858 */
1859 if (musb->dyn_fifo)
1860 status = ep_config_from_table(musb);
1861 else
1862 status = ep_config_from_hw(musb);
1863
1864 /* start the session again */
1865 if (status == 0)
1866 musb_start(musb);
1867 }
1868
1869 /* --------------------------------------------------------------------------
1870 * Init support
1871 */
1872
1873 static struct musb *allocate_instance(struct device *dev,
1874 struct musb_hdrc_config *config, void __iomem *mbase)
1875 {
1876 struct musb *musb;
1877 struct musb_hw_ep *ep;
1878 int epnum;
1879 int ret;
1880
1881 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1882 if (!musb)
1883 return NULL;
1884
1885 INIT_LIST_HEAD(&musb->control);
1886 INIT_LIST_HEAD(&musb->in_bulk);
1887 INIT_LIST_HEAD(&musb->out_bulk);
1888
1889 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1890 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1891 musb->mregs = mbase;
1892 musb->ctrl_base = mbase;
1893 musb->nIrq = -ENODEV;
1894 musb->config = config;
1895 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1896 for (epnum = 0, ep = musb->endpoints;
1897 epnum < musb->config->num_eps;
1898 epnum++, ep++) {
1899 ep->musb = musb;
1900 ep->epnum = epnum;
1901 }
1902
1903 musb->controller = dev;
1904
1905 ret = musb_host_alloc(musb);
1906 if (ret < 0)
1907 goto err_free;
1908
1909 dev_set_drvdata(dev, musb);
1910
1911 return musb;
1912
1913 err_free:
1914 return NULL;
1915 }
1916
1917 static void musb_free(struct musb *musb)
1918 {
1919 /* this has multiple entry modes. it handles fault cleanup after
1920 * probe(), where things may be partially set up, as well as rmmod
1921 * cleanup after everything's been de-activated.
1922 */
1923
1924 #ifdef CONFIG_SYSFS
1925 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1926 #endif
1927
1928 if (musb->nIrq >= 0) {
1929 if (musb->irq_wake)
1930 disable_irq_wake(musb->nIrq);
1931 free_irq(musb->nIrq, musb);
1932 }
1933
1934 musb_host_free(musb);
1935 }
1936
1937 static void musb_deassert_reset(struct work_struct *work)
1938 {
1939 struct musb *musb;
1940 unsigned long flags;
1941
1942 musb = container_of(work, struct musb, deassert_reset_work.work);
1943
1944 spin_lock_irqsave(&musb->lock, flags);
1945
1946 if (musb->port1_status & USB_PORT_STAT_RESET)
1947 musb_port_reset(musb, false);
1948
1949 spin_unlock_irqrestore(&musb->lock, flags);
1950 }
1951
1952 /*
1953 * Perform generic per-controller initialization.
1954 *
1955 * @dev: the controller (already clocked, etc)
1956 * @nIrq: IRQ number
1957 * @ctrl: virtual address of controller registers,
1958 * not yet corrected for platform-specific offsets
1959 */
1960 static int
1961 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1962 {
1963 int status;
1964 struct musb *musb;
1965 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1966
1967 /* The driver might handle more features than the board; OK.
1968 * Fail when the board needs a feature that's not enabled.
1969 */
1970 if (!plat) {
1971 dev_dbg(dev, "no platform_data?\n");
1972 status = -ENODEV;
1973 goto fail0;
1974 }
1975
1976 /* allocate */
1977 musb = allocate_instance(dev, plat->config, ctrl);
1978 if (!musb) {
1979 status = -ENOMEM;
1980 goto fail0;
1981 }
1982
1983 spin_lock_init(&musb->lock);
1984 musb->board_set_power = plat->set_power;
1985 musb->min_power = plat->min_power;
1986 musb->ops = plat->platform_ops;
1987 musb->port_mode = plat->mode;
1988
1989 /*
1990 * Initialize the default IO functions. At least omap2430 needs
1991 * these early. We initialize the platform specific IO functions
1992 * later on.
1993 */
1994 musb_readb = musb_default_readb;
1995 musb_writeb = musb_default_writeb;
1996 musb_readw = musb_default_readw;
1997 musb_writew = musb_default_writew;
1998 musb_readl = musb_default_readl;
1999 musb_writel = musb_default_writel;
2000
2001 /* We need musb_read/write functions initialized for PM */
2002 pm_runtime_use_autosuspend(musb->controller);
2003 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2004 pm_runtime_irq_safe(musb->controller);
2005 pm_runtime_enable(musb->controller);
2006
2007 /* The musb_platform_init() call:
2008 * - adjusts musb->mregs
2009 * - sets the musb->isr
2010 * - may initialize an integrated transceiver
2011 * - initializes musb->xceiv, usually by otg_get_phy()
2012 * - stops powering VBUS
2013 *
2014 * There are various transceiver configurations. Blackfin,
2015 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2016 * external/discrete ones in various flavors (twl4030 family,
2017 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2018 */
2019 status = musb_platform_init(musb);
2020 if (status < 0)
2021 goto fail1;
2022
2023 if (!musb->isr) {
2024 status = -ENODEV;
2025 goto fail2;
2026 }
2027
2028 if (musb->ops->quirks)
2029 musb->io.quirks = musb->ops->quirks;
2030
2031 /* At least tusb6010 has it's own offsets.. */
2032 if (musb->ops->ep_offset)
2033 musb->io.ep_offset = musb->ops->ep_offset;
2034 if (musb->ops->ep_select)
2035 musb->io.ep_select = musb->ops->ep_select;
2036
2037 /* ..and some devices use indexed offset or flat offset */
2038 if (musb->io.quirks & MUSB_INDEXED_EP) {
2039 musb->io.ep_offset = musb_indexed_ep_offset;
2040 musb->io.ep_select = musb_indexed_ep_select;
2041 } else {
2042 musb->io.ep_offset = musb_flat_ep_offset;
2043 musb->io.ep_select = musb_flat_ep_select;
2044 }
2045
2046 if (musb->ops->fifo_mode)
2047 fifo_mode = musb->ops->fifo_mode;
2048 else
2049 fifo_mode = 4;
2050
2051 if (musb->ops->fifo_offset)
2052 musb->io.fifo_offset = musb->ops->fifo_offset;
2053 else
2054 musb->io.fifo_offset = musb_default_fifo_offset;
2055
2056 if (musb->ops->readb)
2057 musb_readb = musb->ops->readb;
2058 if (musb->ops->writeb)
2059 musb_writeb = musb->ops->writeb;
2060 if (musb->ops->readw)
2061 musb_readw = musb->ops->readw;
2062 if (musb->ops->writew)
2063 musb_writew = musb->ops->writew;
2064 if (musb->ops->readl)
2065 musb_readl = musb->ops->readl;
2066 if (musb->ops->writel)
2067 musb_writel = musb->ops->writel;
2068
2069 if (musb->ops->read_fifo)
2070 musb->io.read_fifo = musb->ops->read_fifo;
2071 else
2072 musb->io.read_fifo = musb_default_read_fifo;
2073
2074 if (musb->ops->write_fifo)
2075 musb->io.write_fifo = musb->ops->write_fifo;
2076 else
2077 musb->io.write_fifo = musb_default_write_fifo;
2078
2079 if (!musb->xceiv->io_ops) {
2080 musb->xceiv->io_dev = musb->controller;
2081 musb->xceiv->io_priv = musb->mregs;
2082 musb->xceiv->io_ops = &musb_ulpi_access;
2083 }
2084
2085 pm_runtime_get_sync(musb->controller);
2086
2087 if (use_dma && dev->dma_mask) {
2088 musb->dma_controller = dma_controller_create(musb, musb->mregs);
2089 if (IS_ERR(musb->dma_controller)) {
2090 status = PTR_ERR(musb->dma_controller);
2091 goto fail2_5;
2092 }
2093 }
2094
2095 /* be sure interrupts are disabled before connecting ISR */
2096 musb_platform_disable(musb);
2097 musb_generic_disable(musb);
2098
2099 /* Init IRQ workqueue before request_irq */
2100 INIT_WORK(&musb->irq_work, musb_irq_work);
2101 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
2102 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2103 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2104
2105 /* setup musb parts of the core (especially endpoints) */
2106 status = musb_core_init(plat->config->multipoint
2107 ? MUSB_CONTROLLER_MHDRC
2108 : MUSB_CONTROLLER_HDRC, musb);
2109 if (status < 0)
2110 goto fail3;
2111
2112 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2113
2114 /* attach to the IRQ */
2115 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2116 dev_err(dev, "request_irq %d failed!\n", nIrq);
2117 status = -ENODEV;
2118 goto fail3;
2119 }
2120 musb->nIrq = nIrq;
2121 /* FIXME this handles wakeup irqs wrong */
2122 if (enable_irq_wake(nIrq) == 0) {
2123 musb->irq_wake = 1;
2124 device_init_wakeup(dev, 1);
2125 } else {
2126 musb->irq_wake = 0;
2127 }
2128
2129 /* program PHY to use external vBus if required */
2130 if (plat->extvbus) {
2131 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2132 busctl |= MUSB_ULPI_USE_EXTVBUS;
2133 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2134 }
2135
2136 if (musb->xceiv->otg->default_a) {
2137 MUSB_HST_MODE(musb);
2138 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2139 } else {
2140 MUSB_DEV_MODE(musb);
2141 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2142 }
2143
2144 switch (musb->port_mode) {
2145 case MUSB_PORT_MODE_HOST:
2146 status = musb_host_setup(musb, plat->power);
2147 if (status < 0)
2148 goto fail3;
2149 status = musb_platform_set_mode(musb, MUSB_HOST);
2150 break;
2151 case MUSB_PORT_MODE_GADGET:
2152 status = musb_gadget_setup(musb);
2153 if (status < 0)
2154 goto fail3;
2155 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2156 break;
2157 case MUSB_PORT_MODE_DUAL_ROLE:
2158 status = musb_host_setup(musb, plat->power);
2159 if (status < 0)
2160 goto fail3;
2161 status = musb_gadget_setup(musb);
2162 if (status) {
2163 musb_host_cleanup(musb);
2164 goto fail3;
2165 }
2166 status = musb_platform_set_mode(musb, MUSB_OTG);
2167 break;
2168 default:
2169 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2170 break;
2171 }
2172
2173 if (status < 0)
2174 goto fail3;
2175
2176 status = musb_init_debugfs(musb);
2177 if (status < 0)
2178 goto fail4;
2179
2180 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2181 if (status)
2182 goto fail5;
2183
2184 pm_runtime_put(musb->controller);
2185
2186 return 0;
2187
2188 fail5:
2189 musb_exit_debugfs(musb);
2190
2191 fail4:
2192 musb_gadget_cleanup(musb);
2193 musb_host_cleanup(musb);
2194
2195 fail3:
2196 cancel_work_sync(&musb->irq_work);
2197 cancel_delayed_work_sync(&musb->recover_work);
2198 cancel_delayed_work_sync(&musb->finish_resume_work);
2199 cancel_delayed_work_sync(&musb->deassert_reset_work);
2200 if (musb->dma_controller)
2201 dma_controller_destroy(musb->dma_controller);
2202 fail2_5:
2203 pm_runtime_put_sync(musb->controller);
2204
2205 fail2:
2206 if (musb->irq_wake)
2207 device_init_wakeup(dev, 0);
2208 musb_platform_exit(musb);
2209
2210 fail1:
2211 pm_runtime_disable(musb->controller);
2212 dev_err(musb->controller,
2213 "musb_init_controller failed with status %d\n", status);
2214
2215 musb_free(musb);
2216
2217 fail0:
2218
2219 return status;
2220
2221 }
2222
2223 /*-------------------------------------------------------------------------*/
2224
2225 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2226 * bridge to a platform device; this driver then suffices.
2227 */
2228 static int musb_probe(struct platform_device *pdev)
2229 {
2230 struct device *dev = &pdev->dev;
2231 int irq = platform_get_irq_byname(pdev, "mc");
2232 struct resource *iomem;
2233 void __iomem *base;
2234
2235 if (irq <= 0)
2236 return -ENODEV;
2237
2238 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2239 base = devm_ioremap_resource(dev, iomem);
2240 if (IS_ERR(base))
2241 return PTR_ERR(base);
2242
2243 return musb_init_controller(dev, irq, base);
2244 }
2245
2246 static int musb_remove(struct platform_device *pdev)
2247 {
2248 struct device *dev = &pdev->dev;
2249 struct musb *musb = dev_to_musb(dev);
2250
2251 /* this gets called on rmmod.
2252 * - Host mode: host may still be active
2253 * - Peripheral mode: peripheral is deactivated (or never-activated)
2254 * - OTG mode: both roles are deactivated (or never-activated)
2255 */
2256 musb_exit_debugfs(musb);
2257 musb_shutdown(pdev);
2258
2259 if (musb->dma_controller)
2260 dma_controller_destroy(musb->dma_controller);
2261
2262 cancel_work_sync(&musb->irq_work);
2263 cancel_delayed_work_sync(&musb->recover_work);
2264 cancel_delayed_work_sync(&musb->finish_resume_work);
2265 cancel_delayed_work_sync(&musb->deassert_reset_work);
2266 musb_free(musb);
2267 device_init_wakeup(dev, 0);
2268 return 0;
2269 }
2270
2271 #ifdef CONFIG_PM
2272
2273 static void musb_save_context(struct musb *musb)
2274 {
2275 int i;
2276 void __iomem *musb_base = musb->mregs;
2277 void __iomem *epio;
2278
2279 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2280 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2281 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2282 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2283 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2284 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2285 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2286
2287 for (i = 0; i < musb->config->num_eps; ++i) {
2288 struct musb_hw_ep *hw_ep;
2289
2290 hw_ep = &musb->endpoints[i];
2291 if (!hw_ep)
2292 continue;
2293
2294 epio = hw_ep->regs;
2295 if (!epio)
2296 continue;
2297
2298 musb_writeb(musb_base, MUSB_INDEX, i);
2299 musb->context.index_regs[i].txmaxp =
2300 musb_readw(epio, MUSB_TXMAXP);
2301 musb->context.index_regs[i].txcsr =
2302 musb_readw(epio, MUSB_TXCSR);
2303 musb->context.index_regs[i].rxmaxp =
2304 musb_readw(epio, MUSB_RXMAXP);
2305 musb->context.index_regs[i].rxcsr =
2306 musb_readw(epio, MUSB_RXCSR);
2307
2308 if (musb->dyn_fifo) {
2309 musb->context.index_regs[i].txfifoadd =
2310 musb_read_txfifoadd(musb_base);
2311 musb->context.index_regs[i].rxfifoadd =
2312 musb_read_rxfifoadd(musb_base);
2313 musb->context.index_regs[i].txfifosz =
2314 musb_read_txfifosz(musb_base);
2315 musb->context.index_regs[i].rxfifosz =
2316 musb_read_rxfifosz(musb_base);
2317 }
2318
2319 musb->context.index_regs[i].txtype =
2320 musb_readb(epio, MUSB_TXTYPE);
2321 musb->context.index_regs[i].txinterval =
2322 musb_readb(epio, MUSB_TXINTERVAL);
2323 musb->context.index_regs[i].rxtype =
2324 musb_readb(epio, MUSB_RXTYPE);
2325 musb->context.index_regs[i].rxinterval =
2326 musb_readb(epio, MUSB_RXINTERVAL);
2327
2328 musb->context.index_regs[i].txfunaddr =
2329 musb_read_txfunaddr(musb_base, i);
2330 musb->context.index_regs[i].txhubaddr =
2331 musb_read_txhubaddr(musb_base, i);
2332 musb->context.index_regs[i].txhubport =
2333 musb_read_txhubport(musb_base, i);
2334
2335 musb->context.index_regs[i].rxfunaddr =
2336 musb_read_rxfunaddr(musb_base, i);
2337 musb->context.index_regs[i].rxhubaddr =
2338 musb_read_rxhubaddr(musb_base, i);
2339 musb->context.index_regs[i].rxhubport =
2340 musb_read_rxhubport(musb_base, i);
2341 }
2342 }
2343
2344 static void musb_restore_context(struct musb *musb)
2345 {
2346 int i;
2347 void __iomem *musb_base = musb->mregs;
2348 void __iomem *ep_target_regs;
2349 void __iomem *epio;
2350 u8 power;
2351
2352 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2353 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2354 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2355
2356 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2357 power = musb_readb(musb_base, MUSB_POWER);
2358 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2359 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2360 power |= musb->context.power;
2361 musb_writeb(musb_base, MUSB_POWER, power);
2362
2363 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2364 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2365 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2366 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2367
2368 for (i = 0; i < musb->config->num_eps; ++i) {
2369 struct musb_hw_ep *hw_ep;
2370
2371 hw_ep = &musb->endpoints[i];
2372 if (!hw_ep)
2373 continue;
2374
2375 epio = hw_ep->regs;
2376 if (!epio)
2377 continue;
2378
2379 musb_writeb(musb_base, MUSB_INDEX, i);
2380 musb_writew(epio, MUSB_TXMAXP,
2381 musb->context.index_regs[i].txmaxp);
2382 musb_writew(epio, MUSB_TXCSR,
2383 musb->context.index_regs[i].txcsr);
2384 musb_writew(epio, MUSB_RXMAXP,
2385 musb->context.index_regs[i].rxmaxp);
2386 musb_writew(epio, MUSB_RXCSR,
2387 musb->context.index_regs[i].rxcsr);
2388
2389 if (musb->dyn_fifo) {
2390 musb_write_txfifosz(musb_base,
2391 musb->context.index_regs[i].txfifosz);
2392 musb_write_rxfifosz(musb_base,
2393 musb->context.index_regs[i].rxfifosz);
2394 musb_write_txfifoadd(musb_base,
2395 musb->context.index_regs[i].txfifoadd);
2396 musb_write_rxfifoadd(musb_base,
2397 musb->context.index_regs[i].rxfifoadd);
2398 }
2399
2400 musb_writeb(epio, MUSB_TXTYPE,
2401 musb->context.index_regs[i].txtype);
2402 musb_writeb(epio, MUSB_TXINTERVAL,
2403 musb->context.index_regs[i].txinterval);
2404 musb_writeb(epio, MUSB_RXTYPE,
2405 musb->context.index_regs[i].rxtype);
2406 musb_writeb(epio, MUSB_RXINTERVAL,
2407
2408 musb->context.index_regs[i].rxinterval);
2409 musb_write_txfunaddr(musb_base, i,
2410 musb->context.index_regs[i].txfunaddr);
2411 musb_write_txhubaddr(musb_base, i,
2412 musb->context.index_regs[i].txhubaddr);
2413 musb_write_txhubport(musb_base, i,
2414 musb->context.index_regs[i].txhubport);
2415
2416 ep_target_regs =
2417 musb_read_target_reg_base(i, musb_base);
2418
2419 musb_write_rxfunaddr(ep_target_regs,
2420 musb->context.index_regs[i].rxfunaddr);
2421 musb_write_rxhubaddr(ep_target_regs,
2422 musb->context.index_regs[i].rxhubaddr);
2423 musb_write_rxhubport(ep_target_regs,
2424 musb->context.index_regs[i].rxhubport);
2425 }
2426 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2427 }
2428
2429 static int musb_suspend(struct device *dev)
2430 {
2431 struct musb *musb = dev_to_musb(dev);
2432 unsigned long flags;
2433
2434 spin_lock_irqsave(&musb->lock, flags);
2435
2436 if (is_peripheral_active(musb)) {
2437 /* FIXME force disconnect unless we know USB will wake
2438 * the system up quickly enough to respond ...
2439 */
2440 } else if (is_host_active(musb)) {
2441 /* we know all the children are suspended; sometimes
2442 * they will even be wakeup-enabled.
2443 */
2444 }
2445
2446 musb_save_context(musb);
2447
2448 spin_unlock_irqrestore(&musb->lock, flags);
2449 return 0;
2450 }
2451
2452 static int musb_resume(struct device *dev)
2453 {
2454 struct musb *musb = dev_to_musb(dev);
2455 u8 devctl;
2456 u8 mask;
2457
2458 /*
2459 * For static cmos like DaVinci, register values were preserved
2460 * unless for some reason the whole soc powered down or the USB
2461 * module got reset through the PSC (vs just being disabled).
2462 *
2463 * For the DSPS glue layer though, a full register restore has to
2464 * be done. As it shouldn't harm other platforms, we do it
2465 * unconditionally.
2466 */
2467
2468 musb_restore_context(musb);
2469
2470 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2471 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2472 if ((devctl & mask) != (musb->context.devctl & mask))
2473 musb->port1_status = 0;
2474 if (musb->need_finish_resume) {
2475 musb->need_finish_resume = 0;
2476 schedule_delayed_work(&musb->finish_resume_work,
2477 msecs_to_jiffies(20));
2478 }
2479
2480 /*
2481 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2482 * out of suspend
2483 */
2484 pm_runtime_disable(dev);
2485 pm_runtime_set_active(dev);
2486 pm_runtime_enable(dev);
2487 return 0;
2488 }
2489
2490 static int musb_runtime_suspend(struct device *dev)
2491 {
2492 struct musb *musb = dev_to_musb(dev);
2493
2494 musb_save_context(musb);
2495
2496 return 0;
2497 }
2498
2499 static int musb_runtime_resume(struct device *dev)
2500 {
2501 struct musb *musb = dev_to_musb(dev);
2502 static int first = 1;
2503
2504 /*
2505 * When pm_runtime_get_sync called for the first time in driver
2506 * init, some of the structure is still not initialized which is
2507 * used in restore function. But clock needs to be
2508 * enabled before any register access, so
2509 * pm_runtime_get_sync has to be called.
2510 * Also context restore without save does not make
2511 * any sense
2512 */
2513 if (!first)
2514 musb_restore_context(musb);
2515 first = 0;
2516
2517 if (musb->need_finish_resume) {
2518 musb->need_finish_resume = 0;
2519 schedule_delayed_work(&musb->finish_resume_work,
2520 msecs_to_jiffies(20));
2521 }
2522
2523 return 0;
2524 }
2525
2526 static const struct dev_pm_ops musb_dev_pm_ops = {
2527 .suspend = musb_suspend,
2528 .resume = musb_resume,
2529 .runtime_suspend = musb_runtime_suspend,
2530 .runtime_resume = musb_runtime_resume,
2531 };
2532
2533 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2534 #else
2535 #define MUSB_DEV_PM_OPS NULL
2536 #endif
2537
2538 static struct platform_driver musb_driver = {
2539 .driver = {
2540 .name = (char *)musb_driver_name,
2541 .bus = &platform_bus_type,
2542 .pm = MUSB_DEV_PM_OPS,
2543 },
2544 .probe = musb_probe,
2545 .remove = musb_remove,
2546 .shutdown = musb_shutdown,
2547 };
2548
2549 module_platform_driver(musb_driver);
Linux kernel - Deliverables
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