2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name
[] = MUSB_DRIVER_NAME
;
118 MODULE_DESCRIPTION(DRIVER_INFO
);
119 MODULE_AUTHOR(DRIVER_AUTHOR
);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME
);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb
*dev_to_musb(struct device
*dev
)
128 return dev_get_drvdata(dev
);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy
*phy
, u32 offset
)
136 void __iomem
*addr
= phy
->io_priv
;
142 pm_runtime_get_sync(phy
->io_dev
);
144 /* Make sure the transceiver is not in low power mode */
145 power
= musb_readb(addr
, MUSB_POWER
);
146 power
&= ~MUSB_POWER_SUSPENDM
;
147 musb_writeb(addr
, MUSB_POWER
, power
);
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
154 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
,
155 MUSB_ULPI_REG_REQ
| MUSB_ULPI_RDN_WR
);
157 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
158 & MUSB_ULPI_REG_CMPLT
)) {
166 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
167 r
&= ~MUSB_ULPI_REG_CMPLT
;
168 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
170 ret
= musb_readb(addr
, MUSB_ULPI_REG_DATA
);
173 pm_runtime_put(phy
->io_dev
);
178 static int musb_ulpi_write(struct usb_phy
*phy
, u32 offset
, u32 data
)
180 void __iomem
*addr
= phy
->io_priv
;
186 pm_runtime_get_sync(phy
->io_dev
);
188 /* Make sure the transceiver is not in low power mode */
189 power
= musb_readb(addr
, MUSB_POWER
);
190 power
&= ~MUSB_POWER_SUSPENDM
;
191 musb_writeb(addr
, MUSB_POWER
, power
);
193 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
194 musb_writeb(addr
, MUSB_ULPI_REG_DATA
, (u8
)data
);
195 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, MUSB_ULPI_REG_REQ
);
197 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
198 & MUSB_ULPI_REG_CMPLT
)) {
206 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
207 r
&= ~MUSB_ULPI_REG_CMPLT
;
208 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
211 pm_runtime_put(phy
->io_dev
);
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
220 static struct usb_phy_io_ops musb_ulpi_access
= {
221 .read
= musb_ulpi_read
,
222 .write
= musb_ulpi_write
,
225 /*-------------------------------------------------------------------------*/
227 static u32
musb_default_fifo_offset(u8 epnum
)
229 return 0x20 + (epnum
* 4);
232 /* "flat" mapping: each endpoint has its own i/o address */
233 static void musb_flat_ep_select(void __iomem
*mbase
, u8 epnum
)
237 static u32
musb_flat_ep_offset(u8 epnum
, u16 offset
)
239 return 0x100 + (0x10 * epnum
) + offset
;
242 /* "indexed" mapping: INDEX register controls register bank select */
243 static void musb_indexed_ep_select(void __iomem
*mbase
, u8 epnum
)
245 musb_writeb(mbase
, MUSB_INDEX
, epnum
);
248 static u32
musb_indexed_ep_offset(u8 epnum
, u16 offset
)
250 return 0x10 + offset
;
253 static u8
musb_default_readb(const void __iomem
*addr
, unsigned offset
)
255 return __raw_readb(addr
+ offset
);
258 static void musb_default_writeb(void __iomem
*addr
, unsigned offset
, u8 data
)
260 __raw_writeb(data
, addr
+ offset
);
263 static u16
musb_default_readw(const void __iomem
*addr
, unsigned offset
)
265 return __raw_readw(addr
+ offset
);
268 static void musb_default_writew(void __iomem
*addr
, unsigned offset
, u16 data
)
270 __raw_writew(data
, addr
+ offset
);
273 static u32
musb_default_readl(const void __iomem
*addr
, unsigned offset
)
275 return __raw_readl(addr
+ offset
);
278 static void musb_default_writel(void __iomem
*addr
, unsigned offset
, u32 data
)
280 __raw_writel(data
, addr
+ offset
);
284 * Load an endpoint's FIFO
286 static void musb_default_write_fifo(struct musb_hw_ep
*hw_ep
, u16 len
,
289 struct musb
*musb
= hw_ep
->musb
;
290 void __iomem
*fifo
= hw_ep
->fifo
;
292 if (unlikely(len
== 0))
297 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
298 'T', hw_ep
->epnum
, fifo
, len
, src
);
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src
) == 0)) {
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src
) == 0) {
307 iowrite32_rep(fifo
, src
+ index
, len
>> 2);
308 index
+= len
& ~0x03;
311 musb_writew(fifo
, 0, *(u16
*)&src
[index
]);
316 iowrite16_rep(fifo
, src
+ index
, len
>> 1);
317 index
+= len
& ~0x01;
321 musb_writeb(fifo
, 0, src
[index
]);
324 iowrite8_rep(fifo
, src
, len
);
329 * Unload an endpoint's FIFO
331 static void musb_default_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
333 struct musb
*musb
= hw_ep
->musb
;
334 void __iomem
*fifo
= hw_ep
->fifo
;
336 if (unlikely(len
== 0))
339 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
340 'R', hw_ep
->epnum
, fifo
, len
, dst
);
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst
) == 0)) {
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst
) == 0) {
349 ioread32_rep(fifo
, dst
, len
>> 2);
353 *(u16
*)&dst
[index
] = musb_readw(fifo
, 0);
358 ioread16_rep(fifo
, dst
, len
>> 1);
363 dst
[index
] = musb_readb(fifo
, 0);
366 ioread8_rep(fifo
, dst
, len
);
371 * Old style IO functions
373 u8 (*musb_readb
)(const void __iomem
*addr
, unsigned offset
);
374 EXPORT_SYMBOL_GPL(musb_readb
);
376 void (*musb_writeb
)(void __iomem
*addr
, unsigned offset
, u8 data
);
377 EXPORT_SYMBOL_GPL(musb_writeb
);
379 u16 (*musb_readw
)(const void __iomem
*addr
, unsigned offset
);
380 EXPORT_SYMBOL_GPL(musb_readw
);
382 void (*musb_writew
)(void __iomem
*addr
, unsigned offset
, u16 data
);
383 EXPORT_SYMBOL_GPL(musb_writew
);
385 u32 (*musb_readl
)(const void __iomem
*addr
, unsigned offset
);
386 EXPORT_SYMBOL_GPL(musb_readl
);
388 void (*musb_writel
)(void __iomem
*addr
, unsigned offset
, u32 data
);
389 EXPORT_SYMBOL_GPL(musb_writel
);
392 * New style IO functions
394 void musb_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
396 return hw_ep
->musb
->io
.read_fifo(hw_ep
, len
, dst
);
399 void musb_write_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, const u8
*src
)
401 return hw_ep
->musb
->io
.write_fifo(hw_ep
, len
, src
);
404 /*-------------------------------------------------------------------------*/
406 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
407 static const u8 musb_test_packet
[53] = {
408 /* implicit SYNC then DATA0 to start */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
423 /* implicit CRC16 then EOP to end */
426 void musb_load_testpacket(struct musb
*musb
)
428 void __iomem
*regs
= musb
->endpoints
[0].regs
;
430 musb_ep_select(musb
->mregs
, 0);
431 musb_write_fifo(musb
->control_ep
,
432 sizeof(musb_test_packet
), musb_test_packet
);
433 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_TXPKTRDY
);
436 /*-------------------------------------------------------------------------*/
439 * Handles OTG hnp timeouts, such as b_ase0_brst
441 static void musb_otg_timer_func(unsigned long data
)
443 struct musb
*musb
= (struct musb
*)data
;
446 spin_lock_irqsave(&musb
->lock
, flags
);
447 switch (musb
->xceiv
->otg
->state
) {
448 case OTG_STATE_B_WAIT_ACON
:
449 dev_dbg(musb
->controller
, "HNP: b_wait_acon timeout; back to b_peripheral\n");
450 musb_g_disconnect(musb
);
451 musb
->xceiv
->otg
->state
= OTG_STATE_B_PERIPHERAL
;
454 case OTG_STATE_A_SUSPEND
:
455 case OTG_STATE_A_WAIT_BCON
:
456 dev_dbg(musb
->controller
, "HNP: %s timeout\n",
457 usb_otg_state_string(musb
->xceiv
->otg
->state
));
458 musb_platform_set_vbus(musb
, 0);
459 musb
->xceiv
->otg
->state
= OTG_STATE_A_WAIT_VFALL
;
462 dev_dbg(musb
->controller
, "HNP: Unhandled mode %s\n",
463 usb_otg_state_string(musb
->xceiv
->otg
->state
));
465 spin_unlock_irqrestore(&musb
->lock
, flags
);
469 * Stops the HNP transition. Caller must take care of locking.
471 void musb_hnp_stop(struct musb
*musb
)
473 struct usb_hcd
*hcd
= musb
->hcd
;
474 void __iomem
*mbase
= musb
->mregs
;
477 dev_dbg(musb
->controller
, "HNP: stop from %s\n",
478 usb_otg_state_string(musb
->xceiv
->otg
->state
));
480 switch (musb
->xceiv
->otg
->state
) {
481 case OTG_STATE_A_PERIPHERAL
:
482 musb_g_disconnect(musb
);
483 dev_dbg(musb
->controller
, "HNP: back to %s\n",
484 usb_otg_state_string(musb
->xceiv
->otg
->state
));
486 case OTG_STATE_B_HOST
:
487 dev_dbg(musb
->controller
, "HNP: Disabling HR\n");
489 hcd
->self
.is_b_host
= 0;
490 musb
->xceiv
->otg
->state
= OTG_STATE_B_PERIPHERAL
;
492 reg
= musb_readb(mbase
, MUSB_POWER
);
493 reg
|= MUSB_POWER_SUSPENDM
;
494 musb_writeb(mbase
, MUSB_POWER
, reg
);
495 /* REVISIT: Start SESSION_REQUEST here? */
498 dev_dbg(musb
->controller
, "HNP: Stopping in unknown state %s\n",
499 usb_otg_state_string(musb
->xceiv
->otg
->state
));
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
507 musb
->port1_status
&= ~(USB_PORT_STAT_C_CONNECTION
<< 16);
510 static void musb_generic_disable(struct musb
*musb
);
512 * Interrupt Service Routine to record USB "global" interrupts.
513 * Since these do not happen often and signify things of
514 * paramount importance, it seems OK to check them individually;
515 * the order of the tests is specified in the manual
517 * @param musb instance pointer
518 * @param int_usb register contents
523 static irqreturn_t
musb_stage0_irq(struct musb
*musb
, u8 int_usb
,
526 irqreturn_t handled
= IRQ_NONE
;
528 dev_dbg(musb
->controller
, "<== DevCtl=%02x, int_usb=0x%x\n", devctl
,
531 /* in host mode, the peripheral may issue remote wakeup.
532 * in peripheral mode, the host may resume the link.
533 * spurious RESUME irqs happen too, paired with SUSPEND.
535 if (int_usb
& MUSB_INTR_RESUME
) {
536 handled
= IRQ_HANDLED
;
537 dev_dbg(musb
->controller
, "RESUME (%s)\n", usb_otg_state_string(musb
->xceiv
->otg
->state
));
539 if (devctl
& MUSB_DEVCTL_HM
) {
540 void __iomem
*mbase
= musb
->mregs
;
543 switch (musb
->xceiv
->otg
->state
) {
544 case OTG_STATE_A_SUSPEND
:
545 /* remote wakeup? later, GetPortStatus
546 * will stop RESUME signaling
549 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
550 if (power
& MUSB_POWER_SUSPENDM
) {
552 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
553 dev_dbg(musb
->controller
, "Spurious SUSPENDM\n");
557 power
&= ~MUSB_POWER_SUSPENDM
;
558 musb_writeb(mbase
, MUSB_POWER
,
559 power
| MUSB_POWER_RESUME
);
561 musb
->port1_status
|=
562 (USB_PORT_STAT_C_SUSPEND
<< 16)
563 | MUSB_PORT_STAT_RESUME
;
564 musb
->rh_timer
= jiffies
565 + msecs_to_jiffies(20);
566 musb
->need_finish_resume
= 1;
568 musb
->xceiv
->otg
->state
= OTG_STATE_A_HOST
;
570 musb_host_resume_root_hub(musb
);
572 case OTG_STATE_B_WAIT_ACON
:
573 musb
->xceiv
->otg
->state
= OTG_STATE_B_PERIPHERAL
;
578 WARNING("bogus %s RESUME (%s)\n",
580 usb_otg_state_string(musb
->xceiv
->otg
->state
));
583 switch (musb
->xceiv
->otg
->state
) {
584 case OTG_STATE_A_SUSPEND
:
585 /* possibly DISCONNECT is upcoming */
586 musb
->xceiv
->otg
->state
= OTG_STATE_A_HOST
;
587 musb_host_resume_root_hub(musb
);
589 case OTG_STATE_B_WAIT_ACON
:
590 case OTG_STATE_B_PERIPHERAL
:
591 /* disconnect while suspended? we may
592 * not get a disconnect irq...
594 if ((devctl
& MUSB_DEVCTL_VBUS
)
595 != (3 << MUSB_DEVCTL_VBUS_SHIFT
)
597 musb
->int_usb
|= MUSB_INTR_DISCONNECT
;
598 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
603 case OTG_STATE_B_IDLE
:
604 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
607 WARNING("bogus %s RESUME (%s)\n",
609 usb_otg_state_string(musb
->xceiv
->otg
->state
));
614 /* see manual for the order of the tests */
615 if (int_usb
& MUSB_INTR_SESSREQ
) {
616 void __iomem
*mbase
= musb
->mregs
;
618 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
619 && (devctl
& MUSB_DEVCTL_BDEVICE
)) {
620 dev_dbg(musb
->controller
, "SessReq while on B state\n");
624 dev_dbg(musb
->controller
, "SESSION_REQUEST (%s)\n",
625 usb_otg_state_string(musb
->xceiv
->otg
->state
));
627 /* IRQ arrives from ID pin sense or (later, if VBUS power
628 * is removed) SRP. responses are time critical:
629 * - turn on VBUS (with silicon-specific mechanism)
630 * - go through A_WAIT_VRISE
631 * - ... to A_WAIT_BCON.
632 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
634 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
635 musb
->ep0_stage
= MUSB_EP0_START
;
636 musb
->xceiv
->otg
->state
= OTG_STATE_A_IDLE
;
638 musb_platform_set_vbus(musb
, 1);
640 handled
= IRQ_HANDLED
;
643 if (int_usb
& MUSB_INTR_VBUSERROR
) {
646 /* During connection as an A-Device, we may see a short
647 * current spikes causing voltage drop, because of cable
648 * and peripheral capacitance combined with vbus draw.
649 * (So: less common with truly self-powered devices, where
650 * vbus doesn't act like a power supply.)
652 * Such spikes are short; usually less than ~500 usec, max
653 * of ~2 msec. That is, they're not sustained overcurrent
654 * errors, though they're reported using VBUSERROR irqs.
656 * Workarounds: (a) hardware: use self powered devices.
657 * (b) software: ignore non-repeated VBUS errors.
659 * REVISIT: do delays from lots of DEBUG_KERNEL checks
660 * make trouble here, keeping VBUS < 4.4V ?
662 switch (musb
->xceiv
->otg
->state
) {
663 case OTG_STATE_A_HOST
:
664 /* recovery is dicey once we've gotten past the
665 * initial stages of enumeration, but if VBUS
666 * stayed ok at the other end of the link, and
667 * another reset is due (at least for high speed,
668 * to redo the chirp etc), it might work OK...
670 case OTG_STATE_A_WAIT_BCON
:
671 case OTG_STATE_A_WAIT_VRISE
:
672 if (musb
->vbuserr_retry
) {
673 void __iomem
*mbase
= musb
->mregs
;
675 musb
->vbuserr_retry
--;
677 devctl
|= MUSB_DEVCTL_SESSION
;
678 musb_writeb(mbase
, MUSB_DEVCTL
, devctl
);
680 musb
->port1_status
|=
681 USB_PORT_STAT_OVERCURRENT
682 | (USB_PORT_STAT_C_OVERCURRENT
<< 16);
689 dev_printk(ignore
? KERN_DEBUG
: KERN_ERR
, musb
->controller
,
690 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
691 usb_otg_state_string(musb
->xceiv
->otg
->state
),
694 switch (devctl
& MUSB_DEVCTL_VBUS
) {
695 case 0 << MUSB_DEVCTL_VBUS_SHIFT
:
696 s
= "<SessEnd"; break;
697 case 1 << MUSB_DEVCTL_VBUS_SHIFT
:
698 s
= "<AValid"; break;
699 case 2 << MUSB_DEVCTL_VBUS_SHIFT
:
700 s
= "<VBusValid"; break;
701 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
705 VBUSERR_RETRY_COUNT
- musb
->vbuserr_retry
,
708 /* go through A_WAIT_VFALL then start a new session */
710 musb_platform_set_vbus(musb
, 0);
711 handled
= IRQ_HANDLED
;
714 if (int_usb
& MUSB_INTR_SUSPEND
) {
715 dev_dbg(musb
->controller
, "SUSPEND (%s) devctl %02x\n",
716 usb_otg_state_string(musb
->xceiv
->otg
->state
), devctl
);
717 handled
= IRQ_HANDLED
;
719 switch (musb
->xceiv
->otg
->state
) {
720 case OTG_STATE_A_PERIPHERAL
:
721 /* We also come here if the cable is removed, since
722 * this silicon doesn't report ID-no-longer-grounded.
724 * We depend on T(a_wait_bcon) to shut us down, and
725 * hope users don't do anything dicey during this
726 * undesired detour through A_WAIT_BCON.
729 musb_host_resume_root_hub(musb
);
730 musb_root_disconnect(musb
);
731 musb_platform_try_idle(musb
, jiffies
732 + msecs_to_jiffies(musb
->a_wait_bcon
733 ? : OTG_TIME_A_WAIT_BCON
));
736 case OTG_STATE_B_IDLE
:
737 if (!musb
->is_active
)
739 case OTG_STATE_B_PERIPHERAL
:
740 musb_g_suspend(musb
);
741 musb
->is_active
= musb
->g
.b_hnp_enable
;
742 if (musb
->is_active
) {
743 musb
->xceiv
->otg
->state
= OTG_STATE_B_WAIT_ACON
;
744 dev_dbg(musb
->controller
, "HNP: Setting timer for b_ase0_brst\n");
745 mod_timer(&musb
->otg_timer
, jiffies
747 OTG_TIME_B_ASE0_BRST
));
750 case OTG_STATE_A_WAIT_BCON
:
751 if (musb
->a_wait_bcon
!= 0)
752 musb_platform_try_idle(musb
, jiffies
753 + msecs_to_jiffies(musb
->a_wait_bcon
));
755 case OTG_STATE_A_HOST
:
756 musb
->xceiv
->otg
->state
= OTG_STATE_A_SUSPEND
;
757 musb
->is_active
= musb
->hcd
->self
.b_hnp_enable
;
759 case OTG_STATE_B_HOST
:
760 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
761 dev_dbg(musb
->controller
, "REVISIT: SUSPEND as B_HOST\n");
764 /* "should not happen" */
770 if (int_usb
& MUSB_INTR_CONNECT
) {
771 struct usb_hcd
*hcd
= musb
->hcd
;
773 handled
= IRQ_HANDLED
;
776 musb
->ep0_stage
= MUSB_EP0_START
;
778 /* flush endpoints when transitioning from Device Mode */
779 if (is_peripheral_active(musb
)) {
780 /* REVISIT HNP; just force disconnect */
782 musb
->intrtxe
= musb
->epmask
;
783 musb_writew(musb
->mregs
, MUSB_INTRTXE
, musb
->intrtxe
);
784 musb
->intrrxe
= musb
->epmask
& 0xfffe;
785 musb_writew(musb
->mregs
, MUSB_INTRRXE
, musb
->intrrxe
);
786 musb_writeb(musb
->mregs
, MUSB_INTRUSBE
, 0xf7);
787 musb
->port1_status
&= ~(USB_PORT_STAT_LOW_SPEED
788 |USB_PORT_STAT_HIGH_SPEED
789 |USB_PORT_STAT_ENABLE
791 musb
->port1_status
|= USB_PORT_STAT_CONNECTION
792 |(USB_PORT_STAT_C_CONNECTION
<< 16);
794 /* high vs full speed is just a guess until after reset */
795 if (devctl
& MUSB_DEVCTL_LSDEV
)
796 musb
->port1_status
|= USB_PORT_STAT_LOW_SPEED
;
798 /* indicate new connection to OTG machine */
799 switch (musb
->xceiv
->otg
->state
) {
800 case OTG_STATE_B_PERIPHERAL
:
801 if (int_usb
& MUSB_INTR_SUSPEND
) {
802 dev_dbg(musb
->controller
, "HNP: SUSPEND+CONNECT, now b_host\n");
803 int_usb
&= ~MUSB_INTR_SUSPEND
;
806 dev_dbg(musb
->controller
, "CONNECT as b_peripheral???\n");
808 case OTG_STATE_B_WAIT_ACON
:
809 dev_dbg(musb
->controller
, "HNP: CONNECT, now b_host\n");
811 musb
->xceiv
->otg
->state
= OTG_STATE_B_HOST
;
813 musb
->hcd
->self
.is_b_host
= 1;
814 del_timer(&musb
->otg_timer
);
817 if ((devctl
& MUSB_DEVCTL_VBUS
)
818 == (3 << MUSB_DEVCTL_VBUS_SHIFT
)) {
819 musb
->xceiv
->otg
->state
= OTG_STATE_A_HOST
;
821 hcd
->self
.is_b_host
= 0;
826 musb_host_poke_root_hub(musb
);
828 dev_dbg(musb
->controller
, "CONNECT (%s) devctl %02x\n",
829 usb_otg_state_string(musb
->xceiv
->otg
->state
), devctl
);
832 if (int_usb
& MUSB_INTR_DISCONNECT
) {
833 dev_dbg(musb
->controller
, "DISCONNECT (%s) as %s, devctl %02x\n",
834 usb_otg_state_string(musb
->xceiv
->otg
->state
),
835 MUSB_MODE(musb
), devctl
);
836 handled
= IRQ_HANDLED
;
838 switch (musb
->xceiv
->otg
->state
) {
839 case OTG_STATE_A_HOST
:
840 case OTG_STATE_A_SUSPEND
:
841 musb_host_resume_root_hub(musb
);
842 musb_root_disconnect(musb
);
843 if (musb
->a_wait_bcon
!= 0)
844 musb_platform_try_idle(musb
, jiffies
845 + msecs_to_jiffies(musb
->a_wait_bcon
));
847 case OTG_STATE_B_HOST
:
848 /* REVISIT this behaves for "real disconnect"
849 * cases; make sure the other transitions from
850 * from B_HOST act right too. The B_HOST code
851 * in hnp_stop() is currently not used...
853 musb_root_disconnect(musb
);
855 musb
->hcd
->self
.is_b_host
= 0;
856 musb
->xceiv
->otg
->state
= OTG_STATE_B_PERIPHERAL
;
858 musb_g_disconnect(musb
);
860 case OTG_STATE_A_PERIPHERAL
:
862 musb_root_disconnect(musb
);
864 case OTG_STATE_B_WAIT_ACON
:
866 case OTG_STATE_B_PERIPHERAL
:
867 case OTG_STATE_B_IDLE
:
868 musb_g_disconnect(musb
);
871 WARNING("unhandled DISCONNECT transition (%s)\n",
872 usb_otg_state_string(musb
->xceiv
->otg
->state
));
877 /* mentor saves a bit: bus reset and babble share the same irq.
878 * only host sees babble; only peripheral sees bus reset.
880 if (int_usb
& MUSB_INTR_RESET
) {
881 handled
= IRQ_HANDLED
;
882 if ((devctl
& MUSB_DEVCTL_HM
) != 0) {
884 * Looks like non-HS BABBLE can be ignored, but
885 * HS BABBLE is an error condition. For HS the solution
886 * is to avoid babble in the first place and fix what
887 * caused BABBLE. When HS BABBLE happens we can only
890 if (devctl
& (MUSB_DEVCTL_FSDEV
| MUSB_DEVCTL_LSDEV
))
891 dev_dbg(musb
->controller
, "BABBLE devctl: %02x\n", devctl
);
893 ERR("Stopping host session -- babble\n");
894 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
897 dev_dbg(musb
->controller
, "BUS RESET as %s\n",
898 usb_otg_state_string(musb
->xceiv
->otg
->state
));
899 switch (musb
->xceiv
->otg
->state
) {
900 case OTG_STATE_A_SUSPEND
:
903 case OTG_STATE_A_WAIT_BCON
: /* OPT TD.4.7-900ms */
904 /* never use invalid T(a_wait_bcon) */
905 dev_dbg(musb
->controller
, "HNP: in %s, %d msec timeout\n",
906 usb_otg_state_string(musb
->xceiv
->otg
->state
),
908 mod_timer(&musb
->otg_timer
, jiffies
909 + msecs_to_jiffies(TA_WAIT_BCON(musb
)));
911 case OTG_STATE_A_PERIPHERAL
:
912 del_timer(&musb
->otg_timer
);
915 case OTG_STATE_B_WAIT_ACON
:
916 dev_dbg(musb
->controller
, "HNP: RESET (%s), to b_peripheral\n",
917 usb_otg_state_string(musb
->xceiv
->otg
->state
));
918 musb
->xceiv
->otg
->state
= OTG_STATE_B_PERIPHERAL
;
921 case OTG_STATE_B_IDLE
:
922 musb
->xceiv
->otg
->state
= OTG_STATE_B_PERIPHERAL
;
924 case OTG_STATE_B_PERIPHERAL
:
928 dev_dbg(musb
->controller
, "Unhandled BUS RESET as %s\n",
929 usb_otg_state_string(musb
->xceiv
->otg
->state
));
934 /* handle babble condition */
935 if (int_usb
& MUSB_INTR_BABBLE
&& is_host_active(musb
)) {
936 musb_generic_disable(musb
);
937 schedule_delayed_work(&musb
->recover_work
,
938 msecs_to_jiffies(100));
942 /* REVISIT ... this would be for multiplexing periodic endpoints, or
943 * supporting transfer phasing to prevent exceeding ISO bandwidth
944 * limits of a given frame or microframe.
946 * It's not needed for peripheral side, which dedicates endpoints;
947 * though it _might_ use SOF irqs for other purposes.
949 * And it's not currently needed for host side, which also dedicates
950 * endpoints, relies on TX/RX interval registers, and isn't claimed
951 * to support ISO transfers yet.
953 if (int_usb
& MUSB_INTR_SOF
) {
954 void __iomem
*mbase
= musb
->mregs
;
955 struct musb_hw_ep
*ep
;
959 dev_dbg(musb
->controller
, "START_OF_FRAME\n");
960 handled
= IRQ_HANDLED
;
962 /* start any periodic Tx transfers waiting for current frame */
963 frame
= musb_readw(mbase
, MUSB_FRAME
);
964 ep
= musb
->endpoints
;
965 for (epnum
= 1; (epnum
< musb
->nr_endpoints
)
966 && (musb
->epmask
>= (1 << epnum
));
969 * FIXME handle framecounter wraps (12 bits)
970 * eliminate duplicated StartUrb logic
972 if (ep
->dwWaitFrame
>= frame
) {
974 pr_debug("SOF --> periodic TX%s on %d\n",
975 ep
->tx_channel
? " DMA" : "",
978 musb_h_tx_start(musb
, epnum
);
980 cppi_hostdma_start(musb
, epnum
);
982 } /* end of for loop */
986 schedule_work(&musb
->irq_work
);
991 /*-------------------------------------------------------------------------*/
993 static void musb_generic_disable(struct musb
*musb
)
995 void __iomem
*mbase
= musb
->mregs
;
998 /* disable interrupts */
999 musb_writeb(mbase
, MUSB_INTRUSBE
, 0);
1001 musb_writew(mbase
, MUSB_INTRTXE
, 0);
1003 musb_writew(mbase
, MUSB_INTRRXE
, 0);
1006 musb_writeb(mbase
, MUSB_DEVCTL
, 0);
1008 /* flush pending interrupts */
1009 temp
= musb_readb(mbase
, MUSB_INTRUSB
);
1010 temp
= musb_readw(mbase
, MUSB_INTRTX
);
1011 temp
= musb_readw(mbase
, MUSB_INTRRX
);
1016 * Program the HDRC to start (enable interrupts, dma, etc.).
1018 void musb_start(struct musb
*musb
)
1020 void __iomem
*regs
= musb
->mregs
;
1021 u8 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
1023 dev_dbg(musb
->controller
, "<== devctl %02x\n", devctl
);
1025 /* Set INT enable registers, enable interrupts */
1026 musb
->intrtxe
= musb
->epmask
;
1027 musb_writew(regs
, MUSB_INTRTXE
, musb
->intrtxe
);
1028 musb
->intrrxe
= musb
->epmask
& 0xfffe;
1029 musb_writew(regs
, MUSB_INTRRXE
, musb
->intrrxe
);
1030 musb_writeb(regs
, MUSB_INTRUSBE
, 0xf7);
1032 musb_writeb(regs
, MUSB_TESTMODE
, 0);
1034 /* put into basic highspeed mode and start session */
1035 musb_writeb(regs
, MUSB_POWER
, MUSB_POWER_ISOUPDATE
1037 /* ENSUSPEND wedges tusb */
1038 /* | MUSB_POWER_ENSUSPEND */
1041 musb
->is_active
= 0;
1042 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
1043 devctl
&= ~MUSB_DEVCTL_SESSION
;
1045 /* session started after:
1046 * (a) ID-grounded irq, host mode;
1047 * (b) vbus present/connect IRQ, peripheral mode;
1048 * (c) peripheral initiates, using SRP
1050 if (musb
->port_mode
!= MUSB_PORT_MODE_HOST
&&
1051 (devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
) {
1052 musb
->is_active
= 1;
1054 devctl
|= MUSB_DEVCTL_SESSION
;
1057 musb_platform_enable(musb
);
1058 musb_writeb(regs
, MUSB_DEVCTL
, devctl
);
1062 * Make the HDRC stop (disable interrupts, etc.);
1063 * reversible by musb_start
1064 * called on gadget driver unregister
1065 * with controller locked, irqs blocked
1066 * acts as a NOP unless some role activated the hardware
1068 void musb_stop(struct musb
*musb
)
1070 /* stop IRQs, timers, ... */
1071 musb_platform_disable(musb
);
1072 musb_generic_disable(musb
);
1073 dev_dbg(musb
->controller
, "HDRC disabled\n");
1076 * - mark host and/or peripheral drivers unusable/inactive
1077 * - disable DMA (and enable it in HdrcStart)
1078 * - make sure we can musb_start() after musb_stop(); with
1079 * OTG mode, gadget driver module rmmod/modprobe cycles that
1082 musb_platform_try_idle(musb
, 0);
1085 static void musb_shutdown(struct platform_device
*pdev
)
1087 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
1088 unsigned long flags
;
1090 pm_runtime_get_sync(musb
->controller
);
1092 musb_host_cleanup(musb
);
1093 musb_gadget_cleanup(musb
);
1095 spin_lock_irqsave(&musb
->lock
, flags
);
1096 musb_platform_disable(musb
);
1097 musb_generic_disable(musb
);
1098 spin_unlock_irqrestore(&musb
->lock
, flags
);
1100 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
1101 musb_platform_exit(musb
);
1103 pm_runtime_put(musb
->controller
);
1104 /* FIXME power down */
1108 /*-------------------------------------------------------------------------*/
1111 * The silicon either has hard-wired endpoint configurations, or else
1112 * "dynamic fifo" sizing. The driver has support for both, though at this
1113 * writing only the dynamic sizing is very well tested. Since we switched
1114 * away from compile-time hardware parameters, we can no longer rely on
1115 * dead code elimination to leave only the relevant one in the object file.
1117 * We don't currently use dynamic fifo setup capability to do anything
1118 * more than selecting one of a bunch of predefined configurations.
1120 static ushort fifo_mode
;
1122 /* "modprobe ... fifo_mode=1" etc */
1123 module_param(fifo_mode
, ushort
, 0);
1124 MODULE_PARM_DESC(fifo_mode
, "initial endpoint configuration");
1127 * tables defining fifo_mode values. define more if you like.
1128 * for host side, make sure both halves of ep1 are set up.
1131 /* mode 0 - fits in 2KB */
1132 static struct musb_fifo_cfg mode_0_cfg
[] = {
1133 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1134 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1135 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1136 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1137 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1140 /* mode 1 - fits in 4KB */
1141 static struct musb_fifo_cfg mode_1_cfg
[] = {
1142 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1143 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1144 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1145 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1146 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1149 /* mode 2 - fits in 4KB */
1150 static struct musb_fifo_cfg mode_2_cfg
[] = {
1151 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1152 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1153 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1154 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1155 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1156 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1159 /* mode 3 - fits in 4KB */
1160 static struct musb_fifo_cfg mode_3_cfg
[] = {
1161 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1162 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1163 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1164 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1165 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1166 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1169 /* mode 4 - fits in 16KB */
1170 static struct musb_fifo_cfg mode_4_cfg
[] = {
1171 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1172 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1173 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1174 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1175 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1176 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1177 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1178 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1179 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1180 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1181 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 512, },
1182 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 512, },
1183 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 512, },
1184 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 512, },
1185 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 512, },
1186 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 512, },
1187 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 512, },
1188 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 512, },
1189 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 256, },
1190 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 64, },
1191 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 256, },
1192 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 64, },
1193 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 256, },
1194 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 64, },
1195 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 4096, },
1196 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1197 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1200 /* mode 5 - fits in 8KB */
1201 static struct musb_fifo_cfg mode_5_cfg
[] = {
1202 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1203 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1204 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1205 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1206 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1207 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1208 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1209 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1210 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1211 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1212 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 32, },
1213 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 32, },
1214 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 32, },
1215 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 32, },
1216 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 32, },
1217 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 32, },
1218 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 32, },
1219 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 32, },
1220 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 32, },
1221 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 32, },
1222 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 32, },
1223 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 32, },
1224 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 32, },
1225 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 32, },
1226 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1227 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1228 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1232 * configure a fifo; for non-shared endpoints, this may be called
1233 * once for a tx fifo and once for an rx fifo.
1235 * returns negative errno or offset for next fifo.
1238 fifo_setup(struct musb
*musb
, struct musb_hw_ep
*hw_ep
,
1239 const struct musb_fifo_cfg
*cfg
, u16 offset
)
1241 void __iomem
*mbase
= musb
->mregs
;
1243 u16 maxpacket
= cfg
->maxpacket
;
1244 u16 c_off
= offset
>> 3;
1247 /* expect hw_ep has already been zero-initialized */
1249 size
= ffs(max(maxpacket
, (u16
) 8)) - 1;
1250 maxpacket
= 1 << size
;
1253 if (cfg
->mode
== BUF_DOUBLE
) {
1254 if ((offset
+ (maxpacket
<< 1)) >
1255 (1 << (musb
->config
->ram_bits
+ 2)))
1257 c_size
|= MUSB_FIFOSZ_DPB
;
1259 if ((offset
+ maxpacket
) > (1 << (musb
->config
->ram_bits
+ 2)))
1263 /* configure the FIFO */
1264 musb_writeb(mbase
, MUSB_INDEX
, hw_ep
->epnum
);
1266 /* EP0 reserved endpoint for control, bidirectional;
1267 * EP1 reserved for bulk, two unidirectional halves.
1269 if (hw_ep
->epnum
== 1)
1270 musb
->bulk_ep
= hw_ep
;
1271 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1272 switch (cfg
->style
) {
1274 musb_write_txfifosz(mbase
, c_size
);
1275 musb_write_txfifoadd(mbase
, c_off
);
1276 hw_ep
->tx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1277 hw_ep
->max_packet_sz_tx
= maxpacket
;
1280 musb_write_rxfifosz(mbase
, c_size
);
1281 musb_write_rxfifoadd(mbase
, c_off
);
1282 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1283 hw_ep
->max_packet_sz_rx
= maxpacket
;
1286 musb_write_txfifosz(mbase
, c_size
);
1287 musb_write_txfifoadd(mbase
, c_off
);
1288 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1289 hw_ep
->max_packet_sz_rx
= maxpacket
;
1291 musb_write_rxfifosz(mbase
, c_size
);
1292 musb_write_rxfifoadd(mbase
, c_off
);
1293 hw_ep
->tx_double_buffered
= hw_ep
->rx_double_buffered
;
1294 hw_ep
->max_packet_sz_tx
= maxpacket
;
1296 hw_ep
->is_shared_fifo
= true;
1300 /* NOTE rx and tx endpoint irqs aren't managed separately,
1301 * which happens to be ok
1303 musb
->epmask
|= (1 << hw_ep
->epnum
);
1305 return offset
+ (maxpacket
<< ((c_size
& MUSB_FIFOSZ_DPB
) ? 1 : 0));
1308 static struct musb_fifo_cfg ep0_cfg
= {
1309 .style
= FIFO_RXTX
, .maxpacket
= 64,
1312 static int ep_config_from_table(struct musb
*musb
)
1314 const struct musb_fifo_cfg
*cfg
;
1317 struct musb_hw_ep
*hw_ep
= musb
->endpoints
;
1319 if (musb
->config
->fifo_cfg
) {
1320 cfg
= musb
->config
->fifo_cfg
;
1321 n
= musb
->config
->fifo_cfg_size
;
1325 switch (fifo_mode
) {
1331 n
= ARRAY_SIZE(mode_0_cfg
);
1335 n
= ARRAY_SIZE(mode_1_cfg
);
1339 n
= ARRAY_SIZE(mode_2_cfg
);
1343 n
= ARRAY_SIZE(mode_3_cfg
);
1347 n
= ARRAY_SIZE(mode_4_cfg
);
1351 n
= ARRAY_SIZE(mode_5_cfg
);
1355 printk(KERN_DEBUG
"%s: setup fifo_mode %d\n",
1356 musb_driver_name
, fifo_mode
);
1360 offset
= fifo_setup(musb
, hw_ep
, &ep0_cfg
, 0);
1361 /* assert(offset > 0) */
1363 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1364 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1367 for (i
= 0; i
< n
; i
++) {
1368 u8 epn
= cfg
->hw_ep_num
;
1370 if (epn
>= musb
->config
->num_eps
) {
1371 pr_debug("%s: invalid ep %d\n",
1372 musb_driver_name
, epn
);
1375 offset
= fifo_setup(musb
, hw_ep
+ epn
, cfg
++, offset
);
1377 pr_debug("%s: mem overrun, ep %d\n",
1378 musb_driver_name
, epn
);
1382 musb
->nr_endpoints
= max(epn
, musb
->nr_endpoints
);
1385 printk(KERN_DEBUG
"%s: %d/%d max ep, %d/%d memory\n",
1387 n
+ 1, musb
->config
->num_eps
* 2 - 1,
1388 offset
, (1 << (musb
->config
->ram_bits
+ 2)));
1390 if (!musb
->bulk_ep
) {
1391 pr_debug("%s: missing bulk\n", musb_driver_name
);
1400 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1401 * @param musb the controller
1403 static int ep_config_from_hw(struct musb
*musb
)
1406 struct musb_hw_ep
*hw_ep
;
1407 void __iomem
*mbase
= musb
->mregs
;
1410 dev_dbg(musb
->controller
, "<== static silicon ep config\n");
1412 /* FIXME pick up ep0 maxpacket size */
1414 for (epnum
= 1; epnum
< musb
->config
->num_eps
; epnum
++) {
1415 musb_ep_select(mbase
, epnum
);
1416 hw_ep
= musb
->endpoints
+ epnum
;
1418 ret
= musb_read_fifosize(musb
, hw_ep
, epnum
);
1422 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1424 /* pick an RX/TX endpoint for bulk */
1425 if (hw_ep
->max_packet_sz_tx
< 512
1426 || hw_ep
->max_packet_sz_rx
< 512)
1429 /* REVISIT: this algorithm is lazy, we should at least
1430 * try to pick a double buffered endpoint.
1434 musb
->bulk_ep
= hw_ep
;
1437 if (!musb
->bulk_ep
) {
1438 pr_debug("%s: missing bulk\n", musb_driver_name
);
1445 enum { MUSB_CONTROLLER_MHDRC
, MUSB_CONTROLLER_HDRC
, };
1447 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1448 * configure endpoints, or take their config from silicon
1450 static int musb_core_init(u16 musb_type
, struct musb
*musb
)
1454 char aInfo
[90], aRevision
[32], aDate
[12];
1455 void __iomem
*mbase
= musb
->mregs
;
1459 /* log core options (read using indexed model) */
1460 reg
= musb_read_configdata(mbase
);
1462 strcpy(aInfo
, (reg
& MUSB_CONFIGDATA_UTMIDW
) ? "UTMI-16" : "UTMI-8");
1463 if (reg
& MUSB_CONFIGDATA_DYNFIFO
) {
1464 strcat(aInfo
, ", dyn FIFOs");
1465 musb
->dyn_fifo
= true;
1467 if (reg
& MUSB_CONFIGDATA_MPRXE
) {
1468 strcat(aInfo
, ", bulk combine");
1469 musb
->bulk_combine
= true;
1471 if (reg
& MUSB_CONFIGDATA_MPTXE
) {
1472 strcat(aInfo
, ", bulk split");
1473 musb
->bulk_split
= true;
1475 if (reg
& MUSB_CONFIGDATA_HBRXE
) {
1476 strcat(aInfo
, ", HB-ISO Rx");
1477 musb
->hb_iso_rx
= true;
1479 if (reg
& MUSB_CONFIGDATA_HBTXE
) {
1480 strcat(aInfo
, ", HB-ISO Tx");
1481 musb
->hb_iso_tx
= true;
1483 if (reg
& MUSB_CONFIGDATA_SOFTCONE
)
1484 strcat(aInfo
, ", SoftConn");
1486 printk(KERN_DEBUG
"%s: ConfigData=0x%02x (%s)\n",
1487 musb_driver_name
, reg
, aInfo
);
1490 if (MUSB_CONTROLLER_MHDRC
== musb_type
) {
1491 musb
->is_multipoint
= 1;
1494 musb
->is_multipoint
= 0;
1496 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1498 "%s: kernel must blacklist external hubs\n",
1503 /* log release info */
1504 musb
->hwvers
= musb_read_hwvers(mbase
);
1505 snprintf(aRevision
, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb
->hwvers
),
1506 MUSB_HWVERS_MINOR(musb
->hwvers
),
1507 (musb
->hwvers
& MUSB_HWVERS_RC
) ? "RC" : "");
1508 printk(KERN_DEBUG
"%s: %sHDRC RTL version %s %s\n",
1509 musb_driver_name
, type
, aRevision
, aDate
);
1512 musb_configure_ep0(musb
);
1514 /* discover endpoint configuration */
1515 musb
->nr_endpoints
= 1;
1519 status
= ep_config_from_table(musb
);
1521 status
= ep_config_from_hw(musb
);
1526 /* finish init, and print endpoint config */
1527 for (i
= 0; i
< musb
->nr_endpoints
; i
++) {
1528 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ i
;
1530 hw_ep
->fifo
= musb
->io
.fifo_offset(i
) + mbase
;
1531 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1532 if (musb
->io
.quirks
& MUSB_IN_TUSB
) {
1533 hw_ep
->fifo_async
= musb
->async
+ 0x400 +
1534 musb
->io
.fifo_offset(i
);
1535 hw_ep
->fifo_sync
= musb
->sync
+ 0x400 +
1536 musb
->io
.fifo_offset(i
);
1537 hw_ep
->fifo_sync_va
=
1538 musb
->sync_va
+ 0x400 + musb
->io
.fifo_offset(i
);
1541 hw_ep
->conf
= mbase
- 0x400 + TUSB_EP0_CONF
;
1543 hw_ep
->conf
= mbase
+ 0x400 +
1544 (((i
- 1) & 0xf) << 2);
1548 hw_ep
->regs
= musb
->io
.ep_offset(i
, 0) + mbase
;
1549 hw_ep
->target_regs
= musb_read_target_reg_base(i
, mbase
);
1550 hw_ep
->rx_reinit
= 1;
1551 hw_ep
->tx_reinit
= 1;
1553 if (hw_ep
->max_packet_sz_tx
) {
1554 dev_dbg(musb
->controller
,
1555 "%s: hw_ep %d%s, %smax %d\n",
1556 musb_driver_name
, i
,
1557 hw_ep
->is_shared_fifo
? "shared" : "tx",
1558 hw_ep
->tx_double_buffered
1559 ? "doublebuffer, " : "",
1560 hw_ep
->max_packet_sz_tx
);
1562 if (hw_ep
->max_packet_sz_rx
&& !hw_ep
->is_shared_fifo
) {
1563 dev_dbg(musb
->controller
,
1564 "%s: hw_ep %d%s, %smax %d\n",
1565 musb_driver_name
, i
,
1567 hw_ep
->rx_double_buffered
1568 ? "doublebuffer, " : "",
1569 hw_ep
->max_packet_sz_rx
);
1571 if (!(hw_ep
->max_packet_sz_tx
|| hw_ep
->max_packet_sz_rx
))
1572 dev_dbg(musb
->controller
, "hw_ep %d not configured\n", i
);
1578 /*-------------------------------------------------------------------------*/
1581 * handle all the irqs defined by the HDRC core. for now we expect: other
1582 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1583 * will be assigned, and the irq will already have been acked.
1585 * called in irq context with spinlock held, irqs blocked
1587 irqreturn_t
musb_interrupt(struct musb
*musb
)
1589 irqreturn_t retval
= IRQ_NONE
;
1594 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1596 dev_dbg(musb
->controller
, "** IRQ %s usb%04x tx%04x rx%04x\n",
1597 is_host_active(musb
) ? "host" : "peripheral",
1598 musb
->int_usb
, musb
->int_tx
, musb
->int_rx
);
1600 /* the core can interrupt us for multiple reasons; docs have
1601 * a generic interrupt flowchart to follow
1604 retval
|= musb_stage0_irq(musb
, musb
->int_usb
,
1607 /* "stage 1" is handling endpoint irqs */
1609 /* handle endpoint 0 first */
1610 if (musb
->int_tx
& 1) {
1611 if (is_host_active(musb
))
1612 retval
|= musb_h_ep0_irq(musb
);
1614 retval
|= musb_g_ep0_irq(musb
);
1617 /* RX on endpoints 1-15 */
1618 reg
= musb
->int_rx
>> 1;
1622 /* musb_ep_select(musb->mregs, ep_num); */
1623 /* REVISIT just retval = ep->rx_irq(...) */
1624 retval
= IRQ_HANDLED
;
1625 if (is_host_active(musb
))
1626 musb_host_rx(musb
, ep_num
);
1628 musb_g_rx(musb
, ep_num
);
1635 /* TX on endpoints 1-15 */
1636 reg
= musb
->int_tx
>> 1;
1640 /* musb_ep_select(musb->mregs, ep_num); */
1641 /* REVISIT just retval |= ep->tx_irq(...) */
1642 retval
= IRQ_HANDLED
;
1643 if (is_host_active(musb
))
1644 musb_host_tx(musb
, ep_num
);
1646 musb_g_tx(musb
, ep_num
);
1654 EXPORT_SYMBOL_GPL(musb_interrupt
);
1656 #ifndef CONFIG_MUSB_PIO_ONLY
1657 static bool use_dma
= 1;
1659 /* "modprobe ... use_dma=0" etc */
1660 module_param(use_dma
, bool, 0);
1661 MODULE_PARM_DESC(use_dma
, "enable/disable use of DMA");
1663 void musb_dma_completion(struct musb
*musb
, u8 epnum
, u8 transmit
)
1665 /* called with controller lock already held */
1668 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1669 if (!is_cppi_enabled()) {
1671 if (is_host_active(musb
))
1672 musb_h_ep0_irq(musb
);
1674 musb_g_ep0_irq(musb
);
1678 /* endpoints 1..15 */
1680 if (is_host_active(musb
))
1681 musb_host_tx(musb
, epnum
);
1683 musb_g_tx(musb
, epnum
);
1686 if (is_host_active(musb
))
1687 musb_host_rx(musb
, epnum
);
1689 musb_g_rx(musb
, epnum
);
1693 EXPORT_SYMBOL_GPL(musb_dma_completion
);
1699 /*-------------------------------------------------------------------------*/
1702 musb_mode_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1704 struct musb
*musb
= dev_to_musb(dev
);
1705 unsigned long flags
;
1708 spin_lock_irqsave(&musb
->lock
, flags
);
1709 ret
= sprintf(buf
, "%s\n", usb_otg_state_string(musb
->xceiv
->otg
->state
));
1710 spin_unlock_irqrestore(&musb
->lock
, flags
);
1716 musb_mode_store(struct device
*dev
, struct device_attribute
*attr
,
1717 const char *buf
, size_t n
)
1719 struct musb
*musb
= dev_to_musb(dev
);
1720 unsigned long flags
;
1723 spin_lock_irqsave(&musb
->lock
, flags
);
1724 if (sysfs_streq(buf
, "host"))
1725 status
= musb_platform_set_mode(musb
, MUSB_HOST
);
1726 else if (sysfs_streq(buf
, "peripheral"))
1727 status
= musb_platform_set_mode(musb
, MUSB_PERIPHERAL
);
1728 else if (sysfs_streq(buf
, "otg"))
1729 status
= musb_platform_set_mode(musb
, MUSB_OTG
);
1732 spin_unlock_irqrestore(&musb
->lock
, flags
);
1734 return (status
== 0) ? n
: status
;
1736 static DEVICE_ATTR(mode
, 0644, musb_mode_show
, musb_mode_store
);
1739 musb_vbus_store(struct device
*dev
, struct device_attribute
*attr
,
1740 const char *buf
, size_t n
)
1742 struct musb
*musb
= dev_to_musb(dev
);
1743 unsigned long flags
;
1746 if (sscanf(buf
, "%lu", &val
) < 1) {
1747 dev_err(dev
, "Invalid VBUS timeout ms value\n");
1751 spin_lock_irqsave(&musb
->lock
, flags
);
1752 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1753 musb
->a_wait_bcon
= val
? max_t(int, val
, OTG_TIME_A_WAIT_BCON
) : 0 ;
1754 if (musb
->xceiv
->otg
->state
== OTG_STATE_A_WAIT_BCON
)
1755 musb
->is_active
= 0;
1756 musb_platform_try_idle(musb
, jiffies
+ msecs_to_jiffies(val
));
1757 spin_unlock_irqrestore(&musb
->lock
, flags
);
1763 musb_vbus_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1765 struct musb
*musb
= dev_to_musb(dev
);
1766 unsigned long flags
;
1770 spin_lock_irqsave(&musb
->lock
, flags
);
1771 val
= musb
->a_wait_bcon
;
1772 /* FIXME get_vbus_status() is normally #defined as false...
1773 * and is effectively TUSB-specific.
1775 vbus
= musb_platform_get_vbus_status(musb
);
1776 spin_unlock_irqrestore(&musb
->lock
, flags
);
1778 return sprintf(buf
, "Vbus %s, timeout %lu msec\n",
1779 vbus
? "on" : "off", val
);
1781 static DEVICE_ATTR(vbus
, 0644, musb_vbus_show
, musb_vbus_store
);
1783 /* Gadget drivers can't know that a host is connected so they might want
1784 * to start SRP, but users can. This allows userspace to trigger SRP.
1787 musb_srp_store(struct device
*dev
, struct device_attribute
*attr
,
1788 const char *buf
, size_t n
)
1790 struct musb
*musb
= dev_to_musb(dev
);
1793 if (sscanf(buf
, "%hu", &srp
) != 1
1795 dev_err(dev
, "SRP: Value must be 1\n");
1800 musb_g_wakeup(musb
);
1804 static DEVICE_ATTR(srp
, 0644, NULL
, musb_srp_store
);
1806 static struct attribute
*musb_attributes
[] = {
1807 &dev_attr_mode
.attr
,
1808 &dev_attr_vbus
.attr
,
1813 static const struct attribute_group musb_attr_group
= {
1814 .attrs
= musb_attributes
,
1817 /* Only used to provide driver mode change events */
1818 static void musb_irq_work(struct work_struct
*data
)
1820 struct musb
*musb
= container_of(data
, struct musb
, irq_work
);
1822 if (musb
->xceiv
->otg
->state
!= musb
->xceiv_old_state
) {
1823 musb
->xceiv_old_state
= musb
->xceiv
->otg
->state
;
1824 sysfs_notify(&musb
->controller
->kobj
, NULL
, "mode");
1828 /* Recover from babble interrupt conditions */
1829 static void musb_recover_work(struct work_struct
*data
)
1831 struct musb
*musb
= container_of(data
, struct musb
, recover_work
.work
);
1834 ret
= musb_platform_reset(musb
);
1838 usb_phy_vbus_off(musb
->xceiv
);
1839 usleep_range(100, 200);
1841 usb_phy_vbus_on(musb
->xceiv
);
1842 usleep_range(100, 200);
1845 * When a babble condition occurs, the musb controller
1846 * removes the session bit and the endpoint config is lost.
1849 status
= ep_config_from_table(musb
);
1851 status
= ep_config_from_hw(musb
);
1853 /* start the session again */
1858 /* --------------------------------------------------------------------------
1862 static struct musb
*allocate_instance(struct device
*dev
,
1863 struct musb_hdrc_config
*config
, void __iomem
*mbase
)
1866 struct musb_hw_ep
*ep
;
1870 musb
= devm_kzalloc(dev
, sizeof(*musb
), GFP_KERNEL
);
1874 INIT_LIST_HEAD(&musb
->control
);
1875 INIT_LIST_HEAD(&musb
->in_bulk
);
1876 INIT_LIST_HEAD(&musb
->out_bulk
);
1878 musb
->vbuserr_retry
= VBUSERR_RETRY_COUNT
;
1879 musb
->a_wait_bcon
= OTG_TIME_A_WAIT_BCON
;
1880 musb
->mregs
= mbase
;
1881 musb
->ctrl_base
= mbase
;
1882 musb
->nIrq
= -ENODEV
;
1883 musb
->config
= config
;
1884 BUG_ON(musb
->config
->num_eps
> MUSB_C_NUM_EPS
);
1885 for (epnum
= 0, ep
= musb
->endpoints
;
1886 epnum
< musb
->config
->num_eps
;
1892 musb
->controller
= dev
;
1894 ret
= musb_host_alloc(musb
);
1898 dev_set_drvdata(dev
, musb
);
1906 static void musb_free(struct musb
*musb
)
1908 /* this has multiple entry modes. it handles fault cleanup after
1909 * probe(), where things may be partially set up, as well as rmmod
1910 * cleanup after everything's been de-activated.
1914 sysfs_remove_group(&musb
->controller
->kobj
, &musb_attr_group
);
1917 if (musb
->nIrq
>= 0) {
1919 disable_irq_wake(musb
->nIrq
);
1920 free_irq(musb
->nIrq
, musb
);
1923 musb_host_free(musb
);
1926 static void musb_deassert_reset(struct work_struct
*work
)
1929 unsigned long flags
;
1931 musb
= container_of(work
, struct musb
, deassert_reset_work
.work
);
1933 spin_lock_irqsave(&musb
->lock
, flags
);
1935 if (musb
->port1_status
& USB_PORT_STAT_RESET
)
1936 musb_port_reset(musb
, false);
1938 spin_unlock_irqrestore(&musb
->lock
, flags
);
1942 * Perform generic per-controller initialization.
1944 * @dev: the controller (already clocked, etc)
1946 * @ctrl: virtual address of controller registers,
1947 * not yet corrected for platform-specific offsets
1950 musb_init_controller(struct device
*dev
, int nIrq
, void __iomem
*ctrl
)
1954 struct musb_hdrc_platform_data
*plat
= dev_get_platdata(dev
);
1956 /* The driver might handle more features than the board; OK.
1957 * Fail when the board needs a feature that's not enabled.
1960 dev_dbg(dev
, "no platform_data?\n");
1966 musb
= allocate_instance(dev
, plat
->config
, ctrl
);
1972 spin_lock_init(&musb
->lock
);
1973 musb
->board_set_power
= plat
->set_power
;
1974 musb
->min_power
= plat
->min_power
;
1975 musb
->ops
= plat
->platform_ops
;
1976 musb
->port_mode
= plat
->mode
;
1979 * Initialize the default IO functions. At least omap2430 needs
1980 * these early. We initialize the platform specific IO functions
1983 musb_readb
= musb_default_readb
;
1984 musb_writeb
= musb_default_writeb
;
1985 musb_readw
= musb_default_readw
;
1986 musb_writew
= musb_default_writew
;
1987 musb_readl
= musb_default_readl
;
1988 musb_writel
= musb_default_writel
;
1990 /* We need musb_read/write functions initialized for PM */
1991 pm_runtime_use_autosuspend(musb
->controller
);
1992 pm_runtime_set_autosuspend_delay(musb
->controller
, 200);
1993 pm_runtime_irq_safe(musb
->controller
);
1994 pm_runtime_enable(musb
->controller
);
1996 /* The musb_platform_init() call:
1997 * - adjusts musb->mregs
1998 * - sets the musb->isr
1999 * - may initialize an integrated transceiver
2000 * - initializes musb->xceiv, usually by otg_get_phy()
2001 * - stops powering VBUS
2003 * There are various transceiver configurations. Blackfin,
2004 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2005 * external/discrete ones in various flavors (twl4030 family,
2006 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2008 status
= musb_platform_init(musb
);
2017 if (musb
->ops
->quirks
)
2018 musb
->io
.quirks
= musb
->ops
->quirks
;
2020 /* At least tusb6010 has it's own offsets.. */
2021 if (musb
->ops
->ep_offset
)
2022 musb
->io
.ep_offset
= musb
->ops
->ep_offset
;
2023 if (musb
->ops
->ep_select
)
2024 musb
->io
.ep_select
= musb
->ops
->ep_select
;
2026 /* ..and some devices use indexed offset or flat offset */
2027 if (musb
->io
.quirks
& MUSB_INDEXED_EP
) {
2028 musb
->io
.ep_offset
= musb_indexed_ep_offset
;
2029 musb
->io
.ep_select
= musb_indexed_ep_select
;
2031 musb
->io
.ep_offset
= musb_flat_ep_offset
;
2032 musb
->io
.ep_select
= musb_flat_ep_select
;
2035 if (musb
->ops
->fifo_mode
)
2036 fifo_mode
= musb
->ops
->fifo_mode
;
2040 if (musb
->ops
->fifo_offset
)
2041 musb
->io
.fifo_offset
= musb
->ops
->fifo_offset
;
2043 musb
->io
.fifo_offset
= musb_default_fifo_offset
;
2045 if (musb
->ops
->readb
)
2046 musb_readb
= musb
->ops
->readb
;
2047 if (musb
->ops
->writeb
)
2048 musb_writeb
= musb
->ops
->writeb
;
2049 if (musb
->ops
->readw
)
2050 musb_readw
= musb
->ops
->readw
;
2051 if (musb
->ops
->writew
)
2052 musb_writew
= musb
->ops
->writew
;
2053 if (musb
->ops
->readl
)
2054 musb_readl
= musb
->ops
->readl
;
2055 if (musb
->ops
->writel
)
2056 musb_writel
= musb
->ops
->writel
;
2058 if (musb
->ops
->read_fifo
)
2059 musb
->io
.read_fifo
= musb
->ops
->read_fifo
;
2061 musb
->io
.read_fifo
= musb_default_read_fifo
;
2063 if (musb
->ops
->write_fifo
)
2064 musb
->io
.write_fifo
= musb
->ops
->write_fifo
;
2066 musb
->io
.write_fifo
= musb_default_write_fifo
;
2068 if (!musb
->xceiv
->io_ops
) {
2069 musb
->xceiv
->io_dev
= musb
->controller
;
2070 musb
->xceiv
->io_priv
= musb
->mregs
;
2071 musb
->xceiv
->io_ops
= &musb_ulpi_access
;
2074 pm_runtime_get_sync(musb
->controller
);
2076 if (use_dma
&& dev
->dma_mask
) {
2077 musb
->dma_controller
= dma_controller_create(musb
, musb
->mregs
);
2078 if (IS_ERR(musb
->dma_controller
)) {
2079 status
= PTR_ERR(musb
->dma_controller
);
2084 /* be sure interrupts are disabled before connecting ISR */
2085 musb_platform_disable(musb
);
2086 musb_generic_disable(musb
);
2088 /* Init IRQ workqueue before request_irq */
2089 INIT_WORK(&musb
->irq_work
, musb_irq_work
);
2090 INIT_DELAYED_WORK(&musb
->recover_work
, musb_recover_work
);
2091 INIT_DELAYED_WORK(&musb
->deassert_reset_work
, musb_deassert_reset
);
2092 INIT_DELAYED_WORK(&musb
->finish_resume_work
, musb_host_finish_resume
);
2094 /* setup musb parts of the core (especially endpoints) */
2095 status
= musb_core_init(plat
->config
->multipoint
2096 ? MUSB_CONTROLLER_MHDRC
2097 : MUSB_CONTROLLER_HDRC
, musb
);
2101 setup_timer(&musb
->otg_timer
, musb_otg_timer_func
, (unsigned long) musb
);
2103 /* attach to the IRQ */
2104 if (request_irq(nIrq
, musb
->isr
, 0, dev_name(dev
), musb
)) {
2105 dev_err(dev
, "request_irq %d failed!\n", nIrq
);
2110 /* FIXME this handles wakeup irqs wrong */
2111 if (enable_irq_wake(nIrq
) == 0) {
2113 device_init_wakeup(dev
, 1);
2118 /* program PHY to use external vBus if required */
2119 if (plat
->extvbus
) {
2120 u8 busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
2121 busctl
|= MUSB_ULPI_USE_EXTVBUS
;
2122 musb_write_ulpi_buscontrol(musb
->mregs
, busctl
);
2125 if (musb
->xceiv
->otg
->default_a
) {
2126 MUSB_HST_MODE(musb
);
2127 musb
->xceiv
->otg
->state
= OTG_STATE_A_IDLE
;
2129 MUSB_DEV_MODE(musb
);
2130 musb
->xceiv
->otg
->state
= OTG_STATE_B_IDLE
;
2133 switch (musb
->port_mode
) {
2134 case MUSB_PORT_MODE_HOST
:
2135 status
= musb_host_setup(musb
, plat
->power
);
2138 status
= musb_platform_set_mode(musb
, MUSB_HOST
);
2140 case MUSB_PORT_MODE_GADGET
:
2141 status
= musb_gadget_setup(musb
);
2144 status
= musb_platform_set_mode(musb
, MUSB_PERIPHERAL
);
2146 case MUSB_PORT_MODE_DUAL_ROLE
:
2147 status
= musb_host_setup(musb
, plat
->power
);
2150 status
= musb_gadget_setup(musb
);
2152 musb_host_cleanup(musb
);
2155 status
= musb_platform_set_mode(musb
, MUSB_OTG
);
2158 dev_err(dev
, "unsupported port mode %d\n", musb
->port_mode
);
2165 status
= musb_init_debugfs(musb
);
2169 status
= sysfs_create_group(&musb
->controller
->kobj
, &musb_attr_group
);
2173 pm_runtime_put(musb
->controller
);
2178 musb_exit_debugfs(musb
);
2181 musb_gadget_cleanup(musb
);
2182 musb_host_cleanup(musb
);
2185 cancel_work_sync(&musb
->irq_work
);
2186 cancel_delayed_work_sync(&musb
->recover_work
);
2187 cancel_delayed_work_sync(&musb
->finish_resume_work
);
2188 cancel_delayed_work_sync(&musb
->deassert_reset_work
);
2189 if (musb
->dma_controller
)
2190 dma_controller_destroy(musb
->dma_controller
);
2192 pm_runtime_put_sync(musb
->controller
);
2196 device_init_wakeup(dev
, 0);
2197 musb_platform_exit(musb
);
2200 pm_runtime_disable(musb
->controller
);
2201 dev_err(musb
->controller
,
2202 "musb_init_controller failed with status %d\n", status
);
2212 /*-------------------------------------------------------------------------*/
2214 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2215 * bridge to a platform device; this driver then suffices.
2217 static int musb_probe(struct platform_device
*pdev
)
2219 struct device
*dev
= &pdev
->dev
;
2220 int irq
= platform_get_irq_byname(pdev
, "mc");
2221 struct resource
*iomem
;
2227 iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2228 base
= devm_ioremap_resource(dev
, iomem
);
2230 return PTR_ERR(base
);
2232 return musb_init_controller(dev
, irq
, base
);
2235 static int musb_remove(struct platform_device
*pdev
)
2237 struct device
*dev
= &pdev
->dev
;
2238 struct musb
*musb
= dev_to_musb(dev
);
2240 /* this gets called on rmmod.
2241 * - Host mode: host may still be active
2242 * - Peripheral mode: peripheral is deactivated (or never-activated)
2243 * - OTG mode: both roles are deactivated (or never-activated)
2245 musb_exit_debugfs(musb
);
2246 musb_shutdown(pdev
);
2248 if (musb
->dma_controller
)
2249 dma_controller_destroy(musb
->dma_controller
);
2251 cancel_work_sync(&musb
->irq_work
);
2252 cancel_delayed_work_sync(&musb
->recover_work
);
2253 cancel_delayed_work_sync(&musb
->finish_resume_work
);
2254 cancel_delayed_work_sync(&musb
->deassert_reset_work
);
2256 device_init_wakeup(dev
, 0);
2262 static void musb_save_context(struct musb
*musb
)
2265 void __iomem
*musb_base
= musb
->mregs
;
2268 musb
->context
.frame
= musb_readw(musb_base
, MUSB_FRAME
);
2269 musb
->context
.testmode
= musb_readb(musb_base
, MUSB_TESTMODE
);
2270 musb
->context
.busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
2271 musb
->context
.power
= musb_readb(musb_base
, MUSB_POWER
);
2272 musb
->context
.intrusbe
= musb_readb(musb_base
, MUSB_INTRUSBE
);
2273 musb
->context
.index
= musb_readb(musb_base
, MUSB_INDEX
);
2274 musb
->context
.devctl
= musb_readb(musb_base
, MUSB_DEVCTL
);
2276 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2277 struct musb_hw_ep
*hw_ep
;
2279 hw_ep
= &musb
->endpoints
[i
];
2287 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2288 musb
->context
.index_regs
[i
].txmaxp
=
2289 musb_readw(epio
, MUSB_TXMAXP
);
2290 musb
->context
.index_regs
[i
].txcsr
=
2291 musb_readw(epio
, MUSB_TXCSR
);
2292 musb
->context
.index_regs
[i
].rxmaxp
=
2293 musb_readw(epio
, MUSB_RXMAXP
);
2294 musb
->context
.index_regs
[i
].rxcsr
=
2295 musb_readw(epio
, MUSB_RXCSR
);
2297 if (musb
->dyn_fifo
) {
2298 musb
->context
.index_regs
[i
].txfifoadd
=
2299 musb_read_txfifoadd(musb_base
);
2300 musb
->context
.index_regs
[i
].rxfifoadd
=
2301 musb_read_rxfifoadd(musb_base
);
2302 musb
->context
.index_regs
[i
].txfifosz
=
2303 musb_read_txfifosz(musb_base
);
2304 musb
->context
.index_regs
[i
].rxfifosz
=
2305 musb_read_rxfifosz(musb_base
);
2308 musb
->context
.index_regs
[i
].txtype
=
2309 musb_readb(epio
, MUSB_TXTYPE
);
2310 musb
->context
.index_regs
[i
].txinterval
=
2311 musb_readb(epio
, MUSB_TXINTERVAL
);
2312 musb
->context
.index_regs
[i
].rxtype
=
2313 musb_readb(epio
, MUSB_RXTYPE
);
2314 musb
->context
.index_regs
[i
].rxinterval
=
2315 musb_readb(epio
, MUSB_RXINTERVAL
);
2317 musb
->context
.index_regs
[i
].txfunaddr
=
2318 musb_read_txfunaddr(musb_base
, i
);
2319 musb
->context
.index_regs
[i
].txhubaddr
=
2320 musb_read_txhubaddr(musb_base
, i
);
2321 musb
->context
.index_regs
[i
].txhubport
=
2322 musb_read_txhubport(musb_base
, i
);
2324 musb
->context
.index_regs
[i
].rxfunaddr
=
2325 musb_read_rxfunaddr(musb_base
, i
);
2326 musb
->context
.index_regs
[i
].rxhubaddr
=
2327 musb_read_rxhubaddr(musb_base
, i
);
2328 musb
->context
.index_regs
[i
].rxhubport
=
2329 musb_read_rxhubport(musb_base
, i
);
2333 static void musb_restore_context(struct musb
*musb
)
2336 void __iomem
*musb_base
= musb
->mregs
;
2337 void __iomem
*ep_target_regs
;
2341 musb_writew(musb_base
, MUSB_FRAME
, musb
->context
.frame
);
2342 musb_writeb(musb_base
, MUSB_TESTMODE
, musb
->context
.testmode
);
2343 musb_write_ulpi_buscontrol(musb
->mregs
, musb
->context
.busctl
);
2345 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2346 power
= musb_readb(musb_base
, MUSB_POWER
);
2347 power
&= MUSB_POWER_SUSPENDM
| MUSB_POWER_RESUME
;
2348 musb
->context
.power
&= ~(MUSB_POWER_SUSPENDM
| MUSB_POWER_RESUME
);
2349 power
|= musb
->context
.power
;
2350 musb_writeb(musb_base
, MUSB_POWER
, power
);
2352 musb_writew(musb_base
, MUSB_INTRTXE
, musb
->intrtxe
);
2353 musb_writew(musb_base
, MUSB_INTRRXE
, musb
->intrrxe
);
2354 musb_writeb(musb_base
, MUSB_INTRUSBE
, musb
->context
.intrusbe
);
2355 musb_writeb(musb_base
, MUSB_DEVCTL
, musb
->context
.devctl
);
2357 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2358 struct musb_hw_ep
*hw_ep
;
2360 hw_ep
= &musb
->endpoints
[i
];
2368 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2369 musb_writew(epio
, MUSB_TXMAXP
,
2370 musb
->context
.index_regs
[i
].txmaxp
);
2371 musb_writew(epio
, MUSB_TXCSR
,
2372 musb
->context
.index_regs
[i
].txcsr
);
2373 musb_writew(epio
, MUSB_RXMAXP
,
2374 musb
->context
.index_regs
[i
].rxmaxp
);
2375 musb_writew(epio
, MUSB_RXCSR
,
2376 musb
->context
.index_regs
[i
].rxcsr
);
2378 if (musb
->dyn_fifo
) {
2379 musb_write_txfifosz(musb_base
,
2380 musb
->context
.index_regs
[i
].txfifosz
);
2381 musb_write_rxfifosz(musb_base
,
2382 musb
->context
.index_regs
[i
].rxfifosz
);
2383 musb_write_txfifoadd(musb_base
,
2384 musb
->context
.index_regs
[i
].txfifoadd
);
2385 musb_write_rxfifoadd(musb_base
,
2386 musb
->context
.index_regs
[i
].rxfifoadd
);
2389 musb_writeb(epio
, MUSB_TXTYPE
,
2390 musb
->context
.index_regs
[i
].txtype
);
2391 musb_writeb(epio
, MUSB_TXINTERVAL
,
2392 musb
->context
.index_regs
[i
].txinterval
);
2393 musb_writeb(epio
, MUSB_RXTYPE
,
2394 musb
->context
.index_regs
[i
].rxtype
);
2395 musb_writeb(epio
, MUSB_RXINTERVAL
,
2397 musb
->context
.index_regs
[i
].rxinterval
);
2398 musb_write_txfunaddr(musb_base
, i
,
2399 musb
->context
.index_regs
[i
].txfunaddr
);
2400 musb_write_txhubaddr(musb_base
, i
,
2401 musb
->context
.index_regs
[i
].txhubaddr
);
2402 musb_write_txhubport(musb_base
, i
,
2403 musb
->context
.index_regs
[i
].txhubport
);
2406 musb_read_target_reg_base(i
, musb_base
);
2408 musb_write_rxfunaddr(ep_target_regs
,
2409 musb
->context
.index_regs
[i
].rxfunaddr
);
2410 musb_write_rxhubaddr(ep_target_regs
,
2411 musb
->context
.index_regs
[i
].rxhubaddr
);
2412 musb_write_rxhubport(ep_target_regs
,
2413 musb
->context
.index_regs
[i
].rxhubport
);
2415 musb_writeb(musb_base
, MUSB_INDEX
, musb
->context
.index
);
2418 static int musb_suspend(struct device
*dev
)
2420 struct musb
*musb
= dev_to_musb(dev
);
2421 unsigned long flags
;
2423 spin_lock_irqsave(&musb
->lock
, flags
);
2425 if (is_peripheral_active(musb
)) {
2426 /* FIXME force disconnect unless we know USB will wake
2427 * the system up quickly enough to respond ...
2429 } else if (is_host_active(musb
)) {
2430 /* we know all the children are suspended; sometimes
2431 * they will even be wakeup-enabled.
2435 musb_save_context(musb
);
2437 spin_unlock_irqrestore(&musb
->lock
, flags
);
2441 static int musb_resume(struct device
*dev
)
2443 struct musb
*musb
= dev_to_musb(dev
);
2448 * For static cmos like DaVinci, register values were preserved
2449 * unless for some reason the whole soc powered down or the USB
2450 * module got reset through the PSC (vs just being disabled).
2452 * For the DSPS glue layer though, a full register restore has to
2453 * be done. As it shouldn't harm other platforms, we do it
2457 musb_restore_context(musb
);
2459 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
2460 mask
= MUSB_DEVCTL_BDEVICE
| MUSB_DEVCTL_FSDEV
| MUSB_DEVCTL_LSDEV
;
2461 if ((devctl
& mask
) != (musb
->context
.devctl
& mask
))
2462 musb
->port1_status
= 0;
2463 if (musb
->need_finish_resume
) {
2464 musb
->need_finish_resume
= 0;
2465 schedule_delayed_work(&musb
->finish_resume_work
,
2466 msecs_to_jiffies(20));
2470 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2473 pm_runtime_disable(dev
);
2474 pm_runtime_set_active(dev
);
2475 pm_runtime_enable(dev
);
2479 static int musb_runtime_suspend(struct device
*dev
)
2481 struct musb
*musb
= dev_to_musb(dev
);
2483 musb_save_context(musb
);
2488 static int musb_runtime_resume(struct device
*dev
)
2490 struct musb
*musb
= dev_to_musb(dev
);
2491 static int first
= 1;
2494 * When pm_runtime_get_sync called for the first time in driver
2495 * init, some of the structure is still not initialized which is
2496 * used in restore function. But clock needs to be
2497 * enabled before any register access, so
2498 * pm_runtime_get_sync has to be called.
2499 * Also context restore without save does not make
2503 musb_restore_context(musb
);
2506 if (musb
->need_finish_resume
) {
2507 musb
->need_finish_resume
= 0;
2508 schedule_delayed_work(&musb
->finish_resume_work
,
2509 msecs_to_jiffies(20));
2515 static const struct dev_pm_ops musb_dev_pm_ops
= {
2516 .suspend
= musb_suspend
,
2517 .resume
= musb_resume
,
2518 .runtime_suspend
= musb_runtime_suspend
,
2519 .runtime_resume
= musb_runtime_resume
,
2522 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2524 #define MUSB_DEV_PM_OPS NULL
2527 static struct platform_driver musb_driver
= {
2529 .name
= (char *)musb_driver_name
,
2530 .bus
= &platform_bus_type
,
2531 .pm
= MUSB_DEV_PM_OPS
,
2533 .probe
= musb_probe
,
2534 .remove
= musb_remove
,
2535 .shutdown
= musb_shutdown
,
2538 module_platform_driver(musb_driver
);