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Merge tag 'usb-serial-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/johan...
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102
103 #include "musb_core.h"
104
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111 #define MUSB_VERSION "6.0"
112
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124 /*-------------------------------------------------------------------------*/
125
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128 return dev_get_drvdata(dev);
129 }
130
131 /*-------------------------------------------------------------------------*/
132
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136 void __iomem *addr = phy->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172 out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
176 }
177
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180 void __iomem *addr = phy->io_priv;
181 int i = 0;
182 u8 r = 0;
183 u8 power;
184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
210 out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
214 }
215 #else
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
218 #endif
219
220 static struct usb_phy_io_ops musb_ulpi_access = {
221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223 };
224
225 /*-------------------------------------------------------------------------*/
226
227 static u32 musb_default_fifo_offset(u8 epnum)
228 {
229 return 0x20 + (epnum * 4);
230 }
231
232 /* "flat" mapping: each endpoint has its own i/o address */
233 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
234 {
235 }
236
237 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
238 {
239 return 0x100 + (0x10 * epnum) + offset;
240 }
241
242 /* "indexed" mapping: INDEX register controls register bank select */
243 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
244 {
245 musb_writeb(mbase, MUSB_INDEX, epnum);
246 }
247
248 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
249 {
250 return 0x10 + offset;
251 }
252
253 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
254 {
255 return __raw_readb(addr + offset);
256 }
257
258 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
259 {
260 __raw_writeb(data, addr + offset);
261 }
262
263 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264 {
265 return __raw_readw(addr + offset);
266 }
267
268 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
269 {
270 __raw_writew(data, addr + offset);
271 }
272
273 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
274 {
275 return __raw_readl(addr + offset);
276 }
277
278 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
279 {
280 __raw_writel(data, addr + offset);
281 }
282
283 /*
284 * Load an endpoint's FIFO
285 */
286 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
287 const u8 *src)
288 {
289 struct musb *musb = hw_ep->musb;
290 void __iomem *fifo = hw_ep->fifo;
291
292 if (unlikely(len == 0))
293 return;
294
295 prefetch((u8 *)src);
296
297 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
298 'T', hw_ep->epnum, fifo, len, src);
299
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src) == 0)) {
302 u16 index = 0;
303
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src) == 0) {
306 if (len >= 4) {
307 iowrite32_rep(fifo, src + index, len >> 2);
308 index += len & ~0x03;
309 }
310 if (len & 0x02) {
311 musb_writew(fifo, 0, *(u16 *)&src[index]);
312 index += 2;
313 }
314 } else {
315 if (len >= 2) {
316 iowrite16_rep(fifo, src + index, len >> 1);
317 index += len & ~0x01;
318 }
319 }
320 if (len & 0x01)
321 musb_writeb(fifo, 0, src[index]);
322 } else {
323 /* byte aligned */
324 iowrite8_rep(fifo, src, len);
325 }
326 }
327
328 /*
329 * Unload an endpoint's FIFO
330 */
331 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
332 {
333 struct musb *musb = hw_ep->musb;
334 void __iomem *fifo = hw_ep->fifo;
335
336 if (unlikely(len == 0))
337 return;
338
339 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
340 'R', hw_ep->epnum, fifo, len, dst);
341
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst) == 0)) {
344 u16 index = 0;
345
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst) == 0) {
348 if (len >= 4) {
349 ioread32_rep(fifo, dst, len >> 2);
350 index = len & ~0x03;
351 }
352 if (len & 0x02) {
353 *(u16 *)&dst[index] = musb_readw(fifo, 0);
354 index += 2;
355 }
356 } else {
357 if (len >= 2) {
358 ioread16_rep(fifo, dst, len >> 1);
359 index = len & ~0x01;
360 }
361 }
362 if (len & 0x01)
363 dst[index] = musb_readb(fifo, 0);
364 } else {
365 /* byte aligned */
366 ioread8_rep(fifo, dst, len);
367 }
368 }
369
370 /*
371 * Old style IO functions
372 */
373 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374 EXPORT_SYMBOL_GPL(musb_readb);
375
376 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377 EXPORT_SYMBOL_GPL(musb_writeb);
378
379 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readw);
381
382 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383 EXPORT_SYMBOL_GPL(musb_writew);
384
385 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readl);
387
388 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389 EXPORT_SYMBOL_GPL(musb_writel);
390
391 /*
392 * New style IO functions
393 */
394 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
395 {
396 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
397 }
398
399 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
400 {
401 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
402 }
403
404 /*-------------------------------------------------------------------------*/
405
406 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
407 static const u8 musb_test_packet[53] = {
408 /* implicit SYNC then DATA0 to start */
409
410 /* JKJKJKJK x9 */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
412 /* JJKKJJKK x8 */
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
414 /* JJJJKKKK x8 */
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
418 /* JJJJJJJK x8 */
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
422
423 /* implicit CRC16 then EOP to end */
424 };
425
426 void musb_load_testpacket(struct musb *musb)
427 {
428 void __iomem *regs = musb->endpoints[0].regs;
429
430 musb_ep_select(musb->mregs, 0);
431 musb_write_fifo(musb->control_ep,
432 sizeof(musb_test_packet), musb_test_packet);
433 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
434 }
435
436 /*-------------------------------------------------------------------------*/
437
438 /*
439 * Handles OTG hnp timeouts, such as b_ase0_brst
440 */
441 static void musb_otg_timer_func(unsigned long data)
442 {
443 struct musb *musb = (struct musb *)data;
444 unsigned long flags;
445
446 spin_lock_irqsave(&musb->lock, flags);
447 switch (musb->xceiv->otg->state) {
448 case OTG_STATE_B_WAIT_ACON:
449 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
450 musb_g_disconnect(musb);
451 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
452 musb->is_active = 0;
453 break;
454 case OTG_STATE_A_SUSPEND:
455 case OTG_STATE_A_WAIT_BCON:
456 dev_dbg(musb->controller, "HNP: %s timeout\n",
457 usb_otg_state_string(musb->xceiv->otg->state));
458 musb_platform_set_vbus(musb, 0);
459 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
460 break;
461 default:
462 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
463 usb_otg_state_string(musb->xceiv->otg->state));
464 }
465 spin_unlock_irqrestore(&musb->lock, flags);
466 }
467
468 /*
469 * Stops the HNP transition. Caller must take care of locking.
470 */
471 void musb_hnp_stop(struct musb *musb)
472 {
473 struct usb_hcd *hcd = musb->hcd;
474 void __iomem *mbase = musb->mregs;
475 u8 reg;
476
477 dev_dbg(musb->controller, "HNP: stop from %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479
480 switch (musb->xceiv->otg->state) {
481 case OTG_STATE_A_PERIPHERAL:
482 musb_g_disconnect(musb);
483 dev_dbg(musb->controller, "HNP: back to %s\n",
484 usb_otg_state_string(musb->xceiv->otg->state));
485 break;
486 case OTG_STATE_B_HOST:
487 dev_dbg(musb->controller, "HNP: Disabling HR\n");
488 if (hcd)
489 hcd->self.is_b_host = 0;
490 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
491 MUSB_DEV_MODE(musb);
492 reg = musb_readb(mbase, MUSB_POWER);
493 reg |= MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER, reg);
495 /* REVISIT: Start SESSION_REQUEST here? */
496 break;
497 default:
498 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 }
501
502 /*
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
505 * errors.
506 */
507 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
508 }
509
510 static void musb_recover_from_babble(struct musb *musb);
511
512 /*
513 * Interrupt Service Routine to record USB "global" interrupts.
514 * Since these do not happen often and signify things of
515 * paramount importance, it seems OK to check them individually;
516 * the order of the tests is specified in the manual
517 *
518 * @param musb instance pointer
519 * @param int_usb register contents
520 * @param devctl
521 * @param power
522 */
523
524 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
525 u8 devctl)
526 {
527 irqreturn_t handled = IRQ_NONE;
528
529 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
530 int_usb);
531
532 /* in host mode, the peripheral may issue remote wakeup.
533 * in peripheral mode, the host may resume the link.
534 * spurious RESUME irqs happen too, paired with SUSPEND.
535 */
536 if (int_usb & MUSB_INTR_RESUME) {
537 handled = IRQ_HANDLED;
538 dev_dbg(musb->controller, "RESUME (%s)\n",
539 usb_otg_state_string(musb->xceiv->otg->state));
540
541 if (devctl & MUSB_DEVCTL_HM) {
542 switch (musb->xceiv->otg->state) {
543 case OTG_STATE_A_SUSPEND:
544 /* remote wakeup? later, GetPortStatus
545 * will stop RESUME signaling
546 */
547
548 musb->port1_status |=
549 (USB_PORT_STAT_C_SUSPEND << 16)
550 | MUSB_PORT_STAT_RESUME;
551 musb->rh_timer = jiffies
552 + msecs_to_jiffies(20);
553 musb->need_finish_resume = 1;
554
555 musb->xceiv->otg->state = OTG_STATE_A_HOST;
556 musb->is_active = 1;
557 musb_host_resume_root_hub(musb);
558 break;
559 case OTG_STATE_B_WAIT_ACON:
560 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
561 musb->is_active = 1;
562 MUSB_DEV_MODE(musb);
563 break;
564 default:
565 WARNING("bogus %s RESUME (%s)\n",
566 "host",
567 usb_otg_state_string(musb->xceiv->otg->state));
568 }
569 } else {
570 switch (musb->xceiv->otg->state) {
571 case OTG_STATE_A_SUSPEND:
572 /* possibly DISCONNECT is upcoming */
573 musb->xceiv->otg->state = OTG_STATE_A_HOST;
574 musb_host_resume_root_hub(musb);
575 break;
576 case OTG_STATE_B_WAIT_ACON:
577 case OTG_STATE_B_PERIPHERAL:
578 /* disconnect while suspended? we may
579 * not get a disconnect irq...
580 */
581 if ((devctl & MUSB_DEVCTL_VBUS)
582 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
583 ) {
584 musb->int_usb |= MUSB_INTR_DISCONNECT;
585 musb->int_usb &= ~MUSB_INTR_SUSPEND;
586 break;
587 }
588 musb_g_resume(musb);
589 break;
590 case OTG_STATE_B_IDLE:
591 musb->int_usb &= ~MUSB_INTR_SUSPEND;
592 break;
593 default:
594 WARNING("bogus %s RESUME (%s)\n",
595 "peripheral",
596 usb_otg_state_string(musb->xceiv->otg->state));
597 }
598 }
599 }
600
601 /* see manual for the order of the tests */
602 if (int_usb & MUSB_INTR_SESSREQ) {
603 void __iomem *mbase = musb->mregs;
604
605 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
606 && (devctl & MUSB_DEVCTL_BDEVICE)) {
607 dev_dbg(musb->controller, "SessReq while on B state\n");
608 return IRQ_HANDLED;
609 }
610
611 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
612 usb_otg_state_string(musb->xceiv->otg->state));
613
614 /* IRQ arrives from ID pin sense or (later, if VBUS power
615 * is removed) SRP. responses are time critical:
616 * - turn on VBUS (with silicon-specific mechanism)
617 * - go through A_WAIT_VRISE
618 * - ... to A_WAIT_BCON.
619 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
620 */
621 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
622 musb->ep0_stage = MUSB_EP0_START;
623 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
624 MUSB_HST_MODE(musb);
625 musb_platform_set_vbus(musb, 1);
626
627 handled = IRQ_HANDLED;
628 }
629
630 if (int_usb & MUSB_INTR_VBUSERROR) {
631 int ignore = 0;
632
633 /* During connection as an A-Device, we may see a short
634 * current spikes causing voltage drop, because of cable
635 * and peripheral capacitance combined with vbus draw.
636 * (So: less common with truly self-powered devices, where
637 * vbus doesn't act like a power supply.)
638 *
639 * Such spikes are short; usually less than ~500 usec, max
640 * of ~2 msec. That is, they're not sustained overcurrent
641 * errors, though they're reported using VBUSERROR irqs.
642 *
643 * Workarounds: (a) hardware: use self powered devices.
644 * (b) software: ignore non-repeated VBUS errors.
645 *
646 * REVISIT: do delays from lots of DEBUG_KERNEL checks
647 * make trouble here, keeping VBUS < 4.4V ?
648 */
649 switch (musb->xceiv->otg->state) {
650 case OTG_STATE_A_HOST:
651 /* recovery is dicey once we've gotten past the
652 * initial stages of enumeration, but if VBUS
653 * stayed ok at the other end of the link, and
654 * another reset is due (at least for high speed,
655 * to redo the chirp etc), it might work OK...
656 */
657 case OTG_STATE_A_WAIT_BCON:
658 case OTG_STATE_A_WAIT_VRISE:
659 if (musb->vbuserr_retry) {
660 void __iomem *mbase = musb->mregs;
661
662 musb->vbuserr_retry--;
663 ignore = 1;
664 devctl |= MUSB_DEVCTL_SESSION;
665 musb_writeb(mbase, MUSB_DEVCTL, devctl);
666 } else {
667 musb->port1_status |=
668 USB_PORT_STAT_OVERCURRENT
669 | (USB_PORT_STAT_C_OVERCURRENT << 16);
670 }
671 break;
672 default:
673 break;
674 }
675
676 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
677 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
678 usb_otg_state_string(musb->xceiv->otg->state),
679 devctl,
680 ({ char *s;
681 switch (devctl & MUSB_DEVCTL_VBUS) {
682 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
683 s = "<SessEnd"; break;
684 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
685 s = "<AValid"; break;
686 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
687 s = "<VBusValid"; break;
688 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
689 default:
690 s = "VALID"; break;
691 } s; }),
692 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
693 musb->port1_status);
694
695 /* go through A_WAIT_VFALL then start a new session */
696 if (!ignore)
697 musb_platform_set_vbus(musb, 0);
698 handled = IRQ_HANDLED;
699 }
700
701 if (int_usb & MUSB_INTR_SUSPEND) {
702 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
703 usb_otg_state_string(musb->xceiv->otg->state), devctl);
704 handled = IRQ_HANDLED;
705
706 switch (musb->xceiv->otg->state) {
707 case OTG_STATE_A_PERIPHERAL:
708 /* We also come here if the cable is removed, since
709 * this silicon doesn't report ID-no-longer-grounded.
710 *
711 * We depend on T(a_wait_bcon) to shut us down, and
712 * hope users don't do anything dicey during this
713 * undesired detour through A_WAIT_BCON.
714 */
715 musb_hnp_stop(musb);
716 musb_host_resume_root_hub(musb);
717 musb_root_disconnect(musb);
718 musb_platform_try_idle(musb, jiffies
719 + msecs_to_jiffies(musb->a_wait_bcon
720 ? : OTG_TIME_A_WAIT_BCON));
721
722 break;
723 case OTG_STATE_B_IDLE:
724 if (!musb->is_active)
725 break;
726 case OTG_STATE_B_PERIPHERAL:
727 musb_g_suspend(musb);
728 musb->is_active = musb->g.b_hnp_enable;
729 if (musb->is_active) {
730 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
731 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
732 mod_timer(&musb->otg_timer, jiffies
733 + msecs_to_jiffies(
734 OTG_TIME_B_ASE0_BRST));
735 }
736 break;
737 case OTG_STATE_A_WAIT_BCON:
738 if (musb->a_wait_bcon != 0)
739 musb_platform_try_idle(musb, jiffies
740 + msecs_to_jiffies(musb->a_wait_bcon));
741 break;
742 case OTG_STATE_A_HOST:
743 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
744 musb->is_active = musb->hcd->self.b_hnp_enable;
745 break;
746 case OTG_STATE_B_HOST:
747 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
748 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
749 break;
750 default:
751 /* "should not happen" */
752 musb->is_active = 0;
753 break;
754 }
755 }
756
757 if (int_usb & MUSB_INTR_CONNECT) {
758 struct usb_hcd *hcd = musb->hcd;
759
760 handled = IRQ_HANDLED;
761 musb->is_active = 1;
762
763 musb->ep0_stage = MUSB_EP0_START;
764
765 musb->intrtxe = musb->epmask;
766 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
767 musb->intrrxe = musb->epmask & 0xfffe;
768 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
769 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
770 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
771 |USB_PORT_STAT_HIGH_SPEED
772 |USB_PORT_STAT_ENABLE
773 );
774 musb->port1_status |= USB_PORT_STAT_CONNECTION
775 |(USB_PORT_STAT_C_CONNECTION << 16);
776
777 /* high vs full speed is just a guess until after reset */
778 if (devctl & MUSB_DEVCTL_LSDEV)
779 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
780
781 /* indicate new connection to OTG machine */
782 switch (musb->xceiv->otg->state) {
783 case OTG_STATE_B_PERIPHERAL:
784 if (int_usb & MUSB_INTR_SUSPEND) {
785 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
786 int_usb &= ~MUSB_INTR_SUSPEND;
787 goto b_host;
788 } else
789 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
790 break;
791 case OTG_STATE_B_WAIT_ACON:
792 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
793 b_host:
794 musb->xceiv->otg->state = OTG_STATE_B_HOST;
795 if (musb->hcd)
796 musb->hcd->self.is_b_host = 1;
797 del_timer(&musb->otg_timer);
798 break;
799 default:
800 if ((devctl & MUSB_DEVCTL_VBUS)
801 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
802 musb->xceiv->otg->state = OTG_STATE_A_HOST;
803 if (hcd)
804 hcd->self.is_b_host = 0;
805 }
806 break;
807 }
808
809 musb_host_poke_root_hub(musb);
810
811 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
812 usb_otg_state_string(musb->xceiv->otg->state), devctl);
813 }
814
815 if (int_usb & MUSB_INTR_DISCONNECT) {
816 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
817 usb_otg_state_string(musb->xceiv->otg->state),
818 MUSB_MODE(musb), devctl);
819 handled = IRQ_HANDLED;
820
821 switch (musb->xceiv->otg->state) {
822 case OTG_STATE_A_HOST:
823 case OTG_STATE_A_SUSPEND:
824 musb_host_resume_root_hub(musb);
825 musb_root_disconnect(musb);
826 if (musb->a_wait_bcon != 0)
827 musb_platform_try_idle(musb, jiffies
828 + msecs_to_jiffies(musb->a_wait_bcon));
829 break;
830 case OTG_STATE_B_HOST:
831 /* REVISIT this behaves for "real disconnect"
832 * cases; make sure the other transitions from
833 * from B_HOST act right too. The B_HOST code
834 * in hnp_stop() is currently not used...
835 */
836 musb_root_disconnect(musb);
837 if (musb->hcd)
838 musb->hcd->self.is_b_host = 0;
839 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
840 MUSB_DEV_MODE(musb);
841 musb_g_disconnect(musb);
842 break;
843 case OTG_STATE_A_PERIPHERAL:
844 musb_hnp_stop(musb);
845 musb_root_disconnect(musb);
846 /* FALLTHROUGH */
847 case OTG_STATE_B_WAIT_ACON:
848 /* FALLTHROUGH */
849 case OTG_STATE_B_PERIPHERAL:
850 case OTG_STATE_B_IDLE:
851 musb_g_disconnect(musb);
852 break;
853 default:
854 WARNING("unhandled DISCONNECT transition (%s)\n",
855 usb_otg_state_string(musb->xceiv->otg->state));
856 break;
857 }
858 }
859
860 /* mentor saves a bit: bus reset and babble share the same irq.
861 * only host sees babble; only peripheral sees bus reset.
862 */
863 if (int_usb & MUSB_INTR_RESET) {
864 handled = IRQ_HANDLED;
865 if (devctl & MUSB_DEVCTL_HM) {
866 /*
867 * When BABBLE happens what we can depends on which
868 * platform MUSB is running, because some platforms
869 * implemented proprietary means for 'recovering' from
870 * Babble conditions. One such platform is AM335x. In
871 * most cases, however, the only thing we can do is
872 * drop the session.
873 */
874 dev_err(musb->controller, "Babble\n");
875
876 if (is_host_active(musb))
877 musb_recover_from_babble(musb);
878 } else {
879 dev_dbg(musb->controller, "BUS RESET as %s\n",
880 usb_otg_state_string(musb->xceiv->otg->state));
881 switch (musb->xceiv->otg->state) {
882 case OTG_STATE_A_SUSPEND:
883 musb_g_reset(musb);
884 /* FALLTHROUGH */
885 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
886 /* never use invalid T(a_wait_bcon) */
887 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
888 usb_otg_state_string(musb->xceiv->otg->state),
889 TA_WAIT_BCON(musb));
890 mod_timer(&musb->otg_timer, jiffies
891 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
892 break;
893 case OTG_STATE_A_PERIPHERAL:
894 del_timer(&musb->otg_timer);
895 musb_g_reset(musb);
896 break;
897 case OTG_STATE_B_WAIT_ACON:
898 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
899 usb_otg_state_string(musb->xceiv->otg->state));
900 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
901 musb_g_reset(musb);
902 break;
903 case OTG_STATE_B_IDLE:
904 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
905 /* FALLTHROUGH */
906 case OTG_STATE_B_PERIPHERAL:
907 musb_g_reset(musb);
908 break;
909 default:
910 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
911 usb_otg_state_string(musb->xceiv->otg->state));
912 }
913 }
914 }
915
916 #if 0
917 /* REVISIT ... this would be for multiplexing periodic endpoints, or
918 * supporting transfer phasing to prevent exceeding ISO bandwidth
919 * limits of a given frame or microframe.
920 *
921 * It's not needed for peripheral side, which dedicates endpoints;
922 * though it _might_ use SOF irqs for other purposes.
923 *
924 * And it's not currently needed for host side, which also dedicates
925 * endpoints, relies on TX/RX interval registers, and isn't claimed
926 * to support ISO transfers yet.
927 */
928 if (int_usb & MUSB_INTR_SOF) {
929 void __iomem *mbase = musb->mregs;
930 struct musb_hw_ep *ep;
931 u8 epnum;
932 u16 frame;
933
934 dev_dbg(musb->controller, "START_OF_FRAME\n");
935 handled = IRQ_HANDLED;
936
937 /* start any periodic Tx transfers waiting for current frame */
938 frame = musb_readw(mbase, MUSB_FRAME);
939 ep = musb->endpoints;
940 for (epnum = 1; (epnum < musb->nr_endpoints)
941 && (musb->epmask >= (1 << epnum));
942 epnum++, ep++) {
943 /*
944 * FIXME handle framecounter wraps (12 bits)
945 * eliminate duplicated StartUrb logic
946 */
947 if (ep->dwWaitFrame >= frame) {
948 ep->dwWaitFrame = 0;
949 pr_debug("SOF --> periodic TX%s on %d\n",
950 ep->tx_channel ? " DMA" : "",
951 epnum);
952 if (!ep->tx_channel)
953 musb_h_tx_start(musb, epnum);
954 else
955 cppi_hostdma_start(musb, epnum);
956 }
957 } /* end of for loop */
958 }
959 #endif
960
961 schedule_work(&musb->irq_work);
962
963 return handled;
964 }
965
966 /*-------------------------------------------------------------------------*/
967
968 static void musb_disable_interrupts(struct musb *musb)
969 {
970 void __iomem *mbase = musb->mregs;
971 u16 temp;
972
973 /* disable interrupts */
974 musb_writeb(mbase, MUSB_INTRUSBE, 0);
975 musb->intrtxe = 0;
976 musb_writew(mbase, MUSB_INTRTXE, 0);
977 musb->intrrxe = 0;
978 musb_writew(mbase, MUSB_INTRRXE, 0);
979
980 /* flush pending interrupts */
981 temp = musb_readb(mbase, MUSB_INTRUSB);
982 temp = musb_readw(mbase, MUSB_INTRTX);
983 temp = musb_readw(mbase, MUSB_INTRRX);
984 }
985
986 static void musb_enable_interrupts(struct musb *musb)
987 {
988 void __iomem *regs = musb->mregs;
989
990 /* Set INT enable registers, enable interrupts */
991 musb->intrtxe = musb->epmask;
992 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
993 musb->intrrxe = musb->epmask & 0xfffe;
994 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
995 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
996
997 }
998
999 static void musb_generic_disable(struct musb *musb)
1000 {
1001 void __iomem *mbase = musb->mregs;
1002
1003 musb_disable_interrupts(musb);
1004
1005 /* off */
1006 musb_writeb(mbase, MUSB_DEVCTL, 0);
1007 }
1008
1009 /*
1010 * Program the HDRC to start (enable interrupts, dma, etc.).
1011 */
1012 void musb_start(struct musb *musb)
1013 {
1014 void __iomem *regs = musb->mregs;
1015 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1016
1017 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1018
1019 musb_enable_interrupts(musb);
1020 musb_writeb(regs, MUSB_TESTMODE, 0);
1021
1022 /* put into basic highspeed mode and start session */
1023 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1024 | MUSB_POWER_HSENAB
1025 /* ENSUSPEND wedges tusb */
1026 /* | MUSB_POWER_ENSUSPEND */
1027 );
1028
1029 musb->is_active = 0;
1030 devctl = musb_readb(regs, MUSB_DEVCTL);
1031 devctl &= ~MUSB_DEVCTL_SESSION;
1032
1033 /* session started after:
1034 * (a) ID-grounded irq, host mode;
1035 * (b) vbus present/connect IRQ, peripheral mode;
1036 * (c) peripheral initiates, using SRP
1037 */
1038 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1039 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1040 musb->is_active = 1;
1041 } else {
1042 devctl |= MUSB_DEVCTL_SESSION;
1043 }
1044
1045 musb_platform_enable(musb);
1046 musb_writeb(regs, MUSB_DEVCTL, devctl);
1047 }
1048
1049 /*
1050 * Make the HDRC stop (disable interrupts, etc.);
1051 * reversible by musb_start
1052 * called on gadget driver unregister
1053 * with controller locked, irqs blocked
1054 * acts as a NOP unless some role activated the hardware
1055 */
1056 void musb_stop(struct musb *musb)
1057 {
1058 /* stop IRQs, timers, ... */
1059 musb_platform_disable(musb);
1060 musb_generic_disable(musb);
1061 dev_dbg(musb->controller, "HDRC disabled\n");
1062
1063 /* FIXME
1064 * - mark host and/or peripheral drivers unusable/inactive
1065 * - disable DMA (and enable it in HdrcStart)
1066 * - make sure we can musb_start() after musb_stop(); with
1067 * OTG mode, gadget driver module rmmod/modprobe cycles that
1068 * - ...
1069 */
1070 musb_platform_try_idle(musb, 0);
1071 }
1072
1073 static void musb_shutdown(struct platform_device *pdev)
1074 {
1075 struct musb *musb = dev_to_musb(&pdev->dev);
1076 unsigned long flags;
1077
1078 pm_runtime_get_sync(musb->controller);
1079
1080 musb_host_cleanup(musb);
1081 musb_gadget_cleanup(musb);
1082
1083 spin_lock_irqsave(&musb->lock, flags);
1084 musb_platform_disable(musb);
1085 musb_generic_disable(musb);
1086 spin_unlock_irqrestore(&musb->lock, flags);
1087
1088 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1089 musb_platform_exit(musb);
1090
1091 pm_runtime_put(musb->controller);
1092 /* FIXME power down */
1093 }
1094
1095
1096 /*-------------------------------------------------------------------------*/
1097
1098 /*
1099 * The silicon either has hard-wired endpoint configurations, or else
1100 * "dynamic fifo" sizing. The driver has support for both, though at this
1101 * writing only the dynamic sizing is very well tested. Since we switched
1102 * away from compile-time hardware parameters, we can no longer rely on
1103 * dead code elimination to leave only the relevant one in the object file.
1104 *
1105 * We don't currently use dynamic fifo setup capability to do anything
1106 * more than selecting one of a bunch of predefined configurations.
1107 */
1108 static ushort fifo_mode;
1109
1110 /* "modprobe ... fifo_mode=1" etc */
1111 module_param(fifo_mode, ushort, 0);
1112 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1113
1114 /*
1115 * tables defining fifo_mode values. define more if you like.
1116 * for host side, make sure both halves of ep1 are set up.
1117 */
1118
1119 /* mode 0 - fits in 2KB */
1120 static struct musb_fifo_cfg mode_0_cfg[] = {
1121 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1122 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1123 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1124 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1125 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1126 };
1127
1128 /* mode 1 - fits in 4KB */
1129 static struct musb_fifo_cfg mode_1_cfg[] = {
1130 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1131 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1132 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1133 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1134 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1135 };
1136
1137 /* mode 2 - fits in 4KB */
1138 static struct musb_fifo_cfg mode_2_cfg[] = {
1139 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1142 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1143 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1144 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1145 };
1146
1147 /* mode 3 - fits in 4KB */
1148 static struct musb_fifo_cfg mode_3_cfg[] = {
1149 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1150 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1152 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1153 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155 };
1156
1157 /* mode 4 - fits in 16KB */
1158 static struct musb_fifo_cfg mode_4_cfg[] = {
1159 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1160 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1161 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1162 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1163 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1164 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1165 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1166 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1167 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1168 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1169 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1170 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1171 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1172 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1173 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1174 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1175 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1176 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1177 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1178 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1179 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1180 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1181 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1182 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1183 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1184 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1185 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1186 };
1187
1188 /* mode 5 - fits in 8KB */
1189 static struct musb_fifo_cfg mode_5_cfg[] = {
1190 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1191 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1192 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1193 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1194 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1195 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1196 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1197 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1198 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1199 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1200 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1201 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1202 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1203 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1204 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1205 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1206 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1207 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1208 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1209 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1210 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1211 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1212 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1213 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1214 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1215 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1216 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1217 };
1218
1219 /*
1220 * configure a fifo; for non-shared endpoints, this may be called
1221 * once for a tx fifo and once for an rx fifo.
1222 *
1223 * returns negative errno or offset for next fifo.
1224 */
1225 static int
1226 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1227 const struct musb_fifo_cfg *cfg, u16 offset)
1228 {
1229 void __iomem *mbase = musb->mregs;
1230 int size = 0;
1231 u16 maxpacket = cfg->maxpacket;
1232 u16 c_off = offset >> 3;
1233 u8 c_size;
1234
1235 /* expect hw_ep has already been zero-initialized */
1236
1237 size = ffs(max(maxpacket, (u16) 8)) - 1;
1238 maxpacket = 1 << size;
1239
1240 c_size = size - 3;
1241 if (cfg->mode == BUF_DOUBLE) {
1242 if ((offset + (maxpacket << 1)) >
1243 (1 << (musb->config->ram_bits + 2)))
1244 return -EMSGSIZE;
1245 c_size |= MUSB_FIFOSZ_DPB;
1246 } else {
1247 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1248 return -EMSGSIZE;
1249 }
1250
1251 /* configure the FIFO */
1252 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1253
1254 /* EP0 reserved endpoint for control, bidirectional;
1255 * EP1 reserved for bulk, two unidirectional halves.
1256 */
1257 if (hw_ep->epnum == 1)
1258 musb->bulk_ep = hw_ep;
1259 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1260 switch (cfg->style) {
1261 case FIFO_TX:
1262 musb_write_txfifosz(mbase, c_size);
1263 musb_write_txfifoadd(mbase, c_off);
1264 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1265 hw_ep->max_packet_sz_tx = maxpacket;
1266 break;
1267 case FIFO_RX:
1268 musb_write_rxfifosz(mbase, c_size);
1269 musb_write_rxfifoadd(mbase, c_off);
1270 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1271 hw_ep->max_packet_sz_rx = maxpacket;
1272 break;
1273 case FIFO_RXTX:
1274 musb_write_txfifosz(mbase, c_size);
1275 musb_write_txfifoadd(mbase, c_off);
1276 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1277 hw_ep->max_packet_sz_rx = maxpacket;
1278
1279 musb_write_rxfifosz(mbase, c_size);
1280 musb_write_rxfifoadd(mbase, c_off);
1281 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1282 hw_ep->max_packet_sz_tx = maxpacket;
1283
1284 hw_ep->is_shared_fifo = true;
1285 break;
1286 }
1287
1288 /* NOTE rx and tx endpoint irqs aren't managed separately,
1289 * which happens to be ok
1290 */
1291 musb->epmask |= (1 << hw_ep->epnum);
1292
1293 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1294 }
1295
1296 static struct musb_fifo_cfg ep0_cfg = {
1297 .style = FIFO_RXTX, .maxpacket = 64,
1298 };
1299
1300 static int ep_config_from_table(struct musb *musb)
1301 {
1302 const struct musb_fifo_cfg *cfg;
1303 unsigned i, n;
1304 int offset;
1305 struct musb_hw_ep *hw_ep = musb->endpoints;
1306
1307 if (musb->config->fifo_cfg) {
1308 cfg = musb->config->fifo_cfg;
1309 n = musb->config->fifo_cfg_size;
1310 goto done;
1311 }
1312
1313 switch (fifo_mode) {
1314 default:
1315 fifo_mode = 0;
1316 /* FALLTHROUGH */
1317 case 0:
1318 cfg = mode_0_cfg;
1319 n = ARRAY_SIZE(mode_0_cfg);
1320 break;
1321 case 1:
1322 cfg = mode_1_cfg;
1323 n = ARRAY_SIZE(mode_1_cfg);
1324 break;
1325 case 2:
1326 cfg = mode_2_cfg;
1327 n = ARRAY_SIZE(mode_2_cfg);
1328 break;
1329 case 3:
1330 cfg = mode_3_cfg;
1331 n = ARRAY_SIZE(mode_3_cfg);
1332 break;
1333 case 4:
1334 cfg = mode_4_cfg;
1335 n = ARRAY_SIZE(mode_4_cfg);
1336 break;
1337 case 5:
1338 cfg = mode_5_cfg;
1339 n = ARRAY_SIZE(mode_5_cfg);
1340 break;
1341 }
1342
1343 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1344 musb_driver_name, fifo_mode);
1345
1346
1347 done:
1348 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1349 /* assert(offset > 0) */
1350
1351 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1352 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1353 */
1354
1355 for (i = 0; i < n; i++) {
1356 u8 epn = cfg->hw_ep_num;
1357
1358 if (epn >= musb->config->num_eps) {
1359 pr_debug("%s: invalid ep %d\n",
1360 musb_driver_name, epn);
1361 return -EINVAL;
1362 }
1363 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1364 if (offset < 0) {
1365 pr_debug("%s: mem overrun, ep %d\n",
1366 musb_driver_name, epn);
1367 return offset;
1368 }
1369 epn++;
1370 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1371 }
1372
1373 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1374 musb_driver_name,
1375 n + 1, musb->config->num_eps * 2 - 1,
1376 offset, (1 << (musb->config->ram_bits + 2)));
1377
1378 if (!musb->bulk_ep) {
1379 pr_debug("%s: missing bulk\n", musb_driver_name);
1380 return -EINVAL;
1381 }
1382
1383 return 0;
1384 }
1385
1386
1387 /*
1388 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1389 * @param musb the controller
1390 */
1391 static int ep_config_from_hw(struct musb *musb)
1392 {
1393 u8 epnum = 0;
1394 struct musb_hw_ep *hw_ep;
1395 void __iomem *mbase = musb->mregs;
1396 int ret = 0;
1397
1398 dev_dbg(musb->controller, "<== static silicon ep config\n");
1399
1400 /* FIXME pick up ep0 maxpacket size */
1401
1402 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1403 musb_ep_select(mbase, epnum);
1404 hw_ep = musb->endpoints + epnum;
1405
1406 ret = musb_read_fifosize(musb, hw_ep, epnum);
1407 if (ret < 0)
1408 break;
1409
1410 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1411
1412 /* pick an RX/TX endpoint for bulk */
1413 if (hw_ep->max_packet_sz_tx < 512
1414 || hw_ep->max_packet_sz_rx < 512)
1415 continue;
1416
1417 /* REVISIT: this algorithm is lazy, we should at least
1418 * try to pick a double buffered endpoint.
1419 */
1420 if (musb->bulk_ep)
1421 continue;
1422 musb->bulk_ep = hw_ep;
1423 }
1424
1425 if (!musb->bulk_ep) {
1426 pr_debug("%s: missing bulk\n", musb_driver_name);
1427 return -EINVAL;
1428 }
1429
1430 return 0;
1431 }
1432
1433 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1434
1435 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1436 * configure endpoints, or take their config from silicon
1437 */
1438 static int musb_core_init(u16 musb_type, struct musb *musb)
1439 {
1440 u8 reg;
1441 char *type;
1442 char aInfo[90], aRevision[32], aDate[12];
1443 void __iomem *mbase = musb->mregs;
1444 int status = 0;
1445 int i;
1446
1447 /* log core options (read using indexed model) */
1448 reg = musb_read_configdata(mbase);
1449
1450 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1451 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1452 strcat(aInfo, ", dyn FIFOs");
1453 musb->dyn_fifo = true;
1454 }
1455 if (reg & MUSB_CONFIGDATA_MPRXE) {
1456 strcat(aInfo, ", bulk combine");
1457 musb->bulk_combine = true;
1458 }
1459 if (reg & MUSB_CONFIGDATA_MPTXE) {
1460 strcat(aInfo, ", bulk split");
1461 musb->bulk_split = true;
1462 }
1463 if (reg & MUSB_CONFIGDATA_HBRXE) {
1464 strcat(aInfo, ", HB-ISO Rx");
1465 musb->hb_iso_rx = true;
1466 }
1467 if (reg & MUSB_CONFIGDATA_HBTXE) {
1468 strcat(aInfo, ", HB-ISO Tx");
1469 musb->hb_iso_tx = true;
1470 }
1471 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1472 strcat(aInfo, ", SoftConn");
1473
1474 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1475 musb_driver_name, reg, aInfo);
1476
1477 aDate[0] = 0;
1478 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1479 musb->is_multipoint = 1;
1480 type = "M";
1481 } else {
1482 musb->is_multipoint = 0;
1483 type = "";
1484 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1485 printk(KERN_ERR
1486 "%s: kernel must blacklist external hubs\n",
1487 musb_driver_name);
1488 #endif
1489 }
1490
1491 /* log release info */
1492 musb->hwvers = musb_read_hwvers(mbase);
1493 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1494 MUSB_HWVERS_MINOR(musb->hwvers),
1495 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1496 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1497 musb_driver_name, type, aRevision, aDate);
1498
1499 /* configure ep0 */
1500 musb_configure_ep0(musb);
1501
1502 /* discover endpoint configuration */
1503 musb->nr_endpoints = 1;
1504 musb->epmask = 1;
1505
1506 if (musb->dyn_fifo)
1507 status = ep_config_from_table(musb);
1508 else
1509 status = ep_config_from_hw(musb);
1510
1511 if (status < 0)
1512 return status;
1513
1514 /* finish init, and print endpoint config */
1515 for (i = 0; i < musb->nr_endpoints; i++) {
1516 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1517
1518 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1519 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1520 if (musb->io.quirks & MUSB_IN_TUSB) {
1521 hw_ep->fifo_async = musb->async + 0x400 +
1522 musb->io.fifo_offset(i);
1523 hw_ep->fifo_sync = musb->sync + 0x400 +
1524 musb->io.fifo_offset(i);
1525 hw_ep->fifo_sync_va =
1526 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1527
1528 if (i == 0)
1529 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1530 else
1531 hw_ep->conf = mbase + 0x400 +
1532 (((i - 1) & 0xf) << 2);
1533 }
1534 #endif
1535
1536 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1537 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1538 hw_ep->rx_reinit = 1;
1539 hw_ep->tx_reinit = 1;
1540
1541 if (hw_ep->max_packet_sz_tx) {
1542 dev_dbg(musb->controller,
1543 "%s: hw_ep %d%s, %smax %d\n",
1544 musb_driver_name, i,
1545 hw_ep->is_shared_fifo ? "shared" : "tx",
1546 hw_ep->tx_double_buffered
1547 ? "doublebuffer, " : "",
1548 hw_ep->max_packet_sz_tx);
1549 }
1550 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1551 dev_dbg(musb->controller,
1552 "%s: hw_ep %d%s, %smax %d\n",
1553 musb_driver_name, i,
1554 "rx",
1555 hw_ep->rx_double_buffered
1556 ? "doublebuffer, " : "",
1557 hw_ep->max_packet_sz_rx);
1558 }
1559 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1560 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1561 }
1562
1563 return 0;
1564 }
1565
1566 /*-------------------------------------------------------------------------*/
1567
1568 /*
1569 * handle all the irqs defined by the HDRC core. for now we expect: other
1570 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1571 * will be assigned, and the irq will already have been acked.
1572 *
1573 * called in irq context with spinlock held, irqs blocked
1574 */
1575 irqreturn_t musb_interrupt(struct musb *musb)
1576 {
1577 irqreturn_t retval = IRQ_NONE;
1578 unsigned long status;
1579 unsigned long epnum;
1580 u8 devctl;
1581
1582 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1583 return IRQ_NONE;
1584
1585 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1586
1587 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1588 is_host_active(musb) ? "host" : "peripheral",
1589 musb->int_usb, musb->int_tx, musb->int_rx);
1590
1591 /**
1592 * According to Mentor Graphics' documentation, flowchart on page 98,
1593 * IRQ should be handled as follows:
1594 *
1595 * . Resume IRQ
1596 * . Session Request IRQ
1597 * . VBUS Error IRQ
1598 * . Suspend IRQ
1599 * . Connect IRQ
1600 * . Disconnect IRQ
1601 * . Reset/Babble IRQ
1602 * . SOF IRQ (we're not using this one)
1603 * . Endpoint 0 IRQ
1604 * . TX Endpoints
1605 * . RX Endpoints
1606 *
1607 * We will be following that flowchart in order to avoid any problems
1608 * that might arise with internal Finite State Machine.
1609 */
1610
1611 if (musb->int_usb)
1612 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1613
1614 if (musb->int_tx & 1) {
1615 if (is_host_active(musb))
1616 retval |= musb_h_ep0_irq(musb);
1617 else
1618 retval |= musb_g_ep0_irq(musb);
1619
1620 /* we have just handled endpoint 0 IRQ, clear it */
1621 musb->int_tx &= ~BIT(0);
1622 }
1623
1624 status = musb->int_tx;
1625
1626 for_each_set_bit(epnum, &status, 16) {
1627 retval = IRQ_HANDLED;
1628 if (is_host_active(musb))
1629 musb_host_tx(musb, epnum);
1630 else
1631 musb_g_tx(musb, epnum);
1632 }
1633
1634 status = musb->int_rx;
1635
1636 for_each_set_bit(epnum, &status, 16) {
1637 retval = IRQ_HANDLED;
1638 if (is_host_active(musb))
1639 musb_host_rx(musb, epnum);
1640 else
1641 musb_g_rx(musb, epnum);
1642 }
1643
1644 return retval;
1645 }
1646 EXPORT_SYMBOL_GPL(musb_interrupt);
1647
1648 #ifndef CONFIG_MUSB_PIO_ONLY
1649 static bool use_dma = 1;
1650
1651 /* "modprobe ... use_dma=0" etc */
1652 module_param(use_dma, bool, 0);
1653 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1654
1655 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1656 {
1657 /* called with controller lock already held */
1658
1659 if (!epnum) {
1660 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1661 if (!is_cppi_enabled()) {
1662 /* endpoint 0 */
1663 if (is_host_active(musb))
1664 musb_h_ep0_irq(musb);
1665 else
1666 musb_g_ep0_irq(musb);
1667 }
1668 #endif
1669 } else {
1670 /* endpoints 1..15 */
1671 if (transmit) {
1672 if (is_host_active(musb))
1673 musb_host_tx(musb, epnum);
1674 else
1675 musb_g_tx(musb, epnum);
1676 } else {
1677 /* receive */
1678 if (is_host_active(musb))
1679 musb_host_rx(musb, epnum);
1680 else
1681 musb_g_rx(musb, epnum);
1682 }
1683 }
1684 }
1685 EXPORT_SYMBOL_GPL(musb_dma_completion);
1686
1687 #else
1688 #define use_dma 0
1689 #endif
1690
1691 /*-------------------------------------------------------------------------*/
1692
1693 static ssize_t
1694 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1695 {
1696 struct musb *musb = dev_to_musb(dev);
1697 unsigned long flags;
1698 int ret = -EINVAL;
1699
1700 spin_lock_irqsave(&musb->lock, flags);
1701 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1702 spin_unlock_irqrestore(&musb->lock, flags);
1703
1704 return ret;
1705 }
1706
1707 static ssize_t
1708 musb_mode_store(struct device *dev, struct device_attribute *attr,
1709 const char *buf, size_t n)
1710 {
1711 struct musb *musb = dev_to_musb(dev);
1712 unsigned long flags;
1713 int status;
1714
1715 spin_lock_irqsave(&musb->lock, flags);
1716 if (sysfs_streq(buf, "host"))
1717 status = musb_platform_set_mode(musb, MUSB_HOST);
1718 else if (sysfs_streq(buf, "peripheral"))
1719 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1720 else if (sysfs_streq(buf, "otg"))
1721 status = musb_platform_set_mode(musb, MUSB_OTG);
1722 else
1723 status = -EINVAL;
1724 spin_unlock_irqrestore(&musb->lock, flags);
1725
1726 return (status == 0) ? n : status;
1727 }
1728 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1729
1730 static ssize_t
1731 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1732 const char *buf, size_t n)
1733 {
1734 struct musb *musb = dev_to_musb(dev);
1735 unsigned long flags;
1736 unsigned long val;
1737
1738 if (sscanf(buf, "%lu", &val) < 1) {
1739 dev_err(dev, "Invalid VBUS timeout ms value\n");
1740 return -EINVAL;
1741 }
1742
1743 spin_lock_irqsave(&musb->lock, flags);
1744 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1745 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1746 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1747 musb->is_active = 0;
1748 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1749 spin_unlock_irqrestore(&musb->lock, flags);
1750
1751 return n;
1752 }
1753
1754 static ssize_t
1755 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1756 {
1757 struct musb *musb = dev_to_musb(dev);
1758 unsigned long flags;
1759 unsigned long val;
1760 int vbus;
1761
1762 spin_lock_irqsave(&musb->lock, flags);
1763 val = musb->a_wait_bcon;
1764 /* FIXME get_vbus_status() is normally #defined as false...
1765 * and is effectively TUSB-specific.
1766 */
1767 vbus = musb_platform_get_vbus_status(musb);
1768 spin_unlock_irqrestore(&musb->lock, flags);
1769
1770 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1771 vbus ? "on" : "off", val);
1772 }
1773 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1774
1775 /* Gadget drivers can't know that a host is connected so they might want
1776 * to start SRP, but users can. This allows userspace to trigger SRP.
1777 */
1778 static ssize_t
1779 musb_srp_store(struct device *dev, struct device_attribute *attr,
1780 const char *buf, size_t n)
1781 {
1782 struct musb *musb = dev_to_musb(dev);
1783 unsigned short srp;
1784
1785 if (sscanf(buf, "%hu", &srp) != 1
1786 || (srp != 1)) {
1787 dev_err(dev, "SRP: Value must be 1\n");
1788 return -EINVAL;
1789 }
1790
1791 if (srp == 1)
1792 musb_g_wakeup(musb);
1793
1794 return n;
1795 }
1796 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1797
1798 static struct attribute *musb_attributes[] = {
1799 &dev_attr_mode.attr,
1800 &dev_attr_vbus.attr,
1801 &dev_attr_srp.attr,
1802 NULL
1803 };
1804
1805 static const struct attribute_group musb_attr_group = {
1806 .attrs = musb_attributes,
1807 };
1808
1809 /* Only used to provide driver mode change events */
1810 static void musb_irq_work(struct work_struct *data)
1811 {
1812 struct musb *musb = container_of(data, struct musb, irq_work);
1813
1814 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1815 musb->xceiv_old_state = musb->xceiv->otg->state;
1816 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1817 }
1818 }
1819
1820 static void musb_recover_from_babble(struct musb *musb)
1821 {
1822 int ret;
1823 u8 devctl;
1824
1825 musb_disable_interrupts(musb);
1826
1827 /*
1828 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1829 * it some slack and wait for 10us.
1830 */
1831 udelay(10);
1832
1833 ret = musb_platform_recover(musb);
1834 if (ret) {
1835 musb_enable_interrupts(musb);
1836 return;
1837 }
1838
1839 /* drop session bit */
1840 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1841 devctl &= ~MUSB_DEVCTL_SESSION;
1842 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1843
1844 /* tell usbcore about it */
1845 musb_root_disconnect(musb);
1846
1847 /*
1848 * When a babble condition occurs, the musb controller
1849 * removes the session bit and the endpoint config is lost.
1850 */
1851 if (musb->dyn_fifo)
1852 ret = ep_config_from_table(musb);
1853 else
1854 ret = ep_config_from_hw(musb);
1855
1856 /* restart session */
1857 if (ret == 0)
1858 musb_start(musb);
1859 }
1860
1861 /* --------------------------------------------------------------------------
1862 * Init support
1863 */
1864
1865 static struct musb *allocate_instance(struct device *dev,
1866 struct musb_hdrc_config *config, void __iomem *mbase)
1867 {
1868 struct musb *musb;
1869 struct musb_hw_ep *ep;
1870 int epnum;
1871 int ret;
1872
1873 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1874 if (!musb)
1875 return NULL;
1876
1877 INIT_LIST_HEAD(&musb->control);
1878 INIT_LIST_HEAD(&musb->in_bulk);
1879 INIT_LIST_HEAD(&musb->out_bulk);
1880
1881 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1882 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1883 musb->mregs = mbase;
1884 musb->ctrl_base = mbase;
1885 musb->nIrq = -ENODEV;
1886 musb->config = config;
1887 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1888 for (epnum = 0, ep = musb->endpoints;
1889 epnum < musb->config->num_eps;
1890 epnum++, ep++) {
1891 ep->musb = musb;
1892 ep->epnum = epnum;
1893 }
1894
1895 musb->controller = dev;
1896
1897 ret = musb_host_alloc(musb);
1898 if (ret < 0)
1899 goto err_free;
1900
1901 dev_set_drvdata(dev, musb);
1902
1903 return musb;
1904
1905 err_free:
1906 return NULL;
1907 }
1908
1909 static void musb_free(struct musb *musb)
1910 {
1911 /* this has multiple entry modes. it handles fault cleanup after
1912 * probe(), where things may be partially set up, as well as rmmod
1913 * cleanup after everything's been de-activated.
1914 */
1915
1916 #ifdef CONFIG_SYSFS
1917 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1918 #endif
1919
1920 if (musb->nIrq >= 0) {
1921 if (musb->irq_wake)
1922 disable_irq_wake(musb->nIrq);
1923 free_irq(musb->nIrq, musb);
1924 }
1925
1926 musb_host_free(musb);
1927 }
1928
1929 static void musb_deassert_reset(struct work_struct *work)
1930 {
1931 struct musb *musb;
1932 unsigned long flags;
1933
1934 musb = container_of(work, struct musb, deassert_reset_work.work);
1935
1936 spin_lock_irqsave(&musb->lock, flags);
1937
1938 if (musb->port1_status & USB_PORT_STAT_RESET)
1939 musb_port_reset(musb, false);
1940
1941 spin_unlock_irqrestore(&musb->lock, flags);
1942 }
1943
1944 /*
1945 * Perform generic per-controller initialization.
1946 *
1947 * @dev: the controller (already clocked, etc)
1948 * @nIrq: IRQ number
1949 * @ctrl: virtual address of controller registers,
1950 * not yet corrected for platform-specific offsets
1951 */
1952 static int
1953 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1954 {
1955 int status;
1956 struct musb *musb;
1957 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1958
1959 /* The driver might handle more features than the board; OK.
1960 * Fail when the board needs a feature that's not enabled.
1961 */
1962 if (!plat) {
1963 dev_dbg(dev, "no platform_data?\n");
1964 status = -ENODEV;
1965 goto fail0;
1966 }
1967
1968 /* allocate */
1969 musb = allocate_instance(dev, plat->config, ctrl);
1970 if (!musb) {
1971 status = -ENOMEM;
1972 goto fail0;
1973 }
1974
1975 spin_lock_init(&musb->lock);
1976 musb->board_set_power = plat->set_power;
1977 musb->min_power = plat->min_power;
1978 musb->ops = plat->platform_ops;
1979 musb->port_mode = plat->mode;
1980
1981 /*
1982 * Initialize the default IO functions. At least omap2430 needs
1983 * these early. We initialize the platform specific IO functions
1984 * later on.
1985 */
1986 musb_readb = musb_default_readb;
1987 musb_writeb = musb_default_writeb;
1988 musb_readw = musb_default_readw;
1989 musb_writew = musb_default_writew;
1990 musb_readl = musb_default_readl;
1991 musb_writel = musb_default_writel;
1992
1993 /* We need musb_read/write functions initialized for PM */
1994 pm_runtime_use_autosuspend(musb->controller);
1995 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1996 pm_runtime_irq_safe(musb->controller);
1997 pm_runtime_enable(musb->controller);
1998
1999 /* The musb_platform_init() call:
2000 * - adjusts musb->mregs
2001 * - sets the musb->isr
2002 * - may initialize an integrated transceiver
2003 * - initializes musb->xceiv, usually by otg_get_phy()
2004 * - stops powering VBUS
2005 *
2006 * There are various transceiver configurations. Blackfin,
2007 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2008 * external/discrete ones in various flavors (twl4030 family,
2009 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2010 */
2011 status = musb_platform_init(musb);
2012 if (status < 0)
2013 goto fail1;
2014
2015 if (!musb->isr) {
2016 status = -ENODEV;
2017 goto fail2;
2018 }
2019
2020 if (musb->ops->quirks)
2021 musb->io.quirks = musb->ops->quirks;
2022
2023 /* At least tusb6010 has it's own offsets.. */
2024 if (musb->ops->ep_offset)
2025 musb->io.ep_offset = musb->ops->ep_offset;
2026 if (musb->ops->ep_select)
2027 musb->io.ep_select = musb->ops->ep_select;
2028
2029 /* ..and some devices use indexed offset or flat offset */
2030 if (musb->io.quirks & MUSB_INDEXED_EP) {
2031 musb->io.ep_offset = musb_indexed_ep_offset;
2032 musb->io.ep_select = musb_indexed_ep_select;
2033 } else {
2034 musb->io.ep_offset = musb_flat_ep_offset;
2035 musb->io.ep_select = musb_flat_ep_select;
2036 }
2037
2038 if (musb->ops->fifo_mode)
2039 fifo_mode = musb->ops->fifo_mode;
2040 else
2041 fifo_mode = 4;
2042
2043 if (musb->ops->fifo_offset)
2044 musb->io.fifo_offset = musb->ops->fifo_offset;
2045 else
2046 musb->io.fifo_offset = musb_default_fifo_offset;
2047
2048 if (musb->ops->readb)
2049 musb_readb = musb->ops->readb;
2050 if (musb->ops->writeb)
2051 musb_writeb = musb->ops->writeb;
2052 if (musb->ops->readw)
2053 musb_readw = musb->ops->readw;
2054 if (musb->ops->writew)
2055 musb_writew = musb->ops->writew;
2056 if (musb->ops->readl)
2057 musb_readl = musb->ops->readl;
2058 if (musb->ops->writel)
2059 musb_writel = musb->ops->writel;
2060
2061 if (musb->ops->read_fifo)
2062 musb->io.read_fifo = musb->ops->read_fifo;
2063 else
2064 musb->io.read_fifo = musb_default_read_fifo;
2065
2066 if (musb->ops->write_fifo)
2067 musb->io.write_fifo = musb->ops->write_fifo;
2068 else
2069 musb->io.write_fifo = musb_default_write_fifo;
2070
2071 if (!musb->xceiv->io_ops) {
2072 musb->xceiv->io_dev = musb->controller;
2073 musb->xceiv->io_priv = musb->mregs;
2074 musb->xceiv->io_ops = &musb_ulpi_access;
2075 }
2076
2077 pm_runtime_get_sync(musb->controller);
2078
2079 if (use_dma && dev->dma_mask) {
2080 musb->dma_controller = dma_controller_create(musb, musb->mregs);
2081 if (IS_ERR(musb->dma_controller)) {
2082 status = PTR_ERR(musb->dma_controller);
2083 goto fail2_5;
2084 }
2085 }
2086
2087 /* be sure interrupts are disabled before connecting ISR */
2088 musb_platform_disable(musb);
2089 musb_generic_disable(musb);
2090
2091 /* Init IRQ workqueue before request_irq */
2092 INIT_WORK(&musb->irq_work, musb_irq_work);
2093 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2094 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2095
2096 /* setup musb parts of the core (especially endpoints) */
2097 status = musb_core_init(plat->config->multipoint
2098 ? MUSB_CONTROLLER_MHDRC
2099 : MUSB_CONTROLLER_HDRC, musb);
2100 if (status < 0)
2101 goto fail3;
2102
2103 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2104
2105 /* attach to the IRQ */
2106 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2107 dev_err(dev, "request_irq %d failed!\n", nIrq);
2108 status = -ENODEV;
2109 goto fail3;
2110 }
2111 musb->nIrq = nIrq;
2112 /* FIXME this handles wakeup irqs wrong */
2113 if (enable_irq_wake(nIrq) == 0) {
2114 musb->irq_wake = 1;
2115 device_init_wakeup(dev, 1);
2116 } else {
2117 musb->irq_wake = 0;
2118 }
2119
2120 /* program PHY to use external vBus if required */
2121 if (plat->extvbus) {
2122 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2123 busctl |= MUSB_ULPI_USE_EXTVBUS;
2124 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2125 }
2126
2127 if (musb->xceiv->otg->default_a) {
2128 MUSB_HST_MODE(musb);
2129 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2130 } else {
2131 MUSB_DEV_MODE(musb);
2132 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2133 }
2134
2135 switch (musb->port_mode) {
2136 case MUSB_PORT_MODE_HOST:
2137 status = musb_host_setup(musb, plat->power);
2138 if (status < 0)
2139 goto fail3;
2140 status = musb_platform_set_mode(musb, MUSB_HOST);
2141 break;
2142 case MUSB_PORT_MODE_GADGET:
2143 status = musb_gadget_setup(musb);
2144 if (status < 0)
2145 goto fail3;
2146 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2147 break;
2148 case MUSB_PORT_MODE_DUAL_ROLE:
2149 status = musb_host_setup(musb, plat->power);
2150 if (status < 0)
2151 goto fail3;
2152 status = musb_gadget_setup(musb);
2153 if (status) {
2154 musb_host_cleanup(musb);
2155 goto fail3;
2156 }
2157 status = musb_platform_set_mode(musb, MUSB_OTG);
2158 break;
2159 default:
2160 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2161 break;
2162 }
2163
2164 if (status < 0)
2165 goto fail3;
2166
2167 status = musb_init_debugfs(musb);
2168 if (status < 0)
2169 goto fail4;
2170
2171 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2172 if (status)
2173 goto fail5;
2174
2175 pm_runtime_put(musb->controller);
2176
2177 return 0;
2178
2179 fail5:
2180 musb_exit_debugfs(musb);
2181
2182 fail4:
2183 musb_gadget_cleanup(musb);
2184 musb_host_cleanup(musb);
2185
2186 fail3:
2187 cancel_work_sync(&musb->irq_work);
2188 cancel_delayed_work_sync(&musb->finish_resume_work);
2189 cancel_delayed_work_sync(&musb->deassert_reset_work);
2190 if (musb->dma_controller)
2191 dma_controller_destroy(musb->dma_controller);
2192 fail2_5:
2193 pm_runtime_put_sync(musb->controller);
2194
2195 fail2:
2196 if (musb->irq_wake)
2197 device_init_wakeup(dev, 0);
2198 musb_platform_exit(musb);
2199
2200 fail1:
2201 pm_runtime_disable(musb->controller);
2202 dev_err(musb->controller,
2203 "musb_init_controller failed with status %d\n", status);
2204
2205 musb_free(musb);
2206
2207 fail0:
2208
2209 return status;
2210
2211 }
2212
2213 /*-------------------------------------------------------------------------*/
2214
2215 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2216 * bridge to a platform device; this driver then suffices.
2217 */
2218 static int musb_probe(struct platform_device *pdev)
2219 {
2220 struct device *dev = &pdev->dev;
2221 int irq = platform_get_irq_byname(pdev, "mc");
2222 struct resource *iomem;
2223 void __iomem *base;
2224
2225 if (irq <= 0)
2226 return -ENODEV;
2227
2228 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2229 base = devm_ioremap_resource(dev, iomem);
2230 if (IS_ERR(base))
2231 return PTR_ERR(base);
2232
2233 return musb_init_controller(dev, irq, base);
2234 }
2235
2236 static int musb_remove(struct platform_device *pdev)
2237 {
2238 struct device *dev = &pdev->dev;
2239 struct musb *musb = dev_to_musb(dev);
2240
2241 /* this gets called on rmmod.
2242 * - Host mode: host may still be active
2243 * - Peripheral mode: peripheral is deactivated (or never-activated)
2244 * - OTG mode: both roles are deactivated (or never-activated)
2245 */
2246 musb_exit_debugfs(musb);
2247 musb_shutdown(pdev);
2248
2249 if (musb->dma_controller)
2250 dma_controller_destroy(musb->dma_controller);
2251
2252 cancel_work_sync(&musb->irq_work);
2253 cancel_delayed_work_sync(&musb->finish_resume_work);
2254 cancel_delayed_work_sync(&musb->deassert_reset_work);
2255 musb_free(musb);
2256 device_init_wakeup(dev, 0);
2257 return 0;
2258 }
2259
2260 #ifdef CONFIG_PM
2261
2262 static void musb_save_context(struct musb *musb)
2263 {
2264 int i;
2265 void __iomem *musb_base = musb->mregs;
2266 void __iomem *epio;
2267
2268 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2269 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2270 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2271 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2272 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2273 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2274 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2275
2276 for (i = 0; i < musb->config->num_eps; ++i) {
2277 struct musb_hw_ep *hw_ep;
2278
2279 hw_ep = &musb->endpoints[i];
2280 if (!hw_ep)
2281 continue;
2282
2283 epio = hw_ep->regs;
2284 if (!epio)
2285 continue;
2286
2287 musb_writeb(musb_base, MUSB_INDEX, i);
2288 musb->context.index_regs[i].txmaxp =
2289 musb_readw(epio, MUSB_TXMAXP);
2290 musb->context.index_regs[i].txcsr =
2291 musb_readw(epio, MUSB_TXCSR);
2292 musb->context.index_regs[i].rxmaxp =
2293 musb_readw(epio, MUSB_RXMAXP);
2294 musb->context.index_regs[i].rxcsr =
2295 musb_readw(epio, MUSB_RXCSR);
2296
2297 if (musb->dyn_fifo) {
2298 musb->context.index_regs[i].txfifoadd =
2299 musb_read_txfifoadd(musb_base);
2300 musb->context.index_regs[i].rxfifoadd =
2301 musb_read_rxfifoadd(musb_base);
2302 musb->context.index_regs[i].txfifosz =
2303 musb_read_txfifosz(musb_base);
2304 musb->context.index_regs[i].rxfifosz =
2305 musb_read_rxfifosz(musb_base);
2306 }
2307
2308 musb->context.index_regs[i].txtype =
2309 musb_readb(epio, MUSB_TXTYPE);
2310 musb->context.index_regs[i].txinterval =
2311 musb_readb(epio, MUSB_TXINTERVAL);
2312 musb->context.index_regs[i].rxtype =
2313 musb_readb(epio, MUSB_RXTYPE);
2314 musb->context.index_regs[i].rxinterval =
2315 musb_readb(epio, MUSB_RXINTERVAL);
2316
2317 musb->context.index_regs[i].txfunaddr =
2318 musb_read_txfunaddr(musb_base, i);
2319 musb->context.index_regs[i].txhubaddr =
2320 musb_read_txhubaddr(musb_base, i);
2321 musb->context.index_regs[i].txhubport =
2322 musb_read_txhubport(musb_base, i);
2323
2324 musb->context.index_regs[i].rxfunaddr =
2325 musb_read_rxfunaddr(musb_base, i);
2326 musb->context.index_regs[i].rxhubaddr =
2327 musb_read_rxhubaddr(musb_base, i);
2328 musb->context.index_regs[i].rxhubport =
2329 musb_read_rxhubport(musb_base, i);
2330 }
2331 }
2332
2333 static void musb_restore_context(struct musb *musb)
2334 {
2335 int i;
2336 void __iomem *musb_base = musb->mregs;
2337 void __iomem *ep_target_regs;
2338 void __iomem *epio;
2339 u8 power;
2340
2341 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2342 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2343 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2344
2345 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2346 power = musb_readb(musb_base, MUSB_POWER);
2347 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2348 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2349 power |= musb->context.power;
2350 musb_writeb(musb_base, MUSB_POWER, power);
2351
2352 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2353 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2354 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2355 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2356
2357 for (i = 0; i < musb->config->num_eps; ++i) {
2358 struct musb_hw_ep *hw_ep;
2359
2360 hw_ep = &musb->endpoints[i];
2361 if (!hw_ep)
2362 continue;
2363
2364 epio = hw_ep->regs;
2365 if (!epio)
2366 continue;
2367
2368 musb_writeb(musb_base, MUSB_INDEX, i);
2369 musb_writew(epio, MUSB_TXMAXP,
2370 musb->context.index_regs[i].txmaxp);
2371 musb_writew(epio, MUSB_TXCSR,
2372 musb->context.index_regs[i].txcsr);
2373 musb_writew(epio, MUSB_RXMAXP,
2374 musb->context.index_regs[i].rxmaxp);
2375 musb_writew(epio, MUSB_RXCSR,
2376 musb->context.index_regs[i].rxcsr);
2377
2378 if (musb->dyn_fifo) {
2379 musb_write_txfifosz(musb_base,
2380 musb->context.index_regs[i].txfifosz);
2381 musb_write_rxfifosz(musb_base,
2382 musb->context.index_regs[i].rxfifosz);
2383 musb_write_txfifoadd(musb_base,
2384 musb->context.index_regs[i].txfifoadd);
2385 musb_write_rxfifoadd(musb_base,
2386 musb->context.index_regs[i].rxfifoadd);
2387 }
2388
2389 musb_writeb(epio, MUSB_TXTYPE,
2390 musb->context.index_regs[i].txtype);
2391 musb_writeb(epio, MUSB_TXINTERVAL,
2392 musb->context.index_regs[i].txinterval);
2393 musb_writeb(epio, MUSB_RXTYPE,
2394 musb->context.index_regs[i].rxtype);
2395 musb_writeb(epio, MUSB_RXINTERVAL,
2396
2397 musb->context.index_regs[i].rxinterval);
2398 musb_write_txfunaddr(musb_base, i,
2399 musb->context.index_regs[i].txfunaddr);
2400 musb_write_txhubaddr(musb_base, i,
2401 musb->context.index_regs[i].txhubaddr);
2402 musb_write_txhubport(musb_base, i,
2403 musb->context.index_regs[i].txhubport);
2404
2405 ep_target_regs =
2406 musb_read_target_reg_base(i, musb_base);
2407
2408 musb_write_rxfunaddr(ep_target_regs,
2409 musb->context.index_regs[i].rxfunaddr);
2410 musb_write_rxhubaddr(ep_target_regs,
2411 musb->context.index_regs[i].rxhubaddr);
2412 musb_write_rxhubport(ep_target_regs,
2413 musb->context.index_regs[i].rxhubport);
2414 }
2415 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2416 }
2417
2418 static int musb_suspend(struct device *dev)
2419 {
2420 struct musb *musb = dev_to_musb(dev);
2421 unsigned long flags;
2422
2423 spin_lock_irqsave(&musb->lock, flags);
2424
2425 if (is_peripheral_active(musb)) {
2426 /* FIXME force disconnect unless we know USB will wake
2427 * the system up quickly enough to respond ...
2428 */
2429 } else if (is_host_active(musb)) {
2430 /* we know all the children are suspended; sometimes
2431 * they will even be wakeup-enabled.
2432 */
2433 }
2434
2435 musb_save_context(musb);
2436
2437 spin_unlock_irqrestore(&musb->lock, flags);
2438 return 0;
2439 }
2440
2441 static int musb_resume(struct device *dev)
2442 {
2443 struct musb *musb = dev_to_musb(dev);
2444 u8 devctl;
2445 u8 mask;
2446
2447 /*
2448 * For static cmos like DaVinci, register values were preserved
2449 * unless for some reason the whole soc powered down or the USB
2450 * module got reset through the PSC (vs just being disabled).
2451 *
2452 * For the DSPS glue layer though, a full register restore has to
2453 * be done. As it shouldn't harm other platforms, we do it
2454 * unconditionally.
2455 */
2456
2457 musb_restore_context(musb);
2458
2459 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2460 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2461 if ((devctl & mask) != (musb->context.devctl & mask))
2462 musb->port1_status = 0;
2463 if (musb->need_finish_resume) {
2464 musb->need_finish_resume = 0;
2465 schedule_delayed_work(&musb->finish_resume_work,
2466 msecs_to_jiffies(20));
2467 }
2468
2469 /*
2470 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2471 * out of suspend
2472 */
2473 pm_runtime_disable(dev);
2474 pm_runtime_set_active(dev);
2475 pm_runtime_enable(dev);
2476 return 0;
2477 }
2478
2479 static int musb_runtime_suspend(struct device *dev)
2480 {
2481 struct musb *musb = dev_to_musb(dev);
2482
2483 musb_save_context(musb);
2484
2485 return 0;
2486 }
2487
2488 static int musb_runtime_resume(struct device *dev)
2489 {
2490 struct musb *musb = dev_to_musb(dev);
2491 static int first = 1;
2492
2493 /*
2494 * When pm_runtime_get_sync called for the first time in driver
2495 * init, some of the structure is still not initialized which is
2496 * used in restore function. But clock needs to be
2497 * enabled before any register access, so
2498 * pm_runtime_get_sync has to be called.
2499 * Also context restore without save does not make
2500 * any sense
2501 */
2502 if (!first)
2503 musb_restore_context(musb);
2504 first = 0;
2505
2506 if (musb->need_finish_resume) {
2507 musb->need_finish_resume = 0;
2508 schedule_delayed_work(&musb->finish_resume_work,
2509 msecs_to_jiffies(20));
2510 }
2511
2512 return 0;
2513 }
2514
2515 static const struct dev_pm_ops musb_dev_pm_ops = {
2516 .suspend = musb_suspend,
2517 .resume = musb_resume,
2518 .runtime_suspend = musb_runtime_suspend,
2519 .runtime_resume = musb_runtime_resume,
2520 };
2521
2522 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2523 #else
2524 #define MUSB_DEV_PM_OPS NULL
2525 #endif
2526
2527 static struct platform_driver musb_driver = {
2528 .driver = {
2529 .name = (char *)musb_driver_name,
2530 .bus = &platform_bus_type,
2531 .pm = MUSB_DEV_PM_OPS,
2532 },
2533 .probe = musb_probe,
2534 .remove = musb_remove,
2535 .shutdown = musb_shutdown,
2536 };
2537
2538 module_platform_driver(musb_driver);
Linux kernel - Deliverables
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