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Merge branch 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #ifdef CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107
108 #include "musb_core.h"
109
110
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
116
117
118 unsigned musb_debug;
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
121
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124
125 #define MUSB_VERSION "6.0"
126
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
131
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
136
137
138 /*-------------------------------------------------------------------------*/
139
140 static inline struct musb *dev_to_musb(struct device *dev)
141 {
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
145 #else
146 return dev_get_drvdata(dev);
147 #endif
148 }
149
150 /*-------------------------------------------------------------------------*/
151
152 #ifndef CONFIG_BLACKFIN
153 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
154 {
155 void __iomem *addr = otg->io_priv;
156 int i = 0;
157 u8 r;
158 u8 power;
159
160 /* Make sure the transceiver is not in low power mode */
161 power = musb_readb(addr, MUSB_POWER);
162 power &= ~MUSB_POWER_SUSPENDM;
163 musb_writeb(addr, MUSB_POWER, power);
164
165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
167 */
168
169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
172
173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
174 & MUSB_ULPI_REG_CMPLT)) {
175 i++;
176 if (i == 10000) {
177 DBG(3, "ULPI read timed out\n");
178 return -ETIMEDOUT;
179 }
180
181 }
182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
183 r &= ~MUSB_ULPI_REG_CMPLT;
184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
185
186 return musb_readb(addr, MUSB_ULPI_REG_DATA);
187 }
188
189 static int musb_ulpi_write(struct otg_transceiver *otg,
190 u32 offset, u32 data)
191 {
192 void __iomem *addr = otg->io_priv;
193 int i = 0;
194 u8 r = 0;
195 u8 power;
196
197 /* Make sure the transceiver is not in low power mode */
198 power = musb_readb(addr, MUSB_POWER);
199 power &= ~MUSB_POWER_SUSPENDM;
200 musb_writeb(addr, MUSB_POWER, power);
201
202 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
203 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
205
206 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
207 & MUSB_ULPI_REG_CMPLT)) {
208 i++;
209 if (i == 10000) {
210 DBG(3, "ULPI write timed out\n");
211 return -ETIMEDOUT;
212 }
213 }
214
215 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
216 r &= ~MUSB_ULPI_REG_CMPLT;
217 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
218
219 return 0;
220 }
221 #else
222 #define musb_ulpi_read NULL
223 #define musb_ulpi_write NULL
224 #endif
225
226 static struct otg_io_access_ops musb_ulpi_access = {
227 .read = musb_ulpi_read,
228 .write = musb_ulpi_write,
229 };
230
231 /*-------------------------------------------------------------------------*/
232
233 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
234
235 /*
236 * Load an endpoint's FIFO
237 */
238 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
239 {
240 void __iomem *fifo = hw_ep->fifo;
241
242 prefetch((u8 *)src);
243
244 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
246
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
249 u16 index = 0;
250
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
253 if (len >= 4) {
254 writesl(fifo, src + index, len >> 2);
255 index += len & ~0x03;
256 }
257 if (len & 0x02) {
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 index += 2;
260 }
261 } else {
262 if (len >= 2) {
263 writesw(fifo, src + index, len >> 1);
264 index += len & ~0x01;
265 }
266 }
267 if (len & 0x01)
268 musb_writeb(fifo, 0, src[index]);
269 } else {
270 /* byte aligned */
271 writesb(fifo, src, len);
272 }
273 }
274
275 /*
276 * Unload an endpoint's FIFO
277 */
278 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
279 {
280 void __iomem *fifo = hw_ep->fifo;
281
282 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
283 'R', hw_ep->epnum, fifo, len, dst);
284
285 /* we can't assume unaligned writes work */
286 if (likely((0x01 & (unsigned long) dst) == 0)) {
287 u16 index = 0;
288
289 /* best case is 32bit-aligned destination address */
290 if ((0x02 & (unsigned long) dst) == 0) {
291 if (len >= 4) {
292 readsl(fifo, dst, len >> 2);
293 index = len & ~0x03;
294 }
295 if (len & 0x02) {
296 *(u16 *)&dst[index] = musb_readw(fifo, 0);
297 index += 2;
298 }
299 } else {
300 if (len >= 2) {
301 readsw(fifo, dst, len >> 1);
302 index = len & ~0x01;
303 }
304 }
305 if (len & 0x01)
306 dst[index] = musb_readb(fifo, 0);
307 } else {
308 /* byte aligned */
309 readsb(fifo, dst, len);
310 }
311 }
312
313 #endif /* normal PIO */
314
315
316 /*-------------------------------------------------------------------------*/
317
318 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
319 static const u8 musb_test_packet[53] = {
320 /* implicit SYNC then DATA0 to start */
321
322 /* JKJKJKJK x9 */
323 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 /* JJKKJJKK x8 */
325 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
326 /* JJJJKKKK x8 */
327 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
328 /* JJJJJJJKKKKKKK x8 */
329 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
330 /* JJJJJJJK x8 */
331 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
332 /* JKKKKKKK x10, JK */
333 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
334
335 /* implicit CRC16 then EOP to end */
336 };
337
338 void musb_load_testpacket(struct musb *musb)
339 {
340 void __iomem *regs = musb->endpoints[0].regs;
341
342 musb_ep_select(musb->mregs, 0);
343 musb_write_fifo(musb->control_ep,
344 sizeof(musb_test_packet), musb_test_packet);
345 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
346 }
347
348 /*-------------------------------------------------------------------------*/
349
350 const char *otg_state_string(struct musb *musb)
351 {
352 switch (musb->xceiv->state) {
353 case OTG_STATE_A_IDLE: return "a_idle";
354 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
355 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
356 case OTG_STATE_A_HOST: return "a_host";
357 case OTG_STATE_A_SUSPEND: return "a_suspend";
358 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
359 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
360 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
361 case OTG_STATE_B_IDLE: return "b_idle";
362 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
363 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
364 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
365 case OTG_STATE_B_HOST: return "b_host";
366 default: return "UNDEFINED";
367 }
368 }
369
370 #ifdef CONFIG_USB_MUSB_OTG
371
372 /*
373 * Handles OTG hnp timeouts, such as b_ase0_brst
374 */
375 void musb_otg_timer_func(unsigned long data)
376 {
377 struct musb *musb = (struct musb *)data;
378 unsigned long flags;
379
380 spin_lock_irqsave(&musb->lock, flags);
381 switch (musb->xceiv->state) {
382 case OTG_STATE_B_WAIT_ACON:
383 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
384 musb_g_disconnect(musb);
385 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
386 musb->is_active = 0;
387 break;
388 case OTG_STATE_A_SUSPEND:
389 case OTG_STATE_A_WAIT_BCON:
390 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
391 musb_set_vbus(musb, 0);
392 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
393 break;
394 default:
395 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
396 }
397 musb->ignore_disconnect = 0;
398 spin_unlock_irqrestore(&musb->lock, flags);
399 }
400
401 /*
402 * Stops the HNP transition. Caller must take care of locking.
403 */
404 void musb_hnp_stop(struct musb *musb)
405 {
406 struct usb_hcd *hcd = musb_to_hcd(musb);
407 void __iomem *mbase = musb->mregs;
408 u8 reg;
409
410 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
411
412 switch (musb->xceiv->state) {
413 case OTG_STATE_A_PERIPHERAL:
414 musb_g_disconnect(musb);
415 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
416 break;
417 case OTG_STATE_B_HOST:
418 DBG(1, "HNP: Disabling HR\n");
419 hcd->self.is_b_host = 0;
420 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
421 MUSB_DEV_MODE(musb);
422 reg = musb_readb(mbase, MUSB_POWER);
423 reg |= MUSB_POWER_SUSPENDM;
424 musb_writeb(mbase, MUSB_POWER, reg);
425 /* REVISIT: Start SESSION_REQUEST here? */
426 break;
427 default:
428 DBG(1, "HNP: Stopping in unknown state %s\n",
429 otg_state_string(musb));
430 }
431
432 /*
433 * When returning to A state after HNP, avoid hub_port_rebounce(),
434 * which cause occasional OPT A "Did not receive reset after connect"
435 * errors.
436 */
437 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
438 }
439
440 #endif
441
442 /*
443 * Interrupt Service Routine to record USB "global" interrupts.
444 * Since these do not happen often and signify things of
445 * paramount importance, it seems OK to check them individually;
446 * the order of the tests is specified in the manual
447 *
448 * @param musb instance pointer
449 * @param int_usb register contents
450 * @param devctl
451 * @param power
452 */
453
454 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
455 u8 devctl, u8 power)
456 {
457 irqreturn_t handled = IRQ_NONE;
458
459 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
460 int_usb);
461
462 /* in host mode, the peripheral may issue remote wakeup.
463 * in peripheral mode, the host may resume the link.
464 * spurious RESUME irqs happen too, paired with SUSPEND.
465 */
466 if (int_usb & MUSB_INTR_RESUME) {
467 handled = IRQ_HANDLED;
468 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
469
470 if (devctl & MUSB_DEVCTL_HM) {
471 #ifdef CONFIG_USB_MUSB_HDRC_HCD
472 void __iomem *mbase = musb->mregs;
473
474 switch (musb->xceiv->state) {
475 case OTG_STATE_A_SUSPEND:
476 /* remote wakeup? later, GetPortStatus
477 * will stop RESUME signaling
478 */
479
480 if (power & MUSB_POWER_SUSPENDM) {
481 /* spurious */
482 musb->int_usb &= ~MUSB_INTR_SUSPEND;
483 DBG(2, "Spurious SUSPENDM\n");
484 break;
485 }
486
487 power &= ~MUSB_POWER_SUSPENDM;
488 musb_writeb(mbase, MUSB_POWER,
489 power | MUSB_POWER_RESUME);
490
491 musb->port1_status |=
492 (USB_PORT_STAT_C_SUSPEND << 16)
493 | MUSB_PORT_STAT_RESUME;
494 musb->rh_timer = jiffies
495 + msecs_to_jiffies(20);
496
497 musb->xceiv->state = OTG_STATE_A_HOST;
498 musb->is_active = 1;
499 usb_hcd_resume_root_hub(musb_to_hcd(musb));
500 break;
501 case OTG_STATE_B_WAIT_ACON:
502 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
503 musb->is_active = 1;
504 MUSB_DEV_MODE(musb);
505 break;
506 default:
507 WARNING("bogus %s RESUME (%s)\n",
508 "host",
509 otg_state_string(musb));
510 }
511 #endif
512 } else {
513 switch (musb->xceiv->state) {
514 #ifdef CONFIG_USB_MUSB_HDRC_HCD
515 case OTG_STATE_A_SUSPEND:
516 /* possibly DISCONNECT is upcoming */
517 musb->xceiv->state = OTG_STATE_A_HOST;
518 usb_hcd_resume_root_hub(musb_to_hcd(musb));
519 break;
520 #endif
521 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
522 case OTG_STATE_B_WAIT_ACON:
523 case OTG_STATE_B_PERIPHERAL:
524 /* disconnect while suspended? we may
525 * not get a disconnect irq...
526 */
527 if ((devctl & MUSB_DEVCTL_VBUS)
528 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
529 ) {
530 musb->int_usb |= MUSB_INTR_DISCONNECT;
531 musb->int_usb &= ~MUSB_INTR_SUSPEND;
532 break;
533 }
534 musb_g_resume(musb);
535 break;
536 case OTG_STATE_B_IDLE:
537 musb->int_usb &= ~MUSB_INTR_SUSPEND;
538 break;
539 #endif
540 default:
541 WARNING("bogus %s RESUME (%s)\n",
542 "peripheral",
543 otg_state_string(musb));
544 }
545 }
546 }
547
548 #ifdef CONFIG_USB_MUSB_HDRC_HCD
549 /* see manual for the order of the tests */
550 if (int_usb & MUSB_INTR_SESSREQ) {
551 void __iomem *mbase = musb->mregs;
552
553 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
554
555 /* IRQ arrives from ID pin sense or (later, if VBUS power
556 * is removed) SRP. responses are time critical:
557 * - turn on VBUS (with silicon-specific mechanism)
558 * - go through A_WAIT_VRISE
559 * - ... to A_WAIT_BCON.
560 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
561 */
562 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
563 musb->ep0_stage = MUSB_EP0_START;
564 musb->xceiv->state = OTG_STATE_A_IDLE;
565 MUSB_HST_MODE(musb);
566 musb_set_vbus(musb, 1);
567
568 handled = IRQ_HANDLED;
569 }
570
571 if (int_usb & MUSB_INTR_VBUSERROR) {
572 int ignore = 0;
573
574 /* During connection as an A-Device, we may see a short
575 * current spikes causing voltage drop, because of cable
576 * and peripheral capacitance combined with vbus draw.
577 * (So: less common with truly self-powered devices, where
578 * vbus doesn't act like a power supply.)
579 *
580 * Such spikes are short; usually less than ~500 usec, max
581 * of ~2 msec. That is, they're not sustained overcurrent
582 * errors, though they're reported using VBUSERROR irqs.
583 *
584 * Workarounds: (a) hardware: use self powered devices.
585 * (b) software: ignore non-repeated VBUS errors.
586 *
587 * REVISIT: do delays from lots of DEBUG_KERNEL checks
588 * make trouble here, keeping VBUS < 4.4V ?
589 */
590 switch (musb->xceiv->state) {
591 case OTG_STATE_A_HOST:
592 /* recovery is dicey once we've gotten past the
593 * initial stages of enumeration, but if VBUS
594 * stayed ok at the other end of the link, and
595 * another reset is due (at least for high speed,
596 * to redo the chirp etc), it might work OK...
597 */
598 case OTG_STATE_A_WAIT_BCON:
599 case OTG_STATE_A_WAIT_VRISE:
600 if (musb->vbuserr_retry) {
601 void __iomem *mbase = musb->mregs;
602
603 musb->vbuserr_retry--;
604 ignore = 1;
605 devctl |= MUSB_DEVCTL_SESSION;
606 musb_writeb(mbase, MUSB_DEVCTL, devctl);
607 } else {
608 musb->port1_status |=
609 USB_PORT_STAT_OVERCURRENT
610 | (USB_PORT_STAT_C_OVERCURRENT << 16);
611 }
612 break;
613 default:
614 break;
615 }
616
617 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
618 otg_state_string(musb),
619 devctl,
620 ({ char *s;
621 switch (devctl & MUSB_DEVCTL_VBUS) {
622 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
623 s = "<SessEnd"; break;
624 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
625 s = "<AValid"; break;
626 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
627 s = "<VBusValid"; break;
628 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
629 default:
630 s = "VALID"; break;
631 }; s; }),
632 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
633 musb->port1_status);
634
635 /* go through A_WAIT_VFALL then start a new session */
636 if (!ignore)
637 musb_set_vbus(musb, 0);
638 handled = IRQ_HANDLED;
639 }
640
641 #endif
642 if (int_usb & MUSB_INTR_SUSPEND) {
643 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
644 otg_state_string(musb), devctl, power);
645 handled = IRQ_HANDLED;
646
647 switch (musb->xceiv->state) {
648 #ifdef CONFIG_USB_MUSB_OTG
649 case OTG_STATE_A_PERIPHERAL:
650 /* We also come here if the cable is removed, since
651 * this silicon doesn't report ID-no-longer-grounded.
652 *
653 * We depend on T(a_wait_bcon) to shut us down, and
654 * hope users don't do anything dicey during this
655 * undesired detour through A_WAIT_BCON.
656 */
657 musb_hnp_stop(musb);
658 usb_hcd_resume_root_hub(musb_to_hcd(musb));
659 musb_root_disconnect(musb);
660 musb_platform_try_idle(musb, jiffies
661 + msecs_to_jiffies(musb->a_wait_bcon
662 ? : OTG_TIME_A_WAIT_BCON));
663
664 break;
665 #endif
666 case OTG_STATE_B_IDLE:
667 if (!musb->is_active)
668 break;
669 case OTG_STATE_B_PERIPHERAL:
670 musb_g_suspend(musb);
671 musb->is_active = is_otg_enabled(musb)
672 && musb->xceiv->gadget->b_hnp_enable;
673 if (musb->is_active) {
674 #ifdef CONFIG_USB_MUSB_OTG
675 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
676 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
677 mod_timer(&musb->otg_timer, jiffies
678 + msecs_to_jiffies(
679 OTG_TIME_B_ASE0_BRST));
680 #endif
681 }
682 break;
683 case OTG_STATE_A_WAIT_BCON:
684 if (musb->a_wait_bcon != 0)
685 musb_platform_try_idle(musb, jiffies
686 + msecs_to_jiffies(musb->a_wait_bcon));
687 break;
688 case OTG_STATE_A_HOST:
689 musb->xceiv->state = OTG_STATE_A_SUSPEND;
690 musb->is_active = is_otg_enabled(musb)
691 && musb->xceiv->host->b_hnp_enable;
692 break;
693 case OTG_STATE_B_HOST:
694 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
695 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
696 break;
697 default:
698 /* "should not happen" */
699 musb->is_active = 0;
700 break;
701 }
702 }
703
704 #ifdef CONFIG_USB_MUSB_HDRC_HCD
705 if (int_usb & MUSB_INTR_CONNECT) {
706 struct usb_hcd *hcd = musb_to_hcd(musb);
707 void __iomem *mbase = musb->mregs;
708
709 handled = IRQ_HANDLED;
710 musb->is_active = 1;
711 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
712
713 musb->ep0_stage = MUSB_EP0_START;
714
715 #ifdef CONFIG_USB_MUSB_OTG
716 /* flush endpoints when transitioning from Device Mode */
717 if (is_peripheral_active(musb)) {
718 /* REVISIT HNP; just force disconnect */
719 }
720 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
721 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
722 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
723 #endif
724 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
725 |USB_PORT_STAT_HIGH_SPEED
726 |USB_PORT_STAT_ENABLE
727 );
728 musb->port1_status |= USB_PORT_STAT_CONNECTION
729 |(USB_PORT_STAT_C_CONNECTION << 16);
730
731 /* high vs full speed is just a guess until after reset */
732 if (devctl & MUSB_DEVCTL_LSDEV)
733 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
734
735 /* indicate new connection to OTG machine */
736 switch (musb->xceiv->state) {
737 case OTG_STATE_B_PERIPHERAL:
738 if (int_usb & MUSB_INTR_SUSPEND) {
739 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
740 int_usb &= ~MUSB_INTR_SUSPEND;
741 goto b_host;
742 } else
743 DBG(1, "CONNECT as b_peripheral???\n");
744 break;
745 case OTG_STATE_B_WAIT_ACON:
746 DBG(1, "HNP: CONNECT, now b_host\n");
747 b_host:
748 musb->xceiv->state = OTG_STATE_B_HOST;
749 hcd->self.is_b_host = 1;
750 musb->ignore_disconnect = 0;
751 del_timer(&musb->otg_timer);
752 break;
753 default:
754 if ((devctl & MUSB_DEVCTL_VBUS)
755 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
756 musb->xceiv->state = OTG_STATE_A_HOST;
757 hcd->self.is_b_host = 0;
758 }
759 break;
760 }
761
762 /* poke the root hub */
763 MUSB_HST_MODE(musb);
764 if (hcd->status_urb)
765 usb_hcd_poll_rh_status(hcd);
766 else
767 usb_hcd_resume_root_hub(hcd);
768
769 DBG(1, "CONNECT (%s) devctl %02x\n",
770 otg_state_string(musb), devctl);
771 }
772 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
773
774 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
775 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
776 otg_state_string(musb),
777 MUSB_MODE(musb), devctl);
778 handled = IRQ_HANDLED;
779
780 switch (musb->xceiv->state) {
781 #ifdef CONFIG_USB_MUSB_HDRC_HCD
782 case OTG_STATE_A_HOST:
783 case OTG_STATE_A_SUSPEND:
784 usb_hcd_resume_root_hub(musb_to_hcd(musb));
785 musb_root_disconnect(musb);
786 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
787 musb_platform_try_idle(musb, jiffies
788 + msecs_to_jiffies(musb->a_wait_bcon));
789 break;
790 #endif /* HOST */
791 #ifdef CONFIG_USB_MUSB_OTG
792 case OTG_STATE_B_HOST:
793 /* REVISIT this behaves for "real disconnect"
794 * cases; make sure the other transitions from
795 * from B_HOST act right too. The B_HOST code
796 * in hnp_stop() is currently not used...
797 */
798 musb_root_disconnect(musb);
799 musb_to_hcd(musb)->self.is_b_host = 0;
800 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
801 MUSB_DEV_MODE(musb);
802 musb_g_disconnect(musb);
803 break;
804 case OTG_STATE_A_PERIPHERAL:
805 musb_hnp_stop(musb);
806 musb_root_disconnect(musb);
807 /* FALLTHROUGH */
808 case OTG_STATE_B_WAIT_ACON:
809 /* FALLTHROUGH */
810 #endif /* OTG */
811 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
812 case OTG_STATE_B_PERIPHERAL:
813 case OTG_STATE_B_IDLE:
814 musb_g_disconnect(musb);
815 break;
816 #endif /* GADGET */
817 default:
818 WARNING("unhandled DISCONNECT transition (%s)\n",
819 otg_state_string(musb));
820 break;
821 }
822 }
823
824 /* mentor saves a bit: bus reset and babble share the same irq.
825 * only host sees babble; only peripheral sees bus reset.
826 */
827 if (int_usb & MUSB_INTR_RESET) {
828 handled = IRQ_HANDLED;
829 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
830 /*
831 * Looks like non-HS BABBLE can be ignored, but
832 * HS BABBLE is an error condition. For HS the solution
833 * is to avoid babble in the first place and fix what
834 * caused BABBLE. When HS BABBLE happens we can only
835 * stop the session.
836 */
837 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
838 DBG(1, "BABBLE devctl: %02x\n", devctl);
839 else {
840 ERR("Stopping host session -- babble\n");
841 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
842 }
843 } else if (is_peripheral_capable()) {
844 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
845 switch (musb->xceiv->state) {
846 #ifdef CONFIG_USB_OTG
847 case OTG_STATE_A_SUSPEND:
848 /* We need to ignore disconnect on suspend
849 * otherwise tusb 2.0 won't reconnect after a
850 * power cycle, which breaks otg compliance.
851 */
852 musb->ignore_disconnect = 1;
853 musb_g_reset(musb);
854 /* FALLTHROUGH */
855 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
856 /* never use invalid T(a_wait_bcon) */
857 DBG(1, "HNP: in %s, %d msec timeout\n",
858 otg_state_string(musb),
859 TA_WAIT_BCON(musb));
860 mod_timer(&musb->otg_timer, jiffies
861 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
862 break;
863 case OTG_STATE_A_PERIPHERAL:
864 musb->ignore_disconnect = 0;
865 del_timer(&musb->otg_timer);
866 musb_g_reset(musb);
867 break;
868 case OTG_STATE_B_WAIT_ACON:
869 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
870 otg_state_string(musb));
871 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
872 musb_g_reset(musb);
873 break;
874 #endif
875 case OTG_STATE_B_IDLE:
876 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
877 /* FALLTHROUGH */
878 case OTG_STATE_B_PERIPHERAL:
879 musb_g_reset(musb);
880 break;
881 default:
882 DBG(1, "Unhandled BUS RESET as %s\n",
883 otg_state_string(musb));
884 }
885 }
886 }
887
888 #if 0
889 /* REVISIT ... this would be for multiplexing periodic endpoints, or
890 * supporting transfer phasing to prevent exceeding ISO bandwidth
891 * limits of a given frame or microframe.
892 *
893 * It's not needed for peripheral side, which dedicates endpoints;
894 * though it _might_ use SOF irqs for other purposes.
895 *
896 * And it's not currently needed for host side, which also dedicates
897 * endpoints, relies on TX/RX interval registers, and isn't claimed
898 * to support ISO transfers yet.
899 */
900 if (int_usb & MUSB_INTR_SOF) {
901 void __iomem *mbase = musb->mregs;
902 struct musb_hw_ep *ep;
903 u8 epnum;
904 u16 frame;
905
906 DBG(6, "START_OF_FRAME\n");
907 handled = IRQ_HANDLED;
908
909 /* start any periodic Tx transfers waiting for current frame */
910 frame = musb_readw(mbase, MUSB_FRAME);
911 ep = musb->endpoints;
912 for (epnum = 1; (epnum < musb->nr_endpoints)
913 && (musb->epmask >= (1 << epnum));
914 epnum++, ep++) {
915 /*
916 * FIXME handle framecounter wraps (12 bits)
917 * eliminate duplicated StartUrb logic
918 */
919 if (ep->dwWaitFrame >= frame) {
920 ep->dwWaitFrame = 0;
921 pr_debug("SOF --> periodic TX%s on %d\n",
922 ep->tx_channel ? " DMA" : "",
923 epnum);
924 if (!ep->tx_channel)
925 musb_h_tx_start(musb, epnum);
926 else
927 cppi_hostdma_start(musb, epnum);
928 }
929 } /* end of for loop */
930 }
931 #endif
932
933 schedule_work(&musb->irq_work);
934
935 return handled;
936 }
937
938 /*-------------------------------------------------------------------------*/
939
940 /*
941 * Program the HDRC to start (enable interrupts, dma, etc.).
942 */
943 void musb_start(struct musb *musb)
944 {
945 void __iomem *regs = musb->mregs;
946 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
947
948 DBG(2, "<== devctl %02x\n", devctl);
949
950 /* Set INT enable registers, enable interrupts */
951 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
952 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
953 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
954
955 musb_writeb(regs, MUSB_TESTMODE, 0);
956
957 /* put into basic highspeed mode and start session */
958 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
959 | MUSB_POWER_SOFTCONN
960 | MUSB_POWER_HSENAB
961 /* ENSUSPEND wedges tusb */
962 /* | MUSB_POWER_ENSUSPEND */
963 );
964
965 musb->is_active = 0;
966 devctl = musb_readb(regs, MUSB_DEVCTL);
967 devctl &= ~MUSB_DEVCTL_SESSION;
968
969 if (is_otg_enabled(musb)) {
970 /* session started after:
971 * (a) ID-grounded irq, host mode;
972 * (b) vbus present/connect IRQ, peripheral mode;
973 * (c) peripheral initiates, using SRP
974 */
975 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
976 musb->is_active = 1;
977 else
978 devctl |= MUSB_DEVCTL_SESSION;
979
980 } else if (is_host_enabled(musb)) {
981 /* assume ID pin is hard-wired to ground */
982 devctl |= MUSB_DEVCTL_SESSION;
983
984 } else /* peripheral is enabled */ {
985 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
986 musb->is_active = 1;
987 }
988 musb_platform_enable(musb);
989 musb_writeb(regs, MUSB_DEVCTL, devctl);
990 }
991
992
993 static void musb_generic_disable(struct musb *musb)
994 {
995 void __iomem *mbase = musb->mregs;
996 u16 temp;
997
998 /* disable interrupts */
999 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1000 musb_writew(mbase, MUSB_INTRTXE, 0);
1001 musb_writew(mbase, MUSB_INTRRXE, 0);
1002
1003 /* off */
1004 musb_writeb(mbase, MUSB_DEVCTL, 0);
1005
1006 /* flush pending interrupts */
1007 temp = musb_readb(mbase, MUSB_INTRUSB);
1008 temp = musb_readw(mbase, MUSB_INTRTX);
1009 temp = musb_readw(mbase, MUSB_INTRRX);
1010
1011 }
1012
1013 /*
1014 * Make the HDRC stop (disable interrupts, etc.);
1015 * reversible by musb_start
1016 * called on gadget driver unregister
1017 * with controller locked, irqs blocked
1018 * acts as a NOP unless some role activated the hardware
1019 */
1020 void musb_stop(struct musb *musb)
1021 {
1022 /* stop IRQs, timers, ... */
1023 musb_platform_disable(musb);
1024 musb_generic_disable(musb);
1025 DBG(3, "HDRC disabled\n");
1026
1027 /* FIXME
1028 * - mark host and/or peripheral drivers unusable/inactive
1029 * - disable DMA (and enable it in HdrcStart)
1030 * - make sure we can musb_start() after musb_stop(); with
1031 * OTG mode, gadget driver module rmmod/modprobe cycles that
1032 * - ...
1033 */
1034 musb_platform_try_idle(musb, 0);
1035 }
1036
1037 static void musb_shutdown(struct platform_device *pdev)
1038 {
1039 struct musb *musb = dev_to_musb(&pdev->dev);
1040 unsigned long flags;
1041
1042 spin_lock_irqsave(&musb->lock, flags);
1043 musb_platform_disable(musb);
1044 musb_generic_disable(musb);
1045 if (musb->clock)
1046 clk_put(musb->clock);
1047 spin_unlock_irqrestore(&musb->lock, flags);
1048
1049 /* FIXME power down */
1050 }
1051
1052
1053 /*-------------------------------------------------------------------------*/
1054
1055 /*
1056 * The silicon either has hard-wired endpoint configurations, or else
1057 * "dynamic fifo" sizing. The driver has support for both, though at this
1058 * writing only the dynamic sizing is very well tested. Since we switched
1059 * away from compile-time hardware parameters, we can no longer rely on
1060 * dead code elimination to leave only the relevant one in the object file.
1061 *
1062 * We don't currently use dynamic fifo setup capability to do anything
1063 * more than selecting one of a bunch of predefined configurations.
1064 */
1065 #if defined(CONFIG_USB_TUSB6010) || \
1066 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1067 || defined(CONFIG_ARCH_OMAP4)
1068 static ushort __initdata fifo_mode = 4;
1069 #else
1070 static ushort __initdata fifo_mode = 2;
1071 #endif
1072
1073 /* "modprobe ... fifo_mode=1" etc */
1074 module_param(fifo_mode, ushort, 0);
1075 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1076
1077 /*
1078 * tables defining fifo_mode values. define more if you like.
1079 * for host side, make sure both halves of ep1 are set up.
1080 */
1081
1082 /* mode 0 - fits in 2KB */
1083 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1084 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1087 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1088 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1089 };
1090
1091 /* mode 1 - fits in 4KB */
1092 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1093 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1094 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1095 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1096 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1097 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1098 };
1099
1100 /* mode 2 - fits in 4KB */
1101 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1102 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1107 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1108 };
1109
1110 /* mode 3 - fits in 4KB */
1111 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1112 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1113 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1114 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1115 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1116 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1117 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1118 };
1119
1120 /* mode 4 - fits in 16KB */
1121 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1122 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1123 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1124 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1125 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1126 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1127 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1128 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1129 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1130 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1131 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1132 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1133 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1134 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1139 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1140 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1141 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1142 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1143 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1144 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1145 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1146 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1147 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1148 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1149 };
1150
1151 /* mode 5 - fits in 8KB */
1152 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1153 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1154 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1155 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1156 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1157 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1158 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1159 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1160 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1161 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1162 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1163 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1164 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1165 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1166 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1167 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1168 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1169 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1170 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1171 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1172 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1173 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1174 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1175 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1176 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1177 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1178 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1179 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1180 };
1181
1182 /*
1183 * configure a fifo; for non-shared endpoints, this may be called
1184 * once for a tx fifo and once for an rx fifo.
1185 *
1186 * returns negative errno or offset for next fifo.
1187 */
1188 static int __init
1189 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1190 const struct musb_fifo_cfg *cfg, u16 offset)
1191 {
1192 void __iomem *mbase = musb->mregs;
1193 int size = 0;
1194 u16 maxpacket = cfg->maxpacket;
1195 u16 c_off = offset >> 3;
1196 u8 c_size;
1197
1198 /* expect hw_ep has already been zero-initialized */
1199
1200 size = ffs(max(maxpacket, (u16) 8)) - 1;
1201 maxpacket = 1 << size;
1202
1203 c_size = size - 3;
1204 if (cfg->mode == BUF_DOUBLE) {
1205 if ((offset + (maxpacket << 1)) >
1206 (1 << (musb->config->ram_bits + 2)))
1207 return -EMSGSIZE;
1208 c_size |= MUSB_FIFOSZ_DPB;
1209 } else {
1210 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1211 return -EMSGSIZE;
1212 }
1213
1214 /* configure the FIFO */
1215 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1216
1217 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1218 /* EP0 reserved endpoint for control, bidirectional;
1219 * EP1 reserved for bulk, two unidirection halves.
1220 */
1221 if (hw_ep->epnum == 1)
1222 musb->bulk_ep = hw_ep;
1223 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1224 #endif
1225 switch (cfg->style) {
1226 case FIFO_TX:
1227 musb_write_txfifosz(mbase, c_size);
1228 musb_write_txfifoadd(mbase, c_off);
1229 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1230 hw_ep->max_packet_sz_tx = maxpacket;
1231 break;
1232 case FIFO_RX:
1233 musb_write_rxfifosz(mbase, c_size);
1234 musb_write_rxfifoadd(mbase, c_off);
1235 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1236 hw_ep->max_packet_sz_rx = maxpacket;
1237 break;
1238 case FIFO_RXTX:
1239 musb_write_txfifosz(mbase, c_size);
1240 musb_write_txfifoadd(mbase, c_off);
1241 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1242 hw_ep->max_packet_sz_rx = maxpacket;
1243
1244 musb_write_rxfifosz(mbase, c_size);
1245 musb_write_rxfifoadd(mbase, c_off);
1246 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1247 hw_ep->max_packet_sz_tx = maxpacket;
1248
1249 hw_ep->is_shared_fifo = true;
1250 break;
1251 }
1252
1253 /* NOTE rx and tx endpoint irqs aren't managed separately,
1254 * which happens to be ok
1255 */
1256 musb->epmask |= (1 << hw_ep->epnum);
1257
1258 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1259 }
1260
1261 static struct musb_fifo_cfg __initdata ep0_cfg = {
1262 .style = FIFO_RXTX, .maxpacket = 64,
1263 };
1264
1265 static int __init ep_config_from_table(struct musb *musb)
1266 {
1267 const struct musb_fifo_cfg *cfg;
1268 unsigned i, n;
1269 int offset;
1270 struct musb_hw_ep *hw_ep = musb->endpoints;
1271
1272 if (musb->config->fifo_cfg) {
1273 cfg = musb->config->fifo_cfg;
1274 n = musb->config->fifo_cfg_size;
1275 goto done;
1276 }
1277
1278 switch (fifo_mode) {
1279 default:
1280 fifo_mode = 0;
1281 /* FALLTHROUGH */
1282 case 0:
1283 cfg = mode_0_cfg;
1284 n = ARRAY_SIZE(mode_0_cfg);
1285 break;
1286 case 1:
1287 cfg = mode_1_cfg;
1288 n = ARRAY_SIZE(mode_1_cfg);
1289 break;
1290 case 2:
1291 cfg = mode_2_cfg;
1292 n = ARRAY_SIZE(mode_2_cfg);
1293 break;
1294 case 3:
1295 cfg = mode_3_cfg;
1296 n = ARRAY_SIZE(mode_3_cfg);
1297 break;
1298 case 4:
1299 cfg = mode_4_cfg;
1300 n = ARRAY_SIZE(mode_4_cfg);
1301 break;
1302 case 5:
1303 cfg = mode_5_cfg;
1304 n = ARRAY_SIZE(mode_5_cfg);
1305 break;
1306 }
1307
1308 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1309 musb_driver_name, fifo_mode);
1310
1311
1312 done:
1313 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1314 /* assert(offset > 0) */
1315
1316 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1317 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1318 */
1319
1320 for (i = 0; i < n; i++) {
1321 u8 epn = cfg->hw_ep_num;
1322
1323 if (epn >= musb->config->num_eps) {
1324 pr_debug("%s: invalid ep %d\n",
1325 musb_driver_name, epn);
1326 return -EINVAL;
1327 }
1328 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1329 if (offset < 0) {
1330 pr_debug("%s: mem overrun, ep %d\n",
1331 musb_driver_name, epn);
1332 return -EINVAL;
1333 }
1334 epn++;
1335 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1336 }
1337
1338 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1339 musb_driver_name,
1340 n + 1, musb->config->num_eps * 2 - 1,
1341 offset, (1 << (musb->config->ram_bits + 2)));
1342
1343 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1344 if (!musb->bulk_ep) {
1345 pr_debug("%s: missing bulk\n", musb_driver_name);
1346 return -EINVAL;
1347 }
1348 #endif
1349
1350 return 0;
1351 }
1352
1353
1354 /*
1355 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1356 * @param musb the controller
1357 */
1358 static int __init ep_config_from_hw(struct musb *musb)
1359 {
1360 u8 epnum = 0;
1361 struct musb_hw_ep *hw_ep;
1362 void *mbase = musb->mregs;
1363 int ret = 0;
1364
1365 DBG(2, "<== static silicon ep config\n");
1366
1367 /* FIXME pick up ep0 maxpacket size */
1368
1369 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1370 musb_ep_select(mbase, epnum);
1371 hw_ep = musb->endpoints + epnum;
1372
1373 ret = musb_read_fifosize(musb, hw_ep, epnum);
1374 if (ret < 0)
1375 break;
1376
1377 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1378
1379 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1380 /* pick an RX/TX endpoint for bulk */
1381 if (hw_ep->max_packet_sz_tx < 512
1382 || hw_ep->max_packet_sz_rx < 512)
1383 continue;
1384
1385 /* REVISIT: this algorithm is lazy, we should at least
1386 * try to pick a double buffered endpoint.
1387 */
1388 if (musb->bulk_ep)
1389 continue;
1390 musb->bulk_ep = hw_ep;
1391 #endif
1392 }
1393
1394 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1395 if (!musb->bulk_ep) {
1396 pr_debug("%s: missing bulk\n", musb_driver_name);
1397 return -EINVAL;
1398 }
1399 #endif
1400
1401 return 0;
1402 }
1403
1404 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1405
1406 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1407 * configure endpoints, or take their config from silicon
1408 */
1409 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1410 {
1411 u8 reg;
1412 char *type;
1413 char aInfo[90], aRevision[32], aDate[12];
1414 void __iomem *mbase = musb->mregs;
1415 int status = 0;
1416 int i;
1417
1418 /* log core options (read using indexed model) */
1419 reg = musb_read_configdata(mbase);
1420
1421 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1422 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1423 strcat(aInfo, ", dyn FIFOs");
1424 musb->dyn_fifo = true;
1425 }
1426 if (reg & MUSB_CONFIGDATA_MPRXE) {
1427 strcat(aInfo, ", bulk combine");
1428 musb->bulk_combine = true;
1429 }
1430 if (reg & MUSB_CONFIGDATA_MPTXE) {
1431 strcat(aInfo, ", bulk split");
1432 musb->bulk_split = true;
1433 }
1434 if (reg & MUSB_CONFIGDATA_HBRXE) {
1435 strcat(aInfo, ", HB-ISO Rx");
1436 musb->hb_iso_rx = true;
1437 }
1438 if (reg & MUSB_CONFIGDATA_HBTXE) {
1439 strcat(aInfo, ", HB-ISO Tx");
1440 musb->hb_iso_tx = true;
1441 }
1442 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1443 strcat(aInfo, ", SoftConn");
1444
1445 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1446 musb_driver_name, reg, aInfo);
1447
1448 aDate[0] = 0;
1449 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1450 musb->is_multipoint = 1;
1451 type = "M";
1452 } else {
1453 musb->is_multipoint = 0;
1454 type = "";
1455 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1456 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1457 printk(KERN_ERR
1458 "%s: kernel must blacklist external hubs\n",
1459 musb_driver_name);
1460 #endif
1461 #endif
1462 }
1463
1464 /* log release info */
1465 musb->hwvers = musb_read_hwvers(mbase);
1466 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1467 MUSB_HWVERS_MINOR(musb->hwvers),
1468 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1469 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1470 musb_driver_name, type, aRevision, aDate);
1471
1472 /* configure ep0 */
1473 musb_configure_ep0(musb);
1474
1475 /* discover endpoint configuration */
1476 musb->nr_endpoints = 1;
1477 musb->epmask = 1;
1478
1479 if (musb->dyn_fifo)
1480 status = ep_config_from_table(musb);
1481 else
1482 status = ep_config_from_hw(musb);
1483
1484 if (status < 0)
1485 return status;
1486
1487 /* finish init, and print endpoint config */
1488 for (i = 0; i < musb->nr_endpoints; i++) {
1489 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1490
1491 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1492 #ifdef CONFIG_USB_TUSB6010
1493 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1494 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1495 hw_ep->fifo_sync_va =
1496 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1497
1498 if (i == 0)
1499 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1500 else
1501 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1502 #endif
1503
1504 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1505 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1506 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1507 hw_ep->rx_reinit = 1;
1508 hw_ep->tx_reinit = 1;
1509 #endif
1510
1511 if (hw_ep->max_packet_sz_tx) {
1512 DBG(1,
1513 "%s: hw_ep %d%s, %smax %d\n",
1514 musb_driver_name, i,
1515 hw_ep->is_shared_fifo ? "shared" : "tx",
1516 hw_ep->tx_double_buffered
1517 ? "doublebuffer, " : "",
1518 hw_ep->max_packet_sz_tx);
1519 }
1520 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1521 DBG(1,
1522 "%s: hw_ep %d%s, %smax %d\n",
1523 musb_driver_name, i,
1524 "rx",
1525 hw_ep->rx_double_buffered
1526 ? "doublebuffer, " : "",
1527 hw_ep->max_packet_sz_rx);
1528 }
1529 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1530 DBG(1, "hw_ep %d not configured\n", i);
1531 }
1532
1533 return 0;
1534 }
1535
1536 /*-------------------------------------------------------------------------*/
1537
1538 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
1539 defined(CONFIG_ARCH_OMAP4)
1540
1541 static irqreturn_t generic_interrupt(int irq, void *__hci)
1542 {
1543 unsigned long flags;
1544 irqreturn_t retval = IRQ_NONE;
1545 struct musb *musb = __hci;
1546
1547 spin_lock_irqsave(&musb->lock, flags);
1548
1549 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1550 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1551 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1552
1553 if (musb->int_usb || musb->int_tx || musb->int_rx)
1554 retval = musb_interrupt(musb);
1555
1556 spin_unlock_irqrestore(&musb->lock, flags);
1557
1558 return retval;
1559 }
1560
1561 #else
1562 #define generic_interrupt NULL
1563 #endif
1564
1565 /*
1566 * handle all the irqs defined by the HDRC core. for now we expect: other
1567 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1568 * will be assigned, and the irq will already have been acked.
1569 *
1570 * called in irq context with spinlock held, irqs blocked
1571 */
1572 irqreturn_t musb_interrupt(struct musb *musb)
1573 {
1574 irqreturn_t retval = IRQ_NONE;
1575 u8 devctl, power;
1576 int ep_num;
1577 u32 reg;
1578
1579 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1580 power = musb_readb(musb->mregs, MUSB_POWER);
1581
1582 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1583 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1584 musb->int_usb, musb->int_tx, musb->int_rx);
1585
1586 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1587 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1588 if (!musb->gadget_driver) {
1589 DBG(5, "No gadget driver loaded\n");
1590 return IRQ_HANDLED;
1591 }
1592 #endif
1593
1594 /* the core can interrupt us for multiple reasons; docs have
1595 * a generic interrupt flowchart to follow
1596 */
1597 if (musb->int_usb)
1598 retval |= musb_stage0_irq(musb, musb->int_usb,
1599 devctl, power);
1600
1601 /* "stage 1" is handling endpoint irqs */
1602
1603 /* handle endpoint 0 first */
1604 if (musb->int_tx & 1) {
1605 if (devctl & MUSB_DEVCTL_HM)
1606 retval |= musb_h_ep0_irq(musb);
1607 else
1608 retval |= musb_g_ep0_irq(musb);
1609 }
1610
1611 /* RX on endpoints 1-15 */
1612 reg = musb->int_rx >> 1;
1613 ep_num = 1;
1614 while (reg) {
1615 if (reg & 1) {
1616 /* musb_ep_select(musb->mregs, ep_num); */
1617 /* REVISIT just retval = ep->rx_irq(...) */
1618 retval = IRQ_HANDLED;
1619 if (devctl & MUSB_DEVCTL_HM) {
1620 if (is_host_capable())
1621 musb_host_rx(musb, ep_num);
1622 } else {
1623 if (is_peripheral_capable())
1624 musb_g_rx(musb, ep_num);
1625 }
1626 }
1627
1628 reg >>= 1;
1629 ep_num++;
1630 }
1631
1632 /* TX on endpoints 1-15 */
1633 reg = musb->int_tx >> 1;
1634 ep_num = 1;
1635 while (reg) {
1636 if (reg & 1) {
1637 /* musb_ep_select(musb->mregs, ep_num); */
1638 /* REVISIT just retval |= ep->tx_irq(...) */
1639 retval = IRQ_HANDLED;
1640 if (devctl & MUSB_DEVCTL_HM) {
1641 if (is_host_capable())
1642 musb_host_tx(musb, ep_num);
1643 } else {
1644 if (is_peripheral_capable())
1645 musb_g_tx(musb, ep_num);
1646 }
1647 }
1648 reg >>= 1;
1649 ep_num++;
1650 }
1651
1652 return retval;
1653 }
1654
1655
1656 #ifndef CONFIG_MUSB_PIO_ONLY
1657 static int __initdata use_dma = 1;
1658
1659 /* "modprobe ... use_dma=0" etc */
1660 module_param(use_dma, bool, 0);
1661 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1662
1663 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1664 {
1665 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1666
1667 /* called with controller lock already held */
1668
1669 if (!epnum) {
1670 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1671 if (!is_cppi_enabled()) {
1672 /* endpoint 0 */
1673 if (devctl & MUSB_DEVCTL_HM)
1674 musb_h_ep0_irq(musb);
1675 else
1676 musb_g_ep0_irq(musb);
1677 }
1678 #endif
1679 } else {
1680 /* endpoints 1..15 */
1681 if (transmit) {
1682 if (devctl & MUSB_DEVCTL_HM) {
1683 if (is_host_capable())
1684 musb_host_tx(musb, epnum);
1685 } else {
1686 if (is_peripheral_capable())
1687 musb_g_tx(musb, epnum);
1688 }
1689 } else {
1690 /* receive */
1691 if (devctl & MUSB_DEVCTL_HM) {
1692 if (is_host_capable())
1693 musb_host_rx(musb, epnum);
1694 } else {
1695 if (is_peripheral_capable())
1696 musb_g_rx(musb, epnum);
1697 }
1698 }
1699 }
1700 }
1701
1702 #else
1703 #define use_dma 0
1704 #endif
1705
1706 /*-------------------------------------------------------------------------*/
1707
1708 #ifdef CONFIG_SYSFS
1709
1710 static ssize_t
1711 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1712 {
1713 struct musb *musb = dev_to_musb(dev);
1714 unsigned long flags;
1715 int ret = -EINVAL;
1716
1717 spin_lock_irqsave(&musb->lock, flags);
1718 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1719 spin_unlock_irqrestore(&musb->lock, flags);
1720
1721 return ret;
1722 }
1723
1724 static ssize_t
1725 musb_mode_store(struct device *dev, struct device_attribute *attr,
1726 const char *buf, size_t n)
1727 {
1728 struct musb *musb = dev_to_musb(dev);
1729 unsigned long flags;
1730 int status;
1731
1732 spin_lock_irqsave(&musb->lock, flags);
1733 if (sysfs_streq(buf, "host"))
1734 status = musb_platform_set_mode(musb, MUSB_HOST);
1735 else if (sysfs_streq(buf, "peripheral"))
1736 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1737 else if (sysfs_streq(buf, "otg"))
1738 status = musb_platform_set_mode(musb, MUSB_OTG);
1739 else
1740 status = -EINVAL;
1741 spin_unlock_irqrestore(&musb->lock, flags);
1742
1743 return (status == 0) ? n : status;
1744 }
1745 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1746
1747 static ssize_t
1748 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1749 const char *buf, size_t n)
1750 {
1751 struct musb *musb = dev_to_musb(dev);
1752 unsigned long flags;
1753 unsigned long val;
1754
1755 if (sscanf(buf, "%lu", &val) < 1) {
1756 dev_err(dev, "Invalid VBUS timeout ms value\n");
1757 return -EINVAL;
1758 }
1759
1760 spin_lock_irqsave(&musb->lock, flags);
1761 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1762 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1763 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1764 musb->is_active = 0;
1765 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1766 spin_unlock_irqrestore(&musb->lock, flags);
1767
1768 return n;
1769 }
1770
1771 static ssize_t
1772 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1773 {
1774 struct musb *musb = dev_to_musb(dev);
1775 unsigned long flags;
1776 unsigned long val;
1777 int vbus;
1778
1779 spin_lock_irqsave(&musb->lock, flags);
1780 val = musb->a_wait_bcon;
1781 /* FIXME get_vbus_status() is normally #defined as false...
1782 * and is effectively TUSB-specific.
1783 */
1784 vbus = musb_platform_get_vbus_status(musb);
1785 spin_unlock_irqrestore(&musb->lock, flags);
1786
1787 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1788 vbus ? "on" : "off", val);
1789 }
1790 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1791
1792 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1793
1794 /* Gadget drivers can't know that a host is connected so they might want
1795 * to start SRP, but users can. This allows userspace to trigger SRP.
1796 */
1797 static ssize_t
1798 musb_srp_store(struct device *dev, struct device_attribute *attr,
1799 const char *buf, size_t n)
1800 {
1801 struct musb *musb = dev_to_musb(dev);
1802 unsigned short srp;
1803
1804 if (sscanf(buf, "%hu", &srp) != 1
1805 || (srp != 1)) {
1806 dev_err(dev, "SRP: Value must be 1\n");
1807 return -EINVAL;
1808 }
1809
1810 if (srp == 1)
1811 musb_g_wakeup(musb);
1812
1813 return n;
1814 }
1815 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1816
1817 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1818
1819 static struct attribute *musb_attributes[] = {
1820 &dev_attr_mode.attr,
1821 &dev_attr_vbus.attr,
1822 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1823 &dev_attr_srp.attr,
1824 #endif
1825 NULL
1826 };
1827
1828 static const struct attribute_group musb_attr_group = {
1829 .attrs = musb_attributes,
1830 };
1831
1832 #endif /* sysfs */
1833
1834 /* Only used to provide driver mode change events */
1835 static void musb_irq_work(struct work_struct *data)
1836 {
1837 struct musb *musb = container_of(data, struct musb, irq_work);
1838 static int old_state;
1839
1840 if (musb->xceiv->state != old_state) {
1841 old_state = musb->xceiv->state;
1842 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1843 }
1844 }
1845
1846 /* --------------------------------------------------------------------------
1847 * Init support
1848 */
1849
1850 static struct musb *__init
1851 allocate_instance(struct device *dev,
1852 struct musb_hdrc_config *config, void __iomem *mbase)
1853 {
1854 struct musb *musb;
1855 struct musb_hw_ep *ep;
1856 int epnum;
1857 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1858 struct usb_hcd *hcd;
1859
1860 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1861 if (!hcd)
1862 return NULL;
1863 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1864
1865 musb = hcd_to_musb(hcd);
1866 INIT_LIST_HEAD(&musb->control);
1867 INIT_LIST_HEAD(&musb->in_bulk);
1868 INIT_LIST_HEAD(&musb->out_bulk);
1869
1870 hcd->uses_new_polling = 1;
1871
1872 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1873 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1874 #else
1875 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1876 if (!musb)
1877 return NULL;
1878 dev_set_drvdata(dev, musb);
1879
1880 #endif
1881
1882 musb->mregs = mbase;
1883 musb->ctrl_base = mbase;
1884 musb->nIrq = -ENODEV;
1885 musb->config = config;
1886 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1887 for (epnum = 0, ep = musb->endpoints;
1888 epnum < musb->config->num_eps;
1889 epnum++, ep++) {
1890 ep->musb = musb;
1891 ep->epnum = epnum;
1892 }
1893
1894 musb->controller = dev;
1895 return musb;
1896 }
1897
1898 static void musb_free(struct musb *musb)
1899 {
1900 /* this has multiple entry modes. it handles fault cleanup after
1901 * probe(), where things may be partially set up, as well as rmmod
1902 * cleanup after everything's been de-activated.
1903 */
1904
1905 #ifdef CONFIG_SYSFS
1906 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1907 #endif
1908
1909 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1910 musb_gadget_cleanup(musb);
1911 #endif
1912
1913 if (musb->nIrq >= 0) {
1914 if (musb->irq_wake)
1915 disable_irq_wake(musb->nIrq);
1916 free_irq(musb->nIrq, musb);
1917 }
1918 if (is_dma_capable() && musb->dma_controller) {
1919 struct dma_controller *c = musb->dma_controller;
1920
1921 (void) c->stop(c);
1922 dma_controller_destroy(c);
1923 }
1924
1925 #ifdef CONFIG_USB_MUSB_OTG
1926 put_device(musb->xceiv->dev);
1927 #endif
1928
1929 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1930 usb_put_hcd(musb_to_hcd(musb));
1931 #else
1932 kfree(musb);
1933 #endif
1934 }
1935
1936 /*
1937 * Perform generic per-controller initialization.
1938 *
1939 * @pDevice: the controller (already clocked, etc)
1940 * @nIrq: irq
1941 * @mregs: virtual address of controller registers,
1942 * not yet corrected for platform-specific offsets
1943 */
1944 static int __init
1945 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1946 {
1947 int status;
1948 struct musb *musb;
1949 struct musb_hdrc_platform_data *plat = dev->platform_data;
1950
1951 /* The driver might handle more features than the board; OK.
1952 * Fail when the board needs a feature that's not enabled.
1953 */
1954 if (!plat) {
1955 dev_dbg(dev, "no platform_data?\n");
1956 status = -ENODEV;
1957 goto fail0;
1958 }
1959
1960 switch (plat->mode) {
1961 case MUSB_HOST:
1962 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1963 break;
1964 #else
1965 goto bad_config;
1966 #endif
1967 case MUSB_PERIPHERAL:
1968 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1969 break;
1970 #else
1971 goto bad_config;
1972 #endif
1973 case MUSB_OTG:
1974 #ifdef CONFIG_USB_MUSB_OTG
1975 break;
1976 #else
1977 bad_config:
1978 #endif
1979 default:
1980 dev_err(dev, "incompatible Kconfig role setting\n");
1981 status = -EINVAL;
1982 goto fail0;
1983 }
1984
1985 /* allocate */
1986 musb = allocate_instance(dev, plat->config, ctrl);
1987 if (!musb) {
1988 status = -ENOMEM;
1989 goto fail0;
1990 }
1991
1992 spin_lock_init(&musb->lock);
1993 musb->board_mode = plat->mode;
1994 musb->board_set_power = plat->set_power;
1995 musb->set_clock = plat->set_clock;
1996 musb->min_power = plat->min_power;
1997
1998 /* Clock usage is chip-specific ... functional clock (DaVinci,
1999 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
2000 * code does is make sure a clock handle is available; platform
2001 * code manages it during start/stop and suspend/resume.
2002 */
2003 if (plat->clock) {
2004 musb->clock = clk_get(dev, plat->clock);
2005 if (IS_ERR(musb->clock)) {
2006 status = PTR_ERR(musb->clock);
2007 musb->clock = NULL;
2008 goto fail1;
2009 }
2010 }
2011
2012 /* The musb_platform_init() call:
2013 * - adjusts musb->mregs and musb->isr if needed,
2014 * - may initialize an integrated tranceiver
2015 * - initializes musb->xceiv, usually by otg_get_transceiver()
2016 * - activates clocks.
2017 * - stops powering VBUS
2018 * - assigns musb->board_set_vbus if host mode is enabled
2019 *
2020 * There are various transciever configurations. Blackfin,
2021 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2022 * external/discrete ones in various flavors (twl4030 family,
2023 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2024 */
2025 musb->isr = generic_interrupt;
2026 status = musb_platform_init(musb, plat->board_data);
2027 if (status < 0)
2028 goto fail2;
2029
2030 if (!musb->isr) {
2031 status = -ENODEV;
2032 goto fail3;
2033 }
2034
2035 if (!musb->xceiv->io_ops) {
2036 musb->xceiv->io_priv = musb->mregs;
2037 musb->xceiv->io_ops = &musb_ulpi_access;
2038 }
2039
2040 #ifndef CONFIG_MUSB_PIO_ONLY
2041 if (use_dma && dev->dma_mask) {
2042 struct dma_controller *c;
2043
2044 c = dma_controller_create(musb, musb->mregs);
2045 musb->dma_controller = c;
2046 if (c)
2047 (void) c->start(c);
2048 }
2049 #endif
2050 /* ideally this would be abstracted in platform setup */
2051 if (!is_dma_capable() || !musb->dma_controller)
2052 dev->dma_mask = NULL;
2053
2054 /* be sure interrupts are disabled before connecting ISR */
2055 musb_platform_disable(musb);
2056 musb_generic_disable(musb);
2057
2058 /* setup musb parts of the core (especially endpoints) */
2059 status = musb_core_init(plat->config->multipoint
2060 ? MUSB_CONTROLLER_MHDRC
2061 : MUSB_CONTROLLER_HDRC, musb);
2062 if (status < 0)
2063 goto fail3;
2064
2065 #ifdef CONFIG_USB_MUSB_OTG
2066 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2067 #endif
2068
2069 /* Init IRQ workqueue before request_irq */
2070 INIT_WORK(&musb->irq_work, musb_irq_work);
2071
2072 /* attach to the IRQ */
2073 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2074 dev_err(dev, "request_irq %d failed!\n", nIrq);
2075 status = -ENODEV;
2076 goto fail3;
2077 }
2078 musb->nIrq = nIrq;
2079 /* FIXME this handles wakeup irqs wrong */
2080 if (enable_irq_wake(nIrq) == 0) {
2081 musb->irq_wake = 1;
2082 device_init_wakeup(dev, 1);
2083 } else {
2084 musb->irq_wake = 0;
2085 }
2086
2087 /* host side needs more setup */
2088 if (is_host_enabled(musb)) {
2089 struct usb_hcd *hcd = musb_to_hcd(musb);
2090
2091 otg_set_host(musb->xceiv, &hcd->self);
2092
2093 if (is_otg_enabled(musb))
2094 hcd->self.otg_port = 1;
2095 musb->xceiv->host = &hcd->self;
2096 hcd->power_budget = 2 * (plat->power ? : 250);
2097
2098 /* program PHY to use external vBus if required */
2099 if (plat->extvbus) {
2100 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2101 busctl |= MUSB_ULPI_USE_EXTVBUS;
2102 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2103 }
2104 }
2105
2106 /* For the host-only role, we can activate right away.
2107 * (We expect the ID pin to be forcibly grounded!!)
2108 * Otherwise, wait till the gadget driver hooks up.
2109 */
2110 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2111 MUSB_HST_MODE(musb);
2112 musb->xceiv->default_a = 1;
2113 musb->xceiv->state = OTG_STATE_A_IDLE;
2114
2115 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2116
2117 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2118 "HOST", status,
2119 musb_readb(musb->mregs, MUSB_DEVCTL),
2120 (musb_readb(musb->mregs, MUSB_DEVCTL)
2121 & MUSB_DEVCTL_BDEVICE
2122 ? 'B' : 'A'));
2123
2124 } else /* peripheral is enabled */ {
2125 MUSB_DEV_MODE(musb);
2126 musb->xceiv->default_a = 0;
2127 musb->xceiv->state = OTG_STATE_B_IDLE;
2128
2129 status = musb_gadget_setup(musb);
2130
2131 DBG(1, "%s mode, status %d, dev%02x\n",
2132 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2133 status,
2134 musb_readb(musb->mregs, MUSB_DEVCTL));
2135
2136 }
2137 if (status < 0)
2138 goto fail3;
2139
2140 status = musb_init_debugfs(musb);
2141 if (status < 0)
2142 goto fail4;
2143
2144 #ifdef CONFIG_SYSFS
2145 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2146 if (status)
2147 goto fail5;
2148 #endif
2149
2150 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2151 ({char *s;
2152 switch (musb->board_mode) {
2153 case MUSB_HOST: s = "Host"; break;
2154 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2155 default: s = "OTG"; break;
2156 }; s; }),
2157 ctrl,
2158 (is_dma_capable() && musb->dma_controller)
2159 ? "DMA" : "PIO",
2160 musb->nIrq);
2161
2162 return 0;
2163
2164 fail5:
2165 musb_exit_debugfs(musb);
2166
2167 fail4:
2168 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2169 usb_remove_hcd(musb_to_hcd(musb));
2170 else
2171 musb_gadget_cleanup(musb);
2172
2173 fail3:
2174 if (musb->irq_wake)
2175 device_init_wakeup(dev, 0);
2176 musb_platform_exit(musb);
2177
2178 fail2:
2179 if (musb->clock)
2180 clk_put(musb->clock);
2181
2182 fail1:
2183 dev_err(musb->controller,
2184 "musb_init_controller failed with status %d\n", status);
2185
2186 musb_free(musb);
2187
2188 fail0:
2189
2190 return status;
2191
2192 }
2193
2194 /*-------------------------------------------------------------------------*/
2195
2196 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2197 * bridge to a platform device; this driver then suffices.
2198 */
2199
2200 #ifndef CONFIG_MUSB_PIO_ONLY
2201 static u64 *orig_dma_mask;
2202 #endif
2203
2204 static int __init musb_probe(struct platform_device *pdev)
2205 {
2206 struct device *dev = &pdev->dev;
2207 int irq = platform_get_irq(pdev, 0);
2208 int status;
2209 struct resource *iomem;
2210 void __iomem *base;
2211
2212 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2213 if (!iomem || irq == 0)
2214 return -ENODEV;
2215
2216 base = ioremap(iomem->start, resource_size(iomem));
2217 if (!base) {
2218 dev_err(dev, "ioremap failed\n");
2219 return -ENOMEM;
2220 }
2221
2222 #ifndef CONFIG_MUSB_PIO_ONLY
2223 /* clobbered by use_dma=n */
2224 orig_dma_mask = dev->dma_mask;
2225 #endif
2226 status = musb_init_controller(dev, irq, base);
2227 if (status < 0)
2228 iounmap(base);
2229
2230 return status;
2231 }
2232
2233 static int __exit musb_remove(struct platform_device *pdev)
2234 {
2235 struct musb *musb = dev_to_musb(&pdev->dev);
2236 void __iomem *ctrl_base = musb->ctrl_base;
2237
2238 /* this gets called on rmmod.
2239 * - Host mode: host may still be active
2240 * - Peripheral mode: peripheral is deactivated (or never-activated)
2241 * - OTG mode: both roles are deactivated (or never-activated)
2242 */
2243 musb_exit_debugfs(musb);
2244 musb_shutdown(pdev);
2245 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2246 if (musb->board_mode == MUSB_HOST)
2247 usb_remove_hcd(musb_to_hcd(musb));
2248 #endif
2249 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2250 musb_platform_exit(musb);
2251 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2252
2253 musb_free(musb);
2254 iounmap(ctrl_base);
2255 device_init_wakeup(&pdev->dev, 0);
2256 #ifndef CONFIG_MUSB_PIO_ONLY
2257 pdev->dev.dma_mask = orig_dma_mask;
2258 #endif
2259 return 0;
2260 }
2261
2262 #ifdef CONFIG_PM
2263
2264 static struct musb_context_registers musb_context;
2265
2266 void musb_save_context(struct musb *musb)
2267 {
2268 int i;
2269 void __iomem *musb_base = musb->mregs;
2270
2271 if (is_host_enabled(musb)) {
2272 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2273 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2274 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2275 }
2276 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2277 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2278 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2279 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2280 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2281 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2282
2283 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2284 musb_writeb(musb_base, MUSB_INDEX, i);
2285 musb_context.index_regs[i].txmaxp =
2286 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2287 musb_context.index_regs[i].txcsr =
2288 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2289 musb_context.index_regs[i].rxmaxp =
2290 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2291 musb_context.index_regs[i].rxcsr =
2292 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2293
2294 if (musb->dyn_fifo) {
2295 musb_context.index_regs[i].txfifoadd =
2296 musb_read_txfifoadd(musb_base);
2297 musb_context.index_regs[i].rxfifoadd =
2298 musb_read_rxfifoadd(musb_base);
2299 musb_context.index_regs[i].txfifosz =
2300 musb_read_txfifosz(musb_base);
2301 musb_context.index_regs[i].rxfifosz =
2302 musb_read_rxfifosz(musb_base);
2303 }
2304 if (is_host_enabled(musb)) {
2305 musb_context.index_regs[i].txtype =
2306 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2307 musb_context.index_regs[i].txinterval =
2308 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2309 musb_context.index_regs[i].rxtype =
2310 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2311 musb_context.index_regs[i].rxinterval =
2312 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2313
2314 musb_context.index_regs[i].txfunaddr =
2315 musb_read_txfunaddr(musb_base, i);
2316 musb_context.index_regs[i].txhubaddr =
2317 musb_read_txhubaddr(musb_base, i);
2318 musb_context.index_regs[i].txhubport =
2319 musb_read_txhubport(musb_base, i);
2320
2321 musb_context.index_regs[i].rxfunaddr =
2322 musb_read_rxfunaddr(musb_base, i);
2323 musb_context.index_regs[i].rxhubaddr =
2324 musb_read_rxhubaddr(musb_base, i);
2325 musb_context.index_regs[i].rxhubport =
2326 musb_read_rxhubport(musb_base, i);
2327 }
2328 }
2329
2330 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2331
2332 musb_platform_save_context(musb, &musb_context);
2333 }
2334
2335 void musb_restore_context(struct musb *musb)
2336 {
2337 int i;
2338 void __iomem *musb_base = musb->mregs;
2339 void __iomem *ep_target_regs;
2340
2341 musb_platform_restore_context(musb, &musb_context);
2342
2343 if (is_host_enabled(musb)) {
2344 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2345 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2346 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2347 }
2348 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2349 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2350 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2351 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2352 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2353
2354 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2355 musb_writeb(musb_base, MUSB_INDEX, i);
2356 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2357 musb_context.index_regs[i].txmaxp);
2358 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2359 musb_context.index_regs[i].txcsr);
2360 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2361 musb_context.index_regs[i].rxmaxp);
2362 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2363 musb_context.index_regs[i].rxcsr);
2364
2365 if (musb->dyn_fifo) {
2366 musb_write_txfifosz(musb_base,
2367 musb_context.index_regs[i].txfifosz);
2368 musb_write_rxfifosz(musb_base,
2369 musb_context.index_regs[i].rxfifosz);
2370 musb_write_txfifoadd(musb_base,
2371 musb_context.index_regs[i].txfifoadd);
2372 musb_write_rxfifoadd(musb_base,
2373 musb_context.index_regs[i].rxfifoadd);
2374 }
2375
2376 if (is_host_enabled(musb)) {
2377 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2378 musb_context.index_regs[i].txtype);
2379 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2380 musb_context.index_regs[i].txinterval);
2381 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2382 musb_context.index_regs[i].rxtype);
2383 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2384
2385 musb_context.index_regs[i].rxinterval);
2386 musb_write_txfunaddr(musb_base, i,
2387 musb_context.index_regs[i].txfunaddr);
2388 musb_write_txhubaddr(musb_base, i,
2389 musb_context.index_regs[i].txhubaddr);
2390 musb_write_txhubport(musb_base, i,
2391 musb_context.index_regs[i].txhubport);
2392
2393 ep_target_regs =
2394 musb_read_target_reg_base(i, musb_base);
2395
2396 musb_write_rxfunaddr(ep_target_regs,
2397 musb_context.index_regs[i].rxfunaddr);
2398 musb_write_rxhubaddr(ep_target_regs,
2399 musb_context.index_regs[i].rxhubaddr);
2400 musb_write_rxhubport(ep_target_regs,
2401 musb_context.index_regs[i].rxhubport);
2402 }
2403 }
2404
2405 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2406 }
2407
2408 static int musb_suspend(struct device *dev)
2409 {
2410 struct platform_device *pdev = to_platform_device(dev);
2411 unsigned long flags;
2412 struct musb *musb = dev_to_musb(&pdev->dev);
2413
2414 if (!musb->clock)
2415 return 0;
2416
2417 spin_lock_irqsave(&musb->lock, flags);
2418
2419 if (is_peripheral_active(musb)) {
2420 /* FIXME force disconnect unless we know USB will wake
2421 * the system up quickly enough to respond ...
2422 */
2423 } else if (is_host_active(musb)) {
2424 /* we know all the children are suspended; sometimes
2425 * they will even be wakeup-enabled.
2426 */
2427 }
2428
2429 musb_save_context(musb);
2430
2431 if (musb->set_clock)
2432 musb->set_clock(musb->clock, 0);
2433 else
2434 clk_disable(musb->clock);
2435 spin_unlock_irqrestore(&musb->lock, flags);
2436 return 0;
2437 }
2438
2439 static int musb_resume_noirq(struct device *dev)
2440 {
2441 struct platform_device *pdev = to_platform_device(dev);
2442 struct musb *musb = dev_to_musb(&pdev->dev);
2443
2444 if (!musb->clock)
2445 return 0;
2446
2447 if (musb->set_clock)
2448 musb->set_clock(musb->clock, 1);
2449 else
2450 clk_enable(musb->clock);
2451
2452 musb_restore_context(musb);
2453
2454 /* for static cmos like DaVinci, register values were preserved
2455 * unless for some reason the whole soc powered down or the USB
2456 * module got reset through the PSC (vs just being disabled).
2457 */
2458 return 0;
2459 }
2460
2461 static const struct dev_pm_ops musb_dev_pm_ops = {
2462 .suspend = musb_suspend,
2463 .resume_noirq = musb_resume_noirq,
2464 };
2465
2466 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2467 #else
2468 #define MUSB_DEV_PM_OPS NULL
2469 #endif
2470
2471 static struct platform_driver musb_driver = {
2472 .driver = {
2473 .name = (char *)musb_driver_name,
2474 .bus = &platform_bus_type,
2475 .owner = THIS_MODULE,
2476 .pm = MUSB_DEV_PM_OPS,
2477 },
2478 .remove = __exit_p(musb_remove),
2479 .shutdown = musb_shutdown,
2480 };
2481
2482 /*-------------------------------------------------------------------------*/
2483
2484 static int __init musb_init(void)
2485 {
2486 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2487 if (usb_disabled())
2488 return 0;
2489 #endif
2490
2491 pr_info("%s: version " MUSB_VERSION ", "
2492 #ifdef CONFIG_MUSB_PIO_ONLY
2493 "pio"
2494 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2495 "cppi-dma"
2496 #elif defined(CONFIG_USB_INVENTRA_DMA)
2497 "musb-dma"
2498 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2499 "tusb-omap-dma"
2500 #else
2501 "?dma?"
2502 #endif
2503 ", "
2504 #ifdef CONFIG_USB_MUSB_OTG
2505 "otg (peripheral+host)"
2506 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2507 "peripheral"
2508 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2509 "host"
2510 #endif
2511 ", debug=%d\n",
2512 musb_driver_name, musb_debug);
2513 return platform_driver_probe(&musb_driver, musb_probe);
2514 }
2515
2516 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2517 * and before usb gadget and host-side drivers start to register
2518 */
2519 fs_initcall(musb_init);
2520
2521 static void __exit musb_cleanup(void)
2522 {
2523 platform_driver_unregister(&musb_driver);
2524 }
2525 module_exit(musb_cleanup);
Linux kernel - Deliverables
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