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usb: musb: don't touch devctl from babble recovery
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102
103 #include "musb_core.h"
104
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111 #define MUSB_VERSION "6.0"
112
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124 /*-------------------------------------------------------------------------*/
125
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128 return dev_get_drvdata(dev);
129 }
130
131 /*-------------------------------------------------------------------------*/
132
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136 void __iomem *addr = phy->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172 out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
176 }
177
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180 void __iomem *addr = phy->io_priv;
181 int i = 0;
182 u8 r = 0;
183 u8 power;
184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
210 out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
214 }
215 #else
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
218 #endif
219
220 static struct usb_phy_io_ops musb_ulpi_access = {
221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223 };
224
225 /*-------------------------------------------------------------------------*/
226
227 static u32 musb_default_fifo_offset(u8 epnum)
228 {
229 return 0x20 + (epnum * 4);
230 }
231
232 /* "flat" mapping: each endpoint has its own i/o address */
233 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
234 {
235 }
236
237 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
238 {
239 return 0x100 + (0x10 * epnum) + offset;
240 }
241
242 /* "indexed" mapping: INDEX register controls register bank select */
243 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
244 {
245 musb_writeb(mbase, MUSB_INDEX, epnum);
246 }
247
248 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
249 {
250 return 0x10 + offset;
251 }
252
253 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
254 {
255 return __raw_readb(addr + offset);
256 }
257
258 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
259 {
260 __raw_writeb(data, addr + offset);
261 }
262
263 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264 {
265 return __raw_readw(addr + offset);
266 }
267
268 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
269 {
270 __raw_writew(data, addr + offset);
271 }
272
273 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
274 {
275 return __raw_readl(addr + offset);
276 }
277
278 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
279 {
280 __raw_writel(data, addr + offset);
281 }
282
283 /*
284 * Load an endpoint's FIFO
285 */
286 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
287 const u8 *src)
288 {
289 struct musb *musb = hw_ep->musb;
290 void __iomem *fifo = hw_ep->fifo;
291
292 if (unlikely(len == 0))
293 return;
294
295 prefetch((u8 *)src);
296
297 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
298 'T', hw_ep->epnum, fifo, len, src);
299
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src) == 0)) {
302 u16 index = 0;
303
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src) == 0) {
306 if (len >= 4) {
307 iowrite32_rep(fifo, src + index, len >> 2);
308 index += len & ~0x03;
309 }
310 if (len & 0x02) {
311 musb_writew(fifo, 0, *(u16 *)&src[index]);
312 index += 2;
313 }
314 } else {
315 if (len >= 2) {
316 iowrite16_rep(fifo, src + index, len >> 1);
317 index += len & ~0x01;
318 }
319 }
320 if (len & 0x01)
321 musb_writeb(fifo, 0, src[index]);
322 } else {
323 /* byte aligned */
324 iowrite8_rep(fifo, src, len);
325 }
326 }
327
328 /*
329 * Unload an endpoint's FIFO
330 */
331 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
332 {
333 struct musb *musb = hw_ep->musb;
334 void __iomem *fifo = hw_ep->fifo;
335
336 if (unlikely(len == 0))
337 return;
338
339 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
340 'R', hw_ep->epnum, fifo, len, dst);
341
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst) == 0)) {
344 u16 index = 0;
345
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst) == 0) {
348 if (len >= 4) {
349 ioread32_rep(fifo, dst, len >> 2);
350 index = len & ~0x03;
351 }
352 if (len & 0x02) {
353 *(u16 *)&dst[index] = musb_readw(fifo, 0);
354 index += 2;
355 }
356 } else {
357 if (len >= 2) {
358 ioread16_rep(fifo, dst, len >> 1);
359 index = len & ~0x01;
360 }
361 }
362 if (len & 0x01)
363 dst[index] = musb_readb(fifo, 0);
364 } else {
365 /* byte aligned */
366 ioread8_rep(fifo, dst, len);
367 }
368 }
369
370 /*
371 * Old style IO functions
372 */
373 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374 EXPORT_SYMBOL_GPL(musb_readb);
375
376 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377 EXPORT_SYMBOL_GPL(musb_writeb);
378
379 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readw);
381
382 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383 EXPORT_SYMBOL_GPL(musb_writew);
384
385 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readl);
387
388 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389 EXPORT_SYMBOL_GPL(musb_writel);
390
391 /*
392 * New style IO functions
393 */
394 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
395 {
396 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
397 }
398
399 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
400 {
401 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
402 }
403
404 /*-------------------------------------------------------------------------*/
405
406 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
407 static const u8 musb_test_packet[53] = {
408 /* implicit SYNC then DATA0 to start */
409
410 /* JKJKJKJK x9 */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
412 /* JJKKJJKK x8 */
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
414 /* JJJJKKKK x8 */
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
418 /* JJJJJJJK x8 */
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
422
423 /* implicit CRC16 then EOP to end */
424 };
425
426 void musb_load_testpacket(struct musb *musb)
427 {
428 void __iomem *regs = musb->endpoints[0].regs;
429
430 musb_ep_select(musb->mregs, 0);
431 musb_write_fifo(musb->control_ep,
432 sizeof(musb_test_packet), musb_test_packet);
433 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
434 }
435
436 /*-------------------------------------------------------------------------*/
437
438 /*
439 * Handles OTG hnp timeouts, such as b_ase0_brst
440 */
441 static void musb_otg_timer_func(unsigned long data)
442 {
443 struct musb *musb = (struct musb *)data;
444 unsigned long flags;
445
446 spin_lock_irqsave(&musb->lock, flags);
447 switch (musb->xceiv->otg->state) {
448 case OTG_STATE_B_WAIT_ACON:
449 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
450 musb_g_disconnect(musb);
451 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
452 musb->is_active = 0;
453 break;
454 case OTG_STATE_A_SUSPEND:
455 case OTG_STATE_A_WAIT_BCON:
456 dev_dbg(musb->controller, "HNP: %s timeout\n",
457 usb_otg_state_string(musb->xceiv->otg->state));
458 musb_platform_set_vbus(musb, 0);
459 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
460 break;
461 default:
462 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
463 usb_otg_state_string(musb->xceiv->otg->state));
464 }
465 spin_unlock_irqrestore(&musb->lock, flags);
466 }
467
468 /*
469 * Stops the HNP transition. Caller must take care of locking.
470 */
471 void musb_hnp_stop(struct musb *musb)
472 {
473 struct usb_hcd *hcd = musb->hcd;
474 void __iomem *mbase = musb->mregs;
475 u8 reg;
476
477 dev_dbg(musb->controller, "HNP: stop from %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479
480 switch (musb->xceiv->otg->state) {
481 case OTG_STATE_A_PERIPHERAL:
482 musb_g_disconnect(musb);
483 dev_dbg(musb->controller, "HNP: back to %s\n",
484 usb_otg_state_string(musb->xceiv->otg->state));
485 break;
486 case OTG_STATE_B_HOST:
487 dev_dbg(musb->controller, "HNP: Disabling HR\n");
488 if (hcd)
489 hcd->self.is_b_host = 0;
490 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
491 MUSB_DEV_MODE(musb);
492 reg = musb_readb(mbase, MUSB_POWER);
493 reg |= MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER, reg);
495 /* REVISIT: Start SESSION_REQUEST here? */
496 break;
497 default:
498 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 }
501
502 /*
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
505 * errors.
506 */
507 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
508 }
509
510 static void musb_disable_interrupts(struct musb *musb);
511 static void musb_generic_disable(struct musb *musb);
512
513 /*
514 * Interrupt Service Routine to record USB "global" interrupts.
515 * Since these do not happen often and signify things of
516 * paramount importance, it seems OK to check them individually;
517 * the order of the tests is specified in the manual
518 *
519 * @param musb instance pointer
520 * @param int_usb register contents
521 * @param devctl
522 * @param power
523 */
524
525 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
526 u8 devctl)
527 {
528 irqreturn_t handled = IRQ_NONE;
529
530 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
531 int_usb);
532
533 /* in host mode, the peripheral may issue remote wakeup.
534 * in peripheral mode, the host may resume the link.
535 * spurious RESUME irqs happen too, paired with SUSPEND.
536 */
537 if (int_usb & MUSB_INTR_RESUME) {
538 handled = IRQ_HANDLED;
539 dev_dbg(musb->controller, "RESUME (%s)\n",
540 usb_otg_state_string(musb->xceiv->otg->state));
541
542 if (devctl & MUSB_DEVCTL_HM) {
543 switch (musb->xceiv->otg->state) {
544 case OTG_STATE_A_SUSPEND:
545 /* remote wakeup? later, GetPortStatus
546 * will stop RESUME signaling
547 */
548
549 musb->port1_status |=
550 (USB_PORT_STAT_C_SUSPEND << 16)
551 | MUSB_PORT_STAT_RESUME;
552 musb->rh_timer = jiffies
553 + msecs_to_jiffies(20);
554 musb->need_finish_resume = 1;
555
556 musb->xceiv->otg->state = OTG_STATE_A_HOST;
557 musb->is_active = 1;
558 musb_host_resume_root_hub(musb);
559 break;
560 case OTG_STATE_B_WAIT_ACON:
561 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
562 musb->is_active = 1;
563 MUSB_DEV_MODE(musb);
564 break;
565 default:
566 WARNING("bogus %s RESUME (%s)\n",
567 "host",
568 usb_otg_state_string(musb->xceiv->otg->state));
569 }
570 } else {
571 switch (musb->xceiv->otg->state) {
572 case OTG_STATE_A_SUSPEND:
573 /* possibly DISCONNECT is upcoming */
574 musb->xceiv->otg->state = OTG_STATE_A_HOST;
575 musb_host_resume_root_hub(musb);
576 break;
577 case OTG_STATE_B_WAIT_ACON:
578 case OTG_STATE_B_PERIPHERAL:
579 /* disconnect while suspended? we may
580 * not get a disconnect irq...
581 */
582 if ((devctl & MUSB_DEVCTL_VBUS)
583 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
584 ) {
585 musb->int_usb |= MUSB_INTR_DISCONNECT;
586 musb->int_usb &= ~MUSB_INTR_SUSPEND;
587 break;
588 }
589 musb_g_resume(musb);
590 break;
591 case OTG_STATE_B_IDLE:
592 musb->int_usb &= ~MUSB_INTR_SUSPEND;
593 break;
594 default:
595 WARNING("bogus %s RESUME (%s)\n",
596 "peripheral",
597 usb_otg_state_string(musb->xceiv->otg->state));
598 }
599 }
600 }
601
602 /* see manual for the order of the tests */
603 if (int_usb & MUSB_INTR_SESSREQ) {
604 void __iomem *mbase = musb->mregs;
605
606 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
607 && (devctl & MUSB_DEVCTL_BDEVICE)) {
608 dev_dbg(musb->controller, "SessReq while on B state\n");
609 return IRQ_HANDLED;
610 }
611
612 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
613 usb_otg_state_string(musb->xceiv->otg->state));
614
615 /* IRQ arrives from ID pin sense or (later, if VBUS power
616 * is removed) SRP. responses are time critical:
617 * - turn on VBUS (with silicon-specific mechanism)
618 * - go through A_WAIT_VRISE
619 * - ... to A_WAIT_BCON.
620 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
621 */
622 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
623 musb->ep0_stage = MUSB_EP0_START;
624 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
625 MUSB_HST_MODE(musb);
626 musb_platform_set_vbus(musb, 1);
627
628 handled = IRQ_HANDLED;
629 }
630
631 if (int_usb & MUSB_INTR_VBUSERROR) {
632 int ignore = 0;
633
634 /* During connection as an A-Device, we may see a short
635 * current spikes causing voltage drop, because of cable
636 * and peripheral capacitance combined with vbus draw.
637 * (So: less common with truly self-powered devices, where
638 * vbus doesn't act like a power supply.)
639 *
640 * Such spikes are short; usually less than ~500 usec, max
641 * of ~2 msec. That is, they're not sustained overcurrent
642 * errors, though they're reported using VBUSERROR irqs.
643 *
644 * Workarounds: (a) hardware: use self powered devices.
645 * (b) software: ignore non-repeated VBUS errors.
646 *
647 * REVISIT: do delays from lots of DEBUG_KERNEL checks
648 * make trouble here, keeping VBUS < 4.4V ?
649 */
650 switch (musb->xceiv->otg->state) {
651 case OTG_STATE_A_HOST:
652 /* recovery is dicey once we've gotten past the
653 * initial stages of enumeration, but if VBUS
654 * stayed ok at the other end of the link, and
655 * another reset is due (at least for high speed,
656 * to redo the chirp etc), it might work OK...
657 */
658 case OTG_STATE_A_WAIT_BCON:
659 case OTG_STATE_A_WAIT_VRISE:
660 if (musb->vbuserr_retry) {
661 void __iomem *mbase = musb->mregs;
662
663 musb->vbuserr_retry--;
664 ignore = 1;
665 devctl |= MUSB_DEVCTL_SESSION;
666 musb_writeb(mbase, MUSB_DEVCTL, devctl);
667 } else {
668 musb->port1_status |=
669 USB_PORT_STAT_OVERCURRENT
670 | (USB_PORT_STAT_C_OVERCURRENT << 16);
671 }
672 break;
673 default:
674 break;
675 }
676
677 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
678 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
679 usb_otg_state_string(musb->xceiv->otg->state),
680 devctl,
681 ({ char *s;
682 switch (devctl & MUSB_DEVCTL_VBUS) {
683 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
684 s = "<SessEnd"; break;
685 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
686 s = "<AValid"; break;
687 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
688 s = "<VBusValid"; break;
689 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
690 default:
691 s = "VALID"; break;
692 } s; }),
693 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
694 musb->port1_status);
695
696 /* go through A_WAIT_VFALL then start a new session */
697 if (!ignore)
698 musb_platform_set_vbus(musb, 0);
699 handled = IRQ_HANDLED;
700 }
701
702 if (int_usb & MUSB_INTR_SUSPEND) {
703 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
704 usb_otg_state_string(musb->xceiv->otg->state), devctl);
705 handled = IRQ_HANDLED;
706
707 switch (musb->xceiv->otg->state) {
708 case OTG_STATE_A_PERIPHERAL:
709 /* We also come here if the cable is removed, since
710 * this silicon doesn't report ID-no-longer-grounded.
711 *
712 * We depend on T(a_wait_bcon) to shut us down, and
713 * hope users don't do anything dicey during this
714 * undesired detour through A_WAIT_BCON.
715 */
716 musb_hnp_stop(musb);
717 musb_host_resume_root_hub(musb);
718 musb_root_disconnect(musb);
719 musb_platform_try_idle(musb, jiffies
720 + msecs_to_jiffies(musb->a_wait_bcon
721 ? : OTG_TIME_A_WAIT_BCON));
722
723 break;
724 case OTG_STATE_B_IDLE:
725 if (!musb->is_active)
726 break;
727 case OTG_STATE_B_PERIPHERAL:
728 musb_g_suspend(musb);
729 musb->is_active = musb->g.b_hnp_enable;
730 if (musb->is_active) {
731 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
732 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
733 mod_timer(&musb->otg_timer, jiffies
734 + msecs_to_jiffies(
735 OTG_TIME_B_ASE0_BRST));
736 }
737 break;
738 case OTG_STATE_A_WAIT_BCON:
739 if (musb->a_wait_bcon != 0)
740 musb_platform_try_idle(musb, jiffies
741 + msecs_to_jiffies(musb->a_wait_bcon));
742 break;
743 case OTG_STATE_A_HOST:
744 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
745 musb->is_active = musb->hcd->self.b_hnp_enable;
746 break;
747 case OTG_STATE_B_HOST:
748 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
749 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
750 break;
751 default:
752 /* "should not happen" */
753 musb->is_active = 0;
754 break;
755 }
756 }
757
758 if (int_usb & MUSB_INTR_CONNECT) {
759 struct usb_hcd *hcd = musb->hcd;
760
761 handled = IRQ_HANDLED;
762 musb->is_active = 1;
763
764 musb->ep0_stage = MUSB_EP0_START;
765
766 musb->intrtxe = musb->epmask;
767 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
768 musb->intrrxe = musb->epmask & 0xfffe;
769 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
770 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
771 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
772 |USB_PORT_STAT_HIGH_SPEED
773 |USB_PORT_STAT_ENABLE
774 );
775 musb->port1_status |= USB_PORT_STAT_CONNECTION
776 |(USB_PORT_STAT_C_CONNECTION << 16);
777
778 /* high vs full speed is just a guess until after reset */
779 if (devctl & MUSB_DEVCTL_LSDEV)
780 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
781
782 /* indicate new connection to OTG machine */
783 switch (musb->xceiv->otg->state) {
784 case OTG_STATE_B_PERIPHERAL:
785 if (int_usb & MUSB_INTR_SUSPEND) {
786 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
787 int_usb &= ~MUSB_INTR_SUSPEND;
788 goto b_host;
789 } else
790 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
791 break;
792 case OTG_STATE_B_WAIT_ACON:
793 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
794 b_host:
795 musb->xceiv->otg->state = OTG_STATE_B_HOST;
796 if (musb->hcd)
797 musb->hcd->self.is_b_host = 1;
798 del_timer(&musb->otg_timer);
799 break;
800 default:
801 if ((devctl & MUSB_DEVCTL_VBUS)
802 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
803 musb->xceiv->otg->state = OTG_STATE_A_HOST;
804 if (hcd)
805 hcd->self.is_b_host = 0;
806 }
807 break;
808 }
809
810 musb_host_poke_root_hub(musb);
811
812 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
813 usb_otg_state_string(musb->xceiv->otg->state), devctl);
814 }
815
816 if (int_usb & MUSB_INTR_DISCONNECT) {
817 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
818 usb_otg_state_string(musb->xceiv->otg->state),
819 MUSB_MODE(musb), devctl);
820 handled = IRQ_HANDLED;
821
822 switch (musb->xceiv->otg->state) {
823 case OTG_STATE_A_HOST:
824 case OTG_STATE_A_SUSPEND:
825 musb_host_resume_root_hub(musb);
826 musb_root_disconnect(musb);
827 if (musb->a_wait_bcon != 0)
828 musb_platform_try_idle(musb, jiffies
829 + msecs_to_jiffies(musb->a_wait_bcon));
830 break;
831 case OTG_STATE_B_HOST:
832 /* REVISIT this behaves for "real disconnect"
833 * cases; make sure the other transitions from
834 * from B_HOST act right too. The B_HOST code
835 * in hnp_stop() is currently not used...
836 */
837 musb_root_disconnect(musb);
838 if (musb->hcd)
839 musb->hcd->self.is_b_host = 0;
840 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
841 MUSB_DEV_MODE(musb);
842 musb_g_disconnect(musb);
843 break;
844 case OTG_STATE_A_PERIPHERAL:
845 musb_hnp_stop(musb);
846 musb_root_disconnect(musb);
847 /* FALLTHROUGH */
848 case OTG_STATE_B_WAIT_ACON:
849 /* FALLTHROUGH */
850 case OTG_STATE_B_PERIPHERAL:
851 case OTG_STATE_B_IDLE:
852 musb_g_disconnect(musb);
853 break;
854 default:
855 WARNING("unhandled DISCONNECT transition (%s)\n",
856 usb_otg_state_string(musb->xceiv->otg->state));
857 break;
858 }
859 }
860
861 /* mentor saves a bit: bus reset and babble share the same irq.
862 * only host sees babble; only peripheral sees bus reset.
863 */
864 if (int_usb & MUSB_INTR_RESET) {
865 handled = IRQ_HANDLED;
866 if (devctl & MUSB_DEVCTL_HM) {
867 u8 power = musb_readl(musb->mregs, MUSB_POWER);
868
869 /*
870 * Looks like non-HS BABBLE can be ignored, but
871 * HS BABBLE is an error condition.
872 *
873 * For HS the solution is to avoid babble in the first
874 * place and fix what caused BABBLE.
875 *
876 * When HS BABBLE happens what we can depends on which
877 * platform MUSB is running, because some platforms
878 * implemented proprietary means for 'recovering' from
879 * Babble conditions. One such platform is AM335x. In
880 * most cases, however, the only thing we can do is drop
881 * the session.
882 */
883 if (power & MUSB_POWER_HSMODE) {
884 dev_err(musb->controller, "Babble\n");
885
886 if (is_host_active(musb)) {
887 musb_disable_interrupts(musb);
888 schedule_delayed_work(&musb->recover_work,
889 msecs_to_jiffies(100));
890 }
891 }
892 } else {
893 dev_dbg(musb->controller, "BUS RESET as %s\n",
894 usb_otg_state_string(musb->xceiv->otg->state));
895 switch (musb->xceiv->otg->state) {
896 case OTG_STATE_A_SUSPEND:
897 musb_g_reset(musb);
898 /* FALLTHROUGH */
899 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
900 /* never use invalid T(a_wait_bcon) */
901 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
902 usb_otg_state_string(musb->xceiv->otg->state),
903 TA_WAIT_BCON(musb));
904 mod_timer(&musb->otg_timer, jiffies
905 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
906 break;
907 case OTG_STATE_A_PERIPHERAL:
908 del_timer(&musb->otg_timer);
909 musb_g_reset(musb);
910 break;
911 case OTG_STATE_B_WAIT_ACON:
912 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
913 usb_otg_state_string(musb->xceiv->otg->state));
914 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
915 musb_g_reset(musb);
916 break;
917 case OTG_STATE_B_IDLE:
918 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
919 /* FALLTHROUGH */
920 case OTG_STATE_B_PERIPHERAL:
921 musb_g_reset(musb);
922 break;
923 default:
924 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
925 usb_otg_state_string(musb->xceiv->otg->state));
926 }
927 }
928 }
929
930 #if 0
931 /* REVISIT ... this would be for multiplexing periodic endpoints, or
932 * supporting transfer phasing to prevent exceeding ISO bandwidth
933 * limits of a given frame or microframe.
934 *
935 * It's not needed for peripheral side, which dedicates endpoints;
936 * though it _might_ use SOF irqs for other purposes.
937 *
938 * And it's not currently needed for host side, which also dedicates
939 * endpoints, relies on TX/RX interval registers, and isn't claimed
940 * to support ISO transfers yet.
941 */
942 if (int_usb & MUSB_INTR_SOF) {
943 void __iomem *mbase = musb->mregs;
944 struct musb_hw_ep *ep;
945 u8 epnum;
946 u16 frame;
947
948 dev_dbg(musb->controller, "START_OF_FRAME\n");
949 handled = IRQ_HANDLED;
950
951 /* start any periodic Tx transfers waiting for current frame */
952 frame = musb_readw(mbase, MUSB_FRAME);
953 ep = musb->endpoints;
954 for (epnum = 1; (epnum < musb->nr_endpoints)
955 && (musb->epmask >= (1 << epnum));
956 epnum++, ep++) {
957 /*
958 * FIXME handle framecounter wraps (12 bits)
959 * eliminate duplicated StartUrb logic
960 */
961 if (ep->dwWaitFrame >= frame) {
962 ep->dwWaitFrame = 0;
963 pr_debug("SOF --> periodic TX%s on %d\n",
964 ep->tx_channel ? " DMA" : "",
965 epnum);
966 if (!ep->tx_channel)
967 musb_h_tx_start(musb, epnum);
968 else
969 cppi_hostdma_start(musb, epnum);
970 }
971 } /* end of for loop */
972 }
973 #endif
974
975 schedule_work(&musb->irq_work);
976
977 return handled;
978 }
979
980 /*-------------------------------------------------------------------------*/
981
982 static void musb_disable_interrupts(struct musb *musb)
983 {
984 void __iomem *mbase = musb->mregs;
985 u16 temp;
986
987 /* disable interrupts */
988 musb_writeb(mbase, MUSB_INTRUSBE, 0);
989 musb->intrtxe = 0;
990 musb_writew(mbase, MUSB_INTRTXE, 0);
991 musb->intrrxe = 0;
992 musb_writew(mbase, MUSB_INTRRXE, 0);
993
994 /* flush pending interrupts */
995 temp = musb_readb(mbase, MUSB_INTRUSB);
996 temp = musb_readw(mbase, MUSB_INTRTX);
997 temp = musb_readw(mbase, MUSB_INTRRX);
998 }
999
1000 static void musb_enable_interrupts(struct musb *musb)
1001 {
1002 void __iomem *regs = musb->mregs;
1003
1004 /* Set INT enable registers, enable interrupts */
1005 musb->intrtxe = musb->epmask;
1006 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1007 musb->intrrxe = musb->epmask & 0xfffe;
1008 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1009 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1010
1011 }
1012
1013 static void musb_generic_disable(struct musb *musb)
1014 {
1015 void __iomem *mbase = musb->mregs;
1016
1017 musb_disable_interrupts(musb);
1018
1019 /* off */
1020 musb_writeb(mbase, MUSB_DEVCTL, 0);
1021 }
1022
1023 /*
1024 * Program the HDRC to start (enable interrupts, dma, etc.).
1025 */
1026 void musb_start(struct musb *musb)
1027 {
1028 void __iomem *regs = musb->mregs;
1029 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1030
1031 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1032
1033 musb_enable_interrupts(musb);
1034 musb_writeb(regs, MUSB_TESTMODE, 0);
1035
1036 /* put into basic highspeed mode and start session */
1037 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1038 | MUSB_POWER_HSENAB
1039 /* ENSUSPEND wedges tusb */
1040 /* | MUSB_POWER_ENSUSPEND */
1041 );
1042
1043 musb->is_active = 0;
1044 devctl = musb_readb(regs, MUSB_DEVCTL);
1045 devctl &= ~MUSB_DEVCTL_SESSION;
1046
1047 /* session started after:
1048 * (a) ID-grounded irq, host mode;
1049 * (b) vbus present/connect IRQ, peripheral mode;
1050 * (c) peripheral initiates, using SRP
1051 */
1052 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1053 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1054 musb->is_active = 1;
1055 } else {
1056 devctl |= MUSB_DEVCTL_SESSION;
1057 }
1058
1059 musb_platform_enable(musb);
1060 musb_writeb(regs, MUSB_DEVCTL, devctl);
1061 }
1062
1063 /*
1064 * Make the HDRC stop (disable interrupts, etc.);
1065 * reversible by musb_start
1066 * called on gadget driver unregister
1067 * with controller locked, irqs blocked
1068 * acts as a NOP unless some role activated the hardware
1069 */
1070 void musb_stop(struct musb *musb)
1071 {
1072 /* stop IRQs, timers, ... */
1073 musb_platform_disable(musb);
1074 musb_generic_disable(musb);
1075 dev_dbg(musb->controller, "HDRC disabled\n");
1076
1077 /* FIXME
1078 * - mark host and/or peripheral drivers unusable/inactive
1079 * - disable DMA (and enable it in HdrcStart)
1080 * - make sure we can musb_start() after musb_stop(); with
1081 * OTG mode, gadget driver module rmmod/modprobe cycles that
1082 * - ...
1083 */
1084 musb_platform_try_idle(musb, 0);
1085 }
1086
1087 static void musb_shutdown(struct platform_device *pdev)
1088 {
1089 struct musb *musb = dev_to_musb(&pdev->dev);
1090 unsigned long flags;
1091
1092 pm_runtime_get_sync(musb->controller);
1093
1094 musb_host_cleanup(musb);
1095 musb_gadget_cleanup(musb);
1096
1097 spin_lock_irqsave(&musb->lock, flags);
1098 musb_platform_disable(musb);
1099 musb_generic_disable(musb);
1100 spin_unlock_irqrestore(&musb->lock, flags);
1101
1102 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1103 musb_platform_exit(musb);
1104
1105 pm_runtime_put(musb->controller);
1106 /* FIXME power down */
1107 }
1108
1109
1110 /*-------------------------------------------------------------------------*/
1111
1112 /*
1113 * The silicon either has hard-wired endpoint configurations, or else
1114 * "dynamic fifo" sizing. The driver has support for both, though at this
1115 * writing only the dynamic sizing is very well tested. Since we switched
1116 * away from compile-time hardware parameters, we can no longer rely on
1117 * dead code elimination to leave only the relevant one in the object file.
1118 *
1119 * We don't currently use dynamic fifo setup capability to do anything
1120 * more than selecting one of a bunch of predefined configurations.
1121 */
1122 static ushort fifo_mode;
1123
1124 /* "modprobe ... fifo_mode=1" etc */
1125 module_param(fifo_mode, ushort, 0);
1126 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1127
1128 /*
1129 * tables defining fifo_mode values. define more if you like.
1130 * for host side, make sure both halves of ep1 are set up.
1131 */
1132
1133 /* mode 0 - fits in 2KB */
1134 static struct musb_fifo_cfg mode_0_cfg[] = {
1135 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1136 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1137 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1138 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1139 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1140 };
1141
1142 /* mode 1 - fits in 4KB */
1143 static struct musb_fifo_cfg mode_1_cfg[] = {
1144 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1145 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1146 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1147 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1148 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1149 };
1150
1151 /* mode 2 - fits in 4KB */
1152 static struct musb_fifo_cfg mode_2_cfg[] = {
1153 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1154 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1155 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1156 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1157 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1158 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1159 };
1160
1161 /* mode 3 - fits in 4KB */
1162 static struct musb_fifo_cfg mode_3_cfg[] = {
1163 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1164 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1165 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1166 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1167 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1168 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1169 };
1170
1171 /* mode 4 - fits in 16KB */
1172 static struct musb_fifo_cfg mode_4_cfg[] = {
1173 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1174 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1175 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1176 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1177 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1178 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1179 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1180 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1181 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1182 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1183 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1184 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1185 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1186 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1187 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1188 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1189 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1190 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1191 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1192 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1193 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1194 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1195 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1196 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1197 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1198 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1199 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1200 };
1201
1202 /* mode 5 - fits in 8KB */
1203 static struct musb_fifo_cfg mode_5_cfg[] = {
1204 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1205 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1206 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1207 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1208 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1209 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1210 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1211 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1212 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1213 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1214 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1215 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1216 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1217 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1218 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1219 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1220 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1221 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1222 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1223 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1224 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1225 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1226 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1227 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1228 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1229 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1230 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1231 };
1232
1233 /*
1234 * configure a fifo; for non-shared endpoints, this may be called
1235 * once for a tx fifo and once for an rx fifo.
1236 *
1237 * returns negative errno or offset for next fifo.
1238 */
1239 static int
1240 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1241 const struct musb_fifo_cfg *cfg, u16 offset)
1242 {
1243 void __iomem *mbase = musb->mregs;
1244 int size = 0;
1245 u16 maxpacket = cfg->maxpacket;
1246 u16 c_off = offset >> 3;
1247 u8 c_size;
1248
1249 /* expect hw_ep has already been zero-initialized */
1250
1251 size = ffs(max(maxpacket, (u16) 8)) - 1;
1252 maxpacket = 1 << size;
1253
1254 c_size = size - 3;
1255 if (cfg->mode == BUF_DOUBLE) {
1256 if ((offset + (maxpacket << 1)) >
1257 (1 << (musb->config->ram_bits + 2)))
1258 return -EMSGSIZE;
1259 c_size |= MUSB_FIFOSZ_DPB;
1260 } else {
1261 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1262 return -EMSGSIZE;
1263 }
1264
1265 /* configure the FIFO */
1266 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1267
1268 /* EP0 reserved endpoint for control, bidirectional;
1269 * EP1 reserved for bulk, two unidirectional halves.
1270 */
1271 if (hw_ep->epnum == 1)
1272 musb->bulk_ep = hw_ep;
1273 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1274 switch (cfg->style) {
1275 case FIFO_TX:
1276 musb_write_txfifosz(mbase, c_size);
1277 musb_write_txfifoadd(mbase, c_off);
1278 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1279 hw_ep->max_packet_sz_tx = maxpacket;
1280 break;
1281 case FIFO_RX:
1282 musb_write_rxfifosz(mbase, c_size);
1283 musb_write_rxfifoadd(mbase, c_off);
1284 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1285 hw_ep->max_packet_sz_rx = maxpacket;
1286 break;
1287 case FIFO_RXTX:
1288 musb_write_txfifosz(mbase, c_size);
1289 musb_write_txfifoadd(mbase, c_off);
1290 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291 hw_ep->max_packet_sz_rx = maxpacket;
1292
1293 musb_write_rxfifosz(mbase, c_size);
1294 musb_write_rxfifoadd(mbase, c_off);
1295 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1296 hw_ep->max_packet_sz_tx = maxpacket;
1297
1298 hw_ep->is_shared_fifo = true;
1299 break;
1300 }
1301
1302 /* NOTE rx and tx endpoint irqs aren't managed separately,
1303 * which happens to be ok
1304 */
1305 musb->epmask |= (1 << hw_ep->epnum);
1306
1307 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1308 }
1309
1310 static struct musb_fifo_cfg ep0_cfg = {
1311 .style = FIFO_RXTX, .maxpacket = 64,
1312 };
1313
1314 static int ep_config_from_table(struct musb *musb)
1315 {
1316 const struct musb_fifo_cfg *cfg;
1317 unsigned i, n;
1318 int offset;
1319 struct musb_hw_ep *hw_ep = musb->endpoints;
1320
1321 if (musb->config->fifo_cfg) {
1322 cfg = musb->config->fifo_cfg;
1323 n = musb->config->fifo_cfg_size;
1324 goto done;
1325 }
1326
1327 switch (fifo_mode) {
1328 default:
1329 fifo_mode = 0;
1330 /* FALLTHROUGH */
1331 case 0:
1332 cfg = mode_0_cfg;
1333 n = ARRAY_SIZE(mode_0_cfg);
1334 break;
1335 case 1:
1336 cfg = mode_1_cfg;
1337 n = ARRAY_SIZE(mode_1_cfg);
1338 break;
1339 case 2:
1340 cfg = mode_2_cfg;
1341 n = ARRAY_SIZE(mode_2_cfg);
1342 break;
1343 case 3:
1344 cfg = mode_3_cfg;
1345 n = ARRAY_SIZE(mode_3_cfg);
1346 break;
1347 case 4:
1348 cfg = mode_4_cfg;
1349 n = ARRAY_SIZE(mode_4_cfg);
1350 break;
1351 case 5:
1352 cfg = mode_5_cfg;
1353 n = ARRAY_SIZE(mode_5_cfg);
1354 break;
1355 }
1356
1357 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1358 musb_driver_name, fifo_mode);
1359
1360
1361 done:
1362 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1363 /* assert(offset > 0) */
1364
1365 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1366 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1367 */
1368
1369 for (i = 0; i < n; i++) {
1370 u8 epn = cfg->hw_ep_num;
1371
1372 if (epn >= musb->config->num_eps) {
1373 pr_debug("%s: invalid ep %d\n",
1374 musb_driver_name, epn);
1375 return -EINVAL;
1376 }
1377 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1378 if (offset < 0) {
1379 pr_debug("%s: mem overrun, ep %d\n",
1380 musb_driver_name, epn);
1381 return offset;
1382 }
1383 epn++;
1384 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1385 }
1386
1387 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1388 musb_driver_name,
1389 n + 1, musb->config->num_eps * 2 - 1,
1390 offset, (1 << (musb->config->ram_bits + 2)));
1391
1392 if (!musb->bulk_ep) {
1393 pr_debug("%s: missing bulk\n", musb_driver_name);
1394 return -EINVAL;
1395 }
1396
1397 return 0;
1398 }
1399
1400
1401 /*
1402 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1403 * @param musb the controller
1404 */
1405 static int ep_config_from_hw(struct musb *musb)
1406 {
1407 u8 epnum = 0;
1408 struct musb_hw_ep *hw_ep;
1409 void __iomem *mbase = musb->mregs;
1410 int ret = 0;
1411
1412 dev_dbg(musb->controller, "<== static silicon ep config\n");
1413
1414 /* FIXME pick up ep0 maxpacket size */
1415
1416 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1417 musb_ep_select(mbase, epnum);
1418 hw_ep = musb->endpoints + epnum;
1419
1420 ret = musb_read_fifosize(musb, hw_ep, epnum);
1421 if (ret < 0)
1422 break;
1423
1424 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1425
1426 /* pick an RX/TX endpoint for bulk */
1427 if (hw_ep->max_packet_sz_tx < 512
1428 || hw_ep->max_packet_sz_rx < 512)
1429 continue;
1430
1431 /* REVISIT: this algorithm is lazy, we should at least
1432 * try to pick a double buffered endpoint.
1433 */
1434 if (musb->bulk_ep)
1435 continue;
1436 musb->bulk_ep = hw_ep;
1437 }
1438
1439 if (!musb->bulk_ep) {
1440 pr_debug("%s: missing bulk\n", musb_driver_name);
1441 return -EINVAL;
1442 }
1443
1444 return 0;
1445 }
1446
1447 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1448
1449 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1450 * configure endpoints, or take their config from silicon
1451 */
1452 static int musb_core_init(u16 musb_type, struct musb *musb)
1453 {
1454 u8 reg;
1455 char *type;
1456 char aInfo[90], aRevision[32], aDate[12];
1457 void __iomem *mbase = musb->mregs;
1458 int status = 0;
1459 int i;
1460
1461 /* log core options (read using indexed model) */
1462 reg = musb_read_configdata(mbase);
1463
1464 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1465 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1466 strcat(aInfo, ", dyn FIFOs");
1467 musb->dyn_fifo = true;
1468 }
1469 if (reg & MUSB_CONFIGDATA_MPRXE) {
1470 strcat(aInfo, ", bulk combine");
1471 musb->bulk_combine = true;
1472 }
1473 if (reg & MUSB_CONFIGDATA_MPTXE) {
1474 strcat(aInfo, ", bulk split");
1475 musb->bulk_split = true;
1476 }
1477 if (reg & MUSB_CONFIGDATA_HBRXE) {
1478 strcat(aInfo, ", HB-ISO Rx");
1479 musb->hb_iso_rx = true;
1480 }
1481 if (reg & MUSB_CONFIGDATA_HBTXE) {
1482 strcat(aInfo, ", HB-ISO Tx");
1483 musb->hb_iso_tx = true;
1484 }
1485 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1486 strcat(aInfo, ", SoftConn");
1487
1488 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1489 musb_driver_name, reg, aInfo);
1490
1491 aDate[0] = 0;
1492 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1493 musb->is_multipoint = 1;
1494 type = "M";
1495 } else {
1496 musb->is_multipoint = 0;
1497 type = "";
1498 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1499 printk(KERN_ERR
1500 "%s: kernel must blacklist external hubs\n",
1501 musb_driver_name);
1502 #endif
1503 }
1504
1505 /* log release info */
1506 musb->hwvers = musb_read_hwvers(mbase);
1507 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1508 MUSB_HWVERS_MINOR(musb->hwvers),
1509 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1510 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1511 musb_driver_name, type, aRevision, aDate);
1512
1513 /* configure ep0 */
1514 musb_configure_ep0(musb);
1515
1516 /* discover endpoint configuration */
1517 musb->nr_endpoints = 1;
1518 musb->epmask = 1;
1519
1520 if (musb->dyn_fifo)
1521 status = ep_config_from_table(musb);
1522 else
1523 status = ep_config_from_hw(musb);
1524
1525 if (status < 0)
1526 return status;
1527
1528 /* finish init, and print endpoint config */
1529 for (i = 0; i < musb->nr_endpoints; i++) {
1530 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1531
1532 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1533 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1534 if (musb->io.quirks & MUSB_IN_TUSB) {
1535 hw_ep->fifo_async = musb->async + 0x400 +
1536 musb->io.fifo_offset(i);
1537 hw_ep->fifo_sync = musb->sync + 0x400 +
1538 musb->io.fifo_offset(i);
1539 hw_ep->fifo_sync_va =
1540 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1541
1542 if (i == 0)
1543 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1544 else
1545 hw_ep->conf = mbase + 0x400 +
1546 (((i - 1) & 0xf) << 2);
1547 }
1548 #endif
1549
1550 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1551 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1552 hw_ep->rx_reinit = 1;
1553 hw_ep->tx_reinit = 1;
1554
1555 if (hw_ep->max_packet_sz_tx) {
1556 dev_dbg(musb->controller,
1557 "%s: hw_ep %d%s, %smax %d\n",
1558 musb_driver_name, i,
1559 hw_ep->is_shared_fifo ? "shared" : "tx",
1560 hw_ep->tx_double_buffered
1561 ? "doublebuffer, " : "",
1562 hw_ep->max_packet_sz_tx);
1563 }
1564 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1565 dev_dbg(musb->controller,
1566 "%s: hw_ep %d%s, %smax %d\n",
1567 musb_driver_name, i,
1568 "rx",
1569 hw_ep->rx_double_buffered
1570 ? "doublebuffer, " : "",
1571 hw_ep->max_packet_sz_rx);
1572 }
1573 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1574 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1575 }
1576
1577 return 0;
1578 }
1579
1580 /*-------------------------------------------------------------------------*/
1581
1582 /*
1583 * handle all the irqs defined by the HDRC core. for now we expect: other
1584 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1585 * will be assigned, and the irq will already have been acked.
1586 *
1587 * called in irq context with spinlock held, irqs blocked
1588 */
1589 irqreturn_t musb_interrupt(struct musb *musb)
1590 {
1591 irqreturn_t retval = IRQ_NONE;
1592 unsigned long status;
1593 unsigned long epnum;
1594 u8 devctl;
1595
1596 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1597 return IRQ_NONE;
1598
1599 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1600
1601 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1602 is_host_active(musb) ? "host" : "peripheral",
1603 musb->int_usb, musb->int_tx, musb->int_rx);
1604
1605 /**
1606 * According to Mentor Graphics' documentation, flowchart on page 98,
1607 * IRQ should be handled as follows:
1608 *
1609 * . Resume IRQ
1610 * . Session Request IRQ
1611 * . VBUS Error IRQ
1612 * . Suspend IRQ
1613 * . Connect IRQ
1614 * . Disconnect IRQ
1615 * . Reset/Babble IRQ
1616 * . SOF IRQ (we're not using this one)
1617 * . Endpoint 0 IRQ
1618 * . TX Endpoints
1619 * . RX Endpoints
1620 *
1621 * We will be following that flowchart in order to avoid any problems
1622 * that might arise with internal Finite State Machine.
1623 */
1624
1625 if (musb->int_usb)
1626 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1627
1628 if (musb->int_tx & 1) {
1629 if (is_host_active(musb))
1630 retval |= musb_h_ep0_irq(musb);
1631 else
1632 retval |= musb_g_ep0_irq(musb);
1633
1634 /* we have just handled endpoint 0 IRQ, clear it */
1635 musb->int_tx &= ~BIT(0);
1636 }
1637
1638 status = musb->int_tx;
1639
1640 for_each_set_bit(epnum, &status, 16) {
1641 retval = IRQ_HANDLED;
1642 if (is_host_active(musb))
1643 musb_host_tx(musb, epnum);
1644 else
1645 musb_g_tx(musb, epnum);
1646 }
1647
1648 status = musb->int_rx;
1649
1650 for_each_set_bit(epnum, &status, 16) {
1651 retval = IRQ_HANDLED;
1652 if (is_host_active(musb))
1653 musb_host_rx(musb, epnum);
1654 else
1655 musb_g_rx(musb, epnum);
1656 }
1657
1658 return retval;
1659 }
1660 EXPORT_SYMBOL_GPL(musb_interrupt);
1661
1662 #ifndef CONFIG_MUSB_PIO_ONLY
1663 static bool use_dma = 1;
1664
1665 /* "modprobe ... use_dma=0" etc */
1666 module_param(use_dma, bool, 0);
1667 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1668
1669 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1670 {
1671 /* called with controller lock already held */
1672
1673 if (!epnum) {
1674 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1675 if (!is_cppi_enabled()) {
1676 /* endpoint 0 */
1677 if (is_host_active(musb))
1678 musb_h_ep0_irq(musb);
1679 else
1680 musb_g_ep0_irq(musb);
1681 }
1682 #endif
1683 } else {
1684 /* endpoints 1..15 */
1685 if (transmit) {
1686 if (is_host_active(musb))
1687 musb_host_tx(musb, epnum);
1688 else
1689 musb_g_tx(musb, epnum);
1690 } else {
1691 /* receive */
1692 if (is_host_active(musb))
1693 musb_host_rx(musb, epnum);
1694 else
1695 musb_g_rx(musb, epnum);
1696 }
1697 }
1698 }
1699 EXPORT_SYMBOL_GPL(musb_dma_completion);
1700
1701 #else
1702 #define use_dma 0
1703 #endif
1704
1705 /*-------------------------------------------------------------------------*/
1706
1707 static ssize_t
1708 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1709 {
1710 struct musb *musb = dev_to_musb(dev);
1711 unsigned long flags;
1712 int ret = -EINVAL;
1713
1714 spin_lock_irqsave(&musb->lock, flags);
1715 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1716 spin_unlock_irqrestore(&musb->lock, flags);
1717
1718 return ret;
1719 }
1720
1721 static ssize_t
1722 musb_mode_store(struct device *dev, struct device_attribute *attr,
1723 const char *buf, size_t n)
1724 {
1725 struct musb *musb = dev_to_musb(dev);
1726 unsigned long flags;
1727 int status;
1728
1729 spin_lock_irqsave(&musb->lock, flags);
1730 if (sysfs_streq(buf, "host"))
1731 status = musb_platform_set_mode(musb, MUSB_HOST);
1732 else if (sysfs_streq(buf, "peripheral"))
1733 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1734 else if (sysfs_streq(buf, "otg"))
1735 status = musb_platform_set_mode(musb, MUSB_OTG);
1736 else
1737 status = -EINVAL;
1738 spin_unlock_irqrestore(&musb->lock, flags);
1739
1740 return (status == 0) ? n : status;
1741 }
1742 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1743
1744 static ssize_t
1745 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1746 const char *buf, size_t n)
1747 {
1748 struct musb *musb = dev_to_musb(dev);
1749 unsigned long flags;
1750 unsigned long val;
1751
1752 if (sscanf(buf, "%lu", &val) < 1) {
1753 dev_err(dev, "Invalid VBUS timeout ms value\n");
1754 return -EINVAL;
1755 }
1756
1757 spin_lock_irqsave(&musb->lock, flags);
1758 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1759 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1760 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1761 musb->is_active = 0;
1762 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1763 spin_unlock_irqrestore(&musb->lock, flags);
1764
1765 return n;
1766 }
1767
1768 static ssize_t
1769 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1770 {
1771 struct musb *musb = dev_to_musb(dev);
1772 unsigned long flags;
1773 unsigned long val;
1774 int vbus;
1775
1776 spin_lock_irqsave(&musb->lock, flags);
1777 val = musb->a_wait_bcon;
1778 /* FIXME get_vbus_status() is normally #defined as false...
1779 * and is effectively TUSB-specific.
1780 */
1781 vbus = musb_platform_get_vbus_status(musb);
1782 spin_unlock_irqrestore(&musb->lock, flags);
1783
1784 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1785 vbus ? "on" : "off", val);
1786 }
1787 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1788
1789 /* Gadget drivers can't know that a host is connected so they might want
1790 * to start SRP, but users can. This allows userspace to trigger SRP.
1791 */
1792 static ssize_t
1793 musb_srp_store(struct device *dev, struct device_attribute *attr,
1794 const char *buf, size_t n)
1795 {
1796 struct musb *musb = dev_to_musb(dev);
1797 unsigned short srp;
1798
1799 if (sscanf(buf, "%hu", &srp) != 1
1800 || (srp != 1)) {
1801 dev_err(dev, "SRP: Value must be 1\n");
1802 return -EINVAL;
1803 }
1804
1805 if (srp == 1)
1806 musb_g_wakeup(musb);
1807
1808 return n;
1809 }
1810 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1811
1812 static struct attribute *musb_attributes[] = {
1813 &dev_attr_mode.attr,
1814 &dev_attr_vbus.attr,
1815 &dev_attr_srp.attr,
1816 NULL
1817 };
1818
1819 static const struct attribute_group musb_attr_group = {
1820 .attrs = musb_attributes,
1821 };
1822
1823 /* Only used to provide driver mode change events */
1824 static void musb_irq_work(struct work_struct *data)
1825 {
1826 struct musb *musb = container_of(data, struct musb, irq_work);
1827
1828 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1829 musb->xceiv_old_state = musb->xceiv->otg->state;
1830 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1831 }
1832 }
1833
1834 /* Recover from babble interrupt conditions */
1835 static void musb_recover_work(struct work_struct *data)
1836 {
1837 struct musb *musb = container_of(data, struct musb, recover_work.work);
1838 int status, ret;
1839
1840 ret = musb_platform_reset(musb);
1841 if (ret) {
1842 musb_enable_interrupts(musb);
1843 return;
1844 }
1845
1846 usb_phy_vbus_off(musb->xceiv);
1847 usleep_range(100, 200);
1848
1849 usb_phy_vbus_on(musb->xceiv);
1850 usleep_range(100, 200);
1851
1852 /*
1853 * When a babble condition occurs, the musb controller
1854 * removes the session bit and the endpoint config is lost.
1855 */
1856 if (musb->dyn_fifo)
1857 status = ep_config_from_table(musb);
1858 else
1859 status = ep_config_from_hw(musb);
1860
1861 /* start the session again */
1862 if (status == 0)
1863 musb_start(musb);
1864 }
1865
1866 /* --------------------------------------------------------------------------
1867 * Init support
1868 */
1869
1870 static struct musb *allocate_instance(struct device *dev,
1871 struct musb_hdrc_config *config, void __iomem *mbase)
1872 {
1873 struct musb *musb;
1874 struct musb_hw_ep *ep;
1875 int epnum;
1876 int ret;
1877
1878 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1879 if (!musb)
1880 return NULL;
1881
1882 INIT_LIST_HEAD(&musb->control);
1883 INIT_LIST_HEAD(&musb->in_bulk);
1884 INIT_LIST_HEAD(&musb->out_bulk);
1885
1886 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1887 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1888 musb->mregs = mbase;
1889 musb->ctrl_base = mbase;
1890 musb->nIrq = -ENODEV;
1891 musb->config = config;
1892 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1893 for (epnum = 0, ep = musb->endpoints;
1894 epnum < musb->config->num_eps;
1895 epnum++, ep++) {
1896 ep->musb = musb;
1897 ep->epnum = epnum;
1898 }
1899
1900 musb->controller = dev;
1901
1902 ret = musb_host_alloc(musb);
1903 if (ret < 0)
1904 goto err_free;
1905
1906 dev_set_drvdata(dev, musb);
1907
1908 return musb;
1909
1910 err_free:
1911 return NULL;
1912 }
1913
1914 static void musb_free(struct musb *musb)
1915 {
1916 /* this has multiple entry modes. it handles fault cleanup after
1917 * probe(), where things may be partially set up, as well as rmmod
1918 * cleanup after everything's been de-activated.
1919 */
1920
1921 #ifdef CONFIG_SYSFS
1922 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1923 #endif
1924
1925 if (musb->nIrq >= 0) {
1926 if (musb->irq_wake)
1927 disable_irq_wake(musb->nIrq);
1928 free_irq(musb->nIrq, musb);
1929 }
1930
1931 musb_host_free(musb);
1932 }
1933
1934 static void musb_deassert_reset(struct work_struct *work)
1935 {
1936 struct musb *musb;
1937 unsigned long flags;
1938
1939 musb = container_of(work, struct musb, deassert_reset_work.work);
1940
1941 spin_lock_irqsave(&musb->lock, flags);
1942
1943 if (musb->port1_status & USB_PORT_STAT_RESET)
1944 musb_port_reset(musb, false);
1945
1946 spin_unlock_irqrestore(&musb->lock, flags);
1947 }
1948
1949 /*
1950 * Perform generic per-controller initialization.
1951 *
1952 * @dev: the controller (already clocked, etc)
1953 * @nIrq: IRQ number
1954 * @ctrl: virtual address of controller registers,
1955 * not yet corrected for platform-specific offsets
1956 */
1957 static int
1958 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1959 {
1960 int status;
1961 struct musb *musb;
1962 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1963
1964 /* The driver might handle more features than the board; OK.
1965 * Fail when the board needs a feature that's not enabled.
1966 */
1967 if (!plat) {
1968 dev_dbg(dev, "no platform_data?\n");
1969 status = -ENODEV;
1970 goto fail0;
1971 }
1972
1973 /* allocate */
1974 musb = allocate_instance(dev, plat->config, ctrl);
1975 if (!musb) {
1976 status = -ENOMEM;
1977 goto fail0;
1978 }
1979
1980 spin_lock_init(&musb->lock);
1981 musb->board_set_power = plat->set_power;
1982 musb->min_power = plat->min_power;
1983 musb->ops = plat->platform_ops;
1984 musb->port_mode = plat->mode;
1985
1986 /*
1987 * Initialize the default IO functions. At least omap2430 needs
1988 * these early. We initialize the platform specific IO functions
1989 * later on.
1990 */
1991 musb_readb = musb_default_readb;
1992 musb_writeb = musb_default_writeb;
1993 musb_readw = musb_default_readw;
1994 musb_writew = musb_default_writew;
1995 musb_readl = musb_default_readl;
1996 musb_writel = musb_default_writel;
1997
1998 /* We need musb_read/write functions initialized for PM */
1999 pm_runtime_use_autosuspend(musb->controller);
2000 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2001 pm_runtime_irq_safe(musb->controller);
2002 pm_runtime_enable(musb->controller);
2003
2004 /* The musb_platform_init() call:
2005 * - adjusts musb->mregs
2006 * - sets the musb->isr
2007 * - may initialize an integrated transceiver
2008 * - initializes musb->xceiv, usually by otg_get_phy()
2009 * - stops powering VBUS
2010 *
2011 * There are various transceiver configurations. Blackfin,
2012 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2013 * external/discrete ones in various flavors (twl4030 family,
2014 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2015 */
2016 status = musb_platform_init(musb);
2017 if (status < 0)
2018 goto fail1;
2019
2020 if (!musb->isr) {
2021 status = -ENODEV;
2022 goto fail2;
2023 }
2024
2025 if (musb->ops->quirks)
2026 musb->io.quirks = musb->ops->quirks;
2027
2028 /* At least tusb6010 has it's own offsets.. */
2029 if (musb->ops->ep_offset)
2030 musb->io.ep_offset = musb->ops->ep_offset;
2031 if (musb->ops->ep_select)
2032 musb->io.ep_select = musb->ops->ep_select;
2033
2034 /* ..and some devices use indexed offset or flat offset */
2035 if (musb->io.quirks & MUSB_INDEXED_EP) {
2036 musb->io.ep_offset = musb_indexed_ep_offset;
2037 musb->io.ep_select = musb_indexed_ep_select;
2038 } else {
2039 musb->io.ep_offset = musb_flat_ep_offset;
2040 musb->io.ep_select = musb_flat_ep_select;
2041 }
2042
2043 if (musb->ops->fifo_mode)
2044 fifo_mode = musb->ops->fifo_mode;
2045 else
2046 fifo_mode = 4;
2047
2048 if (musb->ops->fifo_offset)
2049 musb->io.fifo_offset = musb->ops->fifo_offset;
2050 else
2051 musb->io.fifo_offset = musb_default_fifo_offset;
2052
2053 if (musb->ops->readb)
2054 musb_readb = musb->ops->readb;
2055 if (musb->ops->writeb)
2056 musb_writeb = musb->ops->writeb;
2057 if (musb->ops->readw)
2058 musb_readw = musb->ops->readw;
2059 if (musb->ops->writew)
2060 musb_writew = musb->ops->writew;
2061 if (musb->ops->readl)
2062 musb_readl = musb->ops->readl;
2063 if (musb->ops->writel)
2064 musb_writel = musb->ops->writel;
2065
2066 if (musb->ops->read_fifo)
2067 musb->io.read_fifo = musb->ops->read_fifo;
2068 else
2069 musb->io.read_fifo = musb_default_read_fifo;
2070
2071 if (musb->ops->write_fifo)
2072 musb->io.write_fifo = musb->ops->write_fifo;
2073 else
2074 musb->io.write_fifo = musb_default_write_fifo;
2075
2076 if (!musb->xceiv->io_ops) {
2077 musb->xceiv->io_dev = musb->controller;
2078 musb->xceiv->io_priv = musb->mregs;
2079 musb->xceiv->io_ops = &musb_ulpi_access;
2080 }
2081
2082 pm_runtime_get_sync(musb->controller);
2083
2084 if (use_dma && dev->dma_mask) {
2085 musb->dma_controller = dma_controller_create(musb, musb->mregs);
2086 if (IS_ERR(musb->dma_controller)) {
2087 status = PTR_ERR(musb->dma_controller);
2088 goto fail2_5;
2089 }
2090 }
2091
2092 /* be sure interrupts are disabled before connecting ISR */
2093 musb_platform_disable(musb);
2094 musb_generic_disable(musb);
2095
2096 /* Init IRQ workqueue before request_irq */
2097 INIT_WORK(&musb->irq_work, musb_irq_work);
2098 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
2099 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2100 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2101
2102 /* setup musb parts of the core (especially endpoints) */
2103 status = musb_core_init(plat->config->multipoint
2104 ? MUSB_CONTROLLER_MHDRC
2105 : MUSB_CONTROLLER_HDRC, musb);
2106 if (status < 0)
2107 goto fail3;
2108
2109 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2110
2111 /* attach to the IRQ */
2112 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2113 dev_err(dev, "request_irq %d failed!\n", nIrq);
2114 status = -ENODEV;
2115 goto fail3;
2116 }
2117 musb->nIrq = nIrq;
2118 /* FIXME this handles wakeup irqs wrong */
2119 if (enable_irq_wake(nIrq) == 0) {
2120 musb->irq_wake = 1;
2121 device_init_wakeup(dev, 1);
2122 } else {
2123 musb->irq_wake = 0;
2124 }
2125
2126 /* program PHY to use external vBus if required */
2127 if (plat->extvbus) {
2128 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2129 busctl |= MUSB_ULPI_USE_EXTVBUS;
2130 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2131 }
2132
2133 if (musb->xceiv->otg->default_a) {
2134 MUSB_HST_MODE(musb);
2135 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2136 } else {
2137 MUSB_DEV_MODE(musb);
2138 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2139 }
2140
2141 switch (musb->port_mode) {
2142 case MUSB_PORT_MODE_HOST:
2143 status = musb_host_setup(musb, plat->power);
2144 if (status < 0)
2145 goto fail3;
2146 status = musb_platform_set_mode(musb, MUSB_HOST);
2147 break;
2148 case MUSB_PORT_MODE_GADGET:
2149 status = musb_gadget_setup(musb);
2150 if (status < 0)
2151 goto fail3;
2152 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2153 break;
2154 case MUSB_PORT_MODE_DUAL_ROLE:
2155 status = musb_host_setup(musb, plat->power);
2156 if (status < 0)
2157 goto fail3;
2158 status = musb_gadget_setup(musb);
2159 if (status) {
2160 musb_host_cleanup(musb);
2161 goto fail3;
2162 }
2163 status = musb_platform_set_mode(musb, MUSB_OTG);
2164 break;
2165 default:
2166 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2167 break;
2168 }
2169
2170 if (status < 0)
2171 goto fail3;
2172
2173 status = musb_init_debugfs(musb);
2174 if (status < 0)
2175 goto fail4;
2176
2177 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2178 if (status)
2179 goto fail5;
2180
2181 pm_runtime_put(musb->controller);
2182
2183 return 0;
2184
2185 fail5:
2186 musb_exit_debugfs(musb);
2187
2188 fail4:
2189 musb_gadget_cleanup(musb);
2190 musb_host_cleanup(musb);
2191
2192 fail3:
2193 cancel_work_sync(&musb->irq_work);
2194 cancel_delayed_work_sync(&musb->recover_work);
2195 cancel_delayed_work_sync(&musb->finish_resume_work);
2196 cancel_delayed_work_sync(&musb->deassert_reset_work);
2197 if (musb->dma_controller)
2198 dma_controller_destroy(musb->dma_controller);
2199 fail2_5:
2200 pm_runtime_put_sync(musb->controller);
2201
2202 fail2:
2203 if (musb->irq_wake)
2204 device_init_wakeup(dev, 0);
2205 musb_platform_exit(musb);
2206
2207 fail1:
2208 pm_runtime_disable(musb->controller);
2209 dev_err(musb->controller,
2210 "musb_init_controller failed with status %d\n", status);
2211
2212 musb_free(musb);
2213
2214 fail0:
2215
2216 return status;
2217
2218 }
2219
2220 /*-------------------------------------------------------------------------*/
2221
2222 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2223 * bridge to a platform device; this driver then suffices.
2224 */
2225 static int musb_probe(struct platform_device *pdev)
2226 {
2227 struct device *dev = &pdev->dev;
2228 int irq = platform_get_irq_byname(pdev, "mc");
2229 struct resource *iomem;
2230 void __iomem *base;
2231
2232 if (irq <= 0)
2233 return -ENODEV;
2234
2235 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2236 base = devm_ioremap_resource(dev, iomem);
2237 if (IS_ERR(base))
2238 return PTR_ERR(base);
2239
2240 return musb_init_controller(dev, irq, base);
2241 }
2242
2243 static int musb_remove(struct platform_device *pdev)
2244 {
2245 struct device *dev = &pdev->dev;
2246 struct musb *musb = dev_to_musb(dev);
2247
2248 /* this gets called on rmmod.
2249 * - Host mode: host may still be active
2250 * - Peripheral mode: peripheral is deactivated (or never-activated)
2251 * - OTG mode: both roles are deactivated (or never-activated)
2252 */
2253 musb_exit_debugfs(musb);
2254 musb_shutdown(pdev);
2255
2256 if (musb->dma_controller)
2257 dma_controller_destroy(musb->dma_controller);
2258
2259 cancel_work_sync(&musb->irq_work);
2260 cancel_delayed_work_sync(&musb->recover_work);
2261 cancel_delayed_work_sync(&musb->finish_resume_work);
2262 cancel_delayed_work_sync(&musb->deassert_reset_work);
2263 musb_free(musb);
2264 device_init_wakeup(dev, 0);
2265 return 0;
2266 }
2267
2268 #ifdef CONFIG_PM
2269
2270 static void musb_save_context(struct musb *musb)
2271 {
2272 int i;
2273 void __iomem *musb_base = musb->mregs;
2274 void __iomem *epio;
2275
2276 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2277 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2278 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2279 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2280 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2281 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2282 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2283
2284 for (i = 0; i < musb->config->num_eps; ++i) {
2285 struct musb_hw_ep *hw_ep;
2286
2287 hw_ep = &musb->endpoints[i];
2288 if (!hw_ep)
2289 continue;
2290
2291 epio = hw_ep->regs;
2292 if (!epio)
2293 continue;
2294
2295 musb_writeb(musb_base, MUSB_INDEX, i);
2296 musb->context.index_regs[i].txmaxp =
2297 musb_readw(epio, MUSB_TXMAXP);
2298 musb->context.index_regs[i].txcsr =
2299 musb_readw(epio, MUSB_TXCSR);
2300 musb->context.index_regs[i].rxmaxp =
2301 musb_readw(epio, MUSB_RXMAXP);
2302 musb->context.index_regs[i].rxcsr =
2303 musb_readw(epio, MUSB_RXCSR);
2304
2305 if (musb->dyn_fifo) {
2306 musb->context.index_regs[i].txfifoadd =
2307 musb_read_txfifoadd(musb_base);
2308 musb->context.index_regs[i].rxfifoadd =
2309 musb_read_rxfifoadd(musb_base);
2310 musb->context.index_regs[i].txfifosz =
2311 musb_read_txfifosz(musb_base);
2312 musb->context.index_regs[i].rxfifosz =
2313 musb_read_rxfifosz(musb_base);
2314 }
2315
2316 musb->context.index_regs[i].txtype =
2317 musb_readb(epio, MUSB_TXTYPE);
2318 musb->context.index_regs[i].txinterval =
2319 musb_readb(epio, MUSB_TXINTERVAL);
2320 musb->context.index_regs[i].rxtype =
2321 musb_readb(epio, MUSB_RXTYPE);
2322 musb->context.index_regs[i].rxinterval =
2323 musb_readb(epio, MUSB_RXINTERVAL);
2324
2325 musb->context.index_regs[i].txfunaddr =
2326 musb_read_txfunaddr(musb_base, i);
2327 musb->context.index_regs[i].txhubaddr =
2328 musb_read_txhubaddr(musb_base, i);
2329 musb->context.index_regs[i].txhubport =
2330 musb_read_txhubport(musb_base, i);
2331
2332 musb->context.index_regs[i].rxfunaddr =
2333 musb_read_rxfunaddr(musb_base, i);
2334 musb->context.index_regs[i].rxhubaddr =
2335 musb_read_rxhubaddr(musb_base, i);
2336 musb->context.index_regs[i].rxhubport =
2337 musb_read_rxhubport(musb_base, i);
2338 }
2339 }
2340
2341 static void musb_restore_context(struct musb *musb)
2342 {
2343 int i;
2344 void __iomem *musb_base = musb->mregs;
2345 void __iomem *ep_target_regs;
2346 void __iomem *epio;
2347 u8 power;
2348
2349 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2350 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2351 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2352
2353 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2354 power = musb_readb(musb_base, MUSB_POWER);
2355 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2356 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2357 power |= musb->context.power;
2358 musb_writeb(musb_base, MUSB_POWER, power);
2359
2360 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2361 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2362 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2363 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2364
2365 for (i = 0; i < musb->config->num_eps; ++i) {
2366 struct musb_hw_ep *hw_ep;
2367
2368 hw_ep = &musb->endpoints[i];
2369 if (!hw_ep)
2370 continue;
2371
2372 epio = hw_ep->regs;
2373 if (!epio)
2374 continue;
2375
2376 musb_writeb(musb_base, MUSB_INDEX, i);
2377 musb_writew(epio, MUSB_TXMAXP,
2378 musb->context.index_regs[i].txmaxp);
2379 musb_writew(epio, MUSB_TXCSR,
2380 musb->context.index_regs[i].txcsr);
2381 musb_writew(epio, MUSB_RXMAXP,
2382 musb->context.index_regs[i].rxmaxp);
2383 musb_writew(epio, MUSB_RXCSR,
2384 musb->context.index_regs[i].rxcsr);
2385
2386 if (musb->dyn_fifo) {
2387 musb_write_txfifosz(musb_base,
2388 musb->context.index_regs[i].txfifosz);
2389 musb_write_rxfifosz(musb_base,
2390 musb->context.index_regs[i].rxfifosz);
2391 musb_write_txfifoadd(musb_base,
2392 musb->context.index_regs[i].txfifoadd);
2393 musb_write_rxfifoadd(musb_base,
2394 musb->context.index_regs[i].rxfifoadd);
2395 }
2396
2397 musb_writeb(epio, MUSB_TXTYPE,
2398 musb->context.index_regs[i].txtype);
2399 musb_writeb(epio, MUSB_TXINTERVAL,
2400 musb->context.index_regs[i].txinterval);
2401 musb_writeb(epio, MUSB_RXTYPE,
2402 musb->context.index_regs[i].rxtype);
2403 musb_writeb(epio, MUSB_RXINTERVAL,
2404
2405 musb->context.index_regs[i].rxinterval);
2406 musb_write_txfunaddr(musb_base, i,
2407 musb->context.index_regs[i].txfunaddr);
2408 musb_write_txhubaddr(musb_base, i,
2409 musb->context.index_regs[i].txhubaddr);
2410 musb_write_txhubport(musb_base, i,
2411 musb->context.index_regs[i].txhubport);
2412
2413 ep_target_regs =
2414 musb_read_target_reg_base(i, musb_base);
2415
2416 musb_write_rxfunaddr(ep_target_regs,
2417 musb->context.index_regs[i].rxfunaddr);
2418 musb_write_rxhubaddr(ep_target_regs,
2419 musb->context.index_regs[i].rxhubaddr);
2420 musb_write_rxhubport(ep_target_regs,
2421 musb->context.index_regs[i].rxhubport);
2422 }
2423 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2424 }
2425
2426 static int musb_suspend(struct device *dev)
2427 {
2428 struct musb *musb = dev_to_musb(dev);
2429 unsigned long flags;
2430
2431 spin_lock_irqsave(&musb->lock, flags);
2432
2433 if (is_peripheral_active(musb)) {
2434 /* FIXME force disconnect unless we know USB will wake
2435 * the system up quickly enough to respond ...
2436 */
2437 } else if (is_host_active(musb)) {
2438 /* we know all the children are suspended; sometimes
2439 * they will even be wakeup-enabled.
2440 */
2441 }
2442
2443 musb_save_context(musb);
2444
2445 spin_unlock_irqrestore(&musb->lock, flags);
2446 return 0;
2447 }
2448
2449 static int musb_resume(struct device *dev)
2450 {
2451 struct musb *musb = dev_to_musb(dev);
2452 u8 devctl;
2453 u8 mask;
2454
2455 /*
2456 * For static cmos like DaVinci, register values were preserved
2457 * unless for some reason the whole soc powered down or the USB
2458 * module got reset through the PSC (vs just being disabled).
2459 *
2460 * For the DSPS glue layer though, a full register restore has to
2461 * be done. As it shouldn't harm other platforms, we do it
2462 * unconditionally.
2463 */
2464
2465 musb_restore_context(musb);
2466
2467 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2468 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2469 if ((devctl & mask) != (musb->context.devctl & mask))
2470 musb->port1_status = 0;
2471 if (musb->need_finish_resume) {
2472 musb->need_finish_resume = 0;
2473 schedule_delayed_work(&musb->finish_resume_work,
2474 msecs_to_jiffies(20));
2475 }
2476
2477 /*
2478 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2479 * out of suspend
2480 */
2481 pm_runtime_disable(dev);
2482 pm_runtime_set_active(dev);
2483 pm_runtime_enable(dev);
2484 return 0;
2485 }
2486
2487 static int musb_runtime_suspend(struct device *dev)
2488 {
2489 struct musb *musb = dev_to_musb(dev);
2490
2491 musb_save_context(musb);
2492
2493 return 0;
2494 }
2495
2496 static int musb_runtime_resume(struct device *dev)
2497 {
2498 struct musb *musb = dev_to_musb(dev);
2499 static int first = 1;
2500
2501 /*
2502 * When pm_runtime_get_sync called for the first time in driver
2503 * init, some of the structure is still not initialized which is
2504 * used in restore function. But clock needs to be
2505 * enabled before any register access, so
2506 * pm_runtime_get_sync has to be called.
2507 * Also context restore without save does not make
2508 * any sense
2509 */
2510 if (!first)
2511 musb_restore_context(musb);
2512 first = 0;
2513
2514 if (musb->need_finish_resume) {
2515 musb->need_finish_resume = 0;
2516 schedule_delayed_work(&musb->finish_resume_work,
2517 msecs_to_jiffies(20));
2518 }
2519
2520 return 0;
2521 }
2522
2523 static const struct dev_pm_ops musb_dev_pm_ops = {
2524 .suspend = musb_suspend,
2525 .resume = musb_resume,
2526 .runtime_suspend = musb_runtime_suspend,
2527 .runtime_resume = musb_runtime_resume,
2528 };
2529
2530 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2531 #else
2532 #define MUSB_DEV_PM_OPS NULL
2533 #endif
2534
2535 static struct platform_driver musb_driver = {
2536 .driver = {
2537 .name = (char *)musb_driver_name,
2538 .bus = &platform_bus_type,
2539 .pm = MUSB_DEV_PM_OPS,
2540 },
2541 .probe = musb_probe,
2542 .remove = musb_remove,
2543 .shutdown = musb_shutdown,
2544 };
2545
2546 module_platform_driver(musb_driver);
Linux kernel - Deliverables
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