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usb: musb: core: move babble recovery inside babble check
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102
103 #include "musb_core.h"
104
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111 #define MUSB_VERSION "6.0"
112
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124 /*-------------------------------------------------------------------------*/
125
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128 return dev_get_drvdata(dev);
129 }
130
131 /*-------------------------------------------------------------------------*/
132
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136 void __iomem *addr = phy->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172 out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
176 }
177
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180 void __iomem *addr = phy->io_priv;
181 int i = 0;
182 u8 r = 0;
183 u8 power;
184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
210 out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
214 }
215 #else
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
218 #endif
219
220 static struct usb_phy_io_ops musb_ulpi_access = {
221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223 };
224
225 /*-------------------------------------------------------------------------*/
226
227 static u32 musb_default_fifo_offset(u8 epnum)
228 {
229 return 0x20 + (epnum * 4);
230 }
231
232 /* "flat" mapping: each endpoint has its own i/o address */
233 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
234 {
235 }
236
237 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
238 {
239 return 0x100 + (0x10 * epnum) + offset;
240 }
241
242 /* "indexed" mapping: INDEX register controls register bank select */
243 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
244 {
245 musb_writeb(mbase, MUSB_INDEX, epnum);
246 }
247
248 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
249 {
250 return 0x10 + offset;
251 }
252
253 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
254 {
255 return __raw_readb(addr + offset);
256 }
257
258 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
259 {
260 __raw_writeb(data, addr + offset);
261 }
262
263 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264 {
265 return __raw_readw(addr + offset);
266 }
267
268 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
269 {
270 __raw_writew(data, addr + offset);
271 }
272
273 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
274 {
275 return __raw_readl(addr + offset);
276 }
277
278 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
279 {
280 __raw_writel(data, addr + offset);
281 }
282
283 /*
284 * Load an endpoint's FIFO
285 */
286 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
287 const u8 *src)
288 {
289 struct musb *musb = hw_ep->musb;
290 void __iomem *fifo = hw_ep->fifo;
291
292 if (unlikely(len == 0))
293 return;
294
295 prefetch((u8 *)src);
296
297 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
298 'T', hw_ep->epnum, fifo, len, src);
299
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src) == 0)) {
302 u16 index = 0;
303
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src) == 0) {
306 if (len >= 4) {
307 iowrite32_rep(fifo, src + index, len >> 2);
308 index += len & ~0x03;
309 }
310 if (len & 0x02) {
311 musb_writew(fifo, 0, *(u16 *)&src[index]);
312 index += 2;
313 }
314 } else {
315 if (len >= 2) {
316 iowrite16_rep(fifo, src + index, len >> 1);
317 index += len & ~0x01;
318 }
319 }
320 if (len & 0x01)
321 musb_writeb(fifo, 0, src[index]);
322 } else {
323 /* byte aligned */
324 iowrite8_rep(fifo, src, len);
325 }
326 }
327
328 /*
329 * Unload an endpoint's FIFO
330 */
331 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
332 {
333 struct musb *musb = hw_ep->musb;
334 void __iomem *fifo = hw_ep->fifo;
335
336 if (unlikely(len == 0))
337 return;
338
339 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
340 'R', hw_ep->epnum, fifo, len, dst);
341
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst) == 0)) {
344 u16 index = 0;
345
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst) == 0) {
348 if (len >= 4) {
349 ioread32_rep(fifo, dst, len >> 2);
350 index = len & ~0x03;
351 }
352 if (len & 0x02) {
353 *(u16 *)&dst[index] = musb_readw(fifo, 0);
354 index += 2;
355 }
356 } else {
357 if (len >= 2) {
358 ioread16_rep(fifo, dst, len >> 1);
359 index = len & ~0x01;
360 }
361 }
362 if (len & 0x01)
363 dst[index] = musb_readb(fifo, 0);
364 } else {
365 /* byte aligned */
366 ioread8_rep(fifo, dst, len);
367 }
368 }
369
370 /*
371 * Old style IO functions
372 */
373 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374 EXPORT_SYMBOL_GPL(musb_readb);
375
376 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377 EXPORT_SYMBOL_GPL(musb_writeb);
378
379 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readw);
381
382 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383 EXPORT_SYMBOL_GPL(musb_writew);
384
385 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readl);
387
388 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389 EXPORT_SYMBOL_GPL(musb_writel);
390
391 /*
392 * New style IO functions
393 */
394 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
395 {
396 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
397 }
398
399 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
400 {
401 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
402 }
403
404 /*-------------------------------------------------------------------------*/
405
406 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
407 static const u8 musb_test_packet[53] = {
408 /* implicit SYNC then DATA0 to start */
409
410 /* JKJKJKJK x9 */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
412 /* JJKKJJKK x8 */
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
414 /* JJJJKKKK x8 */
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
418 /* JJJJJJJK x8 */
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
422
423 /* implicit CRC16 then EOP to end */
424 };
425
426 void musb_load_testpacket(struct musb *musb)
427 {
428 void __iomem *regs = musb->endpoints[0].regs;
429
430 musb_ep_select(musb->mregs, 0);
431 musb_write_fifo(musb->control_ep,
432 sizeof(musb_test_packet), musb_test_packet);
433 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
434 }
435
436 /*-------------------------------------------------------------------------*/
437
438 /*
439 * Handles OTG hnp timeouts, such as b_ase0_brst
440 */
441 static void musb_otg_timer_func(unsigned long data)
442 {
443 struct musb *musb = (struct musb *)data;
444 unsigned long flags;
445
446 spin_lock_irqsave(&musb->lock, flags);
447 switch (musb->xceiv->otg->state) {
448 case OTG_STATE_B_WAIT_ACON:
449 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
450 musb_g_disconnect(musb);
451 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
452 musb->is_active = 0;
453 break;
454 case OTG_STATE_A_SUSPEND:
455 case OTG_STATE_A_WAIT_BCON:
456 dev_dbg(musb->controller, "HNP: %s timeout\n",
457 usb_otg_state_string(musb->xceiv->otg->state));
458 musb_platform_set_vbus(musb, 0);
459 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
460 break;
461 default:
462 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
463 usb_otg_state_string(musb->xceiv->otg->state));
464 }
465 spin_unlock_irqrestore(&musb->lock, flags);
466 }
467
468 /*
469 * Stops the HNP transition. Caller must take care of locking.
470 */
471 void musb_hnp_stop(struct musb *musb)
472 {
473 struct usb_hcd *hcd = musb->hcd;
474 void __iomem *mbase = musb->mregs;
475 u8 reg;
476
477 dev_dbg(musb->controller, "HNP: stop from %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479
480 switch (musb->xceiv->otg->state) {
481 case OTG_STATE_A_PERIPHERAL:
482 musb_g_disconnect(musb);
483 dev_dbg(musb->controller, "HNP: back to %s\n",
484 usb_otg_state_string(musb->xceiv->otg->state));
485 break;
486 case OTG_STATE_B_HOST:
487 dev_dbg(musb->controller, "HNP: Disabling HR\n");
488 if (hcd)
489 hcd->self.is_b_host = 0;
490 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
491 MUSB_DEV_MODE(musb);
492 reg = musb_readb(mbase, MUSB_POWER);
493 reg |= MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER, reg);
495 /* REVISIT: Start SESSION_REQUEST here? */
496 break;
497 default:
498 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 }
501
502 /*
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
505 * errors.
506 */
507 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
508 }
509
510 static void musb_generic_disable(struct musb *musb);
511 /*
512 * Interrupt Service Routine to record USB "global" interrupts.
513 * Since these do not happen often and signify things of
514 * paramount importance, it seems OK to check them individually;
515 * the order of the tests is specified in the manual
516 *
517 * @param musb instance pointer
518 * @param int_usb register contents
519 * @param devctl
520 * @param power
521 */
522
523 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
524 u8 devctl)
525 {
526 irqreturn_t handled = IRQ_NONE;
527
528 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
529 int_usb);
530
531 /* in host mode, the peripheral may issue remote wakeup.
532 * in peripheral mode, the host may resume the link.
533 * spurious RESUME irqs happen too, paired with SUSPEND.
534 */
535 if (int_usb & MUSB_INTR_RESUME) {
536 handled = IRQ_HANDLED;
537 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->otg->state));
538
539 if (devctl & MUSB_DEVCTL_HM) {
540 void __iomem *mbase = musb->mregs;
541 u8 power;
542
543 switch (musb->xceiv->otg->state) {
544 case OTG_STATE_A_SUSPEND:
545 /* remote wakeup? later, GetPortStatus
546 * will stop RESUME signaling
547 */
548
549 power = musb_readb(musb->mregs, MUSB_POWER);
550 if (power & MUSB_POWER_SUSPENDM) {
551 /* spurious */
552 musb->int_usb &= ~MUSB_INTR_SUSPEND;
553 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
554 break;
555 }
556
557 power &= ~MUSB_POWER_SUSPENDM;
558 musb_writeb(mbase, MUSB_POWER,
559 power | MUSB_POWER_RESUME);
560
561 musb->port1_status |=
562 (USB_PORT_STAT_C_SUSPEND << 16)
563 | MUSB_PORT_STAT_RESUME;
564 musb->rh_timer = jiffies
565 + msecs_to_jiffies(20);
566 musb->need_finish_resume = 1;
567
568 musb->xceiv->otg->state = OTG_STATE_A_HOST;
569 musb->is_active = 1;
570 musb_host_resume_root_hub(musb);
571 break;
572 case OTG_STATE_B_WAIT_ACON:
573 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
574 musb->is_active = 1;
575 MUSB_DEV_MODE(musb);
576 break;
577 default:
578 WARNING("bogus %s RESUME (%s)\n",
579 "host",
580 usb_otg_state_string(musb->xceiv->otg->state));
581 }
582 } else {
583 switch (musb->xceiv->otg->state) {
584 case OTG_STATE_A_SUSPEND:
585 /* possibly DISCONNECT is upcoming */
586 musb->xceiv->otg->state = OTG_STATE_A_HOST;
587 musb_host_resume_root_hub(musb);
588 break;
589 case OTG_STATE_B_WAIT_ACON:
590 case OTG_STATE_B_PERIPHERAL:
591 /* disconnect while suspended? we may
592 * not get a disconnect irq...
593 */
594 if ((devctl & MUSB_DEVCTL_VBUS)
595 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
596 ) {
597 musb->int_usb |= MUSB_INTR_DISCONNECT;
598 musb->int_usb &= ~MUSB_INTR_SUSPEND;
599 break;
600 }
601 musb_g_resume(musb);
602 break;
603 case OTG_STATE_B_IDLE:
604 musb->int_usb &= ~MUSB_INTR_SUSPEND;
605 break;
606 default:
607 WARNING("bogus %s RESUME (%s)\n",
608 "peripheral",
609 usb_otg_state_string(musb->xceiv->otg->state));
610 }
611 }
612 }
613
614 /* see manual for the order of the tests */
615 if (int_usb & MUSB_INTR_SESSREQ) {
616 void __iomem *mbase = musb->mregs;
617
618 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
619 && (devctl & MUSB_DEVCTL_BDEVICE)) {
620 dev_dbg(musb->controller, "SessReq while on B state\n");
621 return IRQ_HANDLED;
622 }
623
624 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
625 usb_otg_state_string(musb->xceiv->otg->state));
626
627 /* IRQ arrives from ID pin sense or (later, if VBUS power
628 * is removed) SRP. responses are time critical:
629 * - turn on VBUS (with silicon-specific mechanism)
630 * - go through A_WAIT_VRISE
631 * - ... to A_WAIT_BCON.
632 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
633 */
634 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
635 musb->ep0_stage = MUSB_EP0_START;
636 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
637 MUSB_HST_MODE(musb);
638 musb_platform_set_vbus(musb, 1);
639
640 handled = IRQ_HANDLED;
641 }
642
643 if (int_usb & MUSB_INTR_VBUSERROR) {
644 int ignore = 0;
645
646 /* During connection as an A-Device, we may see a short
647 * current spikes causing voltage drop, because of cable
648 * and peripheral capacitance combined with vbus draw.
649 * (So: less common with truly self-powered devices, where
650 * vbus doesn't act like a power supply.)
651 *
652 * Such spikes are short; usually less than ~500 usec, max
653 * of ~2 msec. That is, they're not sustained overcurrent
654 * errors, though they're reported using VBUSERROR irqs.
655 *
656 * Workarounds: (a) hardware: use self powered devices.
657 * (b) software: ignore non-repeated VBUS errors.
658 *
659 * REVISIT: do delays from lots of DEBUG_KERNEL checks
660 * make trouble here, keeping VBUS < 4.4V ?
661 */
662 switch (musb->xceiv->otg->state) {
663 case OTG_STATE_A_HOST:
664 /* recovery is dicey once we've gotten past the
665 * initial stages of enumeration, but if VBUS
666 * stayed ok at the other end of the link, and
667 * another reset is due (at least for high speed,
668 * to redo the chirp etc), it might work OK...
669 */
670 case OTG_STATE_A_WAIT_BCON:
671 case OTG_STATE_A_WAIT_VRISE:
672 if (musb->vbuserr_retry) {
673 void __iomem *mbase = musb->mregs;
674
675 musb->vbuserr_retry--;
676 ignore = 1;
677 devctl |= MUSB_DEVCTL_SESSION;
678 musb_writeb(mbase, MUSB_DEVCTL, devctl);
679 } else {
680 musb->port1_status |=
681 USB_PORT_STAT_OVERCURRENT
682 | (USB_PORT_STAT_C_OVERCURRENT << 16);
683 }
684 break;
685 default:
686 break;
687 }
688
689 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
690 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
691 usb_otg_state_string(musb->xceiv->otg->state),
692 devctl,
693 ({ char *s;
694 switch (devctl & MUSB_DEVCTL_VBUS) {
695 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
696 s = "<SessEnd"; break;
697 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<AValid"; break;
699 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<VBusValid"; break;
701 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
702 default:
703 s = "VALID"; break;
704 } s; }),
705 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
706 musb->port1_status);
707
708 /* go through A_WAIT_VFALL then start a new session */
709 if (!ignore)
710 musb_platform_set_vbus(musb, 0);
711 handled = IRQ_HANDLED;
712 }
713
714 if (int_usb & MUSB_INTR_SUSPEND) {
715 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
716 usb_otg_state_string(musb->xceiv->otg->state), devctl);
717 handled = IRQ_HANDLED;
718
719 switch (musb->xceiv->otg->state) {
720 case OTG_STATE_A_PERIPHERAL:
721 /* We also come here if the cable is removed, since
722 * this silicon doesn't report ID-no-longer-grounded.
723 *
724 * We depend on T(a_wait_bcon) to shut us down, and
725 * hope users don't do anything dicey during this
726 * undesired detour through A_WAIT_BCON.
727 */
728 musb_hnp_stop(musb);
729 musb_host_resume_root_hub(musb);
730 musb_root_disconnect(musb);
731 musb_platform_try_idle(musb, jiffies
732 + msecs_to_jiffies(musb->a_wait_bcon
733 ? : OTG_TIME_A_WAIT_BCON));
734
735 break;
736 case OTG_STATE_B_IDLE:
737 if (!musb->is_active)
738 break;
739 case OTG_STATE_B_PERIPHERAL:
740 musb_g_suspend(musb);
741 musb->is_active = musb->g.b_hnp_enable;
742 if (musb->is_active) {
743 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
744 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
745 mod_timer(&musb->otg_timer, jiffies
746 + msecs_to_jiffies(
747 OTG_TIME_B_ASE0_BRST));
748 }
749 break;
750 case OTG_STATE_A_WAIT_BCON:
751 if (musb->a_wait_bcon != 0)
752 musb_platform_try_idle(musb, jiffies
753 + msecs_to_jiffies(musb->a_wait_bcon));
754 break;
755 case OTG_STATE_A_HOST:
756 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
757 musb->is_active = musb->hcd->self.b_hnp_enable;
758 break;
759 case OTG_STATE_B_HOST:
760 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
761 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
762 break;
763 default:
764 /* "should not happen" */
765 musb->is_active = 0;
766 break;
767 }
768 }
769
770 if (int_usb & MUSB_INTR_CONNECT) {
771 struct usb_hcd *hcd = musb->hcd;
772
773 handled = IRQ_HANDLED;
774 musb->is_active = 1;
775
776 musb->ep0_stage = MUSB_EP0_START;
777
778 /* flush endpoints when transitioning from Device Mode */
779 if (is_peripheral_active(musb)) {
780 /* REVISIT HNP; just force disconnect */
781 }
782 musb->intrtxe = musb->epmask;
783 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
784 musb->intrrxe = musb->epmask & 0xfffe;
785 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
786 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
787 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
788 |USB_PORT_STAT_HIGH_SPEED
789 |USB_PORT_STAT_ENABLE
790 );
791 musb->port1_status |= USB_PORT_STAT_CONNECTION
792 |(USB_PORT_STAT_C_CONNECTION << 16);
793
794 /* high vs full speed is just a guess until after reset */
795 if (devctl & MUSB_DEVCTL_LSDEV)
796 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
797
798 /* indicate new connection to OTG machine */
799 switch (musb->xceiv->otg->state) {
800 case OTG_STATE_B_PERIPHERAL:
801 if (int_usb & MUSB_INTR_SUSPEND) {
802 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
803 int_usb &= ~MUSB_INTR_SUSPEND;
804 goto b_host;
805 } else
806 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
807 break;
808 case OTG_STATE_B_WAIT_ACON:
809 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
810 b_host:
811 musb->xceiv->otg->state = OTG_STATE_B_HOST;
812 if (musb->hcd)
813 musb->hcd->self.is_b_host = 1;
814 del_timer(&musb->otg_timer);
815 break;
816 default:
817 if ((devctl & MUSB_DEVCTL_VBUS)
818 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
819 musb->xceiv->otg->state = OTG_STATE_A_HOST;
820 if (hcd)
821 hcd->self.is_b_host = 0;
822 }
823 break;
824 }
825
826 musb_host_poke_root_hub(musb);
827
828 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
829 usb_otg_state_string(musb->xceiv->otg->state), devctl);
830 }
831
832 if (int_usb & MUSB_INTR_DISCONNECT) {
833 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
834 usb_otg_state_string(musb->xceiv->otg->state),
835 MUSB_MODE(musb), devctl);
836 handled = IRQ_HANDLED;
837
838 switch (musb->xceiv->otg->state) {
839 case OTG_STATE_A_HOST:
840 case OTG_STATE_A_SUSPEND:
841 musb_host_resume_root_hub(musb);
842 musb_root_disconnect(musb);
843 if (musb->a_wait_bcon != 0)
844 musb_platform_try_idle(musb, jiffies
845 + msecs_to_jiffies(musb->a_wait_bcon));
846 break;
847 case OTG_STATE_B_HOST:
848 /* REVISIT this behaves for "real disconnect"
849 * cases; make sure the other transitions from
850 * from B_HOST act right too. The B_HOST code
851 * in hnp_stop() is currently not used...
852 */
853 musb_root_disconnect(musb);
854 if (musb->hcd)
855 musb->hcd->self.is_b_host = 0;
856 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
857 MUSB_DEV_MODE(musb);
858 musb_g_disconnect(musb);
859 break;
860 case OTG_STATE_A_PERIPHERAL:
861 musb_hnp_stop(musb);
862 musb_root_disconnect(musb);
863 /* FALLTHROUGH */
864 case OTG_STATE_B_WAIT_ACON:
865 /* FALLTHROUGH */
866 case OTG_STATE_B_PERIPHERAL:
867 case OTG_STATE_B_IDLE:
868 musb_g_disconnect(musb);
869 break;
870 default:
871 WARNING("unhandled DISCONNECT transition (%s)\n",
872 usb_otg_state_string(musb->xceiv->otg->state));
873 break;
874 }
875 }
876
877 /* mentor saves a bit: bus reset and babble share the same irq.
878 * only host sees babble; only peripheral sees bus reset.
879 */
880 if (int_usb & MUSB_INTR_RESET) {
881 handled = IRQ_HANDLED;
882 if (devctl & MUSB_DEVCTL_HM) {
883 u8 power = musb_readl(musb->mregs, MUSB_POWER);
884
885 /*
886 * Looks like non-HS BABBLE can be ignored, but
887 * HS BABBLE is an error condition.
888 *
889 * For HS the solution is to avoid babble in the first
890 * place and fix what caused BABBLE.
891 *
892 * When HS BABBLE happens what we can depends on which
893 * platform MUSB is running, because some platforms
894 * implemented proprietary means for 'recovering' from
895 * Babble conditions. One such platform is AM335x. In
896 * most cases, however, the only thing we can do is drop
897 * the session.
898 */
899 if (power & MUSB_POWER_HSMODE) {
900 ERR("Stopping host session -- babble\n");
901 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
902
903 if (is_host_active(musb)) {
904 musb_generic_disable(musb);
905 schedule_delayed_work(&musb->recover_work,
906 msecs_to_jiffies(100));
907 }
908 }
909 } else {
910 dev_dbg(musb->controller, "BUS RESET as %s\n",
911 usb_otg_state_string(musb->xceiv->otg->state));
912 switch (musb->xceiv->otg->state) {
913 case OTG_STATE_A_SUSPEND:
914 musb_g_reset(musb);
915 /* FALLTHROUGH */
916 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
917 /* never use invalid T(a_wait_bcon) */
918 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
919 usb_otg_state_string(musb->xceiv->otg->state),
920 TA_WAIT_BCON(musb));
921 mod_timer(&musb->otg_timer, jiffies
922 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
923 break;
924 case OTG_STATE_A_PERIPHERAL:
925 del_timer(&musb->otg_timer);
926 musb_g_reset(musb);
927 break;
928 case OTG_STATE_B_WAIT_ACON:
929 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
930 usb_otg_state_string(musb->xceiv->otg->state));
931 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
932 musb_g_reset(musb);
933 break;
934 case OTG_STATE_B_IDLE:
935 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
936 /* FALLTHROUGH */
937 case OTG_STATE_B_PERIPHERAL:
938 musb_g_reset(musb);
939 break;
940 default:
941 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
942 usb_otg_state_string(musb->xceiv->otg->state));
943 }
944 }
945 }
946
947 #if 0
948 /* REVISIT ... this would be for multiplexing periodic endpoints, or
949 * supporting transfer phasing to prevent exceeding ISO bandwidth
950 * limits of a given frame or microframe.
951 *
952 * It's not needed for peripheral side, which dedicates endpoints;
953 * though it _might_ use SOF irqs for other purposes.
954 *
955 * And it's not currently needed for host side, which also dedicates
956 * endpoints, relies on TX/RX interval registers, and isn't claimed
957 * to support ISO transfers yet.
958 */
959 if (int_usb & MUSB_INTR_SOF) {
960 void __iomem *mbase = musb->mregs;
961 struct musb_hw_ep *ep;
962 u8 epnum;
963 u16 frame;
964
965 dev_dbg(musb->controller, "START_OF_FRAME\n");
966 handled = IRQ_HANDLED;
967
968 /* start any periodic Tx transfers waiting for current frame */
969 frame = musb_readw(mbase, MUSB_FRAME);
970 ep = musb->endpoints;
971 for (epnum = 1; (epnum < musb->nr_endpoints)
972 && (musb->epmask >= (1 << epnum));
973 epnum++, ep++) {
974 /*
975 * FIXME handle framecounter wraps (12 bits)
976 * eliminate duplicated StartUrb logic
977 */
978 if (ep->dwWaitFrame >= frame) {
979 ep->dwWaitFrame = 0;
980 pr_debug("SOF --> periodic TX%s on %d\n",
981 ep->tx_channel ? " DMA" : "",
982 epnum);
983 if (!ep->tx_channel)
984 musb_h_tx_start(musb, epnum);
985 else
986 cppi_hostdma_start(musb, epnum);
987 }
988 } /* end of for loop */
989 }
990 #endif
991
992 schedule_work(&musb->irq_work);
993
994 return handled;
995 }
996
997 /*-------------------------------------------------------------------------*/
998
999 static void musb_generic_disable(struct musb *musb)
1000 {
1001 void __iomem *mbase = musb->mregs;
1002 u16 temp;
1003
1004 /* disable interrupts */
1005 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1006 musb->intrtxe = 0;
1007 musb_writew(mbase, MUSB_INTRTXE, 0);
1008 musb->intrrxe = 0;
1009 musb_writew(mbase, MUSB_INTRRXE, 0);
1010
1011 /* off */
1012 musb_writeb(mbase, MUSB_DEVCTL, 0);
1013
1014 /* flush pending interrupts */
1015 temp = musb_readb(mbase, MUSB_INTRUSB);
1016 temp = musb_readw(mbase, MUSB_INTRTX);
1017 temp = musb_readw(mbase, MUSB_INTRRX);
1018
1019 }
1020
1021 /*
1022 * Program the HDRC to start (enable interrupts, dma, etc.).
1023 */
1024 void musb_start(struct musb *musb)
1025 {
1026 void __iomem *regs = musb->mregs;
1027 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1028
1029 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1030
1031 /* Set INT enable registers, enable interrupts */
1032 musb->intrtxe = musb->epmask;
1033 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1034 musb->intrrxe = musb->epmask & 0xfffe;
1035 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1036 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1037
1038 musb_writeb(regs, MUSB_TESTMODE, 0);
1039
1040 /* put into basic highspeed mode and start session */
1041 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1042 | MUSB_POWER_HSENAB
1043 /* ENSUSPEND wedges tusb */
1044 /* | MUSB_POWER_ENSUSPEND */
1045 );
1046
1047 musb->is_active = 0;
1048 devctl = musb_readb(regs, MUSB_DEVCTL);
1049 devctl &= ~MUSB_DEVCTL_SESSION;
1050
1051 /* session started after:
1052 * (a) ID-grounded irq, host mode;
1053 * (b) vbus present/connect IRQ, peripheral mode;
1054 * (c) peripheral initiates, using SRP
1055 */
1056 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1057 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1058 musb->is_active = 1;
1059 } else {
1060 devctl |= MUSB_DEVCTL_SESSION;
1061 }
1062
1063 musb_platform_enable(musb);
1064 musb_writeb(regs, MUSB_DEVCTL, devctl);
1065 }
1066
1067 /*
1068 * Make the HDRC stop (disable interrupts, etc.);
1069 * reversible by musb_start
1070 * called on gadget driver unregister
1071 * with controller locked, irqs blocked
1072 * acts as a NOP unless some role activated the hardware
1073 */
1074 void musb_stop(struct musb *musb)
1075 {
1076 /* stop IRQs, timers, ... */
1077 musb_platform_disable(musb);
1078 musb_generic_disable(musb);
1079 dev_dbg(musb->controller, "HDRC disabled\n");
1080
1081 /* FIXME
1082 * - mark host and/or peripheral drivers unusable/inactive
1083 * - disable DMA (and enable it in HdrcStart)
1084 * - make sure we can musb_start() after musb_stop(); with
1085 * OTG mode, gadget driver module rmmod/modprobe cycles that
1086 * - ...
1087 */
1088 musb_platform_try_idle(musb, 0);
1089 }
1090
1091 static void musb_shutdown(struct platform_device *pdev)
1092 {
1093 struct musb *musb = dev_to_musb(&pdev->dev);
1094 unsigned long flags;
1095
1096 pm_runtime_get_sync(musb->controller);
1097
1098 musb_host_cleanup(musb);
1099 musb_gadget_cleanup(musb);
1100
1101 spin_lock_irqsave(&musb->lock, flags);
1102 musb_platform_disable(musb);
1103 musb_generic_disable(musb);
1104 spin_unlock_irqrestore(&musb->lock, flags);
1105
1106 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1107 musb_platform_exit(musb);
1108
1109 pm_runtime_put(musb->controller);
1110 /* FIXME power down */
1111 }
1112
1113
1114 /*-------------------------------------------------------------------------*/
1115
1116 /*
1117 * The silicon either has hard-wired endpoint configurations, or else
1118 * "dynamic fifo" sizing. The driver has support for both, though at this
1119 * writing only the dynamic sizing is very well tested. Since we switched
1120 * away from compile-time hardware parameters, we can no longer rely on
1121 * dead code elimination to leave only the relevant one in the object file.
1122 *
1123 * We don't currently use dynamic fifo setup capability to do anything
1124 * more than selecting one of a bunch of predefined configurations.
1125 */
1126 static ushort fifo_mode;
1127
1128 /* "modprobe ... fifo_mode=1" etc */
1129 module_param(fifo_mode, ushort, 0);
1130 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1131
1132 /*
1133 * tables defining fifo_mode values. define more if you like.
1134 * for host side, make sure both halves of ep1 are set up.
1135 */
1136
1137 /* mode 0 - fits in 2KB */
1138 static struct musb_fifo_cfg mode_0_cfg[] = {
1139 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1142 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1143 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1144 };
1145
1146 /* mode 1 - fits in 4KB */
1147 static struct musb_fifo_cfg mode_1_cfg[] = {
1148 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1149 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1150 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1152 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1153 };
1154
1155 /* mode 2 - fits in 4KB */
1156 static struct musb_fifo_cfg mode_2_cfg[] = {
1157 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1158 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1159 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1160 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1161 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1162 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1163 };
1164
1165 /* mode 3 - fits in 4KB */
1166 static struct musb_fifo_cfg mode_3_cfg[] = {
1167 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1168 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1169 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1170 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1171 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1172 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1173 };
1174
1175 /* mode 4 - fits in 16KB */
1176 static struct musb_fifo_cfg mode_4_cfg[] = {
1177 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1178 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1179 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1180 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1181 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1182 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1183 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1184 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1185 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1186 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1187 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1188 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1189 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1190 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1191 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1192 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1193 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1194 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1195 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1196 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1197 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1198 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1199 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1200 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1201 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1202 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1203 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1204 };
1205
1206 /* mode 5 - fits in 8KB */
1207 static struct musb_fifo_cfg mode_5_cfg[] = {
1208 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1209 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1210 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1211 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1212 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1213 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1214 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1215 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1216 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1217 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1218 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1219 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1220 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1221 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1222 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1223 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1224 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1225 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1226 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1227 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1228 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1229 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1230 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1231 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1232 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1233 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1234 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1235 };
1236
1237 /*
1238 * configure a fifo; for non-shared endpoints, this may be called
1239 * once for a tx fifo and once for an rx fifo.
1240 *
1241 * returns negative errno or offset for next fifo.
1242 */
1243 static int
1244 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1245 const struct musb_fifo_cfg *cfg, u16 offset)
1246 {
1247 void __iomem *mbase = musb->mregs;
1248 int size = 0;
1249 u16 maxpacket = cfg->maxpacket;
1250 u16 c_off = offset >> 3;
1251 u8 c_size;
1252
1253 /* expect hw_ep has already been zero-initialized */
1254
1255 size = ffs(max(maxpacket, (u16) 8)) - 1;
1256 maxpacket = 1 << size;
1257
1258 c_size = size - 3;
1259 if (cfg->mode == BUF_DOUBLE) {
1260 if ((offset + (maxpacket << 1)) >
1261 (1 << (musb->config->ram_bits + 2)))
1262 return -EMSGSIZE;
1263 c_size |= MUSB_FIFOSZ_DPB;
1264 } else {
1265 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1266 return -EMSGSIZE;
1267 }
1268
1269 /* configure the FIFO */
1270 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1271
1272 /* EP0 reserved endpoint for control, bidirectional;
1273 * EP1 reserved for bulk, two unidirectional halves.
1274 */
1275 if (hw_ep->epnum == 1)
1276 musb->bulk_ep = hw_ep;
1277 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1278 switch (cfg->style) {
1279 case FIFO_TX:
1280 musb_write_txfifosz(mbase, c_size);
1281 musb_write_txfifoadd(mbase, c_off);
1282 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1283 hw_ep->max_packet_sz_tx = maxpacket;
1284 break;
1285 case FIFO_RX:
1286 musb_write_rxfifosz(mbase, c_size);
1287 musb_write_rxfifoadd(mbase, c_off);
1288 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1289 hw_ep->max_packet_sz_rx = maxpacket;
1290 break;
1291 case FIFO_RXTX:
1292 musb_write_txfifosz(mbase, c_size);
1293 musb_write_txfifoadd(mbase, c_off);
1294 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1295 hw_ep->max_packet_sz_rx = maxpacket;
1296
1297 musb_write_rxfifosz(mbase, c_size);
1298 musb_write_rxfifoadd(mbase, c_off);
1299 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1300 hw_ep->max_packet_sz_tx = maxpacket;
1301
1302 hw_ep->is_shared_fifo = true;
1303 break;
1304 }
1305
1306 /* NOTE rx and tx endpoint irqs aren't managed separately,
1307 * which happens to be ok
1308 */
1309 musb->epmask |= (1 << hw_ep->epnum);
1310
1311 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1312 }
1313
1314 static struct musb_fifo_cfg ep0_cfg = {
1315 .style = FIFO_RXTX, .maxpacket = 64,
1316 };
1317
1318 static int ep_config_from_table(struct musb *musb)
1319 {
1320 const struct musb_fifo_cfg *cfg;
1321 unsigned i, n;
1322 int offset;
1323 struct musb_hw_ep *hw_ep = musb->endpoints;
1324
1325 if (musb->config->fifo_cfg) {
1326 cfg = musb->config->fifo_cfg;
1327 n = musb->config->fifo_cfg_size;
1328 goto done;
1329 }
1330
1331 switch (fifo_mode) {
1332 default:
1333 fifo_mode = 0;
1334 /* FALLTHROUGH */
1335 case 0:
1336 cfg = mode_0_cfg;
1337 n = ARRAY_SIZE(mode_0_cfg);
1338 break;
1339 case 1:
1340 cfg = mode_1_cfg;
1341 n = ARRAY_SIZE(mode_1_cfg);
1342 break;
1343 case 2:
1344 cfg = mode_2_cfg;
1345 n = ARRAY_SIZE(mode_2_cfg);
1346 break;
1347 case 3:
1348 cfg = mode_3_cfg;
1349 n = ARRAY_SIZE(mode_3_cfg);
1350 break;
1351 case 4:
1352 cfg = mode_4_cfg;
1353 n = ARRAY_SIZE(mode_4_cfg);
1354 break;
1355 case 5:
1356 cfg = mode_5_cfg;
1357 n = ARRAY_SIZE(mode_5_cfg);
1358 break;
1359 }
1360
1361 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1362 musb_driver_name, fifo_mode);
1363
1364
1365 done:
1366 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1367 /* assert(offset > 0) */
1368
1369 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1370 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1371 */
1372
1373 for (i = 0; i < n; i++) {
1374 u8 epn = cfg->hw_ep_num;
1375
1376 if (epn >= musb->config->num_eps) {
1377 pr_debug("%s: invalid ep %d\n",
1378 musb_driver_name, epn);
1379 return -EINVAL;
1380 }
1381 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1382 if (offset < 0) {
1383 pr_debug("%s: mem overrun, ep %d\n",
1384 musb_driver_name, epn);
1385 return offset;
1386 }
1387 epn++;
1388 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1389 }
1390
1391 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1392 musb_driver_name,
1393 n + 1, musb->config->num_eps * 2 - 1,
1394 offset, (1 << (musb->config->ram_bits + 2)));
1395
1396 if (!musb->bulk_ep) {
1397 pr_debug("%s: missing bulk\n", musb_driver_name);
1398 return -EINVAL;
1399 }
1400
1401 return 0;
1402 }
1403
1404
1405 /*
1406 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1407 * @param musb the controller
1408 */
1409 static int ep_config_from_hw(struct musb *musb)
1410 {
1411 u8 epnum = 0;
1412 struct musb_hw_ep *hw_ep;
1413 void __iomem *mbase = musb->mregs;
1414 int ret = 0;
1415
1416 dev_dbg(musb->controller, "<== static silicon ep config\n");
1417
1418 /* FIXME pick up ep0 maxpacket size */
1419
1420 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1421 musb_ep_select(mbase, epnum);
1422 hw_ep = musb->endpoints + epnum;
1423
1424 ret = musb_read_fifosize(musb, hw_ep, epnum);
1425 if (ret < 0)
1426 break;
1427
1428 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1429
1430 /* pick an RX/TX endpoint for bulk */
1431 if (hw_ep->max_packet_sz_tx < 512
1432 || hw_ep->max_packet_sz_rx < 512)
1433 continue;
1434
1435 /* REVISIT: this algorithm is lazy, we should at least
1436 * try to pick a double buffered endpoint.
1437 */
1438 if (musb->bulk_ep)
1439 continue;
1440 musb->bulk_ep = hw_ep;
1441 }
1442
1443 if (!musb->bulk_ep) {
1444 pr_debug("%s: missing bulk\n", musb_driver_name);
1445 return -EINVAL;
1446 }
1447
1448 return 0;
1449 }
1450
1451 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1452
1453 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1454 * configure endpoints, or take their config from silicon
1455 */
1456 static int musb_core_init(u16 musb_type, struct musb *musb)
1457 {
1458 u8 reg;
1459 char *type;
1460 char aInfo[90], aRevision[32], aDate[12];
1461 void __iomem *mbase = musb->mregs;
1462 int status = 0;
1463 int i;
1464
1465 /* log core options (read using indexed model) */
1466 reg = musb_read_configdata(mbase);
1467
1468 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1469 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1470 strcat(aInfo, ", dyn FIFOs");
1471 musb->dyn_fifo = true;
1472 }
1473 if (reg & MUSB_CONFIGDATA_MPRXE) {
1474 strcat(aInfo, ", bulk combine");
1475 musb->bulk_combine = true;
1476 }
1477 if (reg & MUSB_CONFIGDATA_MPTXE) {
1478 strcat(aInfo, ", bulk split");
1479 musb->bulk_split = true;
1480 }
1481 if (reg & MUSB_CONFIGDATA_HBRXE) {
1482 strcat(aInfo, ", HB-ISO Rx");
1483 musb->hb_iso_rx = true;
1484 }
1485 if (reg & MUSB_CONFIGDATA_HBTXE) {
1486 strcat(aInfo, ", HB-ISO Tx");
1487 musb->hb_iso_tx = true;
1488 }
1489 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1490 strcat(aInfo, ", SoftConn");
1491
1492 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1493 musb_driver_name, reg, aInfo);
1494
1495 aDate[0] = 0;
1496 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1497 musb->is_multipoint = 1;
1498 type = "M";
1499 } else {
1500 musb->is_multipoint = 0;
1501 type = "";
1502 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1503 printk(KERN_ERR
1504 "%s: kernel must blacklist external hubs\n",
1505 musb_driver_name);
1506 #endif
1507 }
1508
1509 /* log release info */
1510 musb->hwvers = musb_read_hwvers(mbase);
1511 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1512 MUSB_HWVERS_MINOR(musb->hwvers),
1513 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1514 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1515 musb_driver_name, type, aRevision, aDate);
1516
1517 /* configure ep0 */
1518 musb_configure_ep0(musb);
1519
1520 /* discover endpoint configuration */
1521 musb->nr_endpoints = 1;
1522 musb->epmask = 1;
1523
1524 if (musb->dyn_fifo)
1525 status = ep_config_from_table(musb);
1526 else
1527 status = ep_config_from_hw(musb);
1528
1529 if (status < 0)
1530 return status;
1531
1532 /* finish init, and print endpoint config */
1533 for (i = 0; i < musb->nr_endpoints; i++) {
1534 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1535
1536 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1537 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1538 if (musb->io.quirks & MUSB_IN_TUSB) {
1539 hw_ep->fifo_async = musb->async + 0x400 +
1540 musb->io.fifo_offset(i);
1541 hw_ep->fifo_sync = musb->sync + 0x400 +
1542 musb->io.fifo_offset(i);
1543 hw_ep->fifo_sync_va =
1544 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1545
1546 if (i == 0)
1547 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1548 else
1549 hw_ep->conf = mbase + 0x400 +
1550 (((i - 1) & 0xf) << 2);
1551 }
1552 #endif
1553
1554 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1555 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1556 hw_ep->rx_reinit = 1;
1557 hw_ep->tx_reinit = 1;
1558
1559 if (hw_ep->max_packet_sz_tx) {
1560 dev_dbg(musb->controller,
1561 "%s: hw_ep %d%s, %smax %d\n",
1562 musb_driver_name, i,
1563 hw_ep->is_shared_fifo ? "shared" : "tx",
1564 hw_ep->tx_double_buffered
1565 ? "doublebuffer, " : "",
1566 hw_ep->max_packet_sz_tx);
1567 }
1568 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1569 dev_dbg(musb->controller,
1570 "%s: hw_ep %d%s, %smax %d\n",
1571 musb_driver_name, i,
1572 "rx",
1573 hw_ep->rx_double_buffered
1574 ? "doublebuffer, " : "",
1575 hw_ep->max_packet_sz_rx);
1576 }
1577 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1578 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1579 }
1580
1581 return 0;
1582 }
1583
1584 /*-------------------------------------------------------------------------*/
1585
1586 /*
1587 * handle all the irqs defined by the HDRC core. for now we expect: other
1588 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1589 * will be assigned, and the irq will already have been acked.
1590 *
1591 * called in irq context with spinlock held, irqs blocked
1592 */
1593 irqreturn_t musb_interrupt(struct musb *musb)
1594 {
1595 irqreturn_t retval = IRQ_NONE;
1596 unsigned long status;
1597 unsigned long epnum;
1598 u8 devctl;
1599
1600 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1601 return IRQ_NONE;
1602
1603 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1604
1605 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1606 is_host_active(musb) ? "host" : "peripheral",
1607 musb->int_usb, musb->int_tx, musb->int_rx);
1608
1609 /**
1610 * According to Mentor Graphics' documentation, flowchart on page 98,
1611 * IRQ should be handled as follows:
1612 *
1613 * . Resume IRQ
1614 * . Session Request IRQ
1615 * . VBUS Error IRQ
1616 * . Suspend IRQ
1617 * . Connect IRQ
1618 * . Disconnect IRQ
1619 * . Reset/Babble IRQ
1620 * . SOF IRQ (we're not using this one)
1621 * . Endpoint 0 IRQ
1622 * . TX Endpoints
1623 * . RX Endpoints
1624 *
1625 * We will be following that flowchart in order to avoid any problems
1626 * that might arise with internal Finite State Machine.
1627 */
1628
1629 if (musb->int_usb)
1630 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1631
1632 if (musb->int_tx & 1) {
1633 if (is_host_active(musb))
1634 retval |= musb_h_ep0_irq(musb);
1635 else
1636 retval |= musb_g_ep0_irq(musb);
1637
1638 /* we have just handled endpoint 0 IRQ, clear it */
1639 musb->int_tx &= ~BIT(0);
1640 }
1641
1642 status = musb->int_tx;
1643
1644 for_each_set_bit(epnum, &status, 16) {
1645 retval = IRQ_HANDLED;
1646 if (is_host_active(musb))
1647 musb_host_tx(musb, epnum);
1648 else
1649 musb_g_tx(musb, epnum);
1650 }
1651
1652 status = musb->int_rx;
1653
1654 for_each_set_bit(epnum, &status, 16) {
1655 retval = IRQ_HANDLED;
1656 if (is_host_active(musb))
1657 musb_host_rx(musb, epnum);
1658 else
1659 musb_g_rx(musb, epnum);
1660 }
1661
1662 return retval;
1663 }
1664 EXPORT_SYMBOL_GPL(musb_interrupt);
1665
1666 #ifndef CONFIG_MUSB_PIO_ONLY
1667 static bool use_dma = 1;
1668
1669 /* "modprobe ... use_dma=0" etc */
1670 module_param(use_dma, bool, 0);
1671 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1672
1673 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1674 {
1675 /* called with controller lock already held */
1676
1677 if (!epnum) {
1678 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1679 if (!is_cppi_enabled()) {
1680 /* endpoint 0 */
1681 if (is_host_active(musb))
1682 musb_h_ep0_irq(musb);
1683 else
1684 musb_g_ep0_irq(musb);
1685 }
1686 #endif
1687 } else {
1688 /* endpoints 1..15 */
1689 if (transmit) {
1690 if (is_host_active(musb))
1691 musb_host_tx(musb, epnum);
1692 else
1693 musb_g_tx(musb, epnum);
1694 } else {
1695 /* receive */
1696 if (is_host_active(musb))
1697 musb_host_rx(musb, epnum);
1698 else
1699 musb_g_rx(musb, epnum);
1700 }
1701 }
1702 }
1703 EXPORT_SYMBOL_GPL(musb_dma_completion);
1704
1705 #else
1706 #define use_dma 0
1707 #endif
1708
1709 /*-------------------------------------------------------------------------*/
1710
1711 static ssize_t
1712 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1713 {
1714 struct musb *musb = dev_to_musb(dev);
1715 unsigned long flags;
1716 int ret = -EINVAL;
1717
1718 spin_lock_irqsave(&musb->lock, flags);
1719 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1720 spin_unlock_irqrestore(&musb->lock, flags);
1721
1722 return ret;
1723 }
1724
1725 static ssize_t
1726 musb_mode_store(struct device *dev, struct device_attribute *attr,
1727 const char *buf, size_t n)
1728 {
1729 struct musb *musb = dev_to_musb(dev);
1730 unsigned long flags;
1731 int status;
1732
1733 spin_lock_irqsave(&musb->lock, flags);
1734 if (sysfs_streq(buf, "host"))
1735 status = musb_platform_set_mode(musb, MUSB_HOST);
1736 else if (sysfs_streq(buf, "peripheral"))
1737 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1738 else if (sysfs_streq(buf, "otg"))
1739 status = musb_platform_set_mode(musb, MUSB_OTG);
1740 else
1741 status = -EINVAL;
1742 spin_unlock_irqrestore(&musb->lock, flags);
1743
1744 return (status == 0) ? n : status;
1745 }
1746 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1747
1748 static ssize_t
1749 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1750 const char *buf, size_t n)
1751 {
1752 struct musb *musb = dev_to_musb(dev);
1753 unsigned long flags;
1754 unsigned long val;
1755
1756 if (sscanf(buf, "%lu", &val) < 1) {
1757 dev_err(dev, "Invalid VBUS timeout ms value\n");
1758 return -EINVAL;
1759 }
1760
1761 spin_lock_irqsave(&musb->lock, flags);
1762 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1763 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1764 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1765 musb->is_active = 0;
1766 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1767 spin_unlock_irqrestore(&musb->lock, flags);
1768
1769 return n;
1770 }
1771
1772 static ssize_t
1773 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1774 {
1775 struct musb *musb = dev_to_musb(dev);
1776 unsigned long flags;
1777 unsigned long val;
1778 int vbus;
1779
1780 spin_lock_irqsave(&musb->lock, flags);
1781 val = musb->a_wait_bcon;
1782 /* FIXME get_vbus_status() is normally #defined as false...
1783 * and is effectively TUSB-specific.
1784 */
1785 vbus = musb_platform_get_vbus_status(musb);
1786 spin_unlock_irqrestore(&musb->lock, flags);
1787
1788 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1789 vbus ? "on" : "off", val);
1790 }
1791 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1792
1793 /* Gadget drivers can't know that a host is connected so they might want
1794 * to start SRP, but users can. This allows userspace to trigger SRP.
1795 */
1796 static ssize_t
1797 musb_srp_store(struct device *dev, struct device_attribute *attr,
1798 const char *buf, size_t n)
1799 {
1800 struct musb *musb = dev_to_musb(dev);
1801 unsigned short srp;
1802
1803 if (sscanf(buf, "%hu", &srp) != 1
1804 || (srp != 1)) {
1805 dev_err(dev, "SRP: Value must be 1\n");
1806 return -EINVAL;
1807 }
1808
1809 if (srp == 1)
1810 musb_g_wakeup(musb);
1811
1812 return n;
1813 }
1814 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1815
1816 static struct attribute *musb_attributes[] = {
1817 &dev_attr_mode.attr,
1818 &dev_attr_vbus.attr,
1819 &dev_attr_srp.attr,
1820 NULL
1821 };
1822
1823 static const struct attribute_group musb_attr_group = {
1824 .attrs = musb_attributes,
1825 };
1826
1827 /* Only used to provide driver mode change events */
1828 static void musb_irq_work(struct work_struct *data)
1829 {
1830 struct musb *musb = container_of(data, struct musb, irq_work);
1831
1832 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1833 musb->xceiv_old_state = musb->xceiv->otg->state;
1834 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1835 }
1836 }
1837
1838 /* Recover from babble interrupt conditions */
1839 static void musb_recover_work(struct work_struct *data)
1840 {
1841 struct musb *musb = container_of(data, struct musb, recover_work.work);
1842 int status, ret;
1843
1844 ret = musb_platform_reset(musb);
1845 if (ret)
1846 return;
1847
1848 usb_phy_vbus_off(musb->xceiv);
1849 usleep_range(100, 200);
1850
1851 usb_phy_vbus_on(musb->xceiv);
1852 usleep_range(100, 200);
1853
1854 /*
1855 * When a babble condition occurs, the musb controller
1856 * removes the session bit and the endpoint config is lost.
1857 */
1858 if (musb->dyn_fifo)
1859 status = ep_config_from_table(musb);
1860 else
1861 status = ep_config_from_hw(musb);
1862
1863 /* start the session again */
1864 if (status == 0)
1865 musb_start(musb);
1866 }
1867
1868 /* --------------------------------------------------------------------------
1869 * Init support
1870 */
1871
1872 static struct musb *allocate_instance(struct device *dev,
1873 struct musb_hdrc_config *config, void __iomem *mbase)
1874 {
1875 struct musb *musb;
1876 struct musb_hw_ep *ep;
1877 int epnum;
1878 int ret;
1879
1880 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1881 if (!musb)
1882 return NULL;
1883
1884 INIT_LIST_HEAD(&musb->control);
1885 INIT_LIST_HEAD(&musb->in_bulk);
1886 INIT_LIST_HEAD(&musb->out_bulk);
1887
1888 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1889 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1890 musb->mregs = mbase;
1891 musb->ctrl_base = mbase;
1892 musb->nIrq = -ENODEV;
1893 musb->config = config;
1894 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1895 for (epnum = 0, ep = musb->endpoints;
1896 epnum < musb->config->num_eps;
1897 epnum++, ep++) {
1898 ep->musb = musb;
1899 ep->epnum = epnum;
1900 }
1901
1902 musb->controller = dev;
1903
1904 ret = musb_host_alloc(musb);
1905 if (ret < 0)
1906 goto err_free;
1907
1908 dev_set_drvdata(dev, musb);
1909
1910 return musb;
1911
1912 err_free:
1913 return NULL;
1914 }
1915
1916 static void musb_free(struct musb *musb)
1917 {
1918 /* this has multiple entry modes. it handles fault cleanup after
1919 * probe(), where things may be partially set up, as well as rmmod
1920 * cleanup after everything's been de-activated.
1921 */
1922
1923 #ifdef CONFIG_SYSFS
1924 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1925 #endif
1926
1927 if (musb->nIrq >= 0) {
1928 if (musb->irq_wake)
1929 disable_irq_wake(musb->nIrq);
1930 free_irq(musb->nIrq, musb);
1931 }
1932
1933 musb_host_free(musb);
1934 }
1935
1936 static void musb_deassert_reset(struct work_struct *work)
1937 {
1938 struct musb *musb;
1939 unsigned long flags;
1940
1941 musb = container_of(work, struct musb, deassert_reset_work.work);
1942
1943 spin_lock_irqsave(&musb->lock, flags);
1944
1945 if (musb->port1_status & USB_PORT_STAT_RESET)
1946 musb_port_reset(musb, false);
1947
1948 spin_unlock_irqrestore(&musb->lock, flags);
1949 }
1950
1951 /*
1952 * Perform generic per-controller initialization.
1953 *
1954 * @dev: the controller (already clocked, etc)
1955 * @nIrq: IRQ number
1956 * @ctrl: virtual address of controller registers,
1957 * not yet corrected for platform-specific offsets
1958 */
1959 static int
1960 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1961 {
1962 int status;
1963 struct musb *musb;
1964 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1965
1966 /* The driver might handle more features than the board; OK.
1967 * Fail when the board needs a feature that's not enabled.
1968 */
1969 if (!plat) {
1970 dev_dbg(dev, "no platform_data?\n");
1971 status = -ENODEV;
1972 goto fail0;
1973 }
1974
1975 /* allocate */
1976 musb = allocate_instance(dev, plat->config, ctrl);
1977 if (!musb) {
1978 status = -ENOMEM;
1979 goto fail0;
1980 }
1981
1982 spin_lock_init(&musb->lock);
1983 musb->board_set_power = plat->set_power;
1984 musb->min_power = plat->min_power;
1985 musb->ops = plat->platform_ops;
1986 musb->port_mode = plat->mode;
1987
1988 /*
1989 * Initialize the default IO functions. At least omap2430 needs
1990 * these early. We initialize the platform specific IO functions
1991 * later on.
1992 */
1993 musb_readb = musb_default_readb;
1994 musb_writeb = musb_default_writeb;
1995 musb_readw = musb_default_readw;
1996 musb_writew = musb_default_writew;
1997 musb_readl = musb_default_readl;
1998 musb_writel = musb_default_writel;
1999
2000 /* We need musb_read/write functions initialized for PM */
2001 pm_runtime_use_autosuspend(musb->controller);
2002 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2003 pm_runtime_irq_safe(musb->controller);
2004 pm_runtime_enable(musb->controller);
2005
2006 /* The musb_platform_init() call:
2007 * - adjusts musb->mregs
2008 * - sets the musb->isr
2009 * - may initialize an integrated transceiver
2010 * - initializes musb->xceiv, usually by otg_get_phy()
2011 * - stops powering VBUS
2012 *
2013 * There are various transceiver configurations. Blackfin,
2014 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2015 * external/discrete ones in various flavors (twl4030 family,
2016 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2017 */
2018 status = musb_platform_init(musb);
2019 if (status < 0)
2020 goto fail1;
2021
2022 if (!musb->isr) {
2023 status = -ENODEV;
2024 goto fail2;
2025 }
2026
2027 if (musb->ops->quirks)
2028 musb->io.quirks = musb->ops->quirks;
2029
2030 /* At least tusb6010 has it's own offsets.. */
2031 if (musb->ops->ep_offset)
2032 musb->io.ep_offset = musb->ops->ep_offset;
2033 if (musb->ops->ep_select)
2034 musb->io.ep_select = musb->ops->ep_select;
2035
2036 /* ..and some devices use indexed offset or flat offset */
2037 if (musb->io.quirks & MUSB_INDEXED_EP) {
2038 musb->io.ep_offset = musb_indexed_ep_offset;
2039 musb->io.ep_select = musb_indexed_ep_select;
2040 } else {
2041 musb->io.ep_offset = musb_flat_ep_offset;
2042 musb->io.ep_select = musb_flat_ep_select;
2043 }
2044
2045 if (musb->ops->fifo_mode)
2046 fifo_mode = musb->ops->fifo_mode;
2047 else
2048 fifo_mode = 4;
2049
2050 if (musb->ops->fifo_offset)
2051 musb->io.fifo_offset = musb->ops->fifo_offset;
2052 else
2053 musb->io.fifo_offset = musb_default_fifo_offset;
2054
2055 if (musb->ops->readb)
2056 musb_readb = musb->ops->readb;
2057 if (musb->ops->writeb)
2058 musb_writeb = musb->ops->writeb;
2059 if (musb->ops->readw)
2060 musb_readw = musb->ops->readw;
2061 if (musb->ops->writew)
2062 musb_writew = musb->ops->writew;
2063 if (musb->ops->readl)
2064 musb_readl = musb->ops->readl;
2065 if (musb->ops->writel)
2066 musb_writel = musb->ops->writel;
2067
2068 if (musb->ops->read_fifo)
2069 musb->io.read_fifo = musb->ops->read_fifo;
2070 else
2071 musb->io.read_fifo = musb_default_read_fifo;
2072
2073 if (musb->ops->write_fifo)
2074 musb->io.write_fifo = musb->ops->write_fifo;
2075 else
2076 musb->io.write_fifo = musb_default_write_fifo;
2077
2078 if (!musb->xceiv->io_ops) {
2079 musb->xceiv->io_dev = musb->controller;
2080 musb->xceiv->io_priv = musb->mregs;
2081 musb->xceiv->io_ops = &musb_ulpi_access;
2082 }
2083
2084 pm_runtime_get_sync(musb->controller);
2085
2086 if (use_dma && dev->dma_mask) {
2087 musb->dma_controller = dma_controller_create(musb, musb->mregs);
2088 if (IS_ERR(musb->dma_controller)) {
2089 status = PTR_ERR(musb->dma_controller);
2090 goto fail2_5;
2091 }
2092 }
2093
2094 /* be sure interrupts are disabled before connecting ISR */
2095 musb_platform_disable(musb);
2096 musb_generic_disable(musb);
2097
2098 /* Init IRQ workqueue before request_irq */
2099 INIT_WORK(&musb->irq_work, musb_irq_work);
2100 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
2101 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2102 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2103
2104 /* setup musb parts of the core (especially endpoints) */
2105 status = musb_core_init(plat->config->multipoint
2106 ? MUSB_CONTROLLER_MHDRC
2107 : MUSB_CONTROLLER_HDRC, musb);
2108 if (status < 0)
2109 goto fail3;
2110
2111 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2112
2113 /* attach to the IRQ */
2114 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2115 dev_err(dev, "request_irq %d failed!\n", nIrq);
2116 status = -ENODEV;
2117 goto fail3;
2118 }
2119 musb->nIrq = nIrq;
2120 /* FIXME this handles wakeup irqs wrong */
2121 if (enable_irq_wake(nIrq) == 0) {
2122 musb->irq_wake = 1;
2123 device_init_wakeup(dev, 1);
2124 } else {
2125 musb->irq_wake = 0;
2126 }
2127
2128 /* program PHY to use external vBus if required */
2129 if (plat->extvbus) {
2130 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2131 busctl |= MUSB_ULPI_USE_EXTVBUS;
2132 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2133 }
2134
2135 if (musb->xceiv->otg->default_a) {
2136 MUSB_HST_MODE(musb);
2137 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2138 } else {
2139 MUSB_DEV_MODE(musb);
2140 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2141 }
2142
2143 switch (musb->port_mode) {
2144 case MUSB_PORT_MODE_HOST:
2145 status = musb_host_setup(musb, plat->power);
2146 if (status < 0)
2147 goto fail3;
2148 status = musb_platform_set_mode(musb, MUSB_HOST);
2149 break;
2150 case MUSB_PORT_MODE_GADGET:
2151 status = musb_gadget_setup(musb);
2152 if (status < 0)
2153 goto fail3;
2154 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2155 break;
2156 case MUSB_PORT_MODE_DUAL_ROLE:
2157 status = musb_host_setup(musb, plat->power);
2158 if (status < 0)
2159 goto fail3;
2160 status = musb_gadget_setup(musb);
2161 if (status) {
2162 musb_host_cleanup(musb);
2163 goto fail3;
2164 }
2165 status = musb_platform_set_mode(musb, MUSB_OTG);
2166 break;
2167 default:
2168 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2169 break;
2170 }
2171
2172 if (status < 0)
2173 goto fail3;
2174
2175 status = musb_init_debugfs(musb);
2176 if (status < 0)
2177 goto fail4;
2178
2179 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2180 if (status)
2181 goto fail5;
2182
2183 pm_runtime_put(musb->controller);
2184
2185 return 0;
2186
2187 fail5:
2188 musb_exit_debugfs(musb);
2189
2190 fail4:
2191 musb_gadget_cleanup(musb);
2192 musb_host_cleanup(musb);
2193
2194 fail3:
2195 cancel_work_sync(&musb->irq_work);
2196 cancel_delayed_work_sync(&musb->recover_work);
2197 cancel_delayed_work_sync(&musb->finish_resume_work);
2198 cancel_delayed_work_sync(&musb->deassert_reset_work);
2199 if (musb->dma_controller)
2200 dma_controller_destroy(musb->dma_controller);
2201 fail2_5:
2202 pm_runtime_put_sync(musb->controller);
2203
2204 fail2:
2205 if (musb->irq_wake)
2206 device_init_wakeup(dev, 0);
2207 musb_platform_exit(musb);
2208
2209 fail1:
2210 pm_runtime_disable(musb->controller);
2211 dev_err(musb->controller,
2212 "musb_init_controller failed with status %d\n", status);
2213
2214 musb_free(musb);
2215
2216 fail0:
2217
2218 return status;
2219
2220 }
2221
2222 /*-------------------------------------------------------------------------*/
2223
2224 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2225 * bridge to a platform device; this driver then suffices.
2226 */
2227 static int musb_probe(struct platform_device *pdev)
2228 {
2229 struct device *dev = &pdev->dev;
2230 int irq = platform_get_irq_byname(pdev, "mc");
2231 struct resource *iomem;
2232 void __iomem *base;
2233
2234 if (irq <= 0)
2235 return -ENODEV;
2236
2237 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2238 base = devm_ioremap_resource(dev, iomem);
2239 if (IS_ERR(base))
2240 return PTR_ERR(base);
2241
2242 return musb_init_controller(dev, irq, base);
2243 }
2244
2245 static int musb_remove(struct platform_device *pdev)
2246 {
2247 struct device *dev = &pdev->dev;
2248 struct musb *musb = dev_to_musb(dev);
2249
2250 /* this gets called on rmmod.
2251 * - Host mode: host may still be active
2252 * - Peripheral mode: peripheral is deactivated (or never-activated)
2253 * - OTG mode: both roles are deactivated (or never-activated)
2254 */
2255 musb_exit_debugfs(musb);
2256 musb_shutdown(pdev);
2257
2258 if (musb->dma_controller)
2259 dma_controller_destroy(musb->dma_controller);
2260
2261 cancel_work_sync(&musb->irq_work);
2262 cancel_delayed_work_sync(&musb->recover_work);
2263 cancel_delayed_work_sync(&musb->finish_resume_work);
2264 cancel_delayed_work_sync(&musb->deassert_reset_work);
2265 musb_free(musb);
2266 device_init_wakeup(dev, 0);
2267 return 0;
2268 }
2269
2270 #ifdef CONFIG_PM
2271
2272 static void musb_save_context(struct musb *musb)
2273 {
2274 int i;
2275 void __iomem *musb_base = musb->mregs;
2276 void __iomem *epio;
2277
2278 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2279 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2280 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2281 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2282 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2283 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2284 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2285
2286 for (i = 0; i < musb->config->num_eps; ++i) {
2287 struct musb_hw_ep *hw_ep;
2288
2289 hw_ep = &musb->endpoints[i];
2290 if (!hw_ep)
2291 continue;
2292
2293 epio = hw_ep->regs;
2294 if (!epio)
2295 continue;
2296
2297 musb_writeb(musb_base, MUSB_INDEX, i);
2298 musb->context.index_regs[i].txmaxp =
2299 musb_readw(epio, MUSB_TXMAXP);
2300 musb->context.index_regs[i].txcsr =
2301 musb_readw(epio, MUSB_TXCSR);
2302 musb->context.index_regs[i].rxmaxp =
2303 musb_readw(epio, MUSB_RXMAXP);
2304 musb->context.index_regs[i].rxcsr =
2305 musb_readw(epio, MUSB_RXCSR);
2306
2307 if (musb->dyn_fifo) {
2308 musb->context.index_regs[i].txfifoadd =
2309 musb_read_txfifoadd(musb_base);
2310 musb->context.index_regs[i].rxfifoadd =
2311 musb_read_rxfifoadd(musb_base);
2312 musb->context.index_regs[i].txfifosz =
2313 musb_read_txfifosz(musb_base);
2314 musb->context.index_regs[i].rxfifosz =
2315 musb_read_rxfifosz(musb_base);
2316 }
2317
2318 musb->context.index_regs[i].txtype =
2319 musb_readb(epio, MUSB_TXTYPE);
2320 musb->context.index_regs[i].txinterval =
2321 musb_readb(epio, MUSB_TXINTERVAL);
2322 musb->context.index_regs[i].rxtype =
2323 musb_readb(epio, MUSB_RXTYPE);
2324 musb->context.index_regs[i].rxinterval =
2325 musb_readb(epio, MUSB_RXINTERVAL);
2326
2327 musb->context.index_regs[i].txfunaddr =
2328 musb_read_txfunaddr(musb_base, i);
2329 musb->context.index_regs[i].txhubaddr =
2330 musb_read_txhubaddr(musb_base, i);
2331 musb->context.index_regs[i].txhubport =
2332 musb_read_txhubport(musb_base, i);
2333
2334 musb->context.index_regs[i].rxfunaddr =
2335 musb_read_rxfunaddr(musb_base, i);
2336 musb->context.index_regs[i].rxhubaddr =
2337 musb_read_rxhubaddr(musb_base, i);
2338 musb->context.index_regs[i].rxhubport =
2339 musb_read_rxhubport(musb_base, i);
2340 }
2341 }
2342
2343 static void musb_restore_context(struct musb *musb)
2344 {
2345 int i;
2346 void __iomem *musb_base = musb->mregs;
2347 void __iomem *ep_target_regs;
2348 void __iomem *epio;
2349 u8 power;
2350
2351 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2352 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2353 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2354
2355 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2356 power = musb_readb(musb_base, MUSB_POWER);
2357 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2358 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2359 power |= musb->context.power;
2360 musb_writeb(musb_base, MUSB_POWER, power);
2361
2362 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2363 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2364 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2365 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2366
2367 for (i = 0; i < musb->config->num_eps; ++i) {
2368 struct musb_hw_ep *hw_ep;
2369
2370 hw_ep = &musb->endpoints[i];
2371 if (!hw_ep)
2372 continue;
2373
2374 epio = hw_ep->regs;
2375 if (!epio)
2376 continue;
2377
2378 musb_writeb(musb_base, MUSB_INDEX, i);
2379 musb_writew(epio, MUSB_TXMAXP,
2380 musb->context.index_regs[i].txmaxp);
2381 musb_writew(epio, MUSB_TXCSR,
2382 musb->context.index_regs[i].txcsr);
2383 musb_writew(epio, MUSB_RXMAXP,
2384 musb->context.index_regs[i].rxmaxp);
2385 musb_writew(epio, MUSB_RXCSR,
2386 musb->context.index_regs[i].rxcsr);
2387
2388 if (musb->dyn_fifo) {
2389 musb_write_txfifosz(musb_base,
2390 musb->context.index_regs[i].txfifosz);
2391 musb_write_rxfifosz(musb_base,
2392 musb->context.index_regs[i].rxfifosz);
2393 musb_write_txfifoadd(musb_base,
2394 musb->context.index_regs[i].txfifoadd);
2395 musb_write_rxfifoadd(musb_base,
2396 musb->context.index_regs[i].rxfifoadd);
2397 }
2398
2399 musb_writeb(epio, MUSB_TXTYPE,
2400 musb->context.index_regs[i].txtype);
2401 musb_writeb(epio, MUSB_TXINTERVAL,
2402 musb->context.index_regs[i].txinterval);
2403 musb_writeb(epio, MUSB_RXTYPE,
2404 musb->context.index_regs[i].rxtype);
2405 musb_writeb(epio, MUSB_RXINTERVAL,
2406
2407 musb->context.index_regs[i].rxinterval);
2408 musb_write_txfunaddr(musb_base, i,
2409 musb->context.index_regs[i].txfunaddr);
2410 musb_write_txhubaddr(musb_base, i,
2411 musb->context.index_regs[i].txhubaddr);
2412 musb_write_txhubport(musb_base, i,
2413 musb->context.index_regs[i].txhubport);
2414
2415 ep_target_regs =
2416 musb_read_target_reg_base(i, musb_base);
2417
2418 musb_write_rxfunaddr(ep_target_regs,
2419 musb->context.index_regs[i].rxfunaddr);
2420 musb_write_rxhubaddr(ep_target_regs,
2421 musb->context.index_regs[i].rxhubaddr);
2422 musb_write_rxhubport(ep_target_regs,
2423 musb->context.index_regs[i].rxhubport);
2424 }
2425 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2426 }
2427
2428 static int musb_suspend(struct device *dev)
2429 {
2430 struct musb *musb = dev_to_musb(dev);
2431 unsigned long flags;
2432
2433 spin_lock_irqsave(&musb->lock, flags);
2434
2435 if (is_peripheral_active(musb)) {
2436 /* FIXME force disconnect unless we know USB will wake
2437 * the system up quickly enough to respond ...
2438 */
2439 } else if (is_host_active(musb)) {
2440 /* we know all the children are suspended; sometimes
2441 * they will even be wakeup-enabled.
2442 */
2443 }
2444
2445 musb_save_context(musb);
2446
2447 spin_unlock_irqrestore(&musb->lock, flags);
2448 return 0;
2449 }
2450
2451 static int musb_resume(struct device *dev)
2452 {
2453 struct musb *musb = dev_to_musb(dev);
2454 u8 devctl;
2455 u8 mask;
2456
2457 /*
2458 * For static cmos like DaVinci, register values were preserved
2459 * unless for some reason the whole soc powered down or the USB
2460 * module got reset through the PSC (vs just being disabled).
2461 *
2462 * For the DSPS glue layer though, a full register restore has to
2463 * be done. As it shouldn't harm other platforms, we do it
2464 * unconditionally.
2465 */
2466
2467 musb_restore_context(musb);
2468
2469 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2470 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2471 if ((devctl & mask) != (musb->context.devctl & mask))
2472 musb->port1_status = 0;
2473 if (musb->need_finish_resume) {
2474 musb->need_finish_resume = 0;
2475 schedule_delayed_work(&musb->finish_resume_work,
2476 msecs_to_jiffies(20));
2477 }
2478
2479 /*
2480 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2481 * out of suspend
2482 */
2483 pm_runtime_disable(dev);
2484 pm_runtime_set_active(dev);
2485 pm_runtime_enable(dev);
2486 return 0;
2487 }
2488
2489 static int musb_runtime_suspend(struct device *dev)
2490 {
2491 struct musb *musb = dev_to_musb(dev);
2492
2493 musb_save_context(musb);
2494
2495 return 0;
2496 }
2497
2498 static int musb_runtime_resume(struct device *dev)
2499 {
2500 struct musb *musb = dev_to_musb(dev);
2501 static int first = 1;
2502
2503 /*
2504 * When pm_runtime_get_sync called for the first time in driver
2505 * init, some of the structure is still not initialized which is
2506 * used in restore function. But clock needs to be
2507 * enabled before any register access, so
2508 * pm_runtime_get_sync has to be called.
2509 * Also context restore without save does not make
2510 * any sense
2511 */
2512 if (!first)
2513 musb_restore_context(musb);
2514 first = 0;
2515
2516 if (musb->need_finish_resume) {
2517 musb->need_finish_resume = 0;
2518 schedule_delayed_work(&musb->finish_resume_work,
2519 msecs_to_jiffies(20));
2520 }
2521
2522 return 0;
2523 }
2524
2525 static const struct dev_pm_ops musb_dev_pm_ops = {
2526 .suspend = musb_suspend,
2527 .resume = musb_resume,
2528 .runtime_suspend = musb_runtime_suspend,
2529 .runtime_resume = musb_runtime_resume,
2530 };
2531
2532 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2533 #else
2534 #define MUSB_DEV_PM_OPS NULL
2535 #endif
2536
2537 static struct platform_driver musb_driver = {
2538 .driver = {
2539 .name = (char *)musb_driver_name,
2540 .bus = &platform_bus_type,
2541 .pm = MUSB_DEV_PM_OPS,
2542 },
2543 .probe = musb_probe,
2544 .remove = musb_remove,
2545 .shutdown = musb_shutdown,
2546 };
2547
2548 module_platform_driver(musb_driver);
Linux kernel - Deliverables
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