2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
48 #include "musb_core.h"
51 /* MUSB PERIPHERAL status 3-mar-2006:
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
81 * - ISO not tested ... might work, but only weakly isochronous
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
93 /* ----------------------------------------------------------------------- */
96 * Immediately complete a request.
98 * @param request the request to complete
99 * @param status the status to complete the request with
100 * Context: controller locked, IRQs blocked.
102 void musb_g_giveback(
104 struct usb_request
*request
,
106 __releases(ep
->musb
->lock
)
107 __acquires(ep
->musb
->lock
)
109 struct musb_request
*req
;
113 req
= to_musb_request(request
);
115 list_del(&request
->list
);
116 if (req
->request
.status
== -EINPROGRESS
)
117 req
->request
.status
= status
;
121 spin_unlock(&musb
->lock
);
122 if (is_dma_capable()) {
124 dma_unmap_single(musb
->controller
,
130 req
->request
.dma
= DMA_ADDR_INVALID
;
132 } else if (req
->request
.dma
!= DMA_ADDR_INVALID
)
133 dma_sync_single_for_cpu(musb
->controller
,
140 if (request
->status
== 0)
141 DBG(5, "%s done request %p, %d/%d\n",
142 ep
->end_point
.name
, request
,
143 req
->request
.actual
, req
->request
.length
);
145 DBG(2, "%s request %p, %d/%d fault %d\n",
146 ep
->end_point
.name
, request
,
147 req
->request
.actual
, req
->request
.length
,
149 req
->request
.complete(&req
->ep
->end_point
, &req
->request
);
150 spin_lock(&musb
->lock
);
154 /* ----------------------------------------------------------------------- */
157 * Abort requests queued to an endpoint using the status. Synchronous.
158 * caller locked controller and blocked irqs, and selected this ep.
160 static void nuke(struct musb_ep
*ep
, const int status
)
162 struct musb_request
*req
= NULL
;
163 void __iomem
*epio
= ep
->musb
->endpoints
[ep
->current_epnum
].regs
;
167 if (is_dma_capable() && ep
->dma
) {
168 struct dma_controller
*c
= ep
->musb
->dma_controller
;
173 * The programming guide says that we must not clear
174 * the DMAMODE bit before DMAENAB, so we only
175 * clear it in the second write...
177 musb_writew(epio
, MUSB_TXCSR
,
178 MUSB_TXCSR_DMAMODE
| MUSB_TXCSR_FLUSHFIFO
);
179 musb_writew(epio
, MUSB_TXCSR
,
180 0 | MUSB_TXCSR_FLUSHFIFO
);
182 musb_writew(epio
, MUSB_RXCSR
,
183 0 | MUSB_RXCSR_FLUSHFIFO
);
184 musb_writew(epio
, MUSB_RXCSR
,
185 0 | MUSB_RXCSR_FLUSHFIFO
);
188 value
= c
->channel_abort(ep
->dma
);
189 DBG(value
? 1 : 6, "%s: abort DMA --> %d\n", ep
->name
, value
);
190 c
->channel_release(ep
->dma
);
194 while (!list_empty(&(ep
->req_list
))) {
195 req
= container_of(ep
->req_list
.next
, struct musb_request
,
197 musb_g_giveback(ep
, &req
->request
, status
);
201 /* ----------------------------------------------------------------------- */
203 /* Data transfers - pure PIO, pure DMA, or mixed mode */
206 * This assumes the separate CPPI engine is responding to DMA requests
207 * from the usb core ... sequenced a bit differently from mentor dma.
210 static inline int max_ep_writesize(struct musb
*musb
, struct musb_ep
*ep
)
212 if (can_bulk_split(musb
, ep
->type
))
213 return ep
->hw_ep
->max_packet_sz_tx
;
215 return ep
->packet_sz
;
219 #ifdef CONFIG_USB_INVENTRA_DMA
221 /* Peripheral tx (IN) using Mentor DMA works as follows:
222 Only mode 0 is used for transfers <= wPktSize,
223 mode 1 is used for larger transfers,
225 One of the following happens:
226 - Host sends IN token which causes an endpoint interrupt
228 -> if DMA is currently busy, exit.
229 -> if queue is non-empty, txstate().
231 - Request is queued by the gadget driver.
232 -> if queue was previously empty, txstate()
237 | (data is transferred to the FIFO, then sent out when
238 | IN token(s) are recd from Host.
239 | -> DMA interrupt on completion
241 | -> stop DMA, ~DMAENAB,
242 | -> set TxPktRdy for last short pkt or zlp
243 | -> Complete Request
244 | -> Continue next request (call txstate)
245 |___________________________________|
247 * Non-Mentor DMA engines can of course work differently, such as by
248 * upleveling from irq-per-packet to irq-per-buffer.
254 * An endpoint is transmitting data. This can be called either from
255 * the IRQ routine or from ep.queue() to kickstart a request on an
258 * Context: controller locked, IRQs blocked, endpoint selected
260 static void txstate(struct musb
*musb
, struct musb_request
*req
)
262 u8 epnum
= req
->epnum
;
263 struct musb_ep
*musb_ep
;
264 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
265 struct usb_request
*request
;
266 u16 fifo_count
= 0, csr
;
271 /* we shouldn't get here while DMA is active ... but we do ... */
272 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
273 DBG(4, "dma pending...\n");
277 /* read TXCSR before */
278 csr
= musb_readw(epio
, MUSB_TXCSR
);
280 request
= &req
->request
;
281 fifo_count
= min(max_ep_writesize(musb
, musb_ep
),
282 (int)(request
->length
- request
->actual
));
284 if (csr
& MUSB_TXCSR_TXPKTRDY
) {
285 DBG(5, "%s old packet still ready , txcsr %03x\n",
286 musb_ep
->end_point
.name
, csr
);
290 if (csr
& MUSB_TXCSR_P_SENDSTALL
) {
291 DBG(5, "%s stalling, txcsr %03x\n",
292 musb_ep
->end_point
.name
, csr
);
296 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
297 epnum
, musb_ep
->packet_sz
, fifo_count
,
300 #ifndef CONFIG_MUSB_PIO_ONLY
301 if (is_dma_capable() && musb_ep
->dma
) {
302 struct dma_controller
*c
= musb
->dma_controller
;
304 use_dma
= (request
->dma
!= DMA_ADDR_INVALID
);
306 /* MUSB_TXCSR_P_ISO is still set correctly */
308 #ifdef CONFIG_USB_INVENTRA_DMA
312 /* setup DMA, then program endpoint CSR */
313 request_size
= min_t(size_t, request
->length
,
314 musb_ep
->dma
->max_len
);
315 if (request_size
< musb_ep
->packet_sz
)
316 musb_ep
->dma
->desired_mode
= 0;
318 musb_ep
->dma
->desired_mode
= 1;
320 use_dma
= use_dma
&& c
->channel_program(
321 musb_ep
->dma
, musb_ep
->packet_sz
,
322 musb_ep
->dma
->desired_mode
,
323 request
->dma
+ request
->actual
, request_size
);
325 if (musb_ep
->dma
->desired_mode
== 0) {
327 * We must not clear the DMAMODE bit
328 * before the DMAENAB bit -- and the
329 * latter doesn't always get cleared
330 * before we get here...
332 csr
&= ~(MUSB_TXCSR_AUTOSET
333 | MUSB_TXCSR_DMAENAB
);
334 musb_writew(epio
, MUSB_TXCSR
, csr
335 | MUSB_TXCSR_P_WZC_BITS
);
336 csr
&= ~MUSB_TXCSR_DMAMODE
;
337 csr
|= (MUSB_TXCSR_DMAENAB
|
339 /* against programming guide */
341 csr
|= (MUSB_TXCSR_AUTOSET
346 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
347 musb_writew(epio
, MUSB_TXCSR
, csr
);
351 #elif defined(CONFIG_USB_TI_CPPI_DMA)
352 /* program endpoint CSR first, then setup DMA */
353 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
354 csr
|= MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_DMAMODE
|
356 musb_writew(epio
, MUSB_TXCSR
,
357 (MUSB_TXCSR_P_WZC_BITS
& ~MUSB_TXCSR_P_UNDERRUN
)
360 /* ensure writebuffer is empty */
361 csr
= musb_readw(epio
, MUSB_TXCSR
);
363 /* NOTE host side sets DMAENAB later than this; both are
364 * OK since the transfer dma glue (between CPPI and Mentor
365 * fifos) just tells CPPI it could start. Data only moves
366 * to the USB TX fifo when both fifos are ready.
369 /* "mode" is irrelevant here; handle terminating ZLPs like
370 * PIO does, since the hardware RNDIS mode seems unreliable
371 * except for the last-packet-is-already-short case.
373 use_dma
= use_dma
&& c
->channel_program(
374 musb_ep
->dma
, musb_ep
->packet_sz
,
379 c
->channel_release(musb_ep
->dma
);
381 csr
&= ~MUSB_TXCSR_DMAENAB
;
382 musb_writew(epio
, MUSB_TXCSR
, csr
);
383 /* invariant: prequest->buf is non-null */
385 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
386 use_dma
= use_dma
&& c
->channel_program(
387 musb_ep
->dma
, musb_ep
->packet_sz
,
396 musb_write_fifo(musb_ep
->hw_ep
, fifo_count
,
397 (u8
*) (request
->buf
+ request
->actual
));
398 request
->actual
+= fifo_count
;
399 csr
|= MUSB_TXCSR_TXPKTRDY
;
400 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
401 musb_writew(epio
, MUSB_TXCSR
, csr
);
404 /* host may already have the data when this message shows... */
405 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
406 musb_ep
->end_point
.name
, use_dma
? "dma" : "pio",
407 request
->actual
, request
->length
,
408 musb_readw(epio
, MUSB_TXCSR
),
410 musb_readw(epio
, MUSB_TXMAXP
));
414 * FIFO state update (e.g. data ready).
415 * Called from IRQ, with controller locked.
417 void musb_g_tx(struct musb
*musb
, u8 epnum
)
420 struct usb_request
*request
;
421 u8 __iomem
*mbase
= musb
->mregs
;
422 struct musb_ep
*musb_ep
= &musb
->endpoints
[epnum
].ep_in
;
423 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
424 struct dma_channel
*dma
;
426 musb_ep_select(mbase
, epnum
);
427 request
= next_request(musb_ep
);
429 csr
= musb_readw(epio
, MUSB_TXCSR
);
430 DBG(4, "<== %s, txcsr %04x\n", musb_ep
->end_point
.name
, csr
);
432 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
435 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
436 * probably rates reporting as a host error.
438 if (csr
& MUSB_TXCSR_P_SENTSTALL
) {
439 csr
|= MUSB_TXCSR_P_WZC_BITS
;
440 csr
&= ~MUSB_TXCSR_P_SENTSTALL
;
441 musb_writew(epio
, MUSB_TXCSR
, csr
);
445 if (csr
& MUSB_TXCSR_P_UNDERRUN
) {
446 /* We NAKed, no big deal... little reason to care. */
447 csr
|= MUSB_TXCSR_P_WZC_BITS
;
448 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
449 musb_writew(epio
, MUSB_TXCSR
, csr
);
450 DBG(20, "underrun on ep%d, req %p\n", epnum
, request
);
453 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
455 * SHOULD NOT HAPPEN... has with CPPI though, after
456 * changing SENDSTALL (and other cases); harmless?
458 DBG(5, "%s dma still busy?\n", musb_ep
->end_point
.name
);
465 if (dma
&& (csr
& MUSB_TXCSR_DMAENAB
)) {
467 csr
|= MUSB_TXCSR_P_WZC_BITS
;
468 csr
&= ~(MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_P_UNDERRUN
|
469 MUSB_TXCSR_TXPKTRDY
);
470 musb_writew(epio
, MUSB_TXCSR
, csr
);
471 /* Ensure writebuffer is empty. */
472 csr
= musb_readw(epio
, MUSB_TXCSR
);
473 request
->actual
+= musb_ep
->dma
->actual_len
;
474 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
475 epnum
, csr
, musb_ep
->dma
->actual_len
, request
);
478 if (is_dma
|| request
->actual
== request
->length
) {
480 * First, maybe a terminating short packet. Some DMA
481 * engines might handle this by themselves.
483 if ((request
->zero
&& request
->length
484 && request
->length
% musb_ep
->packet_sz
== 0)
485 #ifdef CONFIG_USB_INVENTRA_DMA
486 || (is_dma
&& (!dma
->desired_mode
||
488 (musb_ep
->packet_sz
- 1))))
492 * On DMA completion, FIFO may not be
495 if (csr
& MUSB_TXCSR_TXPKTRDY
)
498 DBG(4, "sending zero pkt\n");
499 musb_writew(epio
, MUSB_TXCSR
, MUSB_TXCSR_MODE
500 | MUSB_TXCSR_TXPKTRDY
);
504 /* ... or if not, then complete it. */
505 musb_g_giveback(musb_ep
, request
, 0);
507 request
= musb_ep
->desc
? next_request(musb_ep
) : NULL
;
509 DBG(4, "%s idle now\n",
510 musb_ep
->end_point
.name
);
515 txstate(musb
, to_musb_request(request
));
519 /* ------------------------------------------------------------ */
521 #ifdef CONFIG_USB_INVENTRA_DMA
523 /* Peripheral rx (OUT) using Mentor DMA works as follows:
524 - Only mode 0 is used.
526 - Request is queued by the gadget class driver.
527 -> if queue was previously empty, rxstate()
529 - Host sends OUT token which causes an endpoint interrupt
531 | -> if request queued, call rxstate
533 | | -> DMA interrupt on completion
537 | | -> if data recd = max expected
538 | | by the request, or host
539 | | sent a short packet,
540 | | complete the request,
541 | | and start the next one.
542 | |_____________________________________|
543 | else just wait for the host
544 | to send the next OUT token.
545 |__________________________________________________|
547 * Non-Mentor DMA engines can of course work differently.
553 * Context: controller locked, IRQs blocked, endpoint selected
555 static void rxstate(struct musb
*musb
, struct musb_request
*req
)
557 const u8 epnum
= req
->epnum
;
558 struct usb_request
*request
= &req
->request
;
559 struct musb_ep
*musb_ep
;
560 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
561 unsigned fifo_count
= 0;
563 u16 csr
= musb_readw(epio
, MUSB_RXCSR
);
564 struct musb_hw_ep
*hw_ep
= &musb
->endpoints
[epnum
];
566 if (hw_ep
->is_shared_fifo
)
567 musb_ep
= &hw_ep
->ep_in
;
569 musb_ep
= &hw_ep
->ep_out
;
571 len
= musb_ep
->packet_sz
;
573 /* We shouldn't get here while DMA is active, but we do... */
574 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
575 DBG(4, "DMA pending...\n");
579 if (csr
& MUSB_RXCSR_P_SENDSTALL
) {
580 DBG(5, "%s stalling, RXCSR %04x\n",
581 musb_ep
->end_point
.name
, csr
);
585 if (is_cppi_enabled() && musb_ep
->dma
) {
586 struct dma_controller
*c
= musb
->dma_controller
;
587 struct dma_channel
*channel
= musb_ep
->dma
;
589 /* NOTE: CPPI won't actually stop advancing the DMA
590 * queue after short packet transfers, so this is almost
591 * always going to run as IRQ-per-packet DMA so that
592 * faults will be handled correctly.
594 if (c
->channel_program(channel
,
596 !request
->short_not_ok
,
597 request
->dma
+ request
->actual
,
598 request
->length
- request
->actual
)) {
600 /* make sure that if an rxpkt arrived after the irq,
601 * the cppi engine will be ready to take it as soon
604 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
605 | MUSB_RXCSR_DMAMODE
);
606 csr
|= MUSB_RXCSR_DMAENAB
| MUSB_RXCSR_P_WZC_BITS
;
607 musb_writew(epio
, MUSB_RXCSR
, csr
);
612 if (csr
& MUSB_RXCSR_RXPKTRDY
) {
613 len
= musb_readw(epio
, MUSB_RXCOUNT
);
614 if (request
->actual
< request
->length
) {
615 #ifdef CONFIG_USB_INVENTRA_DMA
616 if (is_dma_capable() && musb_ep
->dma
) {
617 struct dma_controller
*c
;
618 struct dma_channel
*channel
;
621 c
= musb
->dma_controller
;
622 channel
= musb_ep
->dma
;
624 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
625 * mode 0 only. So we do not get endpoint interrupts due to DMA
626 * completion. We only get interrupts from DMA controller.
628 * We could operate in DMA mode 1 if we knew the size of the tranfer
629 * in advance. For mass storage class, request->length = what the host
630 * sends, so that'd work. But for pretty much everything else,
631 * request->length is routinely more than what the host sends. For
632 * most these gadgets, end of is signified either by a short packet,
633 * or filling the last byte of the buffer. (Sending extra data in
634 * that last pckate should trigger an overflow fault.) But in mode 1,
635 * we don't get DMA completion interrrupt for short packets.
637 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
638 * to get endpoint interrupt on every DMA req, but that didn't seem
641 * REVISIT an updated g_file_storage can set req->short_not_ok, which
642 * then becomes usable as a runtime "use mode 1" hint...
645 csr
|= MUSB_RXCSR_DMAENAB
;
646 csr
|= MUSB_RXCSR_AUTOCLEAR
;
648 /* csr |= MUSB_RXCSR_DMAMODE; */
650 /* this special sequence (enabling and then
651 * disabling MUSB_RXCSR_DMAMODE) is required
652 * to get DMAReq to activate
654 musb_writew(epio
, MUSB_RXCSR
,
655 csr
| MUSB_RXCSR_DMAMODE
);
657 musb_writew(epio
, MUSB_RXCSR
, csr
);
659 if (request
->actual
< request
->length
) {
660 int transfer_size
= 0;
662 transfer_size
= min(request
->length
,
667 if (transfer_size
<= musb_ep
->packet_sz
)
668 musb_ep
->dma
->desired_mode
= 0;
670 musb_ep
->dma
->desired_mode
= 1;
672 use_dma
= c
->channel_program(
675 channel
->desired_mode
,
684 #endif /* Mentor's DMA */
686 fifo_count
= request
->length
- request
->actual
;
687 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
688 musb_ep
->end_point
.name
,
692 fifo_count
= min_t(unsigned, len
, fifo_count
);
694 #ifdef CONFIG_USB_TUSB_OMAP_DMA
695 if (tusb_dma_omap() && musb_ep
->dma
) {
696 struct dma_controller
*c
= musb
->dma_controller
;
697 struct dma_channel
*channel
= musb_ep
->dma
;
698 u32 dma_addr
= request
->dma
+ request
->actual
;
701 ret
= c
->channel_program(channel
,
703 channel
->desired_mode
,
711 musb_read_fifo(musb_ep
->hw_ep
, fifo_count
, (u8
*)
712 (request
->buf
+ request
->actual
));
713 request
->actual
+= fifo_count
;
715 /* REVISIT if we left anything in the fifo, flush
716 * it and report -EOVERFLOW
720 csr
|= MUSB_RXCSR_P_WZC_BITS
;
721 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
722 musb_writew(epio
, MUSB_RXCSR
, csr
);
726 /* reach the end or short packet detected */
727 if (request
->actual
== request
->length
|| len
< musb_ep
->packet_sz
)
728 musb_g_giveback(musb_ep
, request
, 0);
732 * Data ready for a request; called from IRQ
734 void musb_g_rx(struct musb
*musb
, u8 epnum
)
737 struct usb_request
*request
;
738 void __iomem
*mbase
= musb
->mregs
;
739 struct musb_ep
*musb_ep
;
740 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
741 struct dma_channel
*dma
;
742 struct musb_hw_ep
*hw_ep
= &musb
->endpoints
[epnum
];
744 if (hw_ep
->is_shared_fifo
)
745 musb_ep
= &hw_ep
->ep_in
;
747 musb_ep
= &hw_ep
->ep_out
;
749 musb_ep_select(mbase
, epnum
);
751 request
= next_request(musb_ep
);
755 csr
= musb_readw(epio
, MUSB_RXCSR
);
756 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
758 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep
->end_point
.name
,
759 csr
, dma
? " (dma)" : "", request
);
761 if (csr
& MUSB_RXCSR_P_SENTSTALL
) {
762 csr
|= MUSB_RXCSR_P_WZC_BITS
;
763 csr
&= ~MUSB_RXCSR_P_SENTSTALL
;
764 musb_writew(epio
, MUSB_RXCSR
, csr
);
768 if (csr
& MUSB_RXCSR_P_OVERRUN
) {
769 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
770 csr
&= ~MUSB_RXCSR_P_OVERRUN
;
771 musb_writew(epio
, MUSB_RXCSR
, csr
);
773 DBG(3, "%s iso overrun on %p\n", musb_ep
->name
, request
);
774 if (request
&& request
->status
== -EINPROGRESS
)
775 request
->status
= -EOVERFLOW
;
777 if (csr
& MUSB_RXCSR_INCOMPRX
) {
778 /* REVISIT not necessarily an error */
779 DBG(4, "%s, incomprx\n", musb_ep
->end_point
.name
);
782 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
783 /* "should not happen"; likely RXPKTRDY pending for DMA */
784 DBG((csr
& MUSB_RXCSR_DMAENAB
) ? 4 : 1,
785 "%s busy, csr %04x\n",
786 musb_ep
->end_point
.name
, csr
);
790 if (dma
&& (csr
& MUSB_RXCSR_DMAENAB
)) {
791 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
793 | MUSB_RXCSR_DMAMODE
);
794 musb_writew(epio
, MUSB_RXCSR
,
795 MUSB_RXCSR_P_WZC_BITS
| csr
);
797 request
->actual
+= musb_ep
->dma
->actual_len
;
799 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
801 musb_readw(epio
, MUSB_RXCSR
),
802 musb_ep
->dma
->actual_len
, request
);
804 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
805 /* Autoclear doesn't clear RxPktRdy for short packets */
806 if ((dma
->desired_mode
== 0)
808 & (musb_ep
->packet_sz
- 1))) {
810 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
811 musb_writew(epio
, MUSB_RXCSR
, csr
);
814 /* incomplete, and not short? wait for next IN packet */
815 if ((request
->actual
< request
->length
)
816 && (musb_ep
->dma
->actual_len
817 == musb_ep
->packet_sz
))
820 musb_g_giveback(musb_ep
, request
, 0);
822 request
= next_request(musb_ep
);
827 /* analyze request if the ep is hot */
829 rxstate(musb
, to_musb_request(request
));
831 DBG(3, "packet waiting for %s%s request\n",
832 musb_ep
->desc
? "" : "inactive ",
833 musb_ep
->end_point
.name
);
837 /* ------------------------------------------------------------ */
839 static int musb_gadget_enable(struct usb_ep
*ep
,
840 const struct usb_endpoint_descriptor
*desc
)
843 struct musb_ep
*musb_ep
;
844 struct musb_hw_ep
*hw_ep
;
851 int status
= -EINVAL
;
856 musb_ep
= to_musb_ep(ep
);
857 hw_ep
= musb_ep
->hw_ep
;
859 musb
= musb_ep
->musb
;
861 epnum
= musb_ep
->current_epnum
;
863 spin_lock_irqsave(&musb
->lock
, flags
);
869 musb_ep
->type
= usb_endpoint_type(desc
);
871 /* check direction and (later) maxpacket size against endpoint */
872 if (usb_endpoint_num(desc
) != epnum
)
875 /* REVISIT this rules out high bandwidth periodic transfers */
876 tmp
= le16_to_cpu(desc
->wMaxPacketSize
);
879 musb_ep
->packet_sz
= tmp
;
881 /* enable the interrupts for the endpoint, set the endpoint
882 * packet size (or fail), set the mode, clear the fifo
884 musb_ep_select(mbase
, epnum
);
885 if (usb_endpoint_dir_in(desc
)) {
886 u16 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
888 if (hw_ep
->is_shared_fifo
)
892 if (tmp
> hw_ep
->max_packet_sz_tx
)
895 int_txe
|= (1 << epnum
);
896 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
898 /* REVISIT if can_bulk_split(), use by updating "tmp";
899 * likewise high bandwidth periodic tx
901 /* Set TXMAXP with the FIFO size of the endpoint
902 * to disable double buffering mode. Currently, It seems that double
903 * buffering has problem if musb RTL revision number < 2.0.
905 if (musb
->hwvers
< MUSB_HWVERS_2000
)
906 musb_writew(regs
, MUSB_TXMAXP
, hw_ep
->max_packet_sz_tx
);
908 musb_writew(regs
, MUSB_TXMAXP
, tmp
);
910 csr
= MUSB_TXCSR_MODE
| MUSB_TXCSR_CLRDATATOG
;
911 if (musb_readw(regs
, MUSB_TXCSR
)
912 & MUSB_TXCSR_FIFONOTEMPTY
)
913 csr
|= MUSB_TXCSR_FLUSHFIFO
;
914 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
915 csr
|= MUSB_TXCSR_P_ISO
;
917 /* set twice in case of double buffering */
918 musb_writew(regs
, MUSB_TXCSR
, csr
);
919 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
920 musb_writew(regs
, MUSB_TXCSR
, csr
);
923 u16 int_rxe
= musb_readw(mbase
, MUSB_INTRRXE
);
925 if (hw_ep
->is_shared_fifo
)
929 if (tmp
> hw_ep
->max_packet_sz_rx
)
932 int_rxe
|= (1 << epnum
);
933 musb_writew(mbase
, MUSB_INTRRXE
, int_rxe
);
935 /* REVISIT if can_bulk_combine() use by updating "tmp"
936 * likewise high bandwidth periodic rx
938 /* Set RXMAXP with the FIFO size of the endpoint
939 * to disable double buffering mode.
941 if (musb
->hwvers
< MUSB_HWVERS_2000
)
942 musb_writew(regs
, MUSB_RXMAXP
, hw_ep
->max_packet_sz_rx
);
944 musb_writew(regs
, MUSB_RXMAXP
, tmp
);
946 /* force shared fifo to OUT-only mode */
947 if (hw_ep
->is_shared_fifo
) {
948 csr
= musb_readw(regs
, MUSB_TXCSR
);
949 csr
&= ~(MUSB_TXCSR_MODE
| MUSB_TXCSR_TXPKTRDY
);
950 musb_writew(regs
, MUSB_TXCSR
, csr
);
953 csr
= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_CLRDATATOG
;
954 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
955 csr
|= MUSB_RXCSR_P_ISO
;
956 else if (musb_ep
->type
== USB_ENDPOINT_XFER_INT
)
957 csr
|= MUSB_RXCSR_DISNYET
;
959 /* set twice in case of double buffering */
960 musb_writew(regs
, MUSB_RXCSR
, csr
);
961 musb_writew(regs
, MUSB_RXCSR
, csr
);
964 /* NOTE: all the I/O code _should_ work fine without DMA, in case
965 * for some reason you run out of channels here.
967 if (is_dma_capable() && musb
->dma_controller
) {
968 struct dma_controller
*c
= musb
->dma_controller
;
970 musb_ep
->dma
= c
->channel_alloc(c
, hw_ep
,
971 (desc
->bEndpointAddress
& USB_DIR_IN
));
975 musb_ep
->desc
= desc
;
980 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
981 musb_driver_name
, musb_ep
->end_point
.name
,
982 ({ char *s
; switch (musb_ep
->type
) {
983 case USB_ENDPOINT_XFER_BULK
: s
= "bulk"; break;
984 case USB_ENDPOINT_XFER_INT
: s
= "int"; break;
985 default: s
= "iso"; break;
987 musb_ep
->is_in
? "IN" : "OUT",
988 musb_ep
->dma
? "dma, " : "",
991 schedule_work(&musb
->irq_work
);
994 spin_unlock_irqrestore(&musb
->lock
, flags
);
999 * Disable an endpoint flushing all requests queued.
1001 static int musb_gadget_disable(struct usb_ep
*ep
)
1003 unsigned long flags
;
1006 struct musb_ep
*musb_ep
;
1010 musb_ep
= to_musb_ep(ep
);
1011 musb
= musb_ep
->musb
;
1012 epnum
= musb_ep
->current_epnum
;
1013 epio
= musb
->endpoints
[epnum
].regs
;
1015 spin_lock_irqsave(&musb
->lock
, flags
);
1016 musb_ep_select(musb
->mregs
, epnum
);
1018 /* zero the endpoint sizes */
1019 if (musb_ep
->is_in
) {
1020 u16 int_txe
= musb_readw(musb
->mregs
, MUSB_INTRTXE
);
1021 int_txe
&= ~(1 << epnum
);
1022 musb_writew(musb
->mregs
, MUSB_INTRTXE
, int_txe
);
1023 musb_writew(epio
, MUSB_TXMAXP
, 0);
1025 u16 int_rxe
= musb_readw(musb
->mregs
, MUSB_INTRRXE
);
1026 int_rxe
&= ~(1 << epnum
);
1027 musb_writew(musb
->mregs
, MUSB_INTRRXE
, int_rxe
);
1028 musb_writew(epio
, MUSB_RXMAXP
, 0);
1031 musb_ep
->desc
= NULL
;
1033 /* abort all pending DMA and requests */
1034 nuke(musb_ep
, -ESHUTDOWN
);
1036 schedule_work(&musb
->irq_work
);
1038 spin_unlock_irqrestore(&(musb
->lock
), flags
);
1040 DBG(2, "%s\n", musb_ep
->end_point
.name
);
1046 * Allocate a request for an endpoint.
1047 * Reused by ep0 code.
1049 struct usb_request
*musb_alloc_request(struct usb_ep
*ep
, gfp_t gfp_flags
)
1051 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1052 struct musb_request
*request
= NULL
;
1054 request
= kzalloc(sizeof *request
, gfp_flags
);
1056 INIT_LIST_HEAD(&request
->request
.list
);
1057 request
->request
.dma
= DMA_ADDR_INVALID
;
1058 request
->epnum
= musb_ep
->current_epnum
;
1059 request
->ep
= musb_ep
;
1062 return &request
->request
;
1067 * Reused by ep0 code.
1069 void musb_free_request(struct usb_ep
*ep
, struct usb_request
*req
)
1071 kfree(to_musb_request(req
));
1074 static LIST_HEAD(buffers
);
1076 struct free_record
{
1077 struct list_head list
;
1084 * Context: controller locked, IRQs blocked.
1086 static void musb_ep_restart(struct musb
*musb
, struct musb_request
*req
)
1088 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1089 req
->tx
? "TX/IN" : "RX/OUT",
1090 &req
->request
, req
->request
.length
, req
->epnum
);
1092 musb_ep_select(musb
->mregs
, req
->epnum
);
1099 static int musb_gadget_queue(struct usb_ep
*ep
, struct usb_request
*req
,
1102 struct musb_ep
*musb_ep
;
1103 struct musb_request
*request
;
1106 unsigned long lockflags
;
1113 musb_ep
= to_musb_ep(ep
);
1114 musb
= musb_ep
->musb
;
1116 request
= to_musb_request(req
);
1117 request
->musb
= musb
;
1119 if (request
->ep
!= musb_ep
)
1122 DBG(4, "<== to %s request=%p\n", ep
->name
, req
);
1124 /* request is mine now... */
1125 request
->request
.actual
= 0;
1126 request
->request
.status
= -EINPROGRESS
;
1127 request
->epnum
= musb_ep
->current_epnum
;
1128 request
->tx
= musb_ep
->is_in
;
1130 if (is_dma_capable() && musb_ep
->dma
) {
1131 if (request
->request
.dma
== DMA_ADDR_INVALID
) {
1132 request
->request
.dma
= dma_map_single(
1134 request
->request
.buf
,
1135 request
->request
.length
,
1139 request
->mapped
= 1;
1141 dma_sync_single_for_device(musb
->controller
,
1142 request
->request
.dma
,
1143 request
->request
.length
,
1147 request
->mapped
= 0;
1149 } else if (!req
->buf
) {
1152 request
->mapped
= 0;
1154 spin_lock_irqsave(&musb
->lock
, lockflags
);
1156 /* don't queue if the ep is down */
1157 if (!musb_ep
->desc
) {
1158 DBG(4, "req %p queued to %s while ep %s\n",
1159 req
, ep
->name
, "disabled");
1160 status
= -ESHUTDOWN
;
1164 /* add request to the list */
1165 list_add_tail(&(request
->request
.list
), &(musb_ep
->req_list
));
1167 /* it this is the head of the queue, start i/o ... */
1168 if (!musb_ep
->busy
&& &request
->request
.list
== musb_ep
->req_list
.next
)
1169 musb_ep_restart(musb
, request
);
1172 spin_unlock_irqrestore(&musb
->lock
, lockflags
);
1176 static int musb_gadget_dequeue(struct usb_ep
*ep
, struct usb_request
*request
)
1178 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1179 struct usb_request
*r
;
1180 unsigned long flags
;
1182 struct musb
*musb
= musb_ep
->musb
;
1184 if (!ep
|| !request
|| to_musb_request(request
)->ep
!= musb_ep
)
1187 spin_lock_irqsave(&musb
->lock
, flags
);
1189 list_for_each_entry(r
, &musb_ep
->req_list
, list
) {
1194 DBG(3, "request %p not queued to %s\n", request
, ep
->name
);
1199 /* if the hardware doesn't have the request, easy ... */
1200 if (musb_ep
->req_list
.next
!= &request
->list
|| musb_ep
->busy
)
1201 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1203 /* ... else abort the dma transfer ... */
1204 else if (is_dma_capable() && musb_ep
->dma
) {
1205 struct dma_controller
*c
= musb
->dma_controller
;
1207 musb_ep_select(musb
->mregs
, musb_ep
->current_epnum
);
1208 if (c
->channel_abort
)
1209 status
= c
->channel_abort(musb_ep
->dma
);
1213 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1215 /* NOTE: by sticking to easily tested hardware/driver states,
1216 * we leave counting of in-flight packets imprecise.
1218 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1222 spin_unlock_irqrestore(&musb
->lock
, flags
);
1227 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1228 * data but will queue requests.
1230 * exported to ep0 code
1232 static int musb_gadget_set_halt(struct usb_ep
*ep
, int value
)
1234 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1235 u8 epnum
= musb_ep
->current_epnum
;
1236 struct musb
*musb
= musb_ep
->musb
;
1237 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1238 void __iomem
*mbase
;
1239 unsigned long flags
;
1241 struct musb_request
*request
;
1246 mbase
= musb
->mregs
;
1248 spin_lock_irqsave(&musb
->lock
, flags
);
1250 if ((USB_ENDPOINT_XFER_ISOC
== musb_ep
->type
)) {
1255 musb_ep_select(mbase
, epnum
);
1257 request
= to_musb_request(next_request(musb_ep
));
1260 DBG(3, "request in progress, cannot halt %s\n",
1265 /* Cannot portably stall with non-empty FIFO */
1266 if (musb_ep
->is_in
) {
1267 csr
= musb_readw(epio
, MUSB_TXCSR
);
1268 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1269 DBG(3, "FIFO busy, cannot halt %s\n", ep
->name
);
1275 musb_ep
->wedged
= 0;
1277 /* set/clear the stall and toggle bits */
1278 DBG(2, "%s: %s stall\n", ep
->name
, value
? "set" : "clear");
1279 if (musb_ep
->is_in
) {
1280 csr
= musb_readw(epio
, MUSB_TXCSR
);
1281 csr
|= MUSB_TXCSR_P_WZC_BITS
1282 | MUSB_TXCSR_CLRDATATOG
;
1284 csr
|= MUSB_TXCSR_P_SENDSTALL
;
1286 csr
&= ~(MUSB_TXCSR_P_SENDSTALL
1287 | MUSB_TXCSR_P_SENTSTALL
);
1288 csr
&= ~MUSB_TXCSR_TXPKTRDY
;
1289 musb_writew(epio
, MUSB_TXCSR
, csr
);
1291 csr
= musb_readw(epio
, MUSB_RXCSR
);
1292 csr
|= MUSB_RXCSR_P_WZC_BITS
1293 | MUSB_RXCSR_FLUSHFIFO
1294 | MUSB_RXCSR_CLRDATATOG
;
1296 csr
|= MUSB_RXCSR_P_SENDSTALL
;
1298 csr
&= ~(MUSB_RXCSR_P_SENDSTALL
1299 | MUSB_RXCSR_P_SENTSTALL
);
1300 musb_writew(epio
, MUSB_RXCSR
, csr
);
1303 /* maybe start the first request in the queue */
1304 if (!musb_ep
->busy
&& !value
&& request
) {
1305 DBG(3, "restarting the request\n");
1306 musb_ep_restart(musb
, request
);
1310 spin_unlock_irqrestore(&musb
->lock
, flags
);
1315 * Sets the halt feature with the clear requests ignored
1317 static int musb_gadget_set_wedge(struct usb_ep
*ep
)
1319 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1324 musb_ep
->wedged
= 1;
1326 return usb_ep_set_halt(ep
);
1329 static int musb_gadget_fifo_status(struct usb_ep
*ep
)
1331 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1332 void __iomem
*epio
= musb_ep
->hw_ep
->regs
;
1333 int retval
= -EINVAL
;
1335 if (musb_ep
->desc
&& !musb_ep
->is_in
) {
1336 struct musb
*musb
= musb_ep
->musb
;
1337 int epnum
= musb_ep
->current_epnum
;
1338 void __iomem
*mbase
= musb
->mregs
;
1339 unsigned long flags
;
1341 spin_lock_irqsave(&musb
->lock
, flags
);
1343 musb_ep_select(mbase
, epnum
);
1344 /* FIXME return zero unless RXPKTRDY is set */
1345 retval
= musb_readw(epio
, MUSB_RXCOUNT
);
1347 spin_unlock_irqrestore(&musb
->lock
, flags
);
1352 static void musb_gadget_fifo_flush(struct usb_ep
*ep
)
1354 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1355 struct musb
*musb
= musb_ep
->musb
;
1356 u8 epnum
= musb_ep
->current_epnum
;
1357 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1358 void __iomem
*mbase
;
1359 unsigned long flags
;
1362 mbase
= musb
->mregs
;
1364 spin_lock_irqsave(&musb
->lock
, flags
);
1365 musb_ep_select(mbase
, (u8
) epnum
);
1367 /* disable interrupts */
1368 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
1369 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
& ~(1 << epnum
));
1371 if (musb_ep
->is_in
) {
1372 csr
= musb_readw(epio
, MUSB_TXCSR
);
1373 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1374 csr
|= MUSB_TXCSR_FLUSHFIFO
| MUSB_TXCSR_P_WZC_BITS
;
1375 musb_writew(epio
, MUSB_TXCSR
, csr
);
1376 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1377 musb_writew(epio
, MUSB_TXCSR
, csr
);
1380 csr
= musb_readw(epio
, MUSB_RXCSR
);
1381 csr
|= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_P_WZC_BITS
;
1382 musb_writew(epio
, MUSB_RXCSR
, csr
);
1383 musb_writew(epio
, MUSB_RXCSR
, csr
);
1386 /* re-enable interrupt */
1387 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
1388 spin_unlock_irqrestore(&musb
->lock
, flags
);
1391 static const struct usb_ep_ops musb_ep_ops
= {
1392 .enable
= musb_gadget_enable
,
1393 .disable
= musb_gadget_disable
,
1394 .alloc_request
= musb_alloc_request
,
1395 .free_request
= musb_free_request
,
1396 .queue
= musb_gadget_queue
,
1397 .dequeue
= musb_gadget_dequeue
,
1398 .set_halt
= musb_gadget_set_halt
,
1399 .set_wedge
= musb_gadget_set_wedge
,
1400 .fifo_status
= musb_gadget_fifo_status
,
1401 .fifo_flush
= musb_gadget_fifo_flush
1404 /* ----------------------------------------------------------------------- */
1406 static int musb_gadget_get_frame(struct usb_gadget
*gadget
)
1408 struct musb
*musb
= gadget_to_musb(gadget
);
1410 return (int)musb_readw(musb
->mregs
, MUSB_FRAME
);
1413 static int musb_gadget_wakeup(struct usb_gadget
*gadget
)
1415 struct musb
*musb
= gadget_to_musb(gadget
);
1416 void __iomem
*mregs
= musb
->mregs
;
1417 unsigned long flags
;
1418 int status
= -EINVAL
;
1422 spin_lock_irqsave(&musb
->lock
, flags
);
1424 switch (musb
->xceiv
->state
) {
1425 case OTG_STATE_B_PERIPHERAL
:
1426 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1427 * that's part of the standard usb 1.1 state machine, and
1428 * doesn't affect OTG transitions.
1430 if (musb
->may_wakeup
&& musb
->is_suspended
)
1433 case OTG_STATE_B_IDLE
:
1434 /* Start SRP ... OTG not required. */
1435 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1436 DBG(2, "Sending SRP: devctl: %02x\n", devctl
);
1437 devctl
|= MUSB_DEVCTL_SESSION
;
1438 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
);
1439 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1441 while (!(devctl
& MUSB_DEVCTL_SESSION
)) {
1442 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1447 while (devctl
& MUSB_DEVCTL_SESSION
) {
1448 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1453 /* Block idling for at least 1s */
1454 musb_platform_try_idle(musb
,
1455 jiffies
+ msecs_to_jiffies(1 * HZ
));
1460 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb
));
1466 power
= musb_readb(mregs
, MUSB_POWER
);
1467 power
|= MUSB_POWER_RESUME
;
1468 musb_writeb(mregs
, MUSB_POWER
, power
);
1469 DBG(2, "issue wakeup\n");
1471 /* FIXME do this next chunk in a timer callback, no udelay */
1474 power
= musb_readb(mregs
, MUSB_POWER
);
1475 power
&= ~MUSB_POWER_RESUME
;
1476 musb_writeb(mregs
, MUSB_POWER
, power
);
1478 spin_unlock_irqrestore(&musb
->lock
, flags
);
1483 musb_gadget_set_self_powered(struct usb_gadget
*gadget
, int is_selfpowered
)
1485 struct musb
*musb
= gadget_to_musb(gadget
);
1487 musb
->is_self_powered
= !!is_selfpowered
;
1491 static void musb_pullup(struct musb
*musb
, int is_on
)
1495 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
1497 power
|= MUSB_POWER_SOFTCONN
;
1499 power
&= ~MUSB_POWER_SOFTCONN
;
1501 /* FIXME if on, HdrcStart; if off, HdrcStop */
1503 DBG(3, "gadget %s D+ pullup %s\n",
1504 musb
->gadget_driver
->function
, is_on
? "on" : "off");
1505 musb_writeb(musb
->mregs
, MUSB_POWER
, power
);
1509 static int musb_gadget_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1511 DBG(2, "<= %s =>\n", __func__
);
1514 * FIXME iff driver's softconnect flag is set (as it is during probe,
1515 * though that can clear it), just musb_pullup().
1522 static int musb_gadget_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
1524 struct musb
*musb
= gadget_to_musb(gadget
);
1526 if (!musb
->xceiv
->set_power
)
1528 return otg_set_power(musb
->xceiv
, mA
);
1531 static int musb_gadget_pullup(struct usb_gadget
*gadget
, int is_on
)
1533 struct musb
*musb
= gadget_to_musb(gadget
);
1534 unsigned long flags
;
1538 /* NOTE: this assumes we are sensing vbus; we'd rather
1539 * not pullup unless the B-session is active.
1541 spin_lock_irqsave(&musb
->lock
, flags
);
1542 if (is_on
!= musb
->softconnect
) {
1543 musb
->softconnect
= is_on
;
1544 musb_pullup(musb
, is_on
);
1546 spin_unlock_irqrestore(&musb
->lock
, flags
);
1550 static const struct usb_gadget_ops musb_gadget_operations
= {
1551 .get_frame
= musb_gadget_get_frame
,
1552 .wakeup
= musb_gadget_wakeup
,
1553 .set_selfpowered
= musb_gadget_set_self_powered
,
1554 /* .vbus_session = musb_gadget_vbus_session, */
1555 .vbus_draw
= musb_gadget_vbus_draw
,
1556 .pullup
= musb_gadget_pullup
,
1559 /* ----------------------------------------------------------------------- */
1563 /* Only this registration code "knows" the rule (from USB standards)
1564 * about there being only one external upstream port. It assumes
1565 * all peripheral ports are external...
1567 static struct musb
*the_gadget
;
1569 static void musb_gadget_release(struct device
*dev
)
1571 /* kref_put(WHAT) */
1572 dev_dbg(dev
, "%s\n", __func__
);
1577 init_peripheral_ep(struct musb
*musb
, struct musb_ep
*ep
, u8 epnum
, int is_in
)
1579 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ epnum
;
1581 memset(ep
, 0, sizeof *ep
);
1583 ep
->current_epnum
= epnum
;
1588 INIT_LIST_HEAD(&ep
->req_list
);
1590 sprintf(ep
->name
, "ep%d%s", epnum
,
1591 (!epnum
|| hw_ep
->is_shared_fifo
) ? "" : (
1592 is_in
? "in" : "out"));
1593 ep
->end_point
.name
= ep
->name
;
1594 INIT_LIST_HEAD(&ep
->end_point
.ep_list
);
1596 ep
->end_point
.maxpacket
= 64;
1597 ep
->end_point
.ops
= &musb_g_ep0_ops
;
1598 musb
->g
.ep0
= &ep
->end_point
;
1601 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_tx
;
1603 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_rx
;
1604 ep
->end_point
.ops
= &musb_ep_ops
;
1605 list_add_tail(&ep
->end_point
.ep_list
, &musb
->g
.ep_list
);
1610 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1611 * to the rest of the driver state.
1613 static inline void __init
musb_g_init_endpoints(struct musb
*musb
)
1616 struct musb_hw_ep
*hw_ep
;
1619 /* intialize endpoint list just once */
1620 INIT_LIST_HEAD(&(musb
->g
.ep_list
));
1622 for (epnum
= 0, hw_ep
= musb
->endpoints
;
1623 epnum
< musb
->nr_endpoints
;
1625 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1626 init_peripheral_ep(musb
, &hw_ep
->ep_in
, epnum
, 0);
1629 if (hw_ep
->max_packet_sz_tx
) {
1630 init_peripheral_ep(musb
, &hw_ep
->ep_in
,
1634 if (hw_ep
->max_packet_sz_rx
) {
1635 init_peripheral_ep(musb
, &hw_ep
->ep_out
,
1643 /* called once during driver setup to initialize and link into
1644 * the driver model; memory is zeroed.
1646 int __init
musb_gadget_setup(struct musb
*musb
)
1650 /* REVISIT minor race: if (erroneously) setting up two
1651 * musb peripherals at the same time, only the bus lock
1658 musb
->g
.ops
= &musb_gadget_operations
;
1659 musb
->g
.is_dualspeed
= 1;
1660 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1662 /* this "gadget" abstracts/virtualizes the controller */
1663 dev_set_name(&musb
->g
.dev
, "gadget");
1664 musb
->g
.dev
.parent
= musb
->controller
;
1665 musb
->g
.dev
.dma_mask
= musb
->controller
->dma_mask
;
1666 musb
->g
.dev
.release
= musb_gadget_release
;
1667 musb
->g
.name
= musb_driver_name
;
1669 if (is_otg_enabled(musb
))
1672 musb_g_init_endpoints(musb
);
1674 musb
->is_active
= 0;
1675 musb_platform_try_idle(musb
, 0);
1677 status
= device_register(&musb
->g
.dev
);
1683 void musb_gadget_cleanup(struct musb
*musb
)
1685 if (musb
!= the_gadget
)
1688 device_unregister(&musb
->g
.dev
);
1693 * Register the gadget driver. Used by gadget drivers when
1694 * registering themselves with the controller.
1696 * -EINVAL something went wrong (not driver)
1697 * -EBUSY another gadget is already using the controller
1698 * -ENOMEM no memeory to perform the operation
1700 * @param driver the gadget driver
1701 * @return <0 if error, 0 if everything is fine
1703 int usb_gadget_register_driver(struct usb_gadget_driver
*driver
)
1706 unsigned long flags
;
1707 struct musb
*musb
= the_gadget
;
1710 || driver
->speed
!= USB_SPEED_HIGH
1715 /* driver must be initialized to support peripheral mode */
1717 DBG(1, "%s, no dev??\n", __func__
);
1721 DBG(3, "registering driver %s\n", driver
->function
);
1722 spin_lock_irqsave(&musb
->lock
, flags
);
1724 if (musb
->gadget_driver
) {
1725 DBG(1, "%s is already bound to %s\n",
1727 musb
->gadget_driver
->driver
.name
);
1730 musb
->gadget_driver
= driver
;
1731 musb
->g
.dev
.driver
= &driver
->driver
;
1732 driver
->driver
.bus
= NULL
;
1733 musb
->softconnect
= 1;
1737 spin_unlock_irqrestore(&musb
->lock
, flags
);
1740 retval
= driver
->bind(&musb
->g
);
1742 DBG(3, "bind to driver %s failed --> %d\n",
1743 driver
->driver
.name
, retval
);
1744 musb
->gadget_driver
= NULL
;
1745 musb
->g
.dev
.driver
= NULL
;
1748 spin_lock_irqsave(&musb
->lock
, flags
);
1750 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1751 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1752 musb
->is_active
= 1;
1754 /* FIXME this ignores the softconnect flag. Drivers are
1755 * allowed hold the peripheral inactive until for example
1756 * userspace hooks up printer hardware or DSP codecs, so
1757 * hosts only see fully functional devices.
1760 if (!is_otg_enabled(musb
))
1763 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1765 spin_unlock_irqrestore(&musb
->lock
, flags
);
1767 if (is_otg_enabled(musb
)) {
1768 DBG(3, "OTG startup...\n");
1770 /* REVISIT: funcall to other code, which also
1771 * handles power budgeting ... this way also
1772 * ensures HdrcStart is indirectly called.
1774 retval
= usb_add_hcd(musb_to_hcd(musb
), -1, 0);
1776 DBG(1, "add_hcd failed, %d\n", retval
);
1777 spin_lock_irqsave(&musb
->lock
, flags
);
1778 otg_set_peripheral(musb
->xceiv
, NULL
);
1779 musb
->gadget_driver
= NULL
;
1780 musb
->g
.dev
.driver
= NULL
;
1781 spin_unlock_irqrestore(&musb
->lock
, flags
);
1788 EXPORT_SYMBOL(usb_gadget_register_driver
);
1790 static void stop_activity(struct musb
*musb
, struct usb_gadget_driver
*driver
)
1793 struct musb_hw_ep
*hw_ep
;
1795 /* don't disconnect if it's not connected */
1796 if (musb
->g
.speed
== USB_SPEED_UNKNOWN
)
1799 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1801 /* deactivate the hardware */
1802 if (musb
->softconnect
) {
1803 musb
->softconnect
= 0;
1804 musb_pullup(musb
, 0);
1808 /* killing any outstanding requests will quiesce the driver;
1809 * then report disconnect
1812 for (i
= 0, hw_ep
= musb
->endpoints
;
1813 i
< musb
->nr_endpoints
;
1815 musb_ep_select(musb
->mregs
, i
);
1816 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1817 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1819 if (hw_ep
->max_packet_sz_tx
)
1820 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1821 if (hw_ep
->max_packet_sz_rx
)
1822 nuke(&hw_ep
->ep_out
, -ESHUTDOWN
);
1826 spin_unlock(&musb
->lock
);
1827 driver
->disconnect(&musb
->g
);
1828 spin_lock(&musb
->lock
);
1833 * Unregister the gadget driver. Used by gadget drivers when
1834 * unregistering themselves from the controller.
1836 * @param driver the gadget driver to unregister
1838 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1840 unsigned long flags
;
1842 struct musb
*musb
= the_gadget
;
1844 if (!driver
|| !driver
->unbind
|| !musb
)
1847 /* REVISIT always use otg_set_peripheral() here too;
1848 * this needs to shut down the OTG engine.
1851 spin_lock_irqsave(&musb
->lock
, flags
);
1853 #ifdef CONFIG_USB_MUSB_OTG
1854 musb_hnp_stop(musb
);
1857 if (musb
->gadget_driver
== driver
) {
1859 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1861 musb
->xceiv
->state
= OTG_STATE_UNDEFINED
;
1862 stop_activity(musb
, driver
);
1863 otg_set_peripheral(musb
->xceiv
, NULL
);
1865 DBG(3, "unregistering driver %s\n", driver
->function
);
1866 spin_unlock_irqrestore(&musb
->lock
, flags
);
1867 driver
->unbind(&musb
->g
);
1868 spin_lock_irqsave(&musb
->lock
, flags
);
1870 musb
->gadget_driver
= NULL
;
1871 musb
->g
.dev
.driver
= NULL
;
1873 musb
->is_active
= 0;
1874 musb_platform_try_idle(musb
, 0);
1877 spin_unlock_irqrestore(&musb
->lock
, flags
);
1879 if (is_otg_enabled(musb
) && retval
== 0) {
1880 usb_remove_hcd(musb_to_hcd(musb
));
1881 /* FIXME we need to be able to register another
1882 * gadget driver here and have everything work;
1883 * that currently misbehaves.
1889 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
1892 /* ----------------------------------------------------------------------- */
1894 /* lifecycle operations called through plat_uds.c */
1896 void musb_g_resume(struct musb
*musb
)
1898 musb
->is_suspended
= 0;
1899 switch (musb
->xceiv
->state
) {
1900 case OTG_STATE_B_IDLE
:
1902 case OTG_STATE_B_WAIT_ACON
:
1903 case OTG_STATE_B_PERIPHERAL
:
1904 musb
->is_active
= 1;
1905 if (musb
->gadget_driver
&& musb
->gadget_driver
->resume
) {
1906 spin_unlock(&musb
->lock
);
1907 musb
->gadget_driver
->resume(&musb
->g
);
1908 spin_lock(&musb
->lock
);
1912 WARNING("unhandled RESUME transition (%s)\n",
1913 otg_state_string(musb
));
1917 /* called when SOF packets stop for 3+ msec */
1918 void musb_g_suspend(struct musb
*musb
)
1922 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1923 DBG(3, "devctl %02x\n", devctl
);
1925 switch (musb
->xceiv
->state
) {
1926 case OTG_STATE_B_IDLE
:
1927 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
1928 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
1930 case OTG_STATE_B_PERIPHERAL
:
1931 musb
->is_suspended
= 1;
1932 if (musb
->gadget_driver
&& musb
->gadget_driver
->suspend
) {
1933 spin_unlock(&musb
->lock
);
1934 musb
->gadget_driver
->suspend(&musb
->g
);
1935 spin_lock(&musb
->lock
);
1939 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1940 * A_PERIPHERAL may need care too
1942 WARNING("unhandled SUSPEND transition (%s)\n",
1943 otg_state_string(musb
));
1947 /* Called during SRP */
1948 void musb_g_wakeup(struct musb
*musb
)
1950 musb_gadget_wakeup(&musb
->g
);
1953 /* called when VBUS drops below session threshold, and in other cases */
1954 void musb_g_disconnect(struct musb
*musb
)
1956 void __iomem
*mregs
= musb
->mregs
;
1957 u8 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1959 DBG(3, "devctl %02x\n", devctl
);
1962 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
& MUSB_DEVCTL_SESSION
);
1964 /* don't draw vbus until new b-default session */
1965 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1967 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1968 if (musb
->gadget_driver
&& musb
->gadget_driver
->disconnect
) {
1969 spin_unlock(&musb
->lock
);
1970 musb
->gadget_driver
->disconnect(&musb
->g
);
1971 spin_lock(&musb
->lock
);
1974 switch (musb
->xceiv
->state
) {
1976 #ifdef CONFIG_USB_MUSB_OTG
1977 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1978 otg_state_string(musb
));
1979 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
1980 MUSB_HST_MODE(musb
);
1982 case OTG_STATE_A_PERIPHERAL
:
1983 musb
->xceiv
->state
= OTG_STATE_A_WAIT_BCON
;
1984 MUSB_HST_MODE(musb
);
1986 case OTG_STATE_B_WAIT_ACON
:
1987 case OTG_STATE_B_HOST
:
1989 case OTG_STATE_B_PERIPHERAL
:
1990 case OTG_STATE_B_IDLE
:
1991 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1993 case OTG_STATE_B_SRP_INIT
:
1997 musb
->is_active
= 0;
2000 void musb_g_reset(struct musb
*musb
)
2001 __releases(musb
->lock
)
2002 __acquires(musb
->lock
)
2004 void __iomem
*mbase
= musb
->mregs
;
2005 u8 devctl
= musb_readb(mbase
, MUSB_DEVCTL
);
2008 DBG(3, "<== %s addr=%x driver '%s'\n",
2009 (devctl
& MUSB_DEVCTL_BDEVICE
)
2010 ? "B-Device" : "A-Device",
2011 musb_readb(mbase
, MUSB_FADDR
),
2013 ? musb
->gadget_driver
->driver
.name
2017 /* report disconnect, if we didn't already (flushing EP state) */
2018 if (musb
->g
.speed
!= USB_SPEED_UNKNOWN
)
2019 musb_g_disconnect(musb
);
2022 else if (devctl
& MUSB_DEVCTL_HR
)
2023 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
2026 /* what speed did we negotiate? */
2027 power
= musb_readb(mbase
, MUSB_POWER
);
2028 musb
->g
.speed
= (power
& MUSB_POWER_HSMODE
)
2029 ? USB_SPEED_HIGH
: USB_SPEED_FULL
;
2031 /* start in USB_STATE_DEFAULT */
2032 musb
->is_active
= 1;
2033 musb
->is_suspended
= 0;
2034 MUSB_DEV_MODE(musb
);
2036 musb
->ep0_state
= MUSB_EP0_STAGE_SETUP
;
2038 musb
->may_wakeup
= 0;
2039 musb
->g
.b_hnp_enable
= 0;
2040 musb
->g
.a_alt_hnp_support
= 0;
2041 musb
->g
.a_hnp_support
= 0;
2043 /* Normal reset, as B-Device;
2044 * or else after HNP, as A-Device
2046 if (devctl
& MUSB_DEVCTL_BDEVICE
) {
2047 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
2048 musb
->g
.is_a_peripheral
= 0;
2049 } else if (is_otg_enabled(musb
)) {
2050 musb
->xceiv
->state
= OTG_STATE_A_PERIPHERAL
;
2051 musb
->g
.is_a_peripheral
= 1;
2055 /* start with default limits on VBUS power draw */
2056 (void) musb_gadget_vbus_draw(&musb
->g
,
2057 is_otg_enabled(musb
) ? 8 : 100);