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Merge tag 'perf-urgent-for-mingo-20160726' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / usb / musb / musb_gadget.c
1 /*
2 * MUSB OTG driver peripheral support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45
46 #include "musb_core.h"
47 #include "musb_trace.h"
48
49
50 /* ----------------------------------------------------------------------- */
51
52 #define is_buffer_mapped(req) (is_dma_capable() && \
53 (req->map_state != UN_MAPPED))
54
55 /* Maps the buffer to dma */
56
57 static inline void map_dma_buffer(struct musb_request *request,
58 struct musb *musb, struct musb_ep *musb_ep)
59 {
60 int compatible = true;
61 struct dma_controller *dma = musb->dma_controller;
62
63 request->map_state = UN_MAPPED;
64
65 if (!is_dma_capable() || !musb_ep->dma)
66 return;
67
68 /* Check if DMA engine can handle this request.
69 * DMA code must reject the USB request explicitly.
70 * Default behaviour is to map the request.
71 */
72 if (dma->is_compatible)
73 compatible = dma->is_compatible(musb_ep->dma,
74 musb_ep->packet_sz, request->request.buf,
75 request->request.length);
76 if (!compatible)
77 return;
78
79 if (request->request.dma == DMA_ADDR_INVALID) {
80 dma_addr_t dma_addr;
81 int ret;
82
83 dma_addr = dma_map_single(
84 musb->controller,
85 request->request.buf,
86 request->request.length,
87 request->tx
88 ? DMA_TO_DEVICE
89 : DMA_FROM_DEVICE);
90 ret = dma_mapping_error(musb->controller, dma_addr);
91 if (ret)
92 return;
93
94 request->request.dma = dma_addr;
95 request->map_state = MUSB_MAPPED;
96 } else {
97 dma_sync_single_for_device(musb->controller,
98 request->request.dma,
99 request->request.length,
100 request->tx
101 ? DMA_TO_DEVICE
102 : DMA_FROM_DEVICE);
103 request->map_state = PRE_MAPPED;
104 }
105 }
106
107 /* Unmap the buffer from dma and maps it back to cpu */
108 static inline void unmap_dma_buffer(struct musb_request *request,
109 struct musb *musb)
110 {
111 struct musb_ep *musb_ep = request->ep;
112
113 if (!is_buffer_mapped(request) || !musb_ep->dma)
114 return;
115
116 if (request->request.dma == DMA_ADDR_INVALID) {
117 dev_vdbg(musb->controller,
118 "not unmapping a never mapped buffer\n");
119 return;
120 }
121 if (request->map_state == MUSB_MAPPED) {
122 dma_unmap_single(musb->controller,
123 request->request.dma,
124 request->request.length,
125 request->tx
126 ? DMA_TO_DEVICE
127 : DMA_FROM_DEVICE);
128 request->request.dma = DMA_ADDR_INVALID;
129 } else { /* PRE_MAPPED */
130 dma_sync_single_for_cpu(musb->controller,
131 request->request.dma,
132 request->request.length,
133 request->tx
134 ? DMA_TO_DEVICE
135 : DMA_FROM_DEVICE);
136 }
137 request->map_state = UN_MAPPED;
138 }
139
140 /*
141 * Immediately complete a request.
142 *
143 * @param request the request to complete
144 * @param status the status to complete the request with
145 * Context: controller locked, IRQs blocked.
146 */
147 void musb_g_giveback(
148 struct musb_ep *ep,
149 struct usb_request *request,
150 int status)
151 __releases(ep->musb->lock)
152 __acquires(ep->musb->lock)
153 {
154 struct musb_request *req;
155 struct musb *musb;
156 int busy = ep->busy;
157
158 req = to_musb_request(request);
159
160 list_del(&req->list);
161 if (req->request.status == -EINPROGRESS)
162 req->request.status = status;
163 musb = req->musb;
164
165 ep->busy = 1;
166 spin_unlock(&musb->lock);
167
168 if (!dma_mapping_error(&musb->g.dev, request->dma))
169 unmap_dma_buffer(req, musb);
170
171 trace_musb_req_gb(req);
172 usb_gadget_giveback_request(&req->ep->end_point, &req->request);
173 spin_lock(&musb->lock);
174 ep->busy = busy;
175 }
176
177 /* ----------------------------------------------------------------------- */
178
179 /*
180 * Abort requests queued to an endpoint using the status. Synchronous.
181 * caller locked controller and blocked irqs, and selected this ep.
182 */
183 static void nuke(struct musb_ep *ep, const int status)
184 {
185 struct musb *musb = ep->musb;
186 struct musb_request *req = NULL;
187 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
188
189 ep->busy = 1;
190
191 if (is_dma_capable() && ep->dma) {
192 struct dma_controller *c = ep->musb->dma_controller;
193 int value;
194
195 if (ep->is_in) {
196 /*
197 * The programming guide says that we must not clear
198 * the DMAMODE bit before DMAENAB, so we only
199 * clear it in the second write...
200 */
201 musb_writew(epio, MUSB_TXCSR,
202 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
203 musb_writew(epio, MUSB_TXCSR,
204 0 | MUSB_TXCSR_FLUSHFIFO);
205 } else {
206 musb_writew(epio, MUSB_RXCSR,
207 0 | MUSB_RXCSR_FLUSHFIFO);
208 musb_writew(epio, MUSB_RXCSR,
209 0 | MUSB_RXCSR_FLUSHFIFO);
210 }
211
212 value = c->channel_abort(ep->dma);
213 musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value);
214 c->channel_release(ep->dma);
215 ep->dma = NULL;
216 }
217
218 while (!list_empty(&ep->req_list)) {
219 req = list_first_entry(&ep->req_list, struct musb_request, list);
220 musb_g_giveback(ep, &req->request, status);
221 }
222 }
223
224 /* ----------------------------------------------------------------------- */
225
226 /* Data transfers - pure PIO, pure DMA, or mixed mode */
227
228 /*
229 * This assumes the separate CPPI engine is responding to DMA requests
230 * from the usb core ... sequenced a bit differently from mentor dma.
231 */
232
233 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
234 {
235 if (can_bulk_split(musb, ep->type))
236 return ep->hw_ep->max_packet_sz_tx;
237 else
238 return ep->packet_sz;
239 }
240
241 /*
242 * An endpoint is transmitting data. This can be called either from
243 * the IRQ routine or from ep.queue() to kickstart a request on an
244 * endpoint.
245 *
246 * Context: controller locked, IRQs blocked, endpoint selected
247 */
248 static void txstate(struct musb *musb, struct musb_request *req)
249 {
250 u8 epnum = req->epnum;
251 struct musb_ep *musb_ep;
252 void __iomem *epio = musb->endpoints[epnum].regs;
253 struct usb_request *request;
254 u16 fifo_count = 0, csr;
255 int use_dma = 0;
256
257 musb_ep = req->ep;
258
259 /* Check if EP is disabled */
260 if (!musb_ep->desc) {
261 musb_dbg(musb, "ep:%s disabled - ignore request",
262 musb_ep->end_point.name);
263 return;
264 }
265
266 /* we shouldn't get here while DMA is active ... but we do ... */
267 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
268 musb_dbg(musb, "dma pending...");
269 return;
270 }
271
272 /* read TXCSR before */
273 csr = musb_readw(epio, MUSB_TXCSR);
274
275 request = &req->request;
276 fifo_count = min(max_ep_writesize(musb, musb_ep),
277 (int)(request->length - request->actual));
278
279 if (csr & MUSB_TXCSR_TXPKTRDY) {
280 musb_dbg(musb, "%s old packet still ready , txcsr %03x",
281 musb_ep->end_point.name, csr);
282 return;
283 }
284
285 if (csr & MUSB_TXCSR_P_SENDSTALL) {
286 musb_dbg(musb, "%s stalling, txcsr %03x",
287 musb_ep->end_point.name, csr);
288 return;
289 }
290
291 musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x",
292 epnum, musb_ep->packet_sz, fifo_count,
293 csr);
294
295 #ifndef CONFIG_MUSB_PIO_ONLY
296 if (is_buffer_mapped(req)) {
297 struct dma_controller *c = musb->dma_controller;
298 size_t request_size;
299
300 /* setup DMA, then program endpoint CSR */
301 request_size = min_t(size_t, request->length - request->actual,
302 musb_ep->dma->max_len);
303
304 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
305
306 /* MUSB_TXCSR_P_ISO is still set correctly */
307
308 if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) {
309 if (request_size < musb_ep->packet_sz)
310 musb_ep->dma->desired_mode = 0;
311 else
312 musb_ep->dma->desired_mode = 1;
313
314 use_dma = use_dma && c->channel_program(
315 musb_ep->dma, musb_ep->packet_sz,
316 musb_ep->dma->desired_mode,
317 request->dma + request->actual, request_size);
318 if (use_dma) {
319 if (musb_ep->dma->desired_mode == 0) {
320 /*
321 * We must not clear the DMAMODE bit
322 * before the DMAENAB bit -- and the
323 * latter doesn't always get cleared
324 * before we get here...
325 */
326 csr &= ~(MUSB_TXCSR_AUTOSET
327 | MUSB_TXCSR_DMAENAB);
328 musb_writew(epio, MUSB_TXCSR, csr
329 | MUSB_TXCSR_P_WZC_BITS);
330 csr &= ~MUSB_TXCSR_DMAMODE;
331 csr |= (MUSB_TXCSR_DMAENAB |
332 MUSB_TXCSR_MODE);
333 /* against programming guide */
334 } else {
335 csr |= (MUSB_TXCSR_DMAENAB
336 | MUSB_TXCSR_DMAMODE
337 | MUSB_TXCSR_MODE);
338 /*
339 * Enable Autoset according to table
340 * below
341 * bulk_split hb_mult Autoset_Enable
342 * 0 0 Yes(Normal)
343 * 0 >0 No(High BW ISO)
344 * 1 0 Yes(HS bulk)
345 * 1 >0 Yes(FS bulk)
346 */
347 if (!musb_ep->hb_mult ||
348 can_bulk_split(musb,
349 musb_ep->type))
350 csr |= MUSB_TXCSR_AUTOSET;
351 }
352 csr &= ~MUSB_TXCSR_P_UNDERRUN;
353
354 musb_writew(epio, MUSB_TXCSR, csr);
355 }
356 }
357
358 if (is_cppi_enabled(musb)) {
359 /* program endpoint CSR first, then setup DMA */
360 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
361 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
362 MUSB_TXCSR_MODE;
363 musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
364 ~MUSB_TXCSR_P_UNDERRUN) | csr);
365
366 /* ensure writebuffer is empty */
367 csr = musb_readw(epio, MUSB_TXCSR);
368
369 /*
370 * NOTE host side sets DMAENAB later than this; both are
371 * OK since the transfer dma glue (between CPPI and
372 * Mentor fifos) just tells CPPI it could start. Data
373 * only moves to the USB TX fifo when both fifos are
374 * ready.
375 */
376 /*
377 * "mode" is irrelevant here; handle terminating ZLPs
378 * like PIO does, since the hardware RNDIS mode seems
379 * unreliable except for the
380 * last-packet-is-already-short case.
381 */
382 use_dma = use_dma && c->channel_program(
383 musb_ep->dma, musb_ep->packet_sz,
384 0,
385 request->dma + request->actual,
386 request_size);
387 if (!use_dma) {
388 c->channel_release(musb_ep->dma);
389 musb_ep->dma = NULL;
390 csr &= ~MUSB_TXCSR_DMAENAB;
391 musb_writew(epio, MUSB_TXCSR, csr);
392 /* invariant: prequest->buf is non-null */
393 }
394 } else if (tusb_dma_omap(musb))
395 use_dma = use_dma && c->channel_program(
396 musb_ep->dma, musb_ep->packet_sz,
397 request->zero,
398 request->dma + request->actual,
399 request_size);
400 }
401 #endif
402
403 if (!use_dma) {
404 /*
405 * Unmap the dma buffer back to cpu if dma channel
406 * programming fails
407 */
408 unmap_dma_buffer(req, musb);
409
410 musb_write_fifo(musb_ep->hw_ep, fifo_count,
411 (u8 *) (request->buf + request->actual));
412 request->actual += fifo_count;
413 csr |= MUSB_TXCSR_TXPKTRDY;
414 csr &= ~MUSB_TXCSR_P_UNDERRUN;
415 musb_writew(epio, MUSB_TXCSR, csr);
416 }
417
418 /* host may already have the data when this message shows... */
419 musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d",
420 musb_ep->end_point.name, use_dma ? "dma" : "pio",
421 request->actual, request->length,
422 musb_readw(epio, MUSB_TXCSR),
423 fifo_count,
424 musb_readw(epio, MUSB_TXMAXP));
425 }
426
427 /*
428 * FIFO state update (e.g. data ready).
429 * Called from IRQ, with controller locked.
430 */
431 void musb_g_tx(struct musb *musb, u8 epnum)
432 {
433 u16 csr;
434 struct musb_request *req;
435 struct usb_request *request;
436 u8 __iomem *mbase = musb->mregs;
437 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
438 void __iomem *epio = musb->endpoints[epnum].regs;
439 struct dma_channel *dma;
440
441 musb_ep_select(mbase, epnum);
442 req = next_request(musb_ep);
443 request = &req->request;
444
445 trace_musb_req_tx(req);
446 csr = musb_readw(epio, MUSB_TXCSR);
447 musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);
448
449 dma = is_dma_capable() ? musb_ep->dma : NULL;
450
451 /*
452 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
453 * probably rates reporting as a host error.
454 */
455 if (csr & MUSB_TXCSR_P_SENTSTALL) {
456 csr |= MUSB_TXCSR_P_WZC_BITS;
457 csr &= ~MUSB_TXCSR_P_SENTSTALL;
458 musb_writew(epio, MUSB_TXCSR, csr);
459 return;
460 }
461
462 if (csr & MUSB_TXCSR_P_UNDERRUN) {
463 /* We NAKed, no big deal... little reason to care. */
464 csr |= MUSB_TXCSR_P_WZC_BITS;
465 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
466 musb_writew(epio, MUSB_TXCSR, csr);
467 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
468 epnum, request);
469 }
470
471 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
472 /*
473 * SHOULD NOT HAPPEN... has with CPPI though, after
474 * changing SENDSTALL (and other cases); harmless?
475 */
476 musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name);
477 return;
478 }
479
480 if (request) {
481 u8 is_dma = 0;
482 bool short_packet = false;
483
484 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
485 is_dma = 1;
486 csr |= MUSB_TXCSR_P_WZC_BITS;
487 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
488 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
489 musb_writew(epio, MUSB_TXCSR, csr);
490 /* Ensure writebuffer is empty. */
491 csr = musb_readw(epio, MUSB_TXCSR);
492 request->actual += musb_ep->dma->actual_len;
493 musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p",
494 epnum, csr, musb_ep->dma->actual_len, request);
495 }
496
497 /*
498 * First, maybe a terminating short packet. Some DMA
499 * engines might handle this by themselves.
500 */
501 if ((request->zero && request->length)
502 && (request->length % musb_ep->packet_sz == 0)
503 && (request->actual == request->length))
504 short_packet = true;
505
506 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb)) &&
507 (is_dma && (!dma->desired_mode ||
508 (request->actual &
509 (musb_ep->packet_sz - 1)))))
510 short_packet = true;
511
512 if (short_packet) {
513 /*
514 * On DMA completion, FIFO may not be
515 * available yet...
516 */
517 if (csr & MUSB_TXCSR_TXPKTRDY)
518 return;
519
520 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
521 | MUSB_TXCSR_TXPKTRDY);
522 request->zero = 0;
523 }
524
525 if (request->actual == request->length) {
526 musb_g_giveback(musb_ep, request, 0);
527 /*
528 * In the giveback function the MUSB lock is
529 * released and acquired after sometime. During
530 * this time period the INDEX register could get
531 * changed by the gadget_queue function especially
532 * on SMP systems. Reselect the INDEX to be sure
533 * we are reading/modifying the right registers
534 */
535 musb_ep_select(mbase, epnum);
536 req = musb_ep->desc ? next_request(musb_ep) : NULL;
537 if (!req) {
538 musb_dbg(musb, "%s idle now",
539 musb_ep->end_point.name);
540 return;
541 }
542 }
543
544 txstate(musb, req);
545 }
546 }
547
548 /* ------------------------------------------------------------ */
549
550 /*
551 * Context: controller locked, IRQs blocked, endpoint selected
552 */
553 static void rxstate(struct musb *musb, struct musb_request *req)
554 {
555 const u8 epnum = req->epnum;
556 struct usb_request *request = &req->request;
557 struct musb_ep *musb_ep;
558 void __iomem *epio = musb->endpoints[epnum].regs;
559 unsigned len = 0;
560 u16 fifo_count;
561 u16 csr = musb_readw(epio, MUSB_RXCSR);
562 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
563 u8 use_mode_1;
564
565 if (hw_ep->is_shared_fifo)
566 musb_ep = &hw_ep->ep_in;
567 else
568 musb_ep = &hw_ep->ep_out;
569
570 fifo_count = musb_ep->packet_sz;
571
572 /* Check if EP is disabled */
573 if (!musb_ep->desc) {
574 musb_dbg(musb, "ep:%s disabled - ignore request",
575 musb_ep->end_point.name);
576 return;
577 }
578
579 /* We shouldn't get here while DMA is active, but we do... */
580 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
581 musb_dbg(musb, "DMA pending...");
582 return;
583 }
584
585 if (csr & MUSB_RXCSR_P_SENDSTALL) {
586 musb_dbg(musb, "%s stalling, RXCSR %04x",
587 musb_ep->end_point.name, csr);
588 return;
589 }
590
591 if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
592 struct dma_controller *c = musb->dma_controller;
593 struct dma_channel *channel = musb_ep->dma;
594
595 /* NOTE: CPPI won't actually stop advancing the DMA
596 * queue after short packet transfers, so this is almost
597 * always going to run as IRQ-per-packet DMA so that
598 * faults will be handled correctly.
599 */
600 if (c->channel_program(channel,
601 musb_ep->packet_sz,
602 !request->short_not_ok,
603 request->dma + request->actual,
604 request->length - request->actual)) {
605
606 /* make sure that if an rxpkt arrived after the irq,
607 * the cppi engine will be ready to take it as soon
608 * as DMA is enabled
609 */
610 csr &= ~(MUSB_RXCSR_AUTOCLEAR
611 | MUSB_RXCSR_DMAMODE);
612 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
613 musb_writew(epio, MUSB_RXCSR, csr);
614 return;
615 }
616 }
617
618 if (csr & MUSB_RXCSR_RXPKTRDY) {
619 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
620
621 /*
622 * Enable Mode 1 on RX transfers only when short_not_ok flag
623 * is set. Currently short_not_ok flag is set only from
624 * file_storage and f_mass_storage drivers
625 */
626
627 if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
628 use_mode_1 = 1;
629 else
630 use_mode_1 = 0;
631
632 if (request->actual < request->length) {
633 if (!is_buffer_mapped(req))
634 goto buffer_aint_mapped;
635
636 if (musb_dma_inventra(musb)) {
637 struct dma_controller *c;
638 struct dma_channel *channel;
639 int use_dma = 0;
640 unsigned int transfer_size;
641
642 c = musb->dma_controller;
643 channel = musb_ep->dma;
644
645 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
646 * mode 0 only. So we do not get endpoint interrupts due to DMA
647 * completion. We only get interrupts from DMA controller.
648 *
649 * We could operate in DMA mode 1 if we knew the size of the tranfer
650 * in advance. For mass storage class, request->length = what the host
651 * sends, so that'd work. But for pretty much everything else,
652 * request->length is routinely more than what the host sends. For
653 * most these gadgets, end of is signified either by a short packet,
654 * or filling the last byte of the buffer. (Sending extra data in
655 * that last pckate should trigger an overflow fault.) But in mode 1,
656 * we don't get DMA completion interrupt for short packets.
657 *
658 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
659 * to get endpoint interrupt on every DMA req, but that didn't seem
660 * to work reliably.
661 *
662 * REVISIT an updated g_file_storage can set req->short_not_ok, which
663 * then becomes usable as a runtime "use mode 1" hint...
664 */
665
666 /* Experimental: Mode1 works with mass storage use cases */
667 if (use_mode_1) {
668 csr |= MUSB_RXCSR_AUTOCLEAR;
669 musb_writew(epio, MUSB_RXCSR, csr);
670 csr |= MUSB_RXCSR_DMAENAB;
671 musb_writew(epio, MUSB_RXCSR, csr);
672
673 /*
674 * this special sequence (enabling and then
675 * disabling MUSB_RXCSR_DMAMODE) is required
676 * to get DMAReq to activate
677 */
678 musb_writew(epio, MUSB_RXCSR,
679 csr | MUSB_RXCSR_DMAMODE);
680 musb_writew(epio, MUSB_RXCSR, csr);
681
682 transfer_size = min_t(unsigned int,
683 request->length -
684 request->actual,
685 channel->max_len);
686 musb_ep->dma->desired_mode = 1;
687 } else {
688 if (!musb_ep->hb_mult &&
689 musb_ep->hw_ep->rx_double_buffered)
690 csr |= MUSB_RXCSR_AUTOCLEAR;
691 csr |= MUSB_RXCSR_DMAENAB;
692 musb_writew(epio, MUSB_RXCSR, csr);
693
694 transfer_size = min(request->length - request->actual,
695 (unsigned)fifo_count);
696 musb_ep->dma->desired_mode = 0;
697 }
698
699 use_dma = c->channel_program(
700 channel,
701 musb_ep->packet_sz,
702 channel->desired_mode,
703 request->dma
704 + request->actual,
705 transfer_size);
706
707 if (use_dma)
708 return;
709 }
710
711 if ((musb_dma_ux500(musb)) &&
712 (request->actual < request->length)) {
713
714 struct dma_controller *c;
715 struct dma_channel *channel;
716 unsigned int transfer_size = 0;
717
718 c = musb->dma_controller;
719 channel = musb_ep->dma;
720
721 /* In case first packet is short */
722 if (fifo_count < musb_ep->packet_sz)
723 transfer_size = fifo_count;
724 else if (request->short_not_ok)
725 transfer_size = min_t(unsigned int,
726 request->length -
727 request->actual,
728 channel->max_len);
729 else
730 transfer_size = min_t(unsigned int,
731 request->length -
732 request->actual,
733 (unsigned)fifo_count);
734
735 csr &= ~MUSB_RXCSR_DMAMODE;
736 csr |= (MUSB_RXCSR_DMAENAB |
737 MUSB_RXCSR_AUTOCLEAR);
738
739 musb_writew(epio, MUSB_RXCSR, csr);
740
741 if (transfer_size <= musb_ep->packet_sz) {
742 musb_ep->dma->desired_mode = 0;
743 } else {
744 musb_ep->dma->desired_mode = 1;
745 /* Mode must be set after DMAENAB */
746 csr |= MUSB_RXCSR_DMAMODE;
747 musb_writew(epio, MUSB_RXCSR, csr);
748 }
749
750 if (c->channel_program(channel,
751 musb_ep->packet_sz,
752 channel->desired_mode,
753 request->dma
754 + request->actual,
755 transfer_size))
756
757 return;
758 }
759
760 len = request->length - request->actual;
761 musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d",
762 musb_ep->end_point.name,
763 fifo_count, len,
764 musb_ep->packet_sz);
765
766 fifo_count = min_t(unsigned, len, fifo_count);
767
768 if (tusb_dma_omap(musb)) {
769 struct dma_controller *c = musb->dma_controller;
770 struct dma_channel *channel = musb_ep->dma;
771 u32 dma_addr = request->dma + request->actual;
772 int ret;
773
774 ret = c->channel_program(channel,
775 musb_ep->packet_sz,
776 channel->desired_mode,
777 dma_addr,
778 fifo_count);
779 if (ret)
780 return;
781 }
782
783 /*
784 * Unmap the dma buffer back to cpu if dma channel
785 * programming fails. This buffer is mapped if the
786 * channel allocation is successful
787 */
788 unmap_dma_buffer(req, musb);
789
790 /*
791 * Clear DMAENAB and AUTOCLEAR for the
792 * PIO mode transfer
793 */
794 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
795 musb_writew(epio, MUSB_RXCSR, csr);
796
797 buffer_aint_mapped:
798 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
799 (request->buf + request->actual));
800 request->actual += fifo_count;
801
802 /* REVISIT if we left anything in the fifo, flush
803 * it and report -EOVERFLOW
804 */
805
806 /* ack the read! */
807 csr |= MUSB_RXCSR_P_WZC_BITS;
808 csr &= ~MUSB_RXCSR_RXPKTRDY;
809 musb_writew(epio, MUSB_RXCSR, csr);
810 }
811 }
812
813 /* reach the end or short packet detected */
814 if (request->actual == request->length ||
815 fifo_count < musb_ep->packet_sz)
816 musb_g_giveback(musb_ep, request, 0);
817 }
818
819 /*
820 * Data ready for a request; called from IRQ
821 */
822 void musb_g_rx(struct musb *musb, u8 epnum)
823 {
824 u16 csr;
825 struct musb_request *req;
826 struct usb_request *request;
827 void __iomem *mbase = musb->mregs;
828 struct musb_ep *musb_ep;
829 void __iomem *epio = musb->endpoints[epnum].regs;
830 struct dma_channel *dma;
831 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
832
833 if (hw_ep->is_shared_fifo)
834 musb_ep = &hw_ep->ep_in;
835 else
836 musb_ep = &hw_ep->ep_out;
837
838 musb_ep_select(mbase, epnum);
839
840 req = next_request(musb_ep);
841 if (!req)
842 return;
843
844 trace_musb_req_rx(req);
845 request = &req->request;
846
847 csr = musb_readw(epio, MUSB_RXCSR);
848 dma = is_dma_capable() ? musb_ep->dma : NULL;
849
850 musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name,
851 csr, dma ? " (dma)" : "", request);
852
853 if (csr & MUSB_RXCSR_P_SENTSTALL) {
854 csr |= MUSB_RXCSR_P_WZC_BITS;
855 csr &= ~MUSB_RXCSR_P_SENTSTALL;
856 musb_writew(epio, MUSB_RXCSR, csr);
857 return;
858 }
859
860 if (csr & MUSB_RXCSR_P_OVERRUN) {
861 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
862 csr &= ~MUSB_RXCSR_P_OVERRUN;
863 musb_writew(epio, MUSB_RXCSR, csr);
864
865 musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request);
866 if (request->status == -EINPROGRESS)
867 request->status = -EOVERFLOW;
868 }
869 if (csr & MUSB_RXCSR_INCOMPRX) {
870 /* REVISIT not necessarily an error */
871 musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name);
872 }
873
874 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
875 /* "should not happen"; likely RXPKTRDY pending for DMA */
876 musb_dbg(musb, "%s busy, csr %04x",
877 musb_ep->end_point.name, csr);
878 return;
879 }
880
881 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
882 csr &= ~(MUSB_RXCSR_AUTOCLEAR
883 | MUSB_RXCSR_DMAENAB
884 | MUSB_RXCSR_DMAMODE);
885 musb_writew(epio, MUSB_RXCSR,
886 MUSB_RXCSR_P_WZC_BITS | csr);
887
888 request->actual += musb_ep->dma->actual_len;
889
890 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
891 defined(CONFIG_USB_UX500_DMA)
892 /* Autoclear doesn't clear RxPktRdy for short packets */
893 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
894 || (dma->actual_len
895 & (musb_ep->packet_sz - 1))) {
896 /* ack the read! */
897 csr &= ~MUSB_RXCSR_RXPKTRDY;
898 musb_writew(epio, MUSB_RXCSR, csr);
899 }
900
901 /* incomplete, and not short? wait for next IN packet */
902 if ((request->actual < request->length)
903 && (musb_ep->dma->actual_len
904 == musb_ep->packet_sz)) {
905 /* In double buffer case, continue to unload fifo if
906 * there is Rx packet in FIFO.
907 **/
908 csr = musb_readw(epio, MUSB_RXCSR);
909 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
910 hw_ep->rx_double_buffered)
911 goto exit;
912 return;
913 }
914 #endif
915 musb_g_giveback(musb_ep, request, 0);
916 /*
917 * In the giveback function the MUSB lock is
918 * released and acquired after sometime. During
919 * this time period the INDEX register could get
920 * changed by the gadget_queue function especially
921 * on SMP systems. Reselect the INDEX to be sure
922 * we are reading/modifying the right registers
923 */
924 musb_ep_select(mbase, epnum);
925
926 req = next_request(musb_ep);
927 if (!req)
928 return;
929 }
930 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
931 defined(CONFIG_USB_UX500_DMA)
932 exit:
933 #endif
934 /* Analyze request */
935 rxstate(musb, req);
936 }
937
938 /* ------------------------------------------------------------ */
939
940 static int musb_gadget_enable(struct usb_ep *ep,
941 const struct usb_endpoint_descriptor *desc)
942 {
943 unsigned long flags;
944 struct musb_ep *musb_ep;
945 struct musb_hw_ep *hw_ep;
946 void __iomem *regs;
947 struct musb *musb;
948 void __iomem *mbase;
949 u8 epnum;
950 u16 csr;
951 unsigned tmp;
952 int status = -EINVAL;
953
954 if (!ep || !desc)
955 return -EINVAL;
956
957 musb_ep = to_musb_ep(ep);
958 hw_ep = musb_ep->hw_ep;
959 regs = hw_ep->regs;
960 musb = musb_ep->musb;
961 mbase = musb->mregs;
962 epnum = musb_ep->current_epnum;
963
964 spin_lock_irqsave(&musb->lock, flags);
965
966 if (musb_ep->desc) {
967 status = -EBUSY;
968 goto fail;
969 }
970 musb_ep->type = usb_endpoint_type(desc);
971
972 /* check direction and (later) maxpacket size against endpoint */
973 if (usb_endpoint_num(desc) != epnum)
974 goto fail;
975
976 /* REVISIT this rules out high bandwidth periodic transfers */
977 tmp = usb_endpoint_maxp(desc);
978 if (tmp & ~0x07ff) {
979 int ok;
980
981 if (usb_endpoint_dir_in(desc))
982 ok = musb->hb_iso_tx;
983 else
984 ok = musb->hb_iso_rx;
985
986 if (!ok) {
987 musb_dbg(musb, "no support for high bandwidth ISO");
988 goto fail;
989 }
990 musb_ep->hb_mult = (tmp >> 11) & 3;
991 } else {
992 musb_ep->hb_mult = 0;
993 }
994
995 musb_ep->packet_sz = tmp & 0x7ff;
996 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
997
998 /* enable the interrupts for the endpoint, set the endpoint
999 * packet size (or fail), set the mode, clear the fifo
1000 */
1001 musb_ep_select(mbase, epnum);
1002 if (usb_endpoint_dir_in(desc)) {
1003
1004 if (hw_ep->is_shared_fifo)
1005 musb_ep->is_in = 1;
1006 if (!musb_ep->is_in)
1007 goto fail;
1008
1009 if (tmp > hw_ep->max_packet_sz_tx) {
1010 musb_dbg(musb, "packet size beyond hardware FIFO size");
1011 goto fail;
1012 }
1013
1014 musb->intrtxe |= (1 << epnum);
1015 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1016
1017 /* REVISIT if can_bulk_split(), use by updating "tmp";
1018 * likewise high bandwidth periodic tx
1019 */
1020 /* Set TXMAXP with the FIFO size of the endpoint
1021 * to disable double buffering mode.
1022 */
1023 if (musb->double_buffer_not_ok) {
1024 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1025 } else {
1026 if (can_bulk_split(musb, musb_ep->type))
1027 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
1028 musb_ep->packet_sz) - 1;
1029 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1030 | (musb_ep->hb_mult << 11));
1031 }
1032
1033 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1034 if (musb_readw(regs, MUSB_TXCSR)
1035 & MUSB_TXCSR_FIFONOTEMPTY)
1036 csr |= MUSB_TXCSR_FLUSHFIFO;
1037 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1038 csr |= MUSB_TXCSR_P_ISO;
1039
1040 /* set twice in case of double buffering */
1041 musb_writew(regs, MUSB_TXCSR, csr);
1042 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1043 musb_writew(regs, MUSB_TXCSR, csr);
1044
1045 } else {
1046
1047 if (hw_ep->is_shared_fifo)
1048 musb_ep->is_in = 0;
1049 if (musb_ep->is_in)
1050 goto fail;
1051
1052 if (tmp > hw_ep->max_packet_sz_rx) {
1053 musb_dbg(musb, "packet size beyond hardware FIFO size");
1054 goto fail;
1055 }
1056
1057 musb->intrrxe |= (1 << epnum);
1058 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1059
1060 /* REVISIT if can_bulk_combine() use by updating "tmp"
1061 * likewise high bandwidth periodic rx
1062 */
1063 /* Set RXMAXP with the FIFO size of the endpoint
1064 * to disable double buffering mode.
1065 */
1066 if (musb->double_buffer_not_ok)
1067 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1068 else
1069 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1070 | (musb_ep->hb_mult << 11));
1071
1072 /* force shared fifo to OUT-only mode */
1073 if (hw_ep->is_shared_fifo) {
1074 csr = musb_readw(regs, MUSB_TXCSR);
1075 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1076 musb_writew(regs, MUSB_TXCSR, csr);
1077 }
1078
1079 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1080 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1081 csr |= MUSB_RXCSR_P_ISO;
1082 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1083 csr |= MUSB_RXCSR_DISNYET;
1084
1085 /* set twice in case of double buffering */
1086 musb_writew(regs, MUSB_RXCSR, csr);
1087 musb_writew(regs, MUSB_RXCSR, csr);
1088 }
1089
1090 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1091 * for some reason you run out of channels here.
1092 */
1093 if (is_dma_capable() && musb->dma_controller) {
1094 struct dma_controller *c = musb->dma_controller;
1095
1096 musb_ep->dma = c->channel_alloc(c, hw_ep,
1097 (desc->bEndpointAddress & USB_DIR_IN));
1098 } else
1099 musb_ep->dma = NULL;
1100
1101 musb_ep->desc = desc;
1102 musb_ep->busy = 0;
1103 musb_ep->wedged = 0;
1104 status = 0;
1105
1106 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1107 musb_driver_name, musb_ep->end_point.name,
1108 ({ char *s; switch (musb_ep->type) {
1109 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1110 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1111 default: s = "iso"; break;
1112 } s; }),
1113 musb_ep->is_in ? "IN" : "OUT",
1114 musb_ep->dma ? "dma, " : "",
1115 musb_ep->packet_sz);
1116
1117 schedule_work(&musb->irq_work);
1118
1119 fail:
1120 spin_unlock_irqrestore(&musb->lock, flags);
1121 return status;
1122 }
1123
1124 /*
1125 * Disable an endpoint flushing all requests queued.
1126 */
1127 static int musb_gadget_disable(struct usb_ep *ep)
1128 {
1129 unsigned long flags;
1130 struct musb *musb;
1131 u8 epnum;
1132 struct musb_ep *musb_ep;
1133 void __iomem *epio;
1134 int status = 0;
1135
1136 musb_ep = to_musb_ep(ep);
1137 musb = musb_ep->musb;
1138 epnum = musb_ep->current_epnum;
1139 epio = musb->endpoints[epnum].regs;
1140
1141 spin_lock_irqsave(&musb->lock, flags);
1142 musb_ep_select(musb->mregs, epnum);
1143
1144 /* zero the endpoint sizes */
1145 if (musb_ep->is_in) {
1146 musb->intrtxe &= ~(1 << epnum);
1147 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1148 musb_writew(epio, MUSB_TXMAXP, 0);
1149 } else {
1150 musb->intrrxe &= ~(1 << epnum);
1151 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1152 musb_writew(epio, MUSB_RXMAXP, 0);
1153 }
1154
1155 /* abort all pending DMA and requests */
1156 nuke(musb_ep, -ESHUTDOWN);
1157
1158 musb_ep->desc = NULL;
1159 musb_ep->end_point.desc = NULL;
1160
1161 schedule_work(&musb->irq_work);
1162
1163 spin_unlock_irqrestore(&(musb->lock), flags);
1164
1165 musb_dbg(musb, "%s", musb_ep->end_point.name);
1166
1167 return status;
1168 }
1169
1170 /*
1171 * Allocate a request for an endpoint.
1172 * Reused by ep0 code.
1173 */
1174 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1175 {
1176 struct musb_ep *musb_ep = to_musb_ep(ep);
1177 struct musb_request *request = NULL;
1178
1179 request = kzalloc(sizeof *request, gfp_flags);
1180 if (!request)
1181 return NULL;
1182
1183 request->request.dma = DMA_ADDR_INVALID;
1184 request->epnum = musb_ep->current_epnum;
1185 request->ep = musb_ep;
1186
1187 trace_musb_req_alloc(request);
1188 return &request->request;
1189 }
1190
1191 /*
1192 * Free a request
1193 * Reused by ep0 code.
1194 */
1195 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1196 {
1197 struct musb_request *request = to_musb_request(req);
1198
1199 trace_musb_req_free(request);
1200 kfree(request);
1201 }
1202
1203 static LIST_HEAD(buffers);
1204
1205 struct free_record {
1206 struct list_head list;
1207 struct device *dev;
1208 unsigned bytes;
1209 dma_addr_t dma;
1210 };
1211
1212 /*
1213 * Context: controller locked, IRQs blocked.
1214 */
1215 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1216 {
1217 trace_musb_req_start(req);
1218 musb_ep_select(musb->mregs, req->epnum);
1219 if (req->tx)
1220 txstate(musb, req);
1221 else
1222 rxstate(musb, req);
1223 }
1224
1225 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1226 gfp_t gfp_flags)
1227 {
1228 struct musb_ep *musb_ep;
1229 struct musb_request *request;
1230 struct musb *musb;
1231 int status = 0;
1232 unsigned long lockflags;
1233
1234 if (!ep || !req)
1235 return -EINVAL;
1236 if (!req->buf)
1237 return -ENODATA;
1238
1239 musb_ep = to_musb_ep(ep);
1240 musb = musb_ep->musb;
1241
1242 request = to_musb_request(req);
1243 request->musb = musb;
1244
1245 if (request->ep != musb_ep)
1246 return -EINVAL;
1247
1248 trace_musb_req_enq(request);
1249
1250 /* request is mine now... */
1251 request->request.actual = 0;
1252 request->request.status = -EINPROGRESS;
1253 request->epnum = musb_ep->current_epnum;
1254 request->tx = musb_ep->is_in;
1255
1256 map_dma_buffer(request, musb, musb_ep);
1257
1258 spin_lock_irqsave(&musb->lock, lockflags);
1259
1260 /* don't queue if the ep is down */
1261 if (!musb_ep->desc) {
1262 musb_dbg(musb, "req %p queued to %s while ep %s",
1263 req, ep->name, "disabled");
1264 status = -ESHUTDOWN;
1265 unmap_dma_buffer(request, musb);
1266 goto unlock;
1267 }
1268
1269 /* add request to the list */
1270 list_add_tail(&request->list, &musb_ep->req_list);
1271
1272 /* it this is the head of the queue, start i/o ... */
1273 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1274 musb_ep_restart(musb, request);
1275
1276 unlock:
1277 spin_unlock_irqrestore(&musb->lock, lockflags);
1278 return status;
1279 }
1280
1281 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1282 {
1283 struct musb_ep *musb_ep = to_musb_ep(ep);
1284 struct musb_request *req = to_musb_request(request);
1285 struct musb_request *r;
1286 unsigned long flags;
1287 int status = 0;
1288 struct musb *musb = musb_ep->musb;
1289
1290 if (!ep || !request || req->ep != musb_ep)
1291 return -EINVAL;
1292
1293 trace_musb_req_deq(req);
1294
1295 spin_lock_irqsave(&musb->lock, flags);
1296
1297 list_for_each_entry(r, &musb_ep->req_list, list) {
1298 if (r == req)
1299 break;
1300 }
1301 if (r != req) {
1302 dev_err(musb->controller, "request %p not queued to %s\n",
1303 request, ep->name);
1304 status = -EINVAL;
1305 goto done;
1306 }
1307
1308 /* if the hardware doesn't have the request, easy ... */
1309 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1310 musb_g_giveback(musb_ep, request, -ECONNRESET);
1311
1312 /* ... else abort the dma transfer ... */
1313 else if (is_dma_capable() && musb_ep->dma) {
1314 struct dma_controller *c = musb->dma_controller;
1315
1316 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1317 if (c->channel_abort)
1318 status = c->channel_abort(musb_ep->dma);
1319 else
1320 status = -EBUSY;
1321 if (status == 0)
1322 musb_g_giveback(musb_ep, request, -ECONNRESET);
1323 } else {
1324 /* NOTE: by sticking to easily tested hardware/driver states,
1325 * we leave counting of in-flight packets imprecise.
1326 */
1327 musb_g_giveback(musb_ep, request, -ECONNRESET);
1328 }
1329
1330 done:
1331 spin_unlock_irqrestore(&musb->lock, flags);
1332 return status;
1333 }
1334
1335 /*
1336 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1337 * data but will queue requests.
1338 *
1339 * exported to ep0 code
1340 */
1341 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1342 {
1343 struct musb_ep *musb_ep = to_musb_ep(ep);
1344 u8 epnum = musb_ep->current_epnum;
1345 struct musb *musb = musb_ep->musb;
1346 void __iomem *epio = musb->endpoints[epnum].regs;
1347 void __iomem *mbase;
1348 unsigned long flags;
1349 u16 csr;
1350 struct musb_request *request;
1351 int status = 0;
1352
1353 if (!ep)
1354 return -EINVAL;
1355 mbase = musb->mregs;
1356
1357 spin_lock_irqsave(&musb->lock, flags);
1358
1359 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1360 status = -EINVAL;
1361 goto done;
1362 }
1363
1364 musb_ep_select(mbase, epnum);
1365
1366 request = next_request(musb_ep);
1367 if (value) {
1368 if (request) {
1369 musb_dbg(musb, "request in progress, cannot halt %s",
1370 ep->name);
1371 status = -EAGAIN;
1372 goto done;
1373 }
1374 /* Cannot portably stall with non-empty FIFO */
1375 if (musb_ep->is_in) {
1376 csr = musb_readw(epio, MUSB_TXCSR);
1377 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1378 musb_dbg(musb, "FIFO busy, cannot halt %s",
1379 ep->name);
1380 status = -EAGAIN;
1381 goto done;
1382 }
1383 }
1384 } else
1385 musb_ep->wedged = 0;
1386
1387 /* set/clear the stall and toggle bits */
1388 musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear");
1389 if (musb_ep->is_in) {
1390 csr = musb_readw(epio, MUSB_TXCSR);
1391 csr |= MUSB_TXCSR_P_WZC_BITS
1392 | MUSB_TXCSR_CLRDATATOG;
1393 if (value)
1394 csr |= MUSB_TXCSR_P_SENDSTALL;
1395 else
1396 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1397 | MUSB_TXCSR_P_SENTSTALL);
1398 csr &= ~MUSB_TXCSR_TXPKTRDY;
1399 musb_writew(epio, MUSB_TXCSR, csr);
1400 } else {
1401 csr = musb_readw(epio, MUSB_RXCSR);
1402 csr |= MUSB_RXCSR_P_WZC_BITS
1403 | MUSB_RXCSR_FLUSHFIFO
1404 | MUSB_RXCSR_CLRDATATOG;
1405 if (value)
1406 csr |= MUSB_RXCSR_P_SENDSTALL;
1407 else
1408 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1409 | MUSB_RXCSR_P_SENTSTALL);
1410 musb_writew(epio, MUSB_RXCSR, csr);
1411 }
1412
1413 /* maybe start the first request in the queue */
1414 if (!musb_ep->busy && !value && request) {
1415 musb_dbg(musb, "restarting the request");
1416 musb_ep_restart(musb, request);
1417 }
1418
1419 done:
1420 spin_unlock_irqrestore(&musb->lock, flags);
1421 return status;
1422 }
1423
1424 /*
1425 * Sets the halt feature with the clear requests ignored
1426 */
1427 static int musb_gadget_set_wedge(struct usb_ep *ep)
1428 {
1429 struct musb_ep *musb_ep = to_musb_ep(ep);
1430
1431 if (!ep)
1432 return -EINVAL;
1433
1434 musb_ep->wedged = 1;
1435
1436 return usb_ep_set_halt(ep);
1437 }
1438
1439 static int musb_gadget_fifo_status(struct usb_ep *ep)
1440 {
1441 struct musb_ep *musb_ep = to_musb_ep(ep);
1442 void __iomem *epio = musb_ep->hw_ep->regs;
1443 int retval = -EINVAL;
1444
1445 if (musb_ep->desc && !musb_ep->is_in) {
1446 struct musb *musb = musb_ep->musb;
1447 int epnum = musb_ep->current_epnum;
1448 void __iomem *mbase = musb->mregs;
1449 unsigned long flags;
1450
1451 spin_lock_irqsave(&musb->lock, flags);
1452
1453 musb_ep_select(mbase, epnum);
1454 /* FIXME return zero unless RXPKTRDY is set */
1455 retval = musb_readw(epio, MUSB_RXCOUNT);
1456
1457 spin_unlock_irqrestore(&musb->lock, flags);
1458 }
1459 return retval;
1460 }
1461
1462 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1463 {
1464 struct musb_ep *musb_ep = to_musb_ep(ep);
1465 struct musb *musb = musb_ep->musb;
1466 u8 epnum = musb_ep->current_epnum;
1467 void __iomem *epio = musb->endpoints[epnum].regs;
1468 void __iomem *mbase;
1469 unsigned long flags;
1470 u16 csr;
1471
1472 mbase = musb->mregs;
1473
1474 spin_lock_irqsave(&musb->lock, flags);
1475 musb_ep_select(mbase, (u8) epnum);
1476
1477 /* disable interrupts */
1478 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1479
1480 if (musb_ep->is_in) {
1481 csr = musb_readw(epio, MUSB_TXCSR);
1482 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1483 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1484 /*
1485 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1486 * to interrupt current FIFO loading, but not flushing
1487 * the already loaded ones.
1488 */
1489 csr &= ~MUSB_TXCSR_TXPKTRDY;
1490 musb_writew(epio, MUSB_TXCSR, csr);
1491 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1492 musb_writew(epio, MUSB_TXCSR, csr);
1493 }
1494 } else {
1495 csr = musb_readw(epio, MUSB_RXCSR);
1496 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1497 musb_writew(epio, MUSB_RXCSR, csr);
1498 musb_writew(epio, MUSB_RXCSR, csr);
1499 }
1500
1501 /* re-enable interrupt */
1502 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1503 spin_unlock_irqrestore(&musb->lock, flags);
1504 }
1505
1506 static const struct usb_ep_ops musb_ep_ops = {
1507 .enable = musb_gadget_enable,
1508 .disable = musb_gadget_disable,
1509 .alloc_request = musb_alloc_request,
1510 .free_request = musb_free_request,
1511 .queue = musb_gadget_queue,
1512 .dequeue = musb_gadget_dequeue,
1513 .set_halt = musb_gadget_set_halt,
1514 .set_wedge = musb_gadget_set_wedge,
1515 .fifo_status = musb_gadget_fifo_status,
1516 .fifo_flush = musb_gadget_fifo_flush
1517 };
1518
1519 /* ----------------------------------------------------------------------- */
1520
1521 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1522 {
1523 struct musb *musb = gadget_to_musb(gadget);
1524
1525 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1526 }
1527
1528 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1529 {
1530 struct musb *musb = gadget_to_musb(gadget);
1531 void __iomem *mregs = musb->mregs;
1532 unsigned long flags;
1533 int status = -EINVAL;
1534 u8 power, devctl;
1535 int retries;
1536
1537 spin_lock_irqsave(&musb->lock, flags);
1538
1539 switch (musb->xceiv->otg->state) {
1540 case OTG_STATE_B_PERIPHERAL:
1541 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1542 * that's part of the standard usb 1.1 state machine, and
1543 * doesn't affect OTG transitions.
1544 */
1545 if (musb->may_wakeup && musb->is_suspended)
1546 break;
1547 goto done;
1548 case OTG_STATE_B_IDLE:
1549 /* Start SRP ... OTG not required. */
1550 devctl = musb_readb(mregs, MUSB_DEVCTL);
1551 musb_dbg(musb, "Sending SRP: devctl: %02x", devctl);
1552 devctl |= MUSB_DEVCTL_SESSION;
1553 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1554 devctl = musb_readb(mregs, MUSB_DEVCTL);
1555 retries = 100;
1556 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1557 devctl = musb_readb(mregs, MUSB_DEVCTL);
1558 if (retries-- < 1)
1559 break;
1560 }
1561 retries = 10000;
1562 while (devctl & MUSB_DEVCTL_SESSION) {
1563 devctl = musb_readb(mregs, MUSB_DEVCTL);
1564 if (retries-- < 1)
1565 break;
1566 }
1567
1568 spin_unlock_irqrestore(&musb->lock, flags);
1569 otg_start_srp(musb->xceiv->otg);
1570 spin_lock_irqsave(&musb->lock, flags);
1571
1572 /* Block idling for at least 1s */
1573 musb_platform_try_idle(musb,
1574 jiffies + msecs_to_jiffies(1 * HZ));
1575
1576 status = 0;
1577 goto done;
1578 default:
1579 musb_dbg(musb, "Unhandled wake: %s",
1580 usb_otg_state_string(musb->xceiv->otg->state));
1581 goto done;
1582 }
1583
1584 status = 0;
1585
1586 power = musb_readb(mregs, MUSB_POWER);
1587 power |= MUSB_POWER_RESUME;
1588 musb_writeb(mregs, MUSB_POWER, power);
1589 musb_dbg(musb, "issue wakeup");
1590
1591 /* FIXME do this next chunk in a timer callback, no udelay */
1592 mdelay(2);
1593
1594 power = musb_readb(mregs, MUSB_POWER);
1595 power &= ~MUSB_POWER_RESUME;
1596 musb_writeb(mregs, MUSB_POWER, power);
1597 done:
1598 spin_unlock_irqrestore(&musb->lock, flags);
1599 return status;
1600 }
1601
1602 static int
1603 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1604 {
1605 gadget->is_selfpowered = !!is_selfpowered;
1606 return 0;
1607 }
1608
1609 static void musb_pullup(struct musb *musb, int is_on)
1610 {
1611 u8 power;
1612
1613 power = musb_readb(musb->mregs, MUSB_POWER);
1614 if (is_on)
1615 power |= MUSB_POWER_SOFTCONN;
1616 else
1617 power &= ~MUSB_POWER_SOFTCONN;
1618
1619 /* FIXME if on, HdrcStart; if off, HdrcStop */
1620
1621 musb_dbg(musb, "gadget D+ pullup %s",
1622 is_on ? "on" : "off");
1623 musb_writeb(musb->mregs, MUSB_POWER, power);
1624 }
1625
1626 #if 0
1627 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1628 {
1629 musb_dbg(musb, "<= %s =>\n", __func__);
1630
1631 /*
1632 * FIXME iff driver's softconnect flag is set (as it is during probe,
1633 * though that can clear it), just musb_pullup().
1634 */
1635
1636 return -EINVAL;
1637 }
1638 #endif
1639
1640 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1641 {
1642 struct musb *musb = gadget_to_musb(gadget);
1643
1644 if (!musb->xceiv->set_power)
1645 return -EOPNOTSUPP;
1646 return usb_phy_set_power(musb->xceiv, mA);
1647 }
1648
1649 static void musb_gadget_work(struct work_struct *work)
1650 {
1651 struct musb *musb;
1652 unsigned long flags;
1653
1654 musb = container_of(work, struct musb, gadget_work.work);
1655 pm_runtime_get_sync(musb->controller);
1656 spin_lock_irqsave(&musb->lock, flags);
1657 musb_pullup(musb, musb->softconnect);
1658 spin_unlock_irqrestore(&musb->lock, flags);
1659 pm_runtime_mark_last_busy(musb->controller);
1660 pm_runtime_put_autosuspend(musb->controller);
1661 }
1662
1663 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1664 {
1665 struct musb *musb = gadget_to_musb(gadget);
1666 unsigned long flags;
1667
1668 is_on = !!is_on;
1669
1670 /* NOTE: this assumes we are sensing vbus; we'd rather
1671 * not pullup unless the B-session is active.
1672 */
1673 spin_lock_irqsave(&musb->lock, flags);
1674 if (is_on != musb->softconnect) {
1675 musb->softconnect = is_on;
1676 schedule_delayed_work(&musb->gadget_work, 0);
1677 }
1678 spin_unlock_irqrestore(&musb->lock, flags);
1679
1680 return 0;
1681 }
1682
1683 #ifdef CONFIG_BLACKFIN
1684 static struct usb_ep *musb_match_ep(struct usb_gadget *g,
1685 struct usb_endpoint_descriptor *desc,
1686 struct usb_ss_ep_comp_descriptor *ep_comp)
1687 {
1688 struct usb_ep *ep = NULL;
1689
1690 switch (usb_endpoint_type(desc)) {
1691 case USB_ENDPOINT_XFER_ISOC:
1692 case USB_ENDPOINT_XFER_BULK:
1693 if (usb_endpoint_dir_in(desc))
1694 ep = gadget_find_ep_by_name(g, "ep5in");
1695 else
1696 ep = gadget_find_ep_by_name(g, "ep6out");
1697 break;
1698 case USB_ENDPOINT_XFER_INT:
1699 if (usb_endpoint_dir_in(desc))
1700 ep = gadget_find_ep_by_name(g, "ep1in");
1701 else
1702 ep = gadget_find_ep_by_name(g, "ep2out");
1703 break;
1704 default:
1705 break;
1706 }
1707
1708 if (ep && usb_gadget_ep_match_desc(g, ep, desc, ep_comp))
1709 return ep;
1710
1711 return NULL;
1712 }
1713 #else
1714 #define musb_match_ep NULL
1715 #endif
1716
1717 static int musb_gadget_start(struct usb_gadget *g,
1718 struct usb_gadget_driver *driver);
1719 static int musb_gadget_stop(struct usb_gadget *g);
1720
1721 static const struct usb_gadget_ops musb_gadget_operations = {
1722 .get_frame = musb_gadget_get_frame,
1723 .wakeup = musb_gadget_wakeup,
1724 .set_selfpowered = musb_gadget_set_self_powered,
1725 /* .vbus_session = musb_gadget_vbus_session, */
1726 .vbus_draw = musb_gadget_vbus_draw,
1727 .pullup = musb_gadget_pullup,
1728 .udc_start = musb_gadget_start,
1729 .udc_stop = musb_gadget_stop,
1730 .match_ep = musb_match_ep,
1731 };
1732
1733 /* ----------------------------------------------------------------------- */
1734
1735 /* Registration */
1736
1737 /* Only this registration code "knows" the rule (from USB standards)
1738 * about there being only one external upstream port. It assumes
1739 * all peripheral ports are external...
1740 */
1741
1742 static void
1743 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1744 {
1745 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1746
1747 memset(ep, 0, sizeof *ep);
1748
1749 ep->current_epnum = epnum;
1750 ep->musb = musb;
1751 ep->hw_ep = hw_ep;
1752 ep->is_in = is_in;
1753
1754 INIT_LIST_HEAD(&ep->req_list);
1755
1756 sprintf(ep->name, "ep%d%s", epnum,
1757 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1758 is_in ? "in" : "out"));
1759 ep->end_point.name = ep->name;
1760 INIT_LIST_HEAD(&ep->end_point.ep_list);
1761 if (!epnum) {
1762 usb_ep_set_maxpacket_limit(&ep->end_point, 64);
1763 ep->end_point.caps.type_control = true;
1764 ep->end_point.ops = &musb_g_ep0_ops;
1765 musb->g.ep0 = &ep->end_point;
1766 } else {
1767 if (is_in)
1768 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx);
1769 else
1770 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx);
1771 ep->end_point.caps.type_iso = true;
1772 ep->end_point.caps.type_bulk = true;
1773 ep->end_point.caps.type_int = true;
1774 ep->end_point.ops = &musb_ep_ops;
1775 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1776 }
1777
1778 if (!epnum || hw_ep->is_shared_fifo) {
1779 ep->end_point.caps.dir_in = true;
1780 ep->end_point.caps.dir_out = true;
1781 } else if (is_in)
1782 ep->end_point.caps.dir_in = true;
1783 else
1784 ep->end_point.caps.dir_out = true;
1785 }
1786
1787 /*
1788 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1789 * to the rest of the driver state.
1790 */
1791 static inline void musb_g_init_endpoints(struct musb *musb)
1792 {
1793 u8 epnum;
1794 struct musb_hw_ep *hw_ep;
1795 unsigned count = 0;
1796
1797 /* initialize endpoint list just once */
1798 INIT_LIST_HEAD(&(musb->g.ep_list));
1799
1800 for (epnum = 0, hw_ep = musb->endpoints;
1801 epnum < musb->nr_endpoints;
1802 epnum++, hw_ep++) {
1803 if (hw_ep->is_shared_fifo /* || !epnum */) {
1804 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1805 count++;
1806 } else {
1807 if (hw_ep->max_packet_sz_tx) {
1808 init_peripheral_ep(musb, &hw_ep->ep_in,
1809 epnum, 1);
1810 count++;
1811 }
1812 if (hw_ep->max_packet_sz_rx) {
1813 init_peripheral_ep(musb, &hw_ep->ep_out,
1814 epnum, 0);
1815 count++;
1816 }
1817 }
1818 }
1819 }
1820
1821 /* called once during driver setup to initialize and link into
1822 * the driver model; memory is zeroed.
1823 */
1824 int musb_gadget_setup(struct musb *musb)
1825 {
1826 int status;
1827
1828 /* REVISIT minor race: if (erroneously) setting up two
1829 * musb peripherals at the same time, only the bus lock
1830 * is probably held.
1831 */
1832
1833 musb->g.ops = &musb_gadget_operations;
1834 musb->g.max_speed = USB_SPEED_HIGH;
1835 musb->g.speed = USB_SPEED_UNKNOWN;
1836
1837 MUSB_DEV_MODE(musb);
1838 musb->xceiv->otg->default_a = 0;
1839 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1840
1841 /* this "gadget" abstracts/virtualizes the controller */
1842 musb->g.name = musb_driver_name;
1843 #if IS_ENABLED(CONFIG_USB_MUSB_DUAL_ROLE)
1844 musb->g.is_otg = 1;
1845 #elif IS_ENABLED(CONFIG_USB_MUSB_GADGET)
1846 musb->g.is_otg = 0;
1847 #endif
1848 INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work);
1849 musb_g_init_endpoints(musb);
1850
1851 musb->is_active = 0;
1852 musb_platform_try_idle(musb, 0);
1853
1854 status = usb_add_gadget_udc(musb->controller, &musb->g);
1855 if (status)
1856 goto err;
1857
1858 return 0;
1859 err:
1860 musb->g.dev.parent = NULL;
1861 device_unregister(&musb->g.dev);
1862 return status;
1863 }
1864
1865 void musb_gadget_cleanup(struct musb *musb)
1866 {
1867 if (musb->port_mode == MUSB_PORT_MODE_HOST)
1868 return;
1869
1870 cancel_delayed_work_sync(&musb->gadget_work);
1871 usb_del_gadget_udc(&musb->g);
1872 }
1873
1874 /*
1875 * Register the gadget driver. Used by gadget drivers when
1876 * registering themselves with the controller.
1877 *
1878 * -EINVAL something went wrong (not driver)
1879 * -EBUSY another gadget is already using the controller
1880 * -ENOMEM no memory to perform the operation
1881 *
1882 * @param driver the gadget driver
1883 * @return <0 if error, 0 if everything is fine
1884 */
1885 static int musb_gadget_start(struct usb_gadget *g,
1886 struct usb_gadget_driver *driver)
1887 {
1888 struct musb *musb = gadget_to_musb(g);
1889 struct usb_otg *otg = musb->xceiv->otg;
1890 unsigned long flags;
1891 int retval = 0;
1892
1893 if (driver->max_speed < USB_SPEED_HIGH) {
1894 retval = -EINVAL;
1895 goto err;
1896 }
1897
1898 pm_runtime_get_sync(musb->controller);
1899
1900 musb->softconnect = 0;
1901 musb->gadget_driver = driver;
1902
1903 spin_lock_irqsave(&musb->lock, flags);
1904 musb->is_active = 1;
1905
1906 otg_set_peripheral(otg, &musb->g);
1907 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1908 spin_unlock_irqrestore(&musb->lock, flags);
1909
1910 musb_start(musb);
1911
1912 /* REVISIT: funcall to other code, which also
1913 * handles power budgeting ... this way also
1914 * ensures HdrcStart is indirectly called.
1915 */
1916 if (musb->xceiv->last_event == USB_EVENT_ID)
1917 musb_platform_set_vbus(musb, 1);
1918
1919 pm_runtime_mark_last_busy(musb->controller);
1920 pm_runtime_put_autosuspend(musb->controller);
1921
1922 return 0;
1923
1924 err:
1925 return retval;
1926 }
1927
1928 /*
1929 * Unregister the gadget driver. Used by gadget drivers when
1930 * unregistering themselves from the controller.
1931 *
1932 * @param driver the gadget driver to unregister
1933 */
1934 static int musb_gadget_stop(struct usb_gadget *g)
1935 {
1936 struct musb *musb = gadget_to_musb(g);
1937 unsigned long flags;
1938
1939 pm_runtime_get_sync(musb->controller);
1940
1941 /*
1942 * REVISIT always use otg_set_peripheral() here too;
1943 * this needs to shut down the OTG engine.
1944 */
1945
1946 spin_lock_irqsave(&musb->lock, flags);
1947
1948 musb_hnp_stop(musb);
1949
1950 (void) musb_gadget_vbus_draw(&musb->g, 0);
1951
1952 musb->xceiv->otg->state = OTG_STATE_UNDEFINED;
1953 musb_stop(musb);
1954 otg_set_peripheral(musb->xceiv->otg, NULL);
1955
1956 musb->is_active = 0;
1957 musb->gadget_driver = NULL;
1958 musb_platform_try_idle(musb, 0);
1959 spin_unlock_irqrestore(&musb->lock, flags);
1960
1961 /*
1962 * FIXME we need to be able to register another
1963 * gadget driver here and have everything work;
1964 * that currently misbehaves.
1965 */
1966
1967 pm_runtime_mark_last_busy(musb->controller);
1968 pm_runtime_put_autosuspend(musb->controller);
1969
1970 return 0;
1971 }
1972
1973 /* ----------------------------------------------------------------------- */
1974
1975 /* lifecycle operations called through plat_uds.c */
1976
1977 void musb_g_resume(struct musb *musb)
1978 {
1979 musb->is_suspended = 0;
1980 switch (musb->xceiv->otg->state) {
1981 case OTG_STATE_B_IDLE:
1982 break;
1983 case OTG_STATE_B_WAIT_ACON:
1984 case OTG_STATE_B_PERIPHERAL:
1985 musb->is_active = 1;
1986 if (musb->gadget_driver && musb->gadget_driver->resume) {
1987 spin_unlock(&musb->lock);
1988 musb->gadget_driver->resume(&musb->g);
1989 spin_lock(&musb->lock);
1990 }
1991 break;
1992 default:
1993 WARNING("unhandled RESUME transition (%s)\n",
1994 usb_otg_state_string(musb->xceiv->otg->state));
1995 }
1996 }
1997
1998 /* called when SOF packets stop for 3+ msec */
1999 void musb_g_suspend(struct musb *musb)
2000 {
2001 u8 devctl;
2002
2003 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2004 musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl);
2005
2006 switch (musb->xceiv->otg->state) {
2007 case OTG_STATE_B_IDLE:
2008 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2009 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2010 break;
2011 case OTG_STATE_B_PERIPHERAL:
2012 musb->is_suspended = 1;
2013 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2014 spin_unlock(&musb->lock);
2015 musb->gadget_driver->suspend(&musb->g);
2016 spin_lock(&musb->lock);
2017 }
2018 break;
2019 default:
2020 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2021 * A_PERIPHERAL may need care too
2022 */
2023 WARNING("unhandled SUSPEND transition (%s)",
2024 usb_otg_state_string(musb->xceiv->otg->state));
2025 }
2026 }
2027
2028 /* Called during SRP */
2029 void musb_g_wakeup(struct musb *musb)
2030 {
2031 musb_gadget_wakeup(&musb->g);
2032 }
2033
2034 /* called when VBUS drops below session threshold, and in other cases */
2035 void musb_g_disconnect(struct musb *musb)
2036 {
2037 void __iomem *mregs = musb->mregs;
2038 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2039
2040 musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl);
2041
2042 /* clear HR */
2043 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2044
2045 /* don't draw vbus until new b-default session */
2046 (void) musb_gadget_vbus_draw(&musb->g, 0);
2047
2048 musb->g.speed = USB_SPEED_UNKNOWN;
2049 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2050 spin_unlock(&musb->lock);
2051 musb->gadget_driver->disconnect(&musb->g);
2052 spin_lock(&musb->lock);
2053 }
2054
2055 switch (musb->xceiv->otg->state) {
2056 default:
2057 musb_dbg(musb, "Unhandled disconnect %s, setting a_idle",
2058 usb_otg_state_string(musb->xceiv->otg->state));
2059 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2060 MUSB_HST_MODE(musb);
2061 break;
2062 case OTG_STATE_A_PERIPHERAL:
2063 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2064 MUSB_HST_MODE(musb);
2065 break;
2066 case OTG_STATE_B_WAIT_ACON:
2067 case OTG_STATE_B_HOST:
2068 case OTG_STATE_B_PERIPHERAL:
2069 case OTG_STATE_B_IDLE:
2070 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2071 break;
2072 case OTG_STATE_B_SRP_INIT:
2073 break;
2074 }
2075
2076 musb->is_active = 0;
2077 }
2078
2079 void musb_g_reset(struct musb *musb)
2080 __releases(musb->lock)
2081 __acquires(musb->lock)
2082 {
2083 void __iomem *mbase = musb->mregs;
2084 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2085 u8 power;
2086
2087 musb_dbg(musb, "<== %s driver '%s'",
2088 (devctl & MUSB_DEVCTL_BDEVICE)
2089 ? "B-Device" : "A-Device",
2090 musb->gadget_driver
2091 ? musb->gadget_driver->driver.name
2092 : NULL
2093 );
2094
2095 /* report reset, if we didn't already (flushing EP state) */
2096 if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) {
2097 spin_unlock(&musb->lock);
2098 usb_gadget_udc_reset(&musb->g, musb->gadget_driver);
2099 spin_lock(&musb->lock);
2100 }
2101
2102 /* clear HR */
2103 else if (devctl & MUSB_DEVCTL_HR)
2104 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2105
2106
2107 /* what speed did we negotiate? */
2108 power = musb_readb(mbase, MUSB_POWER);
2109 musb->g.speed = (power & MUSB_POWER_HSMODE)
2110 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2111
2112 /* start in USB_STATE_DEFAULT */
2113 musb->is_active = 1;
2114 musb->is_suspended = 0;
2115 MUSB_DEV_MODE(musb);
2116 musb->address = 0;
2117 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2118
2119 musb->may_wakeup = 0;
2120 musb->g.b_hnp_enable = 0;
2121 musb->g.a_alt_hnp_support = 0;
2122 musb->g.a_hnp_support = 0;
2123 musb->g.quirk_zlp_not_supp = 1;
2124
2125 /* Normal reset, as B-Device;
2126 * or else after HNP, as A-Device
2127 */
2128 if (!musb->g.is_otg) {
2129 /* USB device controllers that are not OTG compatible
2130 * may not have DEVCTL register in silicon.
2131 * In that case, do not rely on devctl for setting
2132 * peripheral mode.
2133 */
2134 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2135 musb->g.is_a_peripheral = 0;
2136 } else if (devctl & MUSB_DEVCTL_BDEVICE) {
2137 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2138 musb->g.is_a_peripheral = 0;
2139 } else {
2140 musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
2141 musb->g.is_a_peripheral = 1;
2142 }
2143
2144 /* start with default limits on VBUS power draw */
2145 (void) musb_gadget_vbus_draw(&musb->g, 8);
2146 }
Linux kernel - Deliverables
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