2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
48 #include "musb_core.h"
51 /* MUSB PERIPHERAL status 3-mar-2006:
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
81 * - ISO not tested ... might work, but only weakly isochronous
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
93 /* ----------------------------------------------------------------------- */
96 * Immediately complete a request.
98 * @param request the request to complete
99 * @param status the status to complete the request with
100 * Context: controller locked, IRQs blocked.
102 void musb_g_giveback(
104 struct usb_request
*request
,
106 __releases(ep
->musb
->lock
)
107 __acquires(ep
->musb
->lock
)
109 struct musb_request
*req
;
113 req
= to_musb_request(request
);
115 list_del(&request
->list
);
116 if (req
->request
.status
== -EINPROGRESS
)
117 req
->request
.status
= status
;
121 spin_unlock(&musb
->lock
);
122 if (is_dma_capable()) {
124 dma_unmap_single(musb
->controller
,
130 req
->request
.dma
= DMA_ADDR_INVALID
;
132 } else if (req
->request
.dma
!= DMA_ADDR_INVALID
)
133 dma_sync_single_for_cpu(musb
->controller
,
140 if (request
->status
== 0)
141 DBG(5, "%s done request %p, %d/%d\n",
142 ep
->end_point
.name
, request
,
143 req
->request
.actual
, req
->request
.length
);
145 DBG(2, "%s request %p, %d/%d fault %d\n",
146 ep
->end_point
.name
, request
,
147 req
->request
.actual
, req
->request
.length
,
149 req
->request
.complete(&req
->ep
->end_point
, &req
->request
);
150 spin_lock(&musb
->lock
);
154 /* ----------------------------------------------------------------------- */
157 * Abort requests queued to an endpoint using the status. Synchronous.
158 * caller locked controller and blocked irqs, and selected this ep.
160 static void nuke(struct musb_ep
*ep
, const int status
)
162 struct musb_request
*req
= NULL
;
163 void __iomem
*epio
= ep
->musb
->endpoints
[ep
->current_epnum
].regs
;
167 if (is_dma_capable() && ep
->dma
) {
168 struct dma_controller
*c
= ep
->musb
->dma_controller
;
173 * The programming guide says that we must not clear
174 * the DMAMODE bit before DMAENAB, so we only
175 * clear it in the second write...
177 musb_writew(epio
, MUSB_TXCSR
,
178 MUSB_TXCSR_DMAMODE
| MUSB_TXCSR_FLUSHFIFO
);
179 musb_writew(epio
, MUSB_TXCSR
,
180 0 | MUSB_TXCSR_FLUSHFIFO
);
182 musb_writew(epio
, MUSB_RXCSR
,
183 0 | MUSB_RXCSR_FLUSHFIFO
);
184 musb_writew(epio
, MUSB_RXCSR
,
185 0 | MUSB_RXCSR_FLUSHFIFO
);
188 value
= c
->channel_abort(ep
->dma
);
189 DBG(value
? 1 : 6, "%s: abort DMA --> %d\n", ep
->name
, value
);
190 c
->channel_release(ep
->dma
);
194 while (!list_empty(&(ep
->req_list
))) {
195 req
= container_of(ep
->req_list
.next
, struct musb_request
,
197 musb_g_giveback(ep
, &req
->request
, status
);
201 /* ----------------------------------------------------------------------- */
203 /* Data transfers - pure PIO, pure DMA, or mixed mode */
206 * This assumes the separate CPPI engine is responding to DMA requests
207 * from the usb core ... sequenced a bit differently from mentor dma.
210 static inline int max_ep_writesize(struct musb
*musb
, struct musb_ep
*ep
)
212 if (can_bulk_split(musb
, ep
->type
))
213 return ep
->hw_ep
->max_packet_sz_tx
;
215 return ep
->packet_sz
;
219 #ifdef CONFIG_USB_INVENTRA_DMA
221 /* Peripheral tx (IN) using Mentor DMA works as follows:
222 Only mode 0 is used for transfers <= wPktSize,
223 mode 1 is used for larger transfers,
225 One of the following happens:
226 - Host sends IN token which causes an endpoint interrupt
228 -> if DMA is currently busy, exit.
229 -> if queue is non-empty, txstate().
231 - Request is queued by the gadget driver.
232 -> if queue was previously empty, txstate()
237 | (data is transferred to the FIFO, then sent out when
238 | IN token(s) are recd from Host.
239 | -> DMA interrupt on completion
241 | -> stop DMA, ~DMAENAB,
242 | -> set TxPktRdy for last short pkt or zlp
243 | -> Complete Request
244 | -> Continue next request (call txstate)
245 |___________________________________|
247 * Non-Mentor DMA engines can of course work differently, such as by
248 * upleveling from irq-per-packet to irq-per-buffer.
254 * An endpoint is transmitting data. This can be called either from
255 * the IRQ routine or from ep.queue() to kickstart a request on an
258 * Context: controller locked, IRQs blocked, endpoint selected
260 static void txstate(struct musb
*musb
, struct musb_request
*req
)
262 u8 epnum
= req
->epnum
;
263 struct musb_ep
*musb_ep
;
264 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
265 struct usb_request
*request
;
266 u16 fifo_count
= 0, csr
;
271 /* we shouldn't get here while DMA is active ... but we do ... */
272 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
273 DBG(4, "dma pending...\n");
277 /* read TXCSR before */
278 csr
= musb_readw(epio
, MUSB_TXCSR
);
280 request
= &req
->request
;
281 fifo_count
= min(max_ep_writesize(musb
, musb_ep
),
282 (int)(request
->length
- request
->actual
));
284 if (csr
& MUSB_TXCSR_TXPKTRDY
) {
285 DBG(5, "%s old packet still ready , txcsr %03x\n",
286 musb_ep
->end_point
.name
, csr
);
290 if (csr
& MUSB_TXCSR_P_SENDSTALL
) {
291 DBG(5, "%s stalling, txcsr %03x\n",
292 musb_ep
->end_point
.name
, csr
);
296 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
297 epnum
, musb_ep
->packet_sz
, fifo_count
,
300 #ifndef CONFIG_MUSB_PIO_ONLY
301 if (is_dma_capable() && musb_ep
->dma
) {
302 struct dma_controller
*c
= musb
->dma_controller
;
305 /* setup DMA, then program endpoint CSR */
306 request_size
= min_t(size_t, request
->length
- request
->actual
,
307 musb_ep
->dma
->max_len
);
309 use_dma
= (request
->dma
!= DMA_ADDR_INVALID
);
311 /* MUSB_TXCSR_P_ISO is still set correctly */
313 #ifdef CONFIG_USB_INVENTRA_DMA
315 if (request_size
< musb_ep
->packet_sz
)
316 musb_ep
->dma
->desired_mode
= 0;
318 musb_ep
->dma
->desired_mode
= 1;
320 use_dma
= use_dma
&& c
->channel_program(
321 musb_ep
->dma
, musb_ep
->packet_sz
,
322 musb_ep
->dma
->desired_mode
,
323 request
->dma
+ request
->actual
, request_size
);
325 if (musb_ep
->dma
->desired_mode
== 0) {
327 * We must not clear the DMAMODE bit
328 * before the DMAENAB bit -- and the
329 * latter doesn't always get cleared
330 * before we get here...
332 csr
&= ~(MUSB_TXCSR_AUTOSET
333 | MUSB_TXCSR_DMAENAB
);
334 musb_writew(epio
, MUSB_TXCSR
, csr
335 | MUSB_TXCSR_P_WZC_BITS
);
336 csr
&= ~MUSB_TXCSR_DMAMODE
;
337 csr
|= (MUSB_TXCSR_DMAENAB
|
339 /* against programming guide */
341 csr
|= (MUSB_TXCSR_DMAENAB
344 if (!musb_ep
->hb_mult
)
345 csr
|= MUSB_TXCSR_AUTOSET
;
347 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
349 musb_writew(epio
, MUSB_TXCSR
, csr
);
353 #elif defined(CONFIG_USB_TI_CPPI_DMA)
354 /* program endpoint CSR first, then setup DMA */
355 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
356 csr
|= MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_DMAMODE
|
358 musb_writew(epio
, MUSB_TXCSR
,
359 (MUSB_TXCSR_P_WZC_BITS
& ~MUSB_TXCSR_P_UNDERRUN
)
362 /* ensure writebuffer is empty */
363 csr
= musb_readw(epio
, MUSB_TXCSR
);
365 /* NOTE host side sets DMAENAB later than this; both are
366 * OK since the transfer dma glue (between CPPI and Mentor
367 * fifos) just tells CPPI it could start. Data only moves
368 * to the USB TX fifo when both fifos are ready.
371 /* "mode" is irrelevant here; handle terminating ZLPs like
372 * PIO does, since the hardware RNDIS mode seems unreliable
373 * except for the last-packet-is-already-short case.
375 use_dma
= use_dma
&& c
->channel_program(
376 musb_ep
->dma
, musb_ep
->packet_sz
,
378 request
->dma
+ request
->actual
,
381 c
->channel_release(musb_ep
->dma
);
383 csr
&= ~MUSB_TXCSR_DMAENAB
;
384 musb_writew(epio
, MUSB_TXCSR
, csr
);
385 /* invariant: prequest->buf is non-null */
387 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
388 use_dma
= use_dma
&& c
->channel_program(
389 musb_ep
->dma
, musb_ep
->packet_sz
,
391 request
->dma
+ request
->actual
,
398 musb_write_fifo(musb_ep
->hw_ep
, fifo_count
,
399 (u8
*) (request
->buf
+ request
->actual
));
400 request
->actual
+= fifo_count
;
401 csr
|= MUSB_TXCSR_TXPKTRDY
;
402 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
403 musb_writew(epio
, MUSB_TXCSR
, csr
);
406 /* host may already have the data when this message shows... */
407 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
408 musb_ep
->end_point
.name
, use_dma
? "dma" : "pio",
409 request
->actual
, request
->length
,
410 musb_readw(epio
, MUSB_TXCSR
),
412 musb_readw(epio
, MUSB_TXMAXP
));
416 * FIFO state update (e.g. data ready).
417 * Called from IRQ, with controller locked.
419 void musb_g_tx(struct musb
*musb
, u8 epnum
)
422 struct usb_request
*request
;
423 u8 __iomem
*mbase
= musb
->mregs
;
424 struct musb_ep
*musb_ep
= &musb
->endpoints
[epnum
].ep_in
;
425 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
426 struct dma_channel
*dma
;
428 musb_ep_select(mbase
, epnum
);
429 request
= next_request(musb_ep
);
431 csr
= musb_readw(epio
, MUSB_TXCSR
);
432 DBG(4, "<== %s, txcsr %04x\n", musb_ep
->end_point
.name
, csr
);
434 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
437 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
438 * probably rates reporting as a host error.
440 if (csr
& MUSB_TXCSR_P_SENTSTALL
) {
441 csr
|= MUSB_TXCSR_P_WZC_BITS
;
442 csr
&= ~MUSB_TXCSR_P_SENTSTALL
;
443 musb_writew(epio
, MUSB_TXCSR
, csr
);
447 if (csr
& MUSB_TXCSR_P_UNDERRUN
) {
448 /* We NAKed, no big deal... little reason to care. */
449 csr
|= MUSB_TXCSR_P_WZC_BITS
;
450 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
451 musb_writew(epio
, MUSB_TXCSR
, csr
);
452 DBG(20, "underrun on ep%d, req %p\n", epnum
, request
);
455 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
457 * SHOULD NOT HAPPEN... has with CPPI though, after
458 * changing SENDSTALL (and other cases); harmless?
460 DBG(5, "%s dma still busy?\n", musb_ep
->end_point
.name
);
467 if (dma
&& (csr
& MUSB_TXCSR_DMAENAB
)) {
469 csr
|= MUSB_TXCSR_P_WZC_BITS
;
470 csr
&= ~(MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_P_UNDERRUN
|
471 MUSB_TXCSR_TXPKTRDY
);
472 musb_writew(epio
, MUSB_TXCSR
, csr
);
473 /* Ensure writebuffer is empty. */
474 csr
= musb_readw(epio
, MUSB_TXCSR
);
475 request
->actual
+= musb_ep
->dma
->actual_len
;
476 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
477 epnum
, csr
, musb_ep
->dma
->actual_len
, request
);
480 if (is_dma
|| request
->actual
== request
->length
) {
482 * First, maybe a terminating short packet. Some DMA
483 * engines might handle this by themselves.
485 if ((request
->zero
&& request
->length
486 && request
->length
% musb_ep
->packet_sz
== 0)
487 #ifdef CONFIG_USB_INVENTRA_DMA
488 || (is_dma
&& (!dma
->desired_mode
||
490 (musb_ep
->packet_sz
- 1))))
494 * On DMA completion, FIFO may not be
497 if (csr
& MUSB_TXCSR_TXPKTRDY
)
500 DBG(4, "sending zero pkt\n");
501 musb_writew(epio
, MUSB_TXCSR
, MUSB_TXCSR_MODE
502 | MUSB_TXCSR_TXPKTRDY
);
506 if (request
->actual
== request
->length
) {
507 musb_g_giveback(musb_ep
, request
, 0);
508 request
= musb_ep
->desc
? next_request(musb_ep
) : NULL
;
510 DBG(4, "%s idle now\n",
511 musb_ep
->end_point
.name
);
517 txstate(musb
, to_musb_request(request
));
521 /* ------------------------------------------------------------ */
523 #ifdef CONFIG_USB_INVENTRA_DMA
525 /* Peripheral rx (OUT) using Mentor DMA works as follows:
526 - Only mode 0 is used.
528 - Request is queued by the gadget class driver.
529 -> if queue was previously empty, rxstate()
531 - Host sends OUT token which causes an endpoint interrupt
533 | -> if request queued, call rxstate
535 | | -> DMA interrupt on completion
539 | | -> if data recd = max expected
540 | | by the request, or host
541 | | sent a short packet,
542 | | complete the request,
543 | | and start the next one.
544 | |_____________________________________|
545 | else just wait for the host
546 | to send the next OUT token.
547 |__________________________________________________|
549 * Non-Mentor DMA engines can of course work differently.
555 * Context: controller locked, IRQs blocked, endpoint selected
557 static void rxstate(struct musb
*musb
, struct musb_request
*req
)
559 const u8 epnum
= req
->epnum
;
560 struct usb_request
*request
= &req
->request
;
561 struct musb_ep
*musb_ep
;
562 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
563 unsigned fifo_count
= 0;
565 u16 csr
= musb_readw(epio
, MUSB_RXCSR
);
566 struct musb_hw_ep
*hw_ep
= &musb
->endpoints
[epnum
];
568 if (hw_ep
->is_shared_fifo
)
569 musb_ep
= &hw_ep
->ep_in
;
571 musb_ep
= &hw_ep
->ep_out
;
573 len
= musb_ep
->packet_sz
;
575 /* We shouldn't get here while DMA is active, but we do... */
576 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
577 DBG(4, "DMA pending...\n");
581 if (csr
& MUSB_RXCSR_P_SENDSTALL
) {
582 DBG(5, "%s stalling, RXCSR %04x\n",
583 musb_ep
->end_point
.name
, csr
);
587 if (is_cppi_enabled() && musb_ep
->dma
) {
588 struct dma_controller
*c
= musb
->dma_controller
;
589 struct dma_channel
*channel
= musb_ep
->dma
;
591 /* NOTE: CPPI won't actually stop advancing the DMA
592 * queue after short packet transfers, so this is almost
593 * always going to run as IRQ-per-packet DMA so that
594 * faults will be handled correctly.
596 if (c
->channel_program(channel
,
598 !request
->short_not_ok
,
599 request
->dma
+ request
->actual
,
600 request
->length
- request
->actual
)) {
602 /* make sure that if an rxpkt arrived after the irq,
603 * the cppi engine will be ready to take it as soon
606 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
607 | MUSB_RXCSR_DMAMODE
);
608 csr
|= MUSB_RXCSR_DMAENAB
| MUSB_RXCSR_P_WZC_BITS
;
609 musb_writew(epio
, MUSB_RXCSR
, csr
);
614 if (csr
& MUSB_RXCSR_RXPKTRDY
) {
615 len
= musb_readw(epio
, MUSB_RXCOUNT
);
616 if (request
->actual
< request
->length
) {
617 #ifdef CONFIG_USB_INVENTRA_DMA
618 if (is_dma_capable() && musb_ep
->dma
) {
619 struct dma_controller
*c
;
620 struct dma_channel
*channel
;
623 c
= musb
->dma_controller
;
624 channel
= musb_ep
->dma
;
626 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
627 * mode 0 only. So we do not get endpoint interrupts due to DMA
628 * completion. We only get interrupts from DMA controller.
630 * We could operate in DMA mode 1 if we knew the size of the tranfer
631 * in advance. For mass storage class, request->length = what the host
632 * sends, so that'd work. But for pretty much everything else,
633 * request->length is routinely more than what the host sends. For
634 * most these gadgets, end of is signified either by a short packet,
635 * or filling the last byte of the buffer. (Sending extra data in
636 * that last pckate should trigger an overflow fault.) But in mode 1,
637 * we don't get DMA completion interrrupt for short packets.
639 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
640 * to get endpoint interrupt on every DMA req, but that didn't seem
643 * REVISIT an updated g_file_storage can set req->short_not_ok, which
644 * then becomes usable as a runtime "use mode 1" hint...
647 csr
|= MUSB_RXCSR_DMAENAB
;
648 if (!musb_ep
->hb_mult
)
649 csr
|= MUSB_RXCSR_AUTOCLEAR
;
651 /* csr |= MUSB_RXCSR_DMAMODE; */
653 /* this special sequence (enabling and then
654 * disabling MUSB_RXCSR_DMAMODE) is required
655 * to get DMAReq to activate
657 musb_writew(epio
, MUSB_RXCSR
,
658 csr
| MUSB_RXCSR_DMAMODE
);
660 musb_writew(epio
, MUSB_RXCSR
, csr
);
662 if (request
->actual
< request
->length
) {
663 int transfer_size
= 0;
665 transfer_size
= min(request
->length
- request
->actual
,
668 transfer_size
= min(request
->length
- request
->actual
,
671 if (transfer_size
<= musb_ep
->packet_sz
)
672 musb_ep
->dma
->desired_mode
= 0;
674 musb_ep
->dma
->desired_mode
= 1;
676 use_dma
= c
->channel_program(
679 channel
->desired_mode
,
688 #endif /* Mentor's DMA */
690 fifo_count
= request
->length
- request
->actual
;
691 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
692 musb_ep
->end_point
.name
,
696 fifo_count
= min_t(unsigned, len
, fifo_count
);
698 #ifdef CONFIG_USB_TUSB_OMAP_DMA
699 if (tusb_dma_omap() && musb_ep
->dma
) {
700 struct dma_controller
*c
= musb
->dma_controller
;
701 struct dma_channel
*channel
= musb_ep
->dma
;
702 u32 dma_addr
= request
->dma
+ request
->actual
;
705 ret
= c
->channel_program(channel
,
707 channel
->desired_mode
,
715 musb_read_fifo(musb_ep
->hw_ep
, fifo_count
, (u8
*)
716 (request
->buf
+ request
->actual
));
717 request
->actual
+= fifo_count
;
719 /* REVISIT if we left anything in the fifo, flush
720 * it and report -EOVERFLOW
724 csr
|= MUSB_RXCSR_P_WZC_BITS
;
725 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
726 musb_writew(epio
, MUSB_RXCSR
, csr
);
730 /* reach the end or short packet detected */
731 if (request
->actual
== request
->length
|| len
< musb_ep
->packet_sz
)
732 musb_g_giveback(musb_ep
, request
, 0);
736 * Data ready for a request; called from IRQ
738 void musb_g_rx(struct musb
*musb
, u8 epnum
)
741 struct usb_request
*request
;
742 void __iomem
*mbase
= musb
->mregs
;
743 struct musb_ep
*musb_ep
;
744 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
745 struct dma_channel
*dma
;
746 struct musb_hw_ep
*hw_ep
= &musb
->endpoints
[epnum
];
748 if (hw_ep
->is_shared_fifo
)
749 musb_ep
= &hw_ep
->ep_in
;
751 musb_ep
= &hw_ep
->ep_out
;
753 musb_ep_select(mbase
, epnum
);
755 request
= next_request(musb_ep
);
759 csr
= musb_readw(epio
, MUSB_RXCSR
);
760 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
762 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep
->end_point
.name
,
763 csr
, dma
? " (dma)" : "", request
);
765 if (csr
& MUSB_RXCSR_P_SENTSTALL
) {
766 csr
|= MUSB_RXCSR_P_WZC_BITS
;
767 csr
&= ~MUSB_RXCSR_P_SENTSTALL
;
768 musb_writew(epio
, MUSB_RXCSR
, csr
);
772 if (csr
& MUSB_RXCSR_P_OVERRUN
) {
773 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
774 csr
&= ~MUSB_RXCSR_P_OVERRUN
;
775 musb_writew(epio
, MUSB_RXCSR
, csr
);
777 DBG(3, "%s iso overrun on %p\n", musb_ep
->name
, request
);
778 if (request
&& request
->status
== -EINPROGRESS
)
779 request
->status
= -EOVERFLOW
;
781 if (csr
& MUSB_RXCSR_INCOMPRX
) {
782 /* REVISIT not necessarily an error */
783 DBG(4, "%s, incomprx\n", musb_ep
->end_point
.name
);
786 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
787 /* "should not happen"; likely RXPKTRDY pending for DMA */
788 DBG((csr
& MUSB_RXCSR_DMAENAB
) ? 4 : 1,
789 "%s busy, csr %04x\n",
790 musb_ep
->end_point
.name
, csr
);
794 if (dma
&& (csr
& MUSB_RXCSR_DMAENAB
)) {
795 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
797 | MUSB_RXCSR_DMAMODE
);
798 musb_writew(epio
, MUSB_RXCSR
,
799 MUSB_RXCSR_P_WZC_BITS
| csr
);
801 request
->actual
+= musb_ep
->dma
->actual_len
;
803 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
805 musb_readw(epio
, MUSB_RXCSR
),
806 musb_ep
->dma
->actual_len
, request
);
808 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
809 /* Autoclear doesn't clear RxPktRdy for short packets */
810 if ((dma
->desired_mode
== 0)
812 & (musb_ep
->packet_sz
- 1))) {
814 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
815 musb_writew(epio
, MUSB_RXCSR
, csr
);
818 /* incomplete, and not short? wait for next IN packet */
819 if ((request
->actual
< request
->length
)
820 && (musb_ep
->dma
->actual_len
821 == musb_ep
->packet_sz
))
824 musb_g_giveback(musb_ep
, request
, 0);
826 request
= next_request(musb_ep
);
831 /* analyze request if the ep is hot */
833 rxstate(musb
, to_musb_request(request
));
835 DBG(3, "packet waiting for %s%s request\n",
836 musb_ep
->desc
? "" : "inactive ",
837 musb_ep
->end_point
.name
);
841 /* ------------------------------------------------------------ */
843 static int musb_gadget_enable(struct usb_ep
*ep
,
844 const struct usb_endpoint_descriptor
*desc
)
847 struct musb_ep
*musb_ep
;
848 struct musb_hw_ep
*hw_ep
;
855 int status
= -EINVAL
;
860 musb_ep
= to_musb_ep(ep
);
861 hw_ep
= musb_ep
->hw_ep
;
863 musb
= musb_ep
->musb
;
865 epnum
= musb_ep
->current_epnum
;
867 spin_lock_irqsave(&musb
->lock
, flags
);
873 musb_ep
->type
= usb_endpoint_type(desc
);
875 /* check direction and (later) maxpacket size against endpoint */
876 if (usb_endpoint_num(desc
) != epnum
)
879 /* REVISIT this rules out high bandwidth periodic transfers */
880 tmp
= le16_to_cpu(desc
->wMaxPacketSize
);
884 if (usb_endpoint_dir_in(desc
))
885 ok
= musb
->hb_iso_tx
;
887 ok
= musb
->hb_iso_rx
;
890 DBG(4, "%s: not support ISO high bandwidth\n", __func__
);
893 musb_ep
->hb_mult
= (tmp
>> 11) & 3;
895 musb_ep
->hb_mult
= 0;
898 musb_ep
->packet_sz
= tmp
& 0x7ff;
899 tmp
= musb_ep
->packet_sz
* (musb_ep
->hb_mult
+ 1);
901 /* enable the interrupts for the endpoint, set the endpoint
902 * packet size (or fail), set the mode, clear the fifo
904 musb_ep_select(mbase
, epnum
);
905 if (usb_endpoint_dir_in(desc
)) {
906 u16 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
908 if (hw_ep
->is_shared_fifo
)
913 if (tmp
> hw_ep
->max_packet_sz_tx
) {
914 DBG(4, "%s: packet size beyond hw fifo size\n", __func__
);
918 int_txe
|= (1 << epnum
);
919 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
921 /* REVISIT if can_bulk_split(), use by updating "tmp";
922 * likewise high bandwidth periodic tx
924 /* Set TXMAXP with the FIFO size of the endpoint
925 * to disable double buffering mode. Currently, It seems that double
926 * buffering has problem if musb RTL revision number < 2.0.
928 if (musb
->hwvers
< MUSB_HWVERS_2000
)
929 musb_writew(regs
, MUSB_TXMAXP
, hw_ep
->max_packet_sz_tx
);
931 musb_writew(regs
, MUSB_TXMAXP
, musb_ep
->packet_sz
| (musb_ep
->hb_mult
<< 11));
933 csr
= MUSB_TXCSR_MODE
| MUSB_TXCSR_CLRDATATOG
;
934 if (musb_readw(regs
, MUSB_TXCSR
)
935 & MUSB_TXCSR_FIFONOTEMPTY
)
936 csr
|= MUSB_TXCSR_FLUSHFIFO
;
937 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
938 csr
|= MUSB_TXCSR_P_ISO
;
940 /* set twice in case of double buffering */
941 musb_writew(regs
, MUSB_TXCSR
, csr
);
942 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
943 musb_writew(regs
, MUSB_TXCSR
, csr
);
946 u16 int_rxe
= musb_readw(mbase
, MUSB_INTRRXE
);
948 if (hw_ep
->is_shared_fifo
)
953 if (tmp
> hw_ep
->max_packet_sz_rx
) {
954 DBG(4, "%s: packet size beyond hw fifo size\n", __func__
);
958 int_rxe
|= (1 << epnum
);
959 musb_writew(mbase
, MUSB_INTRRXE
, int_rxe
);
961 /* REVISIT if can_bulk_combine() use by updating "tmp"
962 * likewise high bandwidth periodic rx
964 /* Set RXMAXP with the FIFO size of the endpoint
965 * to disable double buffering mode.
967 if (musb
->hwvers
< MUSB_HWVERS_2000
)
968 musb_writew(regs
, MUSB_RXMAXP
, hw_ep
->max_packet_sz_rx
);
970 musb_writew(regs
, MUSB_RXMAXP
, musb_ep
->packet_sz
| (musb_ep
->hb_mult
<< 11));
972 /* force shared fifo to OUT-only mode */
973 if (hw_ep
->is_shared_fifo
) {
974 csr
= musb_readw(regs
, MUSB_TXCSR
);
975 csr
&= ~(MUSB_TXCSR_MODE
| MUSB_TXCSR_TXPKTRDY
);
976 musb_writew(regs
, MUSB_TXCSR
, csr
);
979 csr
= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_CLRDATATOG
;
980 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
981 csr
|= MUSB_RXCSR_P_ISO
;
982 else if (musb_ep
->type
== USB_ENDPOINT_XFER_INT
)
983 csr
|= MUSB_RXCSR_DISNYET
;
985 /* set twice in case of double buffering */
986 musb_writew(regs
, MUSB_RXCSR
, csr
);
987 musb_writew(regs
, MUSB_RXCSR
, csr
);
990 /* NOTE: all the I/O code _should_ work fine without DMA, in case
991 * for some reason you run out of channels here.
993 if (is_dma_capable() && musb
->dma_controller
) {
994 struct dma_controller
*c
= musb
->dma_controller
;
996 musb_ep
->dma
= c
->channel_alloc(c
, hw_ep
,
997 (desc
->bEndpointAddress
& USB_DIR_IN
));
1001 musb_ep
->desc
= desc
;
1003 musb_ep
->wedged
= 0;
1006 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1007 musb_driver_name
, musb_ep
->end_point
.name
,
1008 ({ char *s
; switch (musb_ep
->type
) {
1009 case USB_ENDPOINT_XFER_BULK
: s
= "bulk"; break;
1010 case USB_ENDPOINT_XFER_INT
: s
= "int"; break;
1011 default: s
= "iso"; break;
1013 musb_ep
->is_in
? "IN" : "OUT",
1014 musb_ep
->dma
? "dma, " : "",
1015 musb_ep
->packet_sz
);
1017 schedule_work(&musb
->irq_work
);
1020 spin_unlock_irqrestore(&musb
->lock
, flags
);
1025 * Disable an endpoint flushing all requests queued.
1027 static int musb_gadget_disable(struct usb_ep
*ep
)
1029 unsigned long flags
;
1032 struct musb_ep
*musb_ep
;
1036 musb_ep
= to_musb_ep(ep
);
1037 musb
= musb_ep
->musb
;
1038 epnum
= musb_ep
->current_epnum
;
1039 epio
= musb
->endpoints
[epnum
].regs
;
1041 spin_lock_irqsave(&musb
->lock
, flags
);
1042 musb_ep_select(musb
->mregs
, epnum
);
1044 /* zero the endpoint sizes */
1045 if (musb_ep
->is_in
) {
1046 u16 int_txe
= musb_readw(musb
->mregs
, MUSB_INTRTXE
);
1047 int_txe
&= ~(1 << epnum
);
1048 musb_writew(musb
->mregs
, MUSB_INTRTXE
, int_txe
);
1049 musb_writew(epio
, MUSB_TXMAXP
, 0);
1051 u16 int_rxe
= musb_readw(musb
->mregs
, MUSB_INTRRXE
);
1052 int_rxe
&= ~(1 << epnum
);
1053 musb_writew(musb
->mregs
, MUSB_INTRRXE
, int_rxe
);
1054 musb_writew(epio
, MUSB_RXMAXP
, 0);
1057 musb_ep
->desc
= NULL
;
1059 /* abort all pending DMA and requests */
1060 nuke(musb_ep
, -ESHUTDOWN
);
1062 schedule_work(&musb
->irq_work
);
1064 spin_unlock_irqrestore(&(musb
->lock
), flags
);
1066 DBG(2, "%s\n", musb_ep
->end_point
.name
);
1072 * Allocate a request for an endpoint.
1073 * Reused by ep0 code.
1075 struct usb_request
*musb_alloc_request(struct usb_ep
*ep
, gfp_t gfp_flags
)
1077 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1078 struct musb_request
*request
= NULL
;
1080 request
= kzalloc(sizeof *request
, gfp_flags
);
1082 INIT_LIST_HEAD(&request
->request
.list
);
1083 request
->request
.dma
= DMA_ADDR_INVALID
;
1084 request
->epnum
= musb_ep
->current_epnum
;
1085 request
->ep
= musb_ep
;
1088 return &request
->request
;
1093 * Reused by ep0 code.
1095 void musb_free_request(struct usb_ep
*ep
, struct usb_request
*req
)
1097 kfree(to_musb_request(req
));
1100 static LIST_HEAD(buffers
);
1102 struct free_record
{
1103 struct list_head list
;
1110 * Context: controller locked, IRQs blocked.
1112 void musb_ep_restart(struct musb
*musb
, struct musb_request
*req
)
1114 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1115 req
->tx
? "TX/IN" : "RX/OUT",
1116 &req
->request
, req
->request
.length
, req
->epnum
);
1118 musb_ep_select(musb
->mregs
, req
->epnum
);
1125 static int musb_gadget_queue(struct usb_ep
*ep
, struct usb_request
*req
,
1128 struct musb_ep
*musb_ep
;
1129 struct musb_request
*request
;
1132 unsigned long lockflags
;
1139 musb_ep
= to_musb_ep(ep
);
1140 musb
= musb_ep
->musb
;
1142 request
= to_musb_request(req
);
1143 request
->musb
= musb
;
1145 if (request
->ep
!= musb_ep
)
1148 DBG(4, "<== to %s request=%p\n", ep
->name
, req
);
1150 /* request is mine now... */
1151 request
->request
.actual
= 0;
1152 request
->request
.status
= -EINPROGRESS
;
1153 request
->epnum
= musb_ep
->current_epnum
;
1154 request
->tx
= musb_ep
->is_in
;
1156 if (is_dma_capable() && musb_ep
->dma
) {
1157 if (request
->request
.dma
== DMA_ADDR_INVALID
) {
1158 request
->request
.dma
= dma_map_single(
1160 request
->request
.buf
,
1161 request
->request
.length
,
1165 request
->mapped
= 1;
1167 dma_sync_single_for_device(musb
->controller
,
1168 request
->request
.dma
,
1169 request
->request
.length
,
1173 request
->mapped
= 0;
1175 } else if (!req
->buf
) {
1178 request
->mapped
= 0;
1180 spin_lock_irqsave(&musb
->lock
, lockflags
);
1182 /* don't queue if the ep is down */
1183 if (!musb_ep
->desc
) {
1184 DBG(4, "req %p queued to %s while ep %s\n",
1185 req
, ep
->name
, "disabled");
1186 status
= -ESHUTDOWN
;
1190 /* add request to the list */
1191 list_add_tail(&(request
->request
.list
), &(musb_ep
->req_list
));
1193 /* it this is the head of the queue, start i/o ... */
1194 if (!musb_ep
->busy
&& &request
->request
.list
== musb_ep
->req_list
.next
)
1195 musb_ep_restart(musb
, request
);
1198 spin_unlock_irqrestore(&musb
->lock
, lockflags
);
1202 static int musb_gadget_dequeue(struct usb_ep
*ep
, struct usb_request
*request
)
1204 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1205 struct usb_request
*r
;
1206 unsigned long flags
;
1208 struct musb
*musb
= musb_ep
->musb
;
1210 if (!ep
|| !request
|| to_musb_request(request
)->ep
!= musb_ep
)
1213 spin_lock_irqsave(&musb
->lock
, flags
);
1215 list_for_each_entry(r
, &musb_ep
->req_list
, list
) {
1220 DBG(3, "request %p not queued to %s\n", request
, ep
->name
);
1225 /* if the hardware doesn't have the request, easy ... */
1226 if (musb_ep
->req_list
.next
!= &request
->list
|| musb_ep
->busy
)
1227 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1229 /* ... else abort the dma transfer ... */
1230 else if (is_dma_capable() && musb_ep
->dma
) {
1231 struct dma_controller
*c
= musb
->dma_controller
;
1233 musb_ep_select(musb
->mregs
, musb_ep
->current_epnum
);
1234 if (c
->channel_abort
)
1235 status
= c
->channel_abort(musb_ep
->dma
);
1239 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1241 /* NOTE: by sticking to easily tested hardware/driver states,
1242 * we leave counting of in-flight packets imprecise.
1244 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1248 spin_unlock_irqrestore(&musb
->lock
, flags
);
1253 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1254 * data but will queue requests.
1256 * exported to ep0 code
1258 static int musb_gadget_set_halt(struct usb_ep
*ep
, int value
)
1260 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1261 u8 epnum
= musb_ep
->current_epnum
;
1262 struct musb
*musb
= musb_ep
->musb
;
1263 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1264 void __iomem
*mbase
;
1265 unsigned long flags
;
1267 struct musb_request
*request
;
1272 mbase
= musb
->mregs
;
1274 spin_lock_irqsave(&musb
->lock
, flags
);
1276 if ((USB_ENDPOINT_XFER_ISOC
== musb_ep
->type
)) {
1281 musb_ep_select(mbase
, epnum
);
1283 request
= to_musb_request(next_request(musb_ep
));
1286 DBG(3, "request in progress, cannot halt %s\n",
1291 /* Cannot portably stall with non-empty FIFO */
1292 if (musb_ep
->is_in
) {
1293 csr
= musb_readw(epio
, MUSB_TXCSR
);
1294 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1295 DBG(3, "FIFO busy, cannot halt %s\n", ep
->name
);
1301 musb_ep
->wedged
= 0;
1303 /* set/clear the stall and toggle bits */
1304 DBG(2, "%s: %s stall\n", ep
->name
, value
? "set" : "clear");
1305 if (musb_ep
->is_in
) {
1306 csr
= musb_readw(epio
, MUSB_TXCSR
);
1307 csr
|= MUSB_TXCSR_P_WZC_BITS
1308 | MUSB_TXCSR_CLRDATATOG
;
1310 csr
|= MUSB_TXCSR_P_SENDSTALL
;
1312 csr
&= ~(MUSB_TXCSR_P_SENDSTALL
1313 | MUSB_TXCSR_P_SENTSTALL
);
1314 csr
&= ~MUSB_TXCSR_TXPKTRDY
;
1315 musb_writew(epio
, MUSB_TXCSR
, csr
);
1317 csr
= musb_readw(epio
, MUSB_RXCSR
);
1318 csr
|= MUSB_RXCSR_P_WZC_BITS
1319 | MUSB_RXCSR_FLUSHFIFO
1320 | MUSB_RXCSR_CLRDATATOG
;
1322 csr
|= MUSB_RXCSR_P_SENDSTALL
;
1324 csr
&= ~(MUSB_RXCSR_P_SENDSTALL
1325 | MUSB_RXCSR_P_SENTSTALL
);
1326 musb_writew(epio
, MUSB_RXCSR
, csr
);
1329 /* maybe start the first request in the queue */
1330 if (!musb_ep
->busy
&& !value
&& request
) {
1331 DBG(3, "restarting the request\n");
1332 musb_ep_restart(musb
, request
);
1336 spin_unlock_irqrestore(&musb
->lock
, flags
);
1341 * Sets the halt feature with the clear requests ignored
1343 static int musb_gadget_set_wedge(struct usb_ep
*ep
)
1345 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1350 musb_ep
->wedged
= 1;
1352 return usb_ep_set_halt(ep
);
1355 static int musb_gadget_fifo_status(struct usb_ep
*ep
)
1357 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1358 void __iomem
*epio
= musb_ep
->hw_ep
->regs
;
1359 int retval
= -EINVAL
;
1361 if (musb_ep
->desc
&& !musb_ep
->is_in
) {
1362 struct musb
*musb
= musb_ep
->musb
;
1363 int epnum
= musb_ep
->current_epnum
;
1364 void __iomem
*mbase
= musb
->mregs
;
1365 unsigned long flags
;
1367 spin_lock_irqsave(&musb
->lock
, flags
);
1369 musb_ep_select(mbase
, epnum
);
1370 /* FIXME return zero unless RXPKTRDY is set */
1371 retval
= musb_readw(epio
, MUSB_RXCOUNT
);
1373 spin_unlock_irqrestore(&musb
->lock
, flags
);
1378 static void musb_gadget_fifo_flush(struct usb_ep
*ep
)
1380 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1381 struct musb
*musb
= musb_ep
->musb
;
1382 u8 epnum
= musb_ep
->current_epnum
;
1383 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1384 void __iomem
*mbase
;
1385 unsigned long flags
;
1388 mbase
= musb
->mregs
;
1390 spin_lock_irqsave(&musb
->lock
, flags
);
1391 musb_ep_select(mbase
, (u8
) epnum
);
1393 /* disable interrupts */
1394 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
1395 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
& ~(1 << epnum
));
1397 if (musb_ep
->is_in
) {
1398 csr
= musb_readw(epio
, MUSB_TXCSR
);
1399 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1400 csr
|= MUSB_TXCSR_FLUSHFIFO
| MUSB_TXCSR_P_WZC_BITS
;
1401 musb_writew(epio
, MUSB_TXCSR
, csr
);
1402 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1403 musb_writew(epio
, MUSB_TXCSR
, csr
);
1406 csr
= musb_readw(epio
, MUSB_RXCSR
);
1407 csr
|= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_P_WZC_BITS
;
1408 musb_writew(epio
, MUSB_RXCSR
, csr
);
1409 musb_writew(epio
, MUSB_RXCSR
, csr
);
1412 /* re-enable interrupt */
1413 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
1414 spin_unlock_irqrestore(&musb
->lock
, flags
);
1417 static const struct usb_ep_ops musb_ep_ops
= {
1418 .enable
= musb_gadget_enable
,
1419 .disable
= musb_gadget_disable
,
1420 .alloc_request
= musb_alloc_request
,
1421 .free_request
= musb_free_request
,
1422 .queue
= musb_gadget_queue
,
1423 .dequeue
= musb_gadget_dequeue
,
1424 .set_halt
= musb_gadget_set_halt
,
1425 .set_wedge
= musb_gadget_set_wedge
,
1426 .fifo_status
= musb_gadget_fifo_status
,
1427 .fifo_flush
= musb_gadget_fifo_flush
1430 /* ----------------------------------------------------------------------- */
1432 static int musb_gadget_get_frame(struct usb_gadget
*gadget
)
1434 struct musb
*musb
= gadget_to_musb(gadget
);
1436 return (int)musb_readw(musb
->mregs
, MUSB_FRAME
);
1439 static int musb_gadget_wakeup(struct usb_gadget
*gadget
)
1441 struct musb
*musb
= gadget_to_musb(gadget
);
1442 void __iomem
*mregs
= musb
->mregs
;
1443 unsigned long flags
;
1444 int status
= -EINVAL
;
1448 spin_lock_irqsave(&musb
->lock
, flags
);
1450 switch (musb
->xceiv
->state
) {
1451 case OTG_STATE_B_PERIPHERAL
:
1452 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1453 * that's part of the standard usb 1.1 state machine, and
1454 * doesn't affect OTG transitions.
1456 if (musb
->may_wakeup
&& musb
->is_suspended
)
1459 case OTG_STATE_B_IDLE
:
1460 /* Start SRP ... OTG not required. */
1461 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1462 DBG(2, "Sending SRP: devctl: %02x\n", devctl
);
1463 devctl
|= MUSB_DEVCTL_SESSION
;
1464 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
);
1465 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1467 while (!(devctl
& MUSB_DEVCTL_SESSION
)) {
1468 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1473 while (devctl
& MUSB_DEVCTL_SESSION
) {
1474 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1479 /* Block idling for at least 1s */
1480 musb_platform_try_idle(musb
,
1481 jiffies
+ msecs_to_jiffies(1 * HZ
));
1486 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb
));
1492 power
= musb_readb(mregs
, MUSB_POWER
);
1493 power
|= MUSB_POWER_RESUME
;
1494 musb_writeb(mregs
, MUSB_POWER
, power
);
1495 DBG(2, "issue wakeup\n");
1497 /* FIXME do this next chunk in a timer callback, no udelay */
1500 power
= musb_readb(mregs
, MUSB_POWER
);
1501 power
&= ~MUSB_POWER_RESUME
;
1502 musb_writeb(mregs
, MUSB_POWER
, power
);
1504 spin_unlock_irqrestore(&musb
->lock
, flags
);
1509 musb_gadget_set_self_powered(struct usb_gadget
*gadget
, int is_selfpowered
)
1511 struct musb
*musb
= gadget_to_musb(gadget
);
1513 musb
->is_self_powered
= !!is_selfpowered
;
1517 static void musb_pullup(struct musb
*musb
, int is_on
)
1521 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
1523 power
|= MUSB_POWER_SOFTCONN
;
1525 power
&= ~MUSB_POWER_SOFTCONN
;
1527 /* FIXME if on, HdrcStart; if off, HdrcStop */
1529 DBG(3, "gadget %s D+ pullup %s\n",
1530 musb
->gadget_driver
->function
, is_on
? "on" : "off");
1531 musb_writeb(musb
->mregs
, MUSB_POWER
, power
);
1535 static int musb_gadget_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1537 DBG(2, "<= %s =>\n", __func__
);
1540 * FIXME iff driver's softconnect flag is set (as it is during probe,
1541 * though that can clear it), just musb_pullup().
1548 static int musb_gadget_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
1550 struct musb
*musb
= gadget_to_musb(gadget
);
1552 if (!musb
->xceiv
->set_power
)
1554 return otg_set_power(musb
->xceiv
, mA
);
1557 static int musb_gadget_pullup(struct usb_gadget
*gadget
, int is_on
)
1559 struct musb
*musb
= gadget_to_musb(gadget
);
1560 unsigned long flags
;
1564 /* NOTE: this assumes we are sensing vbus; we'd rather
1565 * not pullup unless the B-session is active.
1567 spin_lock_irqsave(&musb
->lock
, flags
);
1568 if (is_on
!= musb
->softconnect
) {
1569 musb
->softconnect
= is_on
;
1570 musb_pullup(musb
, is_on
);
1572 spin_unlock_irqrestore(&musb
->lock
, flags
);
1576 static const struct usb_gadget_ops musb_gadget_operations
= {
1577 .get_frame
= musb_gadget_get_frame
,
1578 .wakeup
= musb_gadget_wakeup
,
1579 .set_selfpowered
= musb_gadget_set_self_powered
,
1580 /* .vbus_session = musb_gadget_vbus_session, */
1581 .vbus_draw
= musb_gadget_vbus_draw
,
1582 .pullup
= musb_gadget_pullup
,
1585 /* ----------------------------------------------------------------------- */
1589 /* Only this registration code "knows" the rule (from USB standards)
1590 * about there being only one external upstream port. It assumes
1591 * all peripheral ports are external...
1593 static struct musb
*the_gadget
;
1595 static void musb_gadget_release(struct device
*dev
)
1597 /* kref_put(WHAT) */
1598 dev_dbg(dev
, "%s\n", __func__
);
1603 init_peripheral_ep(struct musb
*musb
, struct musb_ep
*ep
, u8 epnum
, int is_in
)
1605 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ epnum
;
1607 memset(ep
, 0, sizeof *ep
);
1609 ep
->current_epnum
= epnum
;
1614 INIT_LIST_HEAD(&ep
->req_list
);
1616 sprintf(ep
->name
, "ep%d%s", epnum
,
1617 (!epnum
|| hw_ep
->is_shared_fifo
) ? "" : (
1618 is_in
? "in" : "out"));
1619 ep
->end_point
.name
= ep
->name
;
1620 INIT_LIST_HEAD(&ep
->end_point
.ep_list
);
1622 ep
->end_point
.maxpacket
= 64;
1623 ep
->end_point
.ops
= &musb_g_ep0_ops
;
1624 musb
->g
.ep0
= &ep
->end_point
;
1627 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_tx
;
1629 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_rx
;
1630 ep
->end_point
.ops
= &musb_ep_ops
;
1631 list_add_tail(&ep
->end_point
.ep_list
, &musb
->g
.ep_list
);
1636 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1637 * to the rest of the driver state.
1639 static inline void __init
musb_g_init_endpoints(struct musb
*musb
)
1642 struct musb_hw_ep
*hw_ep
;
1645 /* intialize endpoint list just once */
1646 INIT_LIST_HEAD(&(musb
->g
.ep_list
));
1648 for (epnum
= 0, hw_ep
= musb
->endpoints
;
1649 epnum
< musb
->nr_endpoints
;
1651 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1652 init_peripheral_ep(musb
, &hw_ep
->ep_in
, epnum
, 0);
1655 if (hw_ep
->max_packet_sz_tx
) {
1656 init_peripheral_ep(musb
, &hw_ep
->ep_in
,
1660 if (hw_ep
->max_packet_sz_rx
) {
1661 init_peripheral_ep(musb
, &hw_ep
->ep_out
,
1669 /* called once during driver setup to initialize and link into
1670 * the driver model; memory is zeroed.
1672 int __init
musb_gadget_setup(struct musb
*musb
)
1676 /* REVISIT minor race: if (erroneously) setting up two
1677 * musb peripherals at the same time, only the bus lock
1684 musb
->g
.ops
= &musb_gadget_operations
;
1685 musb
->g
.is_dualspeed
= 1;
1686 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1688 /* this "gadget" abstracts/virtualizes the controller */
1689 dev_set_name(&musb
->g
.dev
, "gadget");
1690 musb
->g
.dev
.parent
= musb
->controller
;
1691 musb
->g
.dev
.dma_mask
= musb
->controller
->dma_mask
;
1692 musb
->g
.dev
.release
= musb_gadget_release
;
1693 musb
->g
.name
= musb_driver_name
;
1695 if (is_otg_enabled(musb
))
1698 musb_g_init_endpoints(musb
);
1700 musb
->is_active
= 0;
1701 musb_platform_try_idle(musb
, 0);
1703 status
= device_register(&musb
->g
.dev
);
1709 void musb_gadget_cleanup(struct musb
*musb
)
1711 if (musb
!= the_gadget
)
1714 device_unregister(&musb
->g
.dev
);
1719 * Register the gadget driver. Used by gadget drivers when
1720 * registering themselves with the controller.
1722 * -EINVAL something went wrong (not driver)
1723 * -EBUSY another gadget is already using the controller
1724 * -ENOMEM no memeory to perform the operation
1726 * @param driver the gadget driver
1727 * @param bind the driver's bind function
1728 * @return <0 if error, 0 if everything is fine
1730 int usb_gadget_probe_driver(struct usb_gadget_driver
*driver
,
1731 int (*bind
)(struct usb_gadget
*))
1734 unsigned long flags
;
1735 struct musb
*musb
= the_gadget
;
1738 || driver
->speed
!= USB_SPEED_HIGH
1739 || !bind
|| !driver
->setup
)
1742 /* driver must be initialized to support peripheral mode */
1744 DBG(1, "%s, no dev??\n", __func__
);
1748 DBG(3, "registering driver %s\n", driver
->function
);
1749 spin_lock_irqsave(&musb
->lock
, flags
);
1751 if (musb
->gadget_driver
) {
1752 DBG(1, "%s is already bound to %s\n",
1754 musb
->gadget_driver
->driver
.name
);
1757 musb
->gadget_driver
= driver
;
1758 musb
->g
.dev
.driver
= &driver
->driver
;
1759 driver
->driver
.bus
= NULL
;
1760 musb
->softconnect
= 1;
1764 spin_unlock_irqrestore(&musb
->lock
, flags
);
1767 retval
= bind(&musb
->g
);
1769 DBG(3, "bind to driver %s failed --> %d\n",
1770 driver
->driver
.name
, retval
);
1771 musb
->gadget_driver
= NULL
;
1772 musb
->g
.dev
.driver
= NULL
;
1775 spin_lock_irqsave(&musb
->lock
, flags
);
1777 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1778 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1779 musb
->is_active
= 1;
1781 /* FIXME this ignores the softconnect flag. Drivers are
1782 * allowed hold the peripheral inactive until for example
1783 * userspace hooks up printer hardware or DSP codecs, so
1784 * hosts only see fully functional devices.
1787 if (!is_otg_enabled(musb
))
1790 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1792 spin_unlock_irqrestore(&musb
->lock
, flags
);
1794 if (is_otg_enabled(musb
)) {
1795 DBG(3, "OTG startup...\n");
1797 /* REVISIT: funcall to other code, which also
1798 * handles power budgeting ... this way also
1799 * ensures HdrcStart is indirectly called.
1801 retval
= usb_add_hcd(musb_to_hcd(musb
), -1, 0);
1803 DBG(1, "add_hcd failed, %d\n", retval
);
1804 spin_lock_irqsave(&musb
->lock
, flags
);
1805 otg_set_peripheral(musb
->xceiv
, NULL
);
1806 musb
->gadget_driver
= NULL
;
1807 musb
->g
.dev
.driver
= NULL
;
1808 spin_unlock_irqrestore(&musb
->lock
, flags
);
1815 EXPORT_SYMBOL(usb_gadget_probe_driver
);
1817 static void stop_activity(struct musb
*musb
, struct usb_gadget_driver
*driver
)
1820 struct musb_hw_ep
*hw_ep
;
1822 /* don't disconnect if it's not connected */
1823 if (musb
->g
.speed
== USB_SPEED_UNKNOWN
)
1826 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1828 /* deactivate the hardware */
1829 if (musb
->softconnect
) {
1830 musb
->softconnect
= 0;
1831 musb_pullup(musb
, 0);
1835 /* killing any outstanding requests will quiesce the driver;
1836 * then report disconnect
1839 for (i
= 0, hw_ep
= musb
->endpoints
;
1840 i
< musb
->nr_endpoints
;
1842 musb_ep_select(musb
->mregs
, i
);
1843 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1844 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1846 if (hw_ep
->max_packet_sz_tx
)
1847 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1848 if (hw_ep
->max_packet_sz_rx
)
1849 nuke(&hw_ep
->ep_out
, -ESHUTDOWN
);
1853 spin_unlock(&musb
->lock
);
1854 driver
->disconnect(&musb
->g
);
1855 spin_lock(&musb
->lock
);
1860 * Unregister the gadget driver. Used by gadget drivers when
1861 * unregistering themselves from the controller.
1863 * @param driver the gadget driver to unregister
1865 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1867 unsigned long flags
;
1869 struct musb
*musb
= the_gadget
;
1871 if (!driver
|| !driver
->unbind
|| !musb
)
1874 /* REVISIT always use otg_set_peripheral() here too;
1875 * this needs to shut down the OTG engine.
1878 spin_lock_irqsave(&musb
->lock
, flags
);
1880 #ifdef CONFIG_USB_MUSB_OTG
1881 musb_hnp_stop(musb
);
1884 if (musb
->gadget_driver
== driver
) {
1886 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1888 musb
->xceiv
->state
= OTG_STATE_UNDEFINED
;
1889 stop_activity(musb
, driver
);
1890 otg_set_peripheral(musb
->xceiv
, NULL
);
1892 DBG(3, "unregistering driver %s\n", driver
->function
);
1893 spin_unlock_irqrestore(&musb
->lock
, flags
);
1894 driver
->unbind(&musb
->g
);
1895 spin_lock_irqsave(&musb
->lock
, flags
);
1897 musb
->gadget_driver
= NULL
;
1898 musb
->g
.dev
.driver
= NULL
;
1900 musb
->is_active
= 0;
1901 musb_platform_try_idle(musb
, 0);
1904 spin_unlock_irqrestore(&musb
->lock
, flags
);
1906 if (is_otg_enabled(musb
) && retval
== 0) {
1907 usb_remove_hcd(musb_to_hcd(musb
));
1908 /* FIXME we need to be able to register another
1909 * gadget driver here and have everything work;
1910 * that currently misbehaves.
1916 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
1919 /* ----------------------------------------------------------------------- */
1921 /* lifecycle operations called through plat_uds.c */
1923 void musb_g_resume(struct musb
*musb
)
1925 musb
->is_suspended
= 0;
1926 switch (musb
->xceiv
->state
) {
1927 case OTG_STATE_B_IDLE
:
1929 case OTG_STATE_B_WAIT_ACON
:
1930 case OTG_STATE_B_PERIPHERAL
:
1931 musb
->is_active
= 1;
1932 if (musb
->gadget_driver
&& musb
->gadget_driver
->resume
) {
1933 spin_unlock(&musb
->lock
);
1934 musb
->gadget_driver
->resume(&musb
->g
);
1935 spin_lock(&musb
->lock
);
1939 WARNING("unhandled RESUME transition (%s)\n",
1940 otg_state_string(musb
));
1944 /* called when SOF packets stop for 3+ msec */
1945 void musb_g_suspend(struct musb
*musb
)
1949 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1950 DBG(3, "devctl %02x\n", devctl
);
1952 switch (musb
->xceiv
->state
) {
1953 case OTG_STATE_B_IDLE
:
1954 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
1955 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
1957 case OTG_STATE_B_PERIPHERAL
:
1958 musb
->is_suspended
= 1;
1959 if (musb
->gadget_driver
&& musb
->gadget_driver
->suspend
) {
1960 spin_unlock(&musb
->lock
);
1961 musb
->gadget_driver
->suspend(&musb
->g
);
1962 spin_lock(&musb
->lock
);
1966 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1967 * A_PERIPHERAL may need care too
1969 WARNING("unhandled SUSPEND transition (%s)\n",
1970 otg_state_string(musb
));
1974 /* Called during SRP */
1975 void musb_g_wakeup(struct musb
*musb
)
1977 musb_gadget_wakeup(&musb
->g
);
1980 /* called when VBUS drops below session threshold, and in other cases */
1981 void musb_g_disconnect(struct musb
*musb
)
1983 void __iomem
*mregs
= musb
->mregs
;
1984 u8 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1986 DBG(3, "devctl %02x\n", devctl
);
1989 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
& MUSB_DEVCTL_SESSION
);
1991 /* don't draw vbus until new b-default session */
1992 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1994 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1995 if (musb
->gadget_driver
&& musb
->gadget_driver
->disconnect
) {
1996 spin_unlock(&musb
->lock
);
1997 musb
->gadget_driver
->disconnect(&musb
->g
);
1998 spin_lock(&musb
->lock
);
2001 switch (musb
->xceiv
->state
) {
2003 #ifdef CONFIG_USB_MUSB_OTG
2004 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
2005 otg_state_string(musb
));
2006 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
2007 MUSB_HST_MODE(musb
);
2009 case OTG_STATE_A_PERIPHERAL
:
2010 musb
->xceiv
->state
= OTG_STATE_A_WAIT_BCON
;
2011 MUSB_HST_MODE(musb
);
2013 case OTG_STATE_B_WAIT_ACON
:
2014 case OTG_STATE_B_HOST
:
2016 case OTG_STATE_B_PERIPHERAL
:
2017 case OTG_STATE_B_IDLE
:
2018 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
2020 case OTG_STATE_B_SRP_INIT
:
2024 musb
->is_active
= 0;
2027 void musb_g_reset(struct musb
*musb
)
2028 __releases(musb
->lock
)
2029 __acquires(musb
->lock
)
2031 void __iomem
*mbase
= musb
->mregs
;
2032 u8 devctl
= musb_readb(mbase
, MUSB_DEVCTL
);
2035 DBG(3, "<== %s addr=%x driver '%s'\n",
2036 (devctl
& MUSB_DEVCTL_BDEVICE
)
2037 ? "B-Device" : "A-Device",
2038 musb_readb(mbase
, MUSB_FADDR
),
2040 ? musb
->gadget_driver
->driver
.name
2044 /* report disconnect, if we didn't already (flushing EP state) */
2045 if (musb
->g
.speed
!= USB_SPEED_UNKNOWN
)
2046 musb_g_disconnect(musb
);
2049 else if (devctl
& MUSB_DEVCTL_HR
)
2050 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
2053 /* what speed did we negotiate? */
2054 power
= musb_readb(mbase
, MUSB_POWER
);
2055 musb
->g
.speed
= (power
& MUSB_POWER_HSMODE
)
2056 ? USB_SPEED_HIGH
: USB_SPEED_FULL
;
2058 /* start in USB_STATE_DEFAULT */
2059 musb
->is_active
= 1;
2060 musb
->is_suspended
= 0;
2061 MUSB_DEV_MODE(musb
);
2063 musb
->ep0_state
= MUSB_EP0_STAGE_SETUP
;
2065 musb
->may_wakeup
= 0;
2066 musb
->g
.b_hnp_enable
= 0;
2067 musb
->g
.a_alt_hnp_support
= 0;
2068 musb
->g
.a_hnp_support
= 0;
2070 /* Normal reset, as B-Device;
2071 * or else after HNP, as A-Device
2073 if (devctl
& MUSB_DEVCTL_BDEVICE
) {
2074 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
2075 musb
->g
.is_a_peripheral
= 0;
2076 } else if (is_otg_enabled(musb
)) {
2077 musb
->xceiv
->state
= OTG_STATE_A_PERIPHERAL
;
2078 musb
->g
.is_a_peripheral
= 1;
2082 /* start with default limits on VBUS power draw */
2083 (void) musb_gadget_vbus_draw(&musb
->g
,
2084 is_otg_enabled(musb
) ? 8 : 100);