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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / drivers / usb / phy / phy-msm-usb.c
1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36
37 #include <linux/usb.h>
38 #include <linux/usb/otg.h>
39 #include <linux/usb/of.h>
40 #include <linux/usb/ulpi.h>
41 #include <linux/usb/gadget.h>
42 #include <linux/usb/hcd.h>
43 #include <linux/usb/msm_hsusb.h>
44 #include <linux/usb/msm_hsusb_hw.h>
45 #include <linux/regulator/consumer.h>
46
47 #define MSM_USB_BASE (motg->regs)
48 #define DRIVER_NAME "msm_otg"
49
50 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
51 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
52
53 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
54 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
55 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
56 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
57
58 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
59 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
60 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
61 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
62
63 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
64 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
65 #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
66
67 enum vdd_levels {
68 VDD_LEVEL_NONE = 0,
69 VDD_LEVEL_MIN,
70 VDD_LEVEL_MAX,
71 };
72
73 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
74 {
75 int ret = 0;
76
77 if (init) {
78 ret = regulator_set_voltage(motg->vddcx,
79 motg->vdd_levels[VDD_LEVEL_MIN],
80 motg->vdd_levels[VDD_LEVEL_MAX]);
81 if (ret) {
82 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
83 return ret;
84 }
85
86 ret = regulator_enable(motg->vddcx);
87 if (ret)
88 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
89 } else {
90 ret = regulator_set_voltage(motg->vddcx, 0,
91 motg->vdd_levels[VDD_LEVEL_MAX]);
92 if (ret)
93 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
94 ret = regulator_disable(motg->vddcx);
95 if (ret)
96 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
97 }
98
99 return ret;
100 }
101
102 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
103 {
104 int rc = 0;
105
106 if (init) {
107 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
108 USB_PHY_3P3_VOL_MAX);
109 if (rc) {
110 dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
111 goto exit;
112 }
113 rc = regulator_enable(motg->v3p3);
114 if (rc) {
115 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
116 goto exit;
117 }
118 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
119 USB_PHY_1P8_VOL_MAX);
120 if (rc) {
121 dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
122 goto disable_3p3;
123 }
124 rc = regulator_enable(motg->v1p8);
125 if (rc) {
126 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
127 goto disable_3p3;
128 }
129
130 return 0;
131 }
132
133 regulator_disable(motg->v1p8);
134 disable_3p3:
135 regulator_disable(motg->v3p3);
136 exit:
137 return rc;
138 }
139
140 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
141 {
142 int ret = 0;
143
144 if (on) {
145 ret = regulator_set_optimum_mode(motg->v1p8,
146 USB_PHY_1P8_HPM_LOAD);
147 if (ret < 0) {
148 pr_err("Could not set HPM for v1p8\n");
149 return ret;
150 }
151 ret = regulator_set_optimum_mode(motg->v3p3,
152 USB_PHY_3P3_HPM_LOAD);
153 if (ret < 0) {
154 pr_err("Could not set HPM for v3p3\n");
155 regulator_set_optimum_mode(motg->v1p8,
156 USB_PHY_1P8_LPM_LOAD);
157 return ret;
158 }
159 } else {
160 ret = regulator_set_optimum_mode(motg->v1p8,
161 USB_PHY_1P8_LPM_LOAD);
162 if (ret < 0)
163 pr_err("Could not set LPM for v1p8\n");
164 ret = regulator_set_optimum_mode(motg->v3p3,
165 USB_PHY_3P3_LPM_LOAD);
166 if (ret < 0)
167 pr_err("Could not set LPM for v3p3\n");
168 }
169
170 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
171 return ret < 0 ? ret : 0;
172 }
173
174 static int ulpi_read(struct usb_phy *phy, u32 reg)
175 {
176 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
177 int cnt = 0;
178
179 /* initiate read operation */
180 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
181 USB_ULPI_VIEWPORT);
182
183 /* wait for completion */
184 while (cnt < ULPI_IO_TIMEOUT_USEC) {
185 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
186 break;
187 udelay(1);
188 cnt++;
189 }
190
191 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
192 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
193 readl(USB_ULPI_VIEWPORT));
194 return -ETIMEDOUT;
195 }
196 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
197 }
198
199 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
200 {
201 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
202 int cnt = 0;
203
204 /* initiate write operation */
205 writel(ULPI_RUN | ULPI_WRITE |
206 ULPI_ADDR(reg) | ULPI_DATA(val),
207 USB_ULPI_VIEWPORT);
208
209 /* wait for completion */
210 while (cnt < ULPI_IO_TIMEOUT_USEC) {
211 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
212 break;
213 udelay(1);
214 cnt++;
215 }
216
217 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
218 dev_err(phy->dev, "ulpi_write: timeout\n");
219 return -ETIMEDOUT;
220 }
221 return 0;
222 }
223
224 static struct usb_phy_io_ops msm_otg_io_ops = {
225 .read = ulpi_read,
226 .write = ulpi_write,
227 };
228
229 static void ulpi_init(struct msm_otg *motg)
230 {
231 struct msm_otg_platform_data *pdata = motg->pdata;
232 int *seq = pdata->phy_init_seq, idx;
233 u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
234
235 for (idx = 0; idx < pdata->phy_init_sz; idx++) {
236 if (seq[idx] == -1)
237 continue;
238
239 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
240 seq[idx], addr + idx);
241 ulpi_write(&motg->phy, seq[idx], addr + idx);
242 }
243 }
244
245 static int msm_phy_notify_disconnect(struct usb_phy *phy,
246 enum usb_device_speed speed)
247 {
248 int val;
249
250 /*
251 * Put the transceiver in non-driving mode. Otherwise host
252 * may not detect soft-disconnection.
253 */
254 val = ulpi_read(phy, ULPI_FUNC_CTRL);
255 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
256 val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
257 ulpi_write(phy, val, ULPI_FUNC_CTRL);
258
259 return 0;
260 }
261
262 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
263 {
264 int ret;
265
266 if (assert)
267 ret = reset_control_assert(motg->link_rst);
268 else
269 ret = reset_control_deassert(motg->link_rst);
270
271 if (ret)
272 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
273 assert ? "assert" : "deassert");
274
275 return ret;
276 }
277
278 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
279 {
280 int ret = 0;
281
282 if (motg->phy_rst)
283 ret = reset_control_reset(motg->phy_rst);
284
285 if (ret)
286 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
287
288 return ret;
289 }
290
291 static int msm_link_reset(struct msm_otg *motg)
292 {
293 u32 val;
294 int ret;
295
296 ret = msm_otg_link_clk_reset(motg, 1);
297 if (ret)
298 return ret;
299
300 /* wait for 1ms delay as suggested in HPG. */
301 usleep_range(1000, 1200);
302
303 ret = msm_otg_link_clk_reset(motg, 0);
304 if (ret)
305 return ret;
306
307 if (motg->phy_number)
308 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
309
310 /* put transceiver in serial mode as part of reset */
311 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
312 writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
313
314 return 0;
315 }
316
317 static int msm_otg_reset(struct usb_phy *phy)
318 {
319 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
320 int cnt = 0;
321
322 writel(USBCMD_RESET, USB_USBCMD);
323 while (cnt < LINK_RESET_TIMEOUT_USEC) {
324 if (!(readl(USB_USBCMD) & USBCMD_RESET))
325 break;
326 udelay(1);
327 cnt++;
328 }
329 if (cnt >= LINK_RESET_TIMEOUT_USEC)
330 return -ETIMEDOUT;
331
332 /* select ULPI phy and clear other status/control bits in PORTSC */
333 writel(PORTSC_PTS_ULPI, USB_PORTSC);
334
335 writel(0x0, USB_AHBBURST);
336 writel(0x08, USB_AHBMODE);
337
338 if (motg->phy_number)
339 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
340 return 0;
341 }
342
343 static void msm_phy_reset(struct msm_otg *motg)
344 {
345 void __iomem *addr;
346
347 if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
348 msm_otg_phy_clk_reset(motg);
349 return;
350 }
351
352 addr = USB_PHY_CTRL;
353 if (motg->phy_number)
354 addr = USB_PHY_CTRL2;
355
356 /* Assert USB PHY_POR */
357 writel(readl(addr) | PHY_POR_ASSERT, addr);
358
359 /*
360 * wait for minimum 10 microseconds as suggested in HPG.
361 * Use a slightly larger value since the exact value didn't
362 * work 100% of the time.
363 */
364 udelay(12);
365
366 /* Deassert USB PHY_POR */
367 writel(readl(addr) & ~PHY_POR_ASSERT, addr);
368 }
369
370 static int msm_usb_reset(struct usb_phy *phy)
371 {
372 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
373 int ret;
374
375 if (!IS_ERR(motg->core_clk))
376 clk_prepare_enable(motg->core_clk);
377
378 ret = msm_link_reset(motg);
379 if (ret) {
380 dev_err(phy->dev, "phy_reset failed\n");
381 return ret;
382 }
383
384 ret = msm_otg_reset(&motg->phy);
385 if (ret) {
386 dev_err(phy->dev, "link reset failed\n");
387 return ret;
388 }
389
390 msleep(100);
391
392 /* Reset USB PHY after performing USB Link RESET */
393 msm_phy_reset(motg);
394
395 if (!IS_ERR(motg->core_clk))
396 clk_disable_unprepare(motg->core_clk);
397
398 return 0;
399 }
400
401 static int msm_phy_init(struct usb_phy *phy)
402 {
403 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
404 struct msm_otg_platform_data *pdata = motg->pdata;
405 u32 val, ulpi_val = 0;
406
407 /* Program USB PHY Override registers. */
408 ulpi_init(motg);
409
410 /*
411 * It is recommended in HPG to reset USB PHY after programming
412 * USB PHY Override registers.
413 */
414 msm_phy_reset(motg);
415
416 if (pdata->otg_control == OTG_PHY_CONTROL) {
417 val = readl(USB_OTGSC);
418 if (pdata->mode == USB_DR_MODE_OTG) {
419 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
420 val |= OTGSC_IDIE | OTGSC_BSVIE;
421 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
422 ulpi_val = ULPI_INT_SESS_VALID;
423 val |= OTGSC_BSVIE;
424 }
425 writel(val, USB_OTGSC);
426 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
427 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
428 }
429
430 if (motg->phy_number)
431 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
432
433 return 0;
434 }
435
436 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
437 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
438
439 #ifdef CONFIG_PM
440
441 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
442 {
443 int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
444 int min_vol;
445 int ret;
446
447 if (high)
448 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
449 else
450 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
451
452 ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
453 if (ret) {
454 pr_err("Cannot set vddcx voltage\n");
455 return ret;
456 }
457
458 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
459
460 return ret;
461 }
462
463 static int msm_otg_suspend(struct msm_otg *motg)
464 {
465 struct usb_phy *phy = &motg->phy;
466 struct usb_bus *bus = phy->otg->host;
467 struct msm_otg_platform_data *pdata = motg->pdata;
468 void __iomem *addr;
469 int cnt = 0;
470
471 if (atomic_read(&motg->in_lpm))
472 return 0;
473
474 disable_irq(motg->irq);
475 /*
476 * Chipidea 45-nm PHY suspend sequence:
477 *
478 * Interrupt Latch Register auto-clear feature is not present
479 * in all PHY versions. Latch register is clear on read type.
480 * Clear latch register to avoid spurious wakeup from
481 * low power mode (LPM).
482 *
483 * PHY comparators are disabled when PHY enters into low power
484 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
485 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
486 * PHY comparators. This save significant amount of power.
487 *
488 * PLL is not turned off when PHY enters into low power mode (LPM).
489 * Disable PLL for maximum power savings.
490 */
491
492 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
493 ulpi_read(phy, 0x14);
494 if (pdata->otg_control == OTG_PHY_CONTROL)
495 ulpi_write(phy, 0x01, 0x30);
496 ulpi_write(phy, 0x08, 0x09);
497 }
498
499 /*
500 * PHY may take some time or even fail to enter into low power
501 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
502 * in failure case.
503 */
504 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
505 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
506 if (readl(USB_PORTSC) & PORTSC_PHCD)
507 break;
508 udelay(1);
509 cnt++;
510 }
511
512 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
513 dev_err(phy->dev, "Unable to suspend PHY\n");
514 msm_otg_reset(phy);
515 enable_irq(motg->irq);
516 return -ETIMEDOUT;
517 }
518
519 /*
520 * PHY has capability to generate interrupt asynchronously in low
521 * power mode (LPM). This interrupt is level triggered. So USB IRQ
522 * line must be disabled till async interrupt enable bit is cleared
523 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
524 * block data communication from PHY.
525 */
526 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
527
528 addr = USB_PHY_CTRL;
529 if (motg->phy_number)
530 addr = USB_PHY_CTRL2;
531
532 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
533 motg->pdata->otg_control == OTG_PMIC_CONTROL)
534 writel(readl(addr) | PHY_RETEN, addr);
535
536 clk_disable_unprepare(motg->pclk);
537 clk_disable_unprepare(motg->clk);
538 if (!IS_ERR(motg->core_clk))
539 clk_disable_unprepare(motg->core_clk);
540
541 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
542 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
543 msm_hsusb_ldo_set_mode(motg, 0);
544 msm_hsusb_config_vddcx(motg, 0);
545 }
546
547 if (device_may_wakeup(phy->dev))
548 enable_irq_wake(motg->irq);
549 if (bus)
550 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
551
552 atomic_set(&motg->in_lpm, 1);
553 enable_irq(motg->irq);
554
555 dev_info(phy->dev, "USB in low power mode\n");
556
557 return 0;
558 }
559
560 static int msm_otg_resume(struct msm_otg *motg)
561 {
562 struct usb_phy *phy = &motg->phy;
563 struct usb_bus *bus = phy->otg->host;
564 void __iomem *addr;
565 int cnt = 0;
566 unsigned temp;
567
568 if (!atomic_read(&motg->in_lpm))
569 return 0;
570
571 clk_prepare_enable(motg->pclk);
572 clk_prepare_enable(motg->clk);
573 if (!IS_ERR(motg->core_clk))
574 clk_prepare_enable(motg->core_clk);
575
576 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
577 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
578
579 addr = USB_PHY_CTRL;
580 if (motg->phy_number)
581 addr = USB_PHY_CTRL2;
582
583 msm_hsusb_ldo_set_mode(motg, 1);
584 msm_hsusb_config_vddcx(motg, 1);
585 writel(readl(addr) & ~PHY_RETEN, addr);
586 }
587
588 temp = readl(USB_USBCMD);
589 temp &= ~ASYNC_INTR_CTRL;
590 temp &= ~ULPI_STP_CTRL;
591 writel(temp, USB_USBCMD);
592
593 /*
594 * PHY comes out of low power mode (LPM) in case of wakeup
595 * from asynchronous interrupt.
596 */
597 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
598 goto skip_phy_resume;
599
600 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
601 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
602 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
603 break;
604 udelay(1);
605 cnt++;
606 }
607
608 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
609 /*
610 * This is a fatal error. Reset the link and
611 * PHY. USB state can not be restored. Re-insertion
612 * of USB cable is the only way to get USB working.
613 */
614 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
615 msm_otg_reset(phy);
616 }
617
618 skip_phy_resume:
619 if (device_may_wakeup(phy->dev))
620 disable_irq_wake(motg->irq);
621 if (bus)
622 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
623
624 atomic_set(&motg->in_lpm, 0);
625
626 if (motg->async_int) {
627 motg->async_int = 0;
628 pm_runtime_put(phy->dev);
629 enable_irq(motg->irq);
630 }
631
632 dev_info(phy->dev, "USB exited from low power mode\n");
633
634 return 0;
635 }
636 #endif
637
638 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
639 {
640 if (motg->cur_power == mA)
641 return;
642
643 /* TODO: Notify PMIC about available current */
644 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
645 motg->cur_power = mA;
646 }
647
648 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
649 {
650 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
651
652 /*
653 * Gadget driver uses set_power method to notify about the
654 * available current based on suspend/configured states.
655 *
656 * IDEV_CHG can be drawn irrespective of suspend/un-configured
657 * states when CDP/ACA is connected.
658 */
659 if (motg->chg_type == USB_SDP_CHARGER)
660 msm_otg_notify_charger(motg, mA);
661
662 return 0;
663 }
664
665 static void msm_otg_start_host(struct usb_phy *phy, int on)
666 {
667 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
668 struct msm_otg_platform_data *pdata = motg->pdata;
669 struct usb_hcd *hcd;
670
671 if (!phy->otg->host)
672 return;
673
674 hcd = bus_to_hcd(phy->otg->host);
675
676 if (on) {
677 dev_dbg(phy->dev, "host on\n");
678
679 if (pdata->vbus_power)
680 pdata->vbus_power(1);
681 /*
682 * Some boards have a switch cotrolled by gpio
683 * to enable/disable internal HUB. Enable internal
684 * HUB before kicking the host.
685 */
686 if (pdata->setup_gpio)
687 pdata->setup_gpio(OTG_STATE_A_HOST);
688 #ifdef CONFIG_USB
689 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
690 device_wakeup_enable(hcd->self.controller);
691 #endif
692 } else {
693 dev_dbg(phy->dev, "host off\n");
694
695 #ifdef CONFIG_USB
696 usb_remove_hcd(hcd);
697 #endif
698 if (pdata->setup_gpio)
699 pdata->setup_gpio(OTG_STATE_UNDEFINED);
700 if (pdata->vbus_power)
701 pdata->vbus_power(0);
702 }
703 }
704
705 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
706 {
707 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
708 struct usb_hcd *hcd;
709
710 /*
711 * Fail host registration if this board can support
712 * only peripheral configuration.
713 */
714 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
715 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
716 return -ENODEV;
717 }
718
719 if (!host) {
720 if (otg->state == OTG_STATE_A_HOST) {
721 pm_runtime_get_sync(otg->usb_phy->dev);
722 msm_otg_start_host(otg->usb_phy, 0);
723 otg->host = NULL;
724 otg->state = OTG_STATE_UNDEFINED;
725 schedule_work(&motg->sm_work);
726 } else {
727 otg->host = NULL;
728 }
729
730 return 0;
731 }
732
733 hcd = bus_to_hcd(host);
734 hcd->power_budget = motg->pdata->power_budget;
735
736 otg->host = host;
737 dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
738
739 /*
740 * Kick the state machine work, if peripheral is not supported
741 * or peripheral is already registered with us.
742 */
743 if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
744 pm_runtime_get_sync(otg->usb_phy->dev);
745 schedule_work(&motg->sm_work);
746 }
747
748 return 0;
749 }
750
751 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
752 {
753 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
754 struct msm_otg_platform_data *pdata = motg->pdata;
755
756 if (!phy->otg->gadget)
757 return;
758
759 if (on) {
760 dev_dbg(phy->dev, "gadget on\n");
761 /*
762 * Some boards have a switch cotrolled by gpio
763 * to enable/disable internal HUB. Disable internal
764 * HUB before kicking the gadget.
765 */
766 if (pdata->setup_gpio)
767 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
768 usb_gadget_vbus_connect(phy->otg->gadget);
769 } else {
770 dev_dbg(phy->dev, "gadget off\n");
771 usb_gadget_vbus_disconnect(phy->otg->gadget);
772 if (pdata->setup_gpio)
773 pdata->setup_gpio(OTG_STATE_UNDEFINED);
774 }
775
776 }
777
778 static int msm_otg_set_peripheral(struct usb_otg *otg,
779 struct usb_gadget *gadget)
780 {
781 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
782
783 /*
784 * Fail peripheral registration if this board can support
785 * only host configuration.
786 */
787 if (motg->pdata->mode == USB_DR_MODE_HOST) {
788 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
789 return -ENODEV;
790 }
791
792 if (!gadget) {
793 if (otg->state == OTG_STATE_B_PERIPHERAL) {
794 pm_runtime_get_sync(otg->usb_phy->dev);
795 msm_otg_start_peripheral(otg->usb_phy, 0);
796 otg->gadget = NULL;
797 otg->state = OTG_STATE_UNDEFINED;
798 schedule_work(&motg->sm_work);
799 } else {
800 otg->gadget = NULL;
801 }
802
803 return 0;
804 }
805 otg->gadget = gadget;
806 dev_dbg(otg->usb_phy->dev,
807 "peripheral driver registered w/ tranceiver\n");
808
809 /*
810 * Kick the state machine work, if host is not supported
811 * or host is already registered with us.
812 */
813 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
814 pm_runtime_get_sync(otg->usb_phy->dev);
815 schedule_work(&motg->sm_work);
816 }
817
818 return 0;
819 }
820
821 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
822 {
823 struct usb_phy *phy = &motg->phy;
824 u32 chg_det;
825 bool ret = false;
826
827 switch (motg->pdata->phy_type) {
828 case CI_45NM_INTEGRATED_PHY:
829 chg_det = ulpi_read(phy, 0x34);
830 ret = chg_det & (1 << 4);
831 break;
832 case SNPS_28NM_INTEGRATED_PHY:
833 chg_det = ulpi_read(phy, 0x87);
834 ret = chg_det & 1;
835 break;
836 default:
837 break;
838 }
839 return ret;
840 }
841
842 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
843 {
844 struct usb_phy *phy = &motg->phy;
845 u32 chg_det;
846
847 switch (motg->pdata->phy_type) {
848 case CI_45NM_INTEGRATED_PHY:
849 chg_det = ulpi_read(phy, 0x34);
850 /* Turn off charger block */
851 chg_det |= ~(1 << 1);
852 ulpi_write(phy, chg_det, 0x34);
853 udelay(20);
854 /* control chg block via ULPI */
855 chg_det &= ~(1 << 3);
856 ulpi_write(phy, chg_det, 0x34);
857 /* put it in host mode for enabling D- source */
858 chg_det &= ~(1 << 2);
859 ulpi_write(phy, chg_det, 0x34);
860 /* Turn on chg detect block */
861 chg_det &= ~(1 << 1);
862 ulpi_write(phy, chg_det, 0x34);
863 udelay(20);
864 /* enable chg detection */
865 chg_det &= ~(1 << 0);
866 ulpi_write(phy, chg_det, 0x34);
867 break;
868 case SNPS_28NM_INTEGRATED_PHY:
869 /*
870 * Configure DM as current source, DP as current sink
871 * and enable battery charging comparators.
872 */
873 ulpi_write(phy, 0x8, 0x85);
874 ulpi_write(phy, 0x2, 0x85);
875 ulpi_write(phy, 0x1, 0x85);
876 break;
877 default:
878 break;
879 }
880 }
881
882 static bool msm_chg_check_primary_det(struct msm_otg *motg)
883 {
884 struct usb_phy *phy = &motg->phy;
885 u32 chg_det;
886 bool ret = false;
887
888 switch (motg->pdata->phy_type) {
889 case CI_45NM_INTEGRATED_PHY:
890 chg_det = ulpi_read(phy, 0x34);
891 ret = chg_det & (1 << 4);
892 break;
893 case SNPS_28NM_INTEGRATED_PHY:
894 chg_det = ulpi_read(phy, 0x87);
895 ret = chg_det & 1;
896 break;
897 default:
898 break;
899 }
900 return ret;
901 }
902
903 static void msm_chg_enable_primary_det(struct msm_otg *motg)
904 {
905 struct usb_phy *phy = &motg->phy;
906 u32 chg_det;
907
908 switch (motg->pdata->phy_type) {
909 case CI_45NM_INTEGRATED_PHY:
910 chg_det = ulpi_read(phy, 0x34);
911 /* enable chg detection */
912 chg_det &= ~(1 << 0);
913 ulpi_write(phy, chg_det, 0x34);
914 break;
915 case SNPS_28NM_INTEGRATED_PHY:
916 /*
917 * Configure DP as current source, DM as current sink
918 * and enable battery charging comparators.
919 */
920 ulpi_write(phy, 0x2, 0x85);
921 ulpi_write(phy, 0x1, 0x85);
922 break;
923 default:
924 break;
925 }
926 }
927
928 static bool msm_chg_check_dcd(struct msm_otg *motg)
929 {
930 struct usb_phy *phy = &motg->phy;
931 u32 line_state;
932 bool ret = false;
933
934 switch (motg->pdata->phy_type) {
935 case CI_45NM_INTEGRATED_PHY:
936 line_state = ulpi_read(phy, 0x15);
937 ret = !(line_state & 1);
938 break;
939 case SNPS_28NM_INTEGRATED_PHY:
940 line_state = ulpi_read(phy, 0x87);
941 ret = line_state & 2;
942 break;
943 default:
944 break;
945 }
946 return ret;
947 }
948
949 static void msm_chg_disable_dcd(struct msm_otg *motg)
950 {
951 struct usb_phy *phy = &motg->phy;
952 u32 chg_det;
953
954 switch (motg->pdata->phy_type) {
955 case CI_45NM_INTEGRATED_PHY:
956 chg_det = ulpi_read(phy, 0x34);
957 chg_det &= ~(1 << 5);
958 ulpi_write(phy, chg_det, 0x34);
959 break;
960 case SNPS_28NM_INTEGRATED_PHY:
961 ulpi_write(phy, 0x10, 0x86);
962 break;
963 default:
964 break;
965 }
966 }
967
968 static void msm_chg_enable_dcd(struct msm_otg *motg)
969 {
970 struct usb_phy *phy = &motg->phy;
971 u32 chg_det;
972
973 switch (motg->pdata->phy_type) {
974 case CI_45NM_INTEGRATED_PHY:
975 chg_det = ulpi_read(phy, 0x34);
976 /* Turn on D+ current source */
977 chg_det |= (1 << 5);
978 ulpi_write(phy, chg_det, 0x34);
979 break;
980 case SNPS_28NM_INTEGRATED_PHY:
981 /* Data contact detection enable */
982 ulpi_write(phy, 0x10, 0x85);
983 break;
984 default:
985 break;
986 }
987 }
988
989 static void msm_chg_block_on(struct msm_otg *motg)
990 {
991 struct usb_phy *phy = &motg->phy;
992 u32 func_ctrl, chg_det;
993
994 /* put the controller in non-driving mode */
995 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
996 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
997 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
998 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
999
1000 switch (motg->pdata->phy_type) {
1001 case CI_45NM_INTEGRATED_PHY:
1002 chg_det = ulpi_read(phy, 0x34);
1003 /* control chg block via ULPI */
1004 chg_det &= ~(1 << 3);
1005 ulpi_write(phy, chg_det, 0x34);
1006 /* Turn on chg detect block */
1007 chg_det &= ~(1 << 1);
1008 ulpi_write(phy, chg_det, 0x34);
1009 udelay(20);
1010 break;
1011 case SNPS_28NM_INTEGRATED_PHY:
1012 /* Clear charger detecting control bits */
1013 ulpi_write(phy, 0x3F, 0x86);
1014 /* Clear alt interrupt latch and enable bits */
1015 ulpi_write(phy, 0x1F, 0x92);
1016 ulpi_write(phy, 0x1F, 0x95);
1017 udelay(100);
1018 break;
1019 default:
1020 break;
1021 }
1022 }
1023
1024 static void msm_chg_block_off(struct msm_otg *motg)
1025 {
1026 struct usb_phy *phy = &motg->phy;
1027 u32 func_ctrl, chg_det;
1028
1029 switch (motg->pdata->phy_type) {
1030 case CI_45NM_INTEGRATED_PHY:
1031 chg_det = ulpi_read(phy, 0x34);
1032 /* Turn off charger block */
1033 chg_det |= ~(1 << 1);
1034 ulpi_write(phy, chg_det, 0x34);
1035 break;
1036 case SNPS_28NM_INTEGRATED_PHY:
1037 /* Clear charger detecting control bits */
1038 ulpi_write(phy, 0x3F, 0x86);
1039 /* Clear alt interrupt latch and enable bits */
1040 ulpi_write(phy, 0x1F, 0x92);
1041 ulpi_write(phy, 0x1F, 0x95);
1042 break;
1043 default:
1044 break;
1045 }
1046
1047 /* put the controller in normal mode */
1048 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1049 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1050 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1051 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1052 }
1053
1054 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1055 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1056 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1057 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1058 static void msm_chg_detect_work(struct work_struct *w)
1059 {
1060 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1061 struct usb_phy *phy = &motg->phy;
1062 bool is_dcd, tmout, vout;
1063 unsigned long delay;
1064
1065 dev_dbg(phy->dev, "chg detection work\n");
1066 switch (motg->chg_state) {
1067 case USB_CHG_STATE_UNDEFINED:
1068 pm_runtime_get_sync(phy->dev);
1069 msm_chg_block_on(motg);
1070 msm_chg_enable_dcd(motg);
1071 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1072 motg->dcd_retries = 0;
1073 delay = MSM_CHG_DCD_POLL_TIME;
1074 break;
1075 case USB_CHG_STATE_WAIT_FOR_DCD:
1076 is_dcd = msm_chg_check_dcd(motg);
1077 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1078 if (is_dcd || tmout) {
1079 msm_chg_disable_dcd(motg);
1080 msm_chg_enable_primary_det(motg);
1081 delay = MSM_CHG_PRIMARY_DET_TIME;
1082 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1083 } else {
1084 delay = MSM_CHG_DCD_POLL_TIME;
1085 }
1086 break;
1087 case USB_CHG_STATE_DCD_DONE:
1088 vout = msm_chg_check_primary_det(motg);
1089 if (vout) {
1090 msm_chg_enable_secondary_det(motg);
1091 delay = MSM_CHG_SECONDARY_DET_TIME;
1092 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1093 } else {
1094 motg->chg_type = USB_SDP_CHARGER;
1095 motg->chg_state = USB_CHG_STATE_DETECTED;
1096 delay = 0;
1097 }
1098 break;
1099 case USB_CHG_STATE_PRIMARY_DONE:
1100 vout = msm_chg_check_secondary_det(motg);
1101 if (vout)
1102 motg->chg_type = USB_DCP_CHARGER;
1103 else
1104 motg->chg_type = USB_CDP_CHARGER;
1105 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1106 /* fall through */
1107 case USB_CHG_STATE_SECONDARY_DONE:
1108 motg->chg_state = USB_CHG_STATE_DETECTED;
1109 case USB_CHG_STATE_DETECTED:
1110 msm_chg_block_off(motg);
1111 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1112 schedule_work(&motg->sm_work);
1113 return;
1114 default:
1115 return;
1116 }
1117
1118 schedule_delayed_work(&motg->chg_work, delay);
1119 }
1120
1121 /*
1122 * We support OTG, Peripheral only and Host only configurations. In case
1123 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1124 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1125 * enabled when switch is controlled by user and default mode is supplied
1126 * by board file, which can be changed by userspace later.
1127 */
1128 static void msm_otg_init_sm(struct msm_otg *motg)
1129 {
1130 struct msm_otg_platform_data *pdata = motg->pdata;
1131 u32 otgsc = readl(USB_OTGSC);
1132
1133 switch (pdata->mode) {
1134 case USB_DR_MODE_OTG:
1135 if (pdata->otg_control == OTG_PHY_CONTROL) {
1136 if (otgsc & OTGSC_ID)
1137 set_bit(ID, &motg->inputs);
1138 else
1139 clear_bit(ID, &motg->inputs);
1140
1141 if (otgsc & OTGSC_BSV)
1142 set_bit(B_SESS_VLD, &motg->inputs);
1143 else
1144 clear_bit(B_SESS_VLD, &motg->inputs);
1145 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1146 set_bit(ID, &motg->inputs);
1147 clear_bit(B_SESS_VLD, &motg->inputs);
1148 }
1149 break;
1150 case USB_DR_MODE_HOST:
1151 clear_bit(ID, &motg->inputs);
1152 break;
1153 case USB_DR_MODE_PERIPHERAL:
1154 set_bit(ID, &motg->inputs);
1155 if (otgsc & OTGSC_BSV)
1156 set_bit(B_SESS_VLD, &motg->inputs);
1157 else
1158 clear_bit(B_SESS_VLD, &motg->inputs);
1159 break;
1160 default:
1161 break;
1162 }
1163 }
1164
1165 static void msm_otg_sm_work(struct work_struct *w)
1166 {
1167 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1168 struct usb_otg *otg = motg->phy.otg;
1169
1170 switch (otg->state) {
1171 case OTG_STATE_UNDEFINED:
1172 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1173 msm_otg_reset(otg->usb_phy);
1174 msm_otg_init_sm(motg);
1175 otg->state = OTG_STATE_B_IDLE;
1176 /* FALL THROUGH */
1177 case OTG_STATE_B_IDLE:
1178 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1179 if (!test_bit(ID, &motg->inputs) && otg->host) {
1180 /* disable BSV bit */
1181 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1182 msm_otg_start_host(otg->usb_phy, 1);
1183 otg->state = OTG_STATE_A_HOST;
1184 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1185 switch (motg->chg_state) {
1186 case USB_CHG_STATE_UNDEFINED:
1187 msm_chg_detect_work(&motg->chg_work.work);
1188 break;
1189 case USB_CHG_STATE_DETECTED:
1190 switch (motg->chg_type) {
1191 case USB_DCP_CHARGER:
1192 msm_otg_notify_charger(motg,
1193 IDEV_CHG_MAX);
1194 break;
1195 case USB_CDP_CHARGER:
1196 msm_otg_notify_charger(motg,
1197 IDEV_CHG_MAX);
1198 msm_otg_start_peripheral(otg->usb_phy,
1199 1);
1200 otg->state
1201 = OTG_STATE_B_PERIPHERAL;
1202 break;
1203 case USB_SDP_CHARGER:
1204 msm_otg_notify_charger(motg, IUNIT);
1205 msm_otg_start_peripheral(otg->usb_phy,
1206 1);
1207 otg->state
1208 = OTG_STATE_B_PERIPHERAL;
1209 break;
1210 default:
1211 break;
1212 }
1213 break;
1214 default:
1215 break;
1216 }
1217 } else {
1218 /*
1219 * If charger detection work is pending, decrement
1220 * the pm usage counter to balance with the one that
1221 * is incremented in charger detection work.
1222 */
1223 if (cancel_delayed_work_sync(&motg->chg_work)) {
1224 pm_runtime_put_sync(otg->usb_phy->dev);
1225 msm_otg_reset(otg->usb_phy);
1226 }
1227 msm_otg_notify_charger(motg, 0);
1228 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1229 motg->chg_type = USB_INVALID_CHARGER;
1230 }
1231
1232 if (otg->state == OTG_STATE_B_IDLE)
1233 pm_runtime_put_sync(otg->usb_phy->dev);
1234 break;
1235 case OTG_STATE_B_PERIPHERAL:
1236 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1237 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1238 !test_bit(ID, &motg->inputs)) {
1239 msm_otg_notify_charger(motg, 0);
1240 msm_otg_start_peripheral(otg->usb_phy, 0);
1241 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1242 motg->chg_type = USB_INVALID_CHARGER;
1243 otg->state = OTG_STATE_B_IDLE;
1244 msm_otg_reset(otg->usb_phy);
1245 schedule_work(w);
1246 }
1247 break;
1248 case OTG_STATE_A_HOST:
1249 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1250 if (test_bit(ID, &motg->inputs)) {
1251 msm_otg_start_host(otg->usb_phy, 0);
1252 otg->state = OTG_STATE_B_IDLE;
1253 msm_otg_reset(otg->usb_phy);
1254 schedule_work(w);
1255 }
1256 break;
1257 default:
1258 break;
1259 }
1260 }
1261
1262 static irqreturn_t msm_otg_irq(int irq, void *data)
1263 {
1264 struct msm_otg *motg = data;
1265 struct usb_phy *phy = &motg->phy;
1266 u32 otgsc = 0;
1267
1268 if (atomic_read(&motg->in_lpm)) {
1269 disable_irq_nosync(irq);
1270 motg->async_int = 1;
1271 pm_runtime_get(phy->dev);
1272 return IRQ_HANDLED;
1273 }
1274
1275 otgsc = readl(USB_OTGSC);
1276 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1277 return IRQ_NONE;
1278
1279 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1280 if (otgsc & OTGSC_ID)
1281 set_bit(ID, &motg->inputs);
1282 else
1283 clear_bit(ID, &motg->inputs);
1284 dev_dbg(phy->dev, "ID set/clear\n");
1285 pm_runtime_get_noresume(phy->dev);
1286 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1287 if (otgsc & OTGSC_BSV)
1288 set_bit(B_SESS_VLD, &motg->inputs);
1289 else
1290 clear_bit(B_SESS_VLD, &motg->inputs);
1291 dev_dbg(phy->dev, "BSV set/clear\n");
1292 pm_runtime_get_noresume(phy->dev);
1293 }
1294
1295 writel(otgsc, USB_OTGSC);
1296 schedule_work(&motg->sm_work);
1297 return IRQ_HANDLED;
1298 }
1299
1300 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1301 {
1302 struct msm_otg *motg = s->private;
1303 struct usb_otg *otg = motg->phy.otg;
1304
1305 switch (otg->state) {
1306 case OTG_STATE_A_HOST:
1307 seq_puts(s, "host\n");
1308 break;
1309 case OTG_STATE_B_PERIPHERAL:
1310 seq_puts(s, "peripheral\n");
1311 break;
1312 default:
1313 seq_puts(s, "none\n");
1314 break;
1315 }
1316
1317 return 0;
1318 }
1319
1320 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1321 {
1322 return single_open(file, msm_otg_mode_show, inode->i_private);
1323 }
1324
1325 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1326 size_t count, loff_t *ppos)
1327 {
1328 struct seq_file *s = file->private_data;
1329 struct msm_otg *motg = s->private;
1330 char buf[16];
1331 struct usb_otg *otg = motg->phy.otg;
1332 int status = count;
1333 enum usb_dr_mode req_mode;
1334
1335 memset(buf, 0x00, sizeof(buf));
1336
1337 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1338 status = -EFAULT;
1339 goto out;
1340 }
1341
1342 if (!strncmp(buf, "host", 4)) {
1343 req_mode = USB_DR_MODE_HOST;
1344 } else if (!strncmp(buf, "peripheral", 10)) {
1345 req_mode = USB_DR_MODE_PERIPHERAL;
1346 } else if (!strncmp(buf, "none", 4)) {
1347 req_mode = USB_DR_MODE_UNKNOWN;
1348 } else {
1349 status = -EINVAL;
1350 goto out;
1351 }
1352
1353 switch (req_mode) {
1354 case USB_DR_MODE_UNKNOWN:
1355 switch (otg->state) {
1356 case OTG_STATE_A_HOST:
1357 case OTG_STATE_B_PERIPHERAL:
1358 set_bit(ID, &motg->inputs);
1359 clear_bit(B_SESS_VLD, &motg->inputs);
1360 break;
1361 default:
1362 goto out;
1363 }
1364 break;
1365 case USB_DR_MODE_PERIPHERAL:
1366 switch (otg->state) {
1367 case OTG_STATE_B_IDLE:
1368 case OTG_STATE_A_HOST:
1369 set_bit(ID, &motg->inputs);
1370 set_bit(B_SESS_VLD, &motg->inputs);
1371 break;
1372 default:
1373 goto out;
1374 }
1375 break;
1376 case USB_DR_MODE_HOST:
1377 switch (otg->state) {
1378 case OTG_STATE_B_IDLE:
1379 case OTG_STATE_B_PERIPHERAL:
1380 clear_bit(ID, &motg->inputs);
1381 break;
1382 default:
1383 goto out;
1384 }
1385 break;
1386 default:
1387 goto out;
1388 }
1389
1390 pm_runtime_get_sync(otg->usb_phy->dev);
1391 schedule_work(&motg->sm_work);
1392 out:
1393 return status;
1394 }
1395
1396 static const struct file_operations msm_otg_mode_fops = {
1397 .open = msm_otg_mode_open,
1398 .read = seq_read,
1399 .write = msm_otg_mode_write,
1400 .llseek = seq_lseek,
1401 .release = single_release,
1402 };
1403
1404 static struct dentry *msm_otg_dbg_root;
1405 static struct dentry *msm_otg_dbg_mode;
1406
1407 static int msm_otg_debugfs_init(struct msm_otg *motg)
1408 {
1409 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1410
1411 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1412 return -ENODEV;
1413
1414 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1415 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1416 if (!msm_otg_dbg_mode) {
1417 debugfs_remove(msm_otg_dbg_root);
1418 msm_otg_dbg_root = NULL;
1419 return -ENODEV;
1420 }
1421
1422 return 0;
1423 }
1424
1425 static void msm_otg_debugfs_cleanup(void)
1426 {
1427 debugfs_remove(msm_otg_dbg_mode);
1428 debugfs_remove(msm_otg_dbg_root);
1429 }
1430
1431 static const struct of_device_id msm_otg_dt_match[] = {
1432 {
1433 .compatible = "qcom,usb-otg-ci",
1434 .data = (void *) CI_45NM_INTEGRATED_PHY
1435 },
1436 {
1437 .compatible = "qcom,usb-otg-snps",
1438 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1439 },
1440 { }
1441 };
1442 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1443
1444 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1445 {
1446 struct msm_otg_platform_data *pdata;
1447 const struct of_device_id *id;
1448 struct device_node *node = pdev->dev.of_node;
1449 struct property *prop;
1450 int len, ret, words;
1451 u32 val, tmp[3];
1452
1453 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1454 if (!pdata)
1455 return -ENOMEM;
1456
1457 motg->pdata = pdata;
1458
1459 id = of_match_device(msm_otg_dt_match, &pdev->dev);
1460 pdata->phy_type = (enum msm_usb_phy_type) id->data;
1461
1462 motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1463 if (IS_ERR(motg->link_rst))
1464 return PTR_ERR(motg->link_rst);
1465
1466 motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1467 if (IS_ERR(motg->phy_rst))
1468 motg->phy_rst = NULL;
1469
1470 pdata->mode = of_usb_get_dr_mode(node);
1471 if (pdata->mode == USB_DR_MODE_UNKNOWN)
1472 pdata->mode = USB_DR_MODE_OTG;
1473
1474 pdata->otg_control = OTG_PHY_CONTROL;
1475 if (!of_property_read_u32(node, "qcom,otg-control", &val))
1476 if (val == OTG_PMIC_CONTROL)
1477 pdata->otg_control = val;
1478
1479 if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1480 motg->phy_number = val;
1481
1482 motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1483 motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1484 motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1485
1486 if (of_get_property(node, "qcom,vdd-levels", &len) &&
1487 len == sizeof(tmp)) {
1488 of_property_read_u32_array(node, "qcom,vdd-levels",
1489 tmp, len / sizeof(*tmp));
1490 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1491 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1492 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1493 }
1494
1495 prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1496 if (!prop || !len)
1497 return 0;
1498
1499 words = len / sizeof(u32);
1500
1501 if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1502 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1503 return 0;
1504 }
1505
1506 pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1507 if (!pdata->phy_init_seq)
1508 return 0;
1509
1510 ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1511 pdata->phy_init_seq, words);
1512 if (!ret)
1513 pdata->phy_init_sz = words;
1514
1515 return 0;
1516 }
1517
1518 static int msm_otg_probe(struct platform_device *pdev)
1519 {
1520 struct regulator_bulk_data regs[3];
1521 int ret = 0;
1522 struct device_node *np = pdev->dev.of_node;
1523 struct msm_otg_platform_data *pdata;
1524 struct resource *res;
1525 struct msm_otg *motg;
1526 struct usb_phy *phy;
1527 void __iomem *phy_select;
1528
1529 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1530 if (!motg)
1531 return -ENOMEM;
1532
1533 pdata = dev_get_platdata(&pdev->dev);
1534 if (!pdata) {
1535 if (!np)
1536 return -ENXIO;
1537 ret = msm_otg_read_dt(pdev, motg);
1538 if (ret)
1539 return ret;
1540 }
1541
1542 motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1543 GFP_KERNEL);
1544 if (!motg->phy.otg)
1545 return -ENOMEM;
1546
1547 phy = &motg->phy;
1548 phy->dev = &pdev->dev;
1549
1550 motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1551 if (IS_ERR(motg->clk)) {
1552 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1553 return PTR_ERR(motg->clk);
1554 }
1555
1556 /*
1557 * If USB Core is running its protocol engine based on CORE CLK,
1558 * CORE CLK must be running at >55Mhz for correct HSUSB
1559 * operation and USB core cannot tolerate frequency changes on
1560 * CORE CLK.
1561 */
1562 motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1563 if (IS_ERR(motg->pclk)) {
1564 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1565 return PTR_ERR(motg->pclk);
1566 }
1567
1568 /*
1569 * USB core clock is not present on all MSM chips. This
1570 * clock is introduced to remove the dependency on AXI
1571 * bus frequency.
1572 */
1573 motg->core_clk = devm_clk_get(&pdev->dev,
1574 np ? "alt_core" : "usb_hs_core_clk");
1575
1576 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1577 if (!res)
1578 return -EINVAL;
1579 motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1580 if (!motg->regs)
1581 return -ENOMEM;
1582
1583 /*
1584 * NOTE: The PHYs can be multiplexed between the chipidea controller
1585 * and the dwc3 controller, using a single bit. It is important that
1586 * the dwc3 driver does not set this bit in an incompatible way.
1587 */
1588 if (motg->phy_number) {
1589 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1590 if (!phy_select)
1591 return -ENOMEM;
1592 /* Enable second PHY with the OTG port */
1593 writel(0x1, phy_select);
1594 }
1595
1596 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1597
1598 motg->irq = platform_get_irq(pdev, 0);
1599 if (motg->irq < 0) {
1600 dev_err(&pdev->dev, "platform_get_irq failed\n");
1601 return motg->irq;
1602 }
1603
1604 regs[0].supply = "vddcx";
1605 regs[1].supply = "v3p3";
1606 regs[2].supply = "v1p8";
1607
1608 ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1609 if (ret)
1610 return ret;
1611
1612 motg->vddcx = regs[0].consumer;
1613 motg->v3p3 = regs[1].consumer;
1614 motg->v1p8 = regs[2].consumer;
1615
1616 clk_set_rate(motg->clk, 60000000);
1617
1618 clk_prepare_enable(motg->clk);
1619 clk_prepare_enable(motg->pclk);
1620
1621 if (!IS_ERR(motg->core_clk))
1622 clk_prepare_enable(motg->core_clk);
1623
1624 ret = msm_hsusb_init_vddcx(motg, 1);
1625 if (ret) {
1626 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1627 goto disable_clks;
1628 }
1629
1630 ret = msm_hsusb_ldo_init(motg, 1);
1631 if (ret) {
1632 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1633 goto disable_vddcx;
1634 }
1635 ret = msm_hsusb_ldo_set_mode(motg, 1);
1636 if (ret) {
1637 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1638 goto disable_ldo;
1639 }
1640
1641 writel(0, USB_USBINTR);
1642 writel(0, USB_OTGSC);
1643
1644 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1645 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1646 ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1647 "msm_otg", motg);
1648 if (ret) {
1649 dev_err(&pdev->dev, "request irq failed\n");
1650 goto disable_ldo;
1651 }
1652
1653 phy->init = msm_phy_init;
1654 phy->set_power = msm_otg_set_power;
1655 phy->notify_disconnect = msm_phy_notify_disconnect;
1656 phy->type = USB_PHY_TYPE_USB2;
1657
1658 phy->io_ops = &msm_otg_io_ops;
1659
1660 phy->otg->usb_phy = &motg->phy;
1661 phy->otg->set_host = msm_otg_set_host;
1662 phy->otg->set_peripheral = msm_otg_set_peripheral;
1663
1664 msm_usb_reset(phy);
1665
1666 ret = usb_add_phy_dev(&motg->phy);
1667 if (ret) {
1668 dev_err(&pdev->dev, "usb_add_phy failed\n");
1669 goto disable_ldo;
1670 }
1671
1672 platform_set_drvdata(pdev, motg);
1673 device_init_wakeup(&pdev->dev, 1);
1674
1675 if (motg->pdata->mode == USB_DR_MODE_OTG &&
1676 motg->pdata->otg_control == OTG_USER_CONTROL) {
1677 ret = msm_otg_debugfs_init(motg);
1678 if (ret)
1679 dev_dbg(&pdev->dev, "Can not create mode change file\n");
1680 }
1681
1682 pm_runtime_set_active(&pdev->dev);
1683 pm_runtime_enable(&pdev->dev);
1684
1685 return 0;
1686
1687 disable_ldo:
1688 msm_hsusb_ldo_init(motg, 0);
1689 disable_vddcx:
1690 msm_hsusb_init_vddcx(motg, 0);
1691 disable_clks:
1692 clk_disable_unprepare(motg->pclk);
1693 clk_disable_unprepare(motg->clk);
1694 if (!IS_ERR(motg->core_clk))
1695 clk_disable_unprepare(motg->core_clk);
1696 return ret;
1697 }
1698
1699 static int msm_otg_remove(struct platform_device *pdev)
1700 {
1701 struct msm_otg *motg = platform_get_drvdata(pdev);
1702 struct usb_phy *phy = &motg->phy;
1703 int cnt = 0;
1704
1705 if (phy->otg->host || phy->otg->gadget)
1706 return -EBUSY;
1707
1708 msm_otg_debugfs_cleanup();
1709 cancel_delayed_work_sync(&motg->chg_work);
1710 cancel_work_sync(&motg->sm_work);
1711
1712 pm_runtime_resume(&pdev->dev);
1713
1714 device_init_wakeup(&pdev->dev, 0);
1715 pm_runtime_disable(&pdev->dev);
1716
1717 usb_remove_phy(phy);
1718 disable_irq(motg->irq);
1719
1720 /*
1721 * Put PHY in low power mode.
1722 */
1723 ulpi_read(phy, 0x14);
1724 ulpi_write(phy, 0x08, 0x09);
1725
1726 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1727 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1728 if (readl(USB_PORTSC) & PORTSC_PHCD)
1729 break;
1730 udelay(1);
1731 cnt++;
1732 }
1733 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1734 dev_err(phy->dev, "Unable to suspend PHY\n");
1735
1736 clk_disable_unprepare(motg->pclk);
1737 clk_disable_unprepare(motg->clk);
1738 if (!IS_ERR(motg->core_clk))
1739 clk_disable_unprepare(motg->core_clk);
1740 msm_hsusb_ldo_init(motg, 0);
1741
1742 pm_runtime_set_suspended(&pdev->dev);
1743
1744 return 0;
1745 }
1746
1747 #ifdef CONFIG_PM
1748 static int msm_otg_runtime_idle(struct device *dev)
1749 {
1750 struct msm_otg *motg = dev_get_drvdata(dev);
1751 struct usb_otg *otg = motg->phy.otg;
1752
1753 dev_dbg(dev, "OTG runtime idle\n");
1754
1755 /*
1756 * It is observed some times that a spurious interrupt
1757 * comes when PHY is put into LPM immediately after PHY reset.
1758 * This 1 sec delay also prevents entering into LPM immediately
1759 * after asynchronous interrupt.
1760 */
1761 if (otg->state != OTG_STATE_UNDEFINED)
1762 pm_schedule_suspend(dev, 1000);
1763
1764 return -EAGAIN;
1765 }
1766
1767 static int msm_otg_runtime_suspend(struct device *dev)
1768 {
1769 struct msm_otg *motg = dev_get_drvdata(dev);
1770
1771 dev_dbg(dev, "OTG runtime suspend\n");
1772 return msm_otg_suspend(motg);
1773 }
1774
1775 static int msm_otg_runtime_resume(struct device *dev)
1776 {
1777 struct msm_otg *motg = dev_get_drvdata(dev);
1778
1779 dev_dbg(dev, "OTG runtime resume\n");
1780 return msm_otg_resume(motg);
1781 }
1782 #endif
1783
1784 #ifdef CONFIG_PM_SLEEP
1785 static int msm_otg_pm_suspend(struct device *dev)
1786 {
1787 struct msm_otg *motg = dev_get_drvdata(dev);
1788
1789 dev_dbg(dev, "OTG PM suspend\n");
1790 return msm_otg_suspend(motg);
1791 }
1792
1793 static int msm_otg_pm_resume(struct device *dev)
1794 {
1795 struct msm_otg *motg = dev_get_drvdata(dev);
1796 int ret;
1797
1798 dev_dbg(dev, "OTG PM resume\n");
1799
1800 ret = msm_otg_resume(motg);
1801 if (ret)
1802 return ret;
1803
1804 /*
1805 * Runtime PM Documentation recommends bringing the
1806 * device to full powered state upon resume.
1807 */
1808 pm_runtime_disable(dev);
1809 pm_runtime_set_active(dev);
1810 pm_runtime_enable(dev);
1811
1812 return 0;
1813 }
1814 #endif
1815
1816 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1817 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1818 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1819 msm_otg_runtime_idle)
1820 };
1821
1822 static struct platform_driver msm_otg_driver = {
1823 .probe = msm_otg_probe,
1824 .remove = msm_otg_remove,
1825 .driver = {
1826 .name = DRIVER_NAME,
1827 .pm = &msm_otg_dev_pm_ops,
1828 .of_match_table = msm_otg_dt_match,
1829 },
1830 };
1831
1832 module_platform_driver(msm_otg_driver);
1833
1834 MODULE_LICENSE("GPL v2");
1835 MODULE_DESCRIPTION("MSM USB transceiver driver");
Linux kernel - Deliverables
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