2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/errno.h>
56 #include <linux/string.h>
58 #include <linux/slab.h>
59 #include <linux/vmalloc.h>
60 #include <linux/delay.h>
61 #include <linux/console.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/spinlock.h>
67 #include <linux/wait.h>
68 #include <linux/backlight.h>
71 #include <asm/uaccess.h>
73 #include <video/mach64.h>
78 #include <asm/machdep.h>
80 #include "../macmodes.h"
88 #include <linux/adb.h>
89 #include <linux/pmu.h>
91 #ifdef CONFIG_BOOTX_TEXT
92 #include <asm/btext.h>
94 #ifdef CONFIG_PMAC_BACKLIGHT
95 #include <asm/backlight.h>
107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
108 /* - must be large enough to catch all GUI-Regs */
109 /* - must be aligned to a PAGE boundary */
110 #define GUI_RESERVE (1 * PAGE_SIZE)
112 /* FIXME: remove the FAIL definition */
113 #define FAIL(msg) do { \
114 if (!(var->activate & FB_ACTIVATE_TEST)) \
115 printk(KERN_CRIT "atyfb: " msg "\n"); \
118 #define FAIL_MAX(msg, x, _max_) do { \
120 if (!(var->activate & FB_ACTIVATE_TEST)) \
121 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
126 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
128 #define DPRINTK(fmt, args...)
131 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
132 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
135 defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
136 static const u32 lt_lcd_regs
[] = {
143 0, /* EXT_VERT_STRETCH */
148 void aty_st_lcd(int index
, u32 val
, const struct atyfb_par
*par
)
150 if (M64_HAS(LT_LCD_REGS
)) {
151 aty_st_le32(lt_lcd_regs
[index
], val
, par
);
155 /* write addr byte */
156 temp
= aty_ld_le32(LCD_INDEX
, par
);
157 aty_st_le32(LCD_INDEX
, (temp
& ~LCD_INDEX_MASK
) | index
, par
);
158 /* write the register value */
159 aty_st_le32(LCD_DATA
, val
, par
);
163 u32
aty_ld_lcd(int index
, const struct atyfb_par
*par
)
165 if (M64_HAS(LT_LCD_REGS
)) {
166 return aty_ld_le32(lt_lcd_regs
[index
], par
);
170 /* write addr byte */
171 temp
= aty_ld_le32(LCD_INDEX
, par
);
172 aty_st_le32(LCD_INDEX
, (temp
& ~LCD_INDEX_MASK
) | index
, par
);
173 /* read the register value */
174 return aty_ld_le32(LCD_DATA
, par
);
177 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
179 #ifdef CONFIG_FB_ATY_GENERIC_LCD
183 * Reduce a fraction by factoring out the largest common divider of the
184 * fraction's numerator and denominator.
186 static void ATIReduceRatio(int *Numerator
, int *Denominator
)
188 int Multiplier
, Divider
, Remainder
;
190 Multiplier
= *Numerator
;
191 Divider
= *Denominator
;
193 while ((Remainder
= Multiplier
% Divider
))
195 Multiplier
= Divider
;
199 *Numerator
/= Divider
;
200 *Denominator
/= Divider
;
204 * The Hardware parameters for each card
207 struct pci_mmap_map
{
211 unsigned long prot_flag
;
212 unsigned long prot_mask
;
215 static struct fb_fix_screeninfo atyfb_fix __devinitdata
= {
217 .type
= FB_TYPE_PACKED_PIXELS
,
218 .visual
= FB_VISUAL_PSEUDOCOLOR
,
224 * Frame buffer device API
227 static int atyfb_open(struct fb_info
*info
, int user
);
228 static int atyfb_release(struct fb_info
*info
, int user
);
229 static int atyfb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
);
230 static int atyfb_set_par(struct fb_info
*info
);
231 static int atyfb_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
232 u_int transp
, struct fb_info
*info
);
233 static int atyfb_pan_display(struct fb_var_screeninfo
*var
, struct fb_info
*info
);
234 static int atyfb_blank(int blank
, struct fb_info
*info
);
235 static int atyfb_ioctl(struct fb_info
*info
, u_int cmd
, u_long arg
);
237 static int atyfb_mmap(struct fb_info
*info
, struct vm_area_struct
*vma
);
239 static int atyfb_sync(struct fb_info
*info
);
245 static int aty_init(struct fb_info
*info
);
246 static void aty_resume_chip(struct fb_info
*info
);
248 static int store_video_par(char *videopar
, unsigned char m64_num
);
251 static struct crtc saved_crtc
;
252 static union aty_pll saved_pll
;
253 static void aty_get_crtc(const struct atyfb_par
*par
, struct crtc
*crtc
);
255 static void aty_set_crtc(const struct atyfb_par
*par
, const struct crtc
*crtc
);
256 static int aty_var_to_crtc(const struct fb_info
*info
, const struct fb_var_screeninfo
*var
, struct crtc
*crtc
);
257 static int aty_crtc_to_var(const struct crtc
*crtc
, struct fb_var_screeninfo
*var
);
258 static void set_off_pitch(struct atyfb_par
*par
, const struct fb_info
*info
);
260 static int read_aty_sense(const struct atyfb_par
*par
);
265 * Interface used by the world
268 static struct fb_var_screeninfo default_var
= {
269 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
270 640, 480, 640, 480, 0, 0, 8, 0,
271 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
272 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
273 0, FB_VMODE_NONINTERLACED
276 static struct fb_videomode defmode
= {
277 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
278 NULL
, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
279 0, FB_VMODE_NONINTERLACED
282 static struct fb_ops atyfb_ops
= {
283 .owner
= THIS_MODULE
,
284 .fb_open
= atyfb_open
,
285 .fb_release
= atyfb_release
,
286 .fb_check_var
= atyfb_check_var
,
287 .fb_set_par
= atyfb_set_par
,
288 .fb_setcolreg
= atyfb_setcolreg
,
289 .fb_pan_display
= atyfb_pan_display
,
290 .fb_blank
= atyfb_blank
,
291 .fb_ioctl
= atyfb_ioctl
,
292 .fb_fillrect
= atyfb_fillrect
,
293 .fb_copyarea
= atyfb_copyarea
,
294 .fb_imageblit
= atyfb_imageblit
,
296 .fb_mmap
= atyfb_mmap
,
298 .fb_sync
= atyfb_sync
,
309 static int comp_sync __devinitdata
= -1;
312 #ifdef CONFIG_PMAC_BACKLIGHT
313 static int backlight __devinitdata
= 1;
315 static int backlight __devinitdata
= 0;
319 static int default_vmode __devinitdata
= VMODE_CHOOSE
;
320 static int default_cmode __devinitdata
= CMODE_CHOOSE
;
322 module_param_named(vmode
, default_vmode
, int, 0);
323 MODULE_PARM_DESC(vmode
, "int: video mode for mac");
324 module_param_named(cmode
, default_cmode
, int, 0);
325 MODULE_PARM_DESC(cmode
, "int: color mode for mac");
329 static unsigned int mach64_count __devinitdata
= 0;
330 static unsigned long phys_vmembase
[FB_MAX
] __devinitdata
= { 0, };
331 static unsigned long phys_size
[FB_MAX
] __devinitdata
= { 0, };
332 static unsigned long phys_guiregbase
[FB_MAX
] __devinitdata
= { 0, };
335 /* top -> down is an evolution of mach64 chipset, any corrections? */
336 #define ATI_CHIP_88800GX (M64F_GX)
337 #define ATI_CHIP_88800CX (M64F_GX)
339 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
340 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
342 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
343 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
345 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
346 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
347 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
349 /* FIXME what is this chip? */
350 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
352 /* make sets shorter */
353 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
355 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
356 /*#define ATI_CHIP_264GTDVD ?*/
357 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
359 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
360 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
361 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
363 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
364 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
369 int pll
, mclk
, xclk
, ecp_max
;
371 } aty_chips
[] __devinitdata
= {
372 #ifdef CONFIG_FB_ATY_GX
374 { PCI_CHIP_MACH64GX
, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX
},
375 { PCI_CHIP_MACH64CX
, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX
},
376 #endif /* CONFIG_FB_ATY_GX */
378 #ifdef CONFIG_FB_ATY_CT
379 { PCI_CHIP_MACH64CT
, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT
},
380 { PCI_CHIP_MACH64ET
, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET
},
382 /* FIXME what is this chip? */
383 { PCI_CHIP_MACH64LT
, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT
},
385 { PCI_CHIP_MACH64VT
, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT
},
386 { PCI_CHIP_MACH64GT
, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT
},
388 { PCI_CHIP_MACH64VU
, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3
},
389 { PCI_CHIP_MACH64GU
, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB
},
391 { PCI_CHIP_MACH64LG
, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG
| M64F_LT_LCD_REGS
| M64F_G3_PB_1024x768
},
393 { PCI_CHIP_MACH64VV
, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4
},
395 { PCI_CHIP_MACH64GV
, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C
},
396 { PCI_CHIP_MACH64GW
, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C
},
397 { PCI_CHIP_MACH64GY
, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C
},
398 { PCI_CHIP_MACH64GZ
, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C
},
400 { PCI_CHIP_MACH64GB
, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO
},
401 { PCI_CHIP_MACH64GD
, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO
},
402 { PCI_CHIP_MACH64GI
, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO
| M64F_MAGIC_VRAM_SIZE
},
403 { PCI_CHIP_MACH64GP
, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO
},
404 { PCI_CHIP_MACH64GQ
, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO
},
406 { PCI_CHIP_MACH64LB
, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO
},
407 { PCI_CHIP_MACH64LD
, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO
},
408 { PCI_CHIP_MACH64LI
, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO
| M64F_G3_PB_1_1
| M64F_G3_PB_1024x768
},
409 { PCI_CHIP_MACH64LP
, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO
| M64F_G3_PB_1024x768
},
410 { PCI_CHIP_MACH64LQ
, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO
},
412 { PCI_CHIP_MACH64GM
, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL
},
413 { PCI_CHIP_MACH64GN
, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL
},
414 { PCI_CHIP_MACH64GO
, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL
},
415 { PCI_CHIP_MACH64GL
, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL
},
416 { PCI_CHIP_MACH64GR
, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL
| M64F_SDRAM_MAGIC_PLL
},
417 { PCI_CHIP_MACH64GS
, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL
},
419 { PCI_CHIP_MACH64LM
, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY
},
420 { PCI_CHIP_MACH64LN
, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY
},
421 { PCI_CHIP_MACH64LR
, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY
},
422 { PCI_CHIP_MACH64LS
, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY
},
423 #endif /* CONFIG_FB_ATY_CT */
427 static int __devinit
correct_chipset(struct atyfb_par
*par
)
435 for (i
= ARRAY_SIZE(aty_chips
) - 1; i
>= 0; i
--)
436 if (par
->pci_id
== aty_chips
[i
].pci_id
)
439 name
= aty_chips
[i
].name
;
440 par
->pll_limits
.pll_max
= aty_chips
[i
].pll
;
441 par
->pll_limits
.mclk
= aty_chips
[i
].mclk
;
442 par
->pll_limits
.xclk
= aty_chips
[i
].xclk
;
443 par
->pll_limits
.ecp_max
= aty_chips
[i
].ecp_max
;
444 par
->features
= aty_chips
[i
].features
;
446 chip_id
= aty_ld_le32(CONFIG_CHIP_ID
, par
);
447 type
= chip_id
& CFG_CHIP_TYPE
;
448 rev
= (chip_id
& CFG_CHIP_REV
) >> 24;
450 switch(par
->pci_id
) {
451 #ifdef CONFIG_FB_ATY_GX
452 case PCI_CHIP_MACH64GX
:
456 case PCI_CHIP_MACH64CX
:
461 #ifdef CONFIG_FB_ATY_CT
462 case PCI_CHIP_MACH64VT
:
463 switch (rev
& 0x07) {
465 switch (rev
& 0xc0) {
467 name
= "ATI264VT (A3) (Mach64 VT)";
468 par
->pll_limits
.pll_max
= 170;
469 par
->pll_limits
.mclk
= 67;
470 par
->pll_limits
.xclk
= 67;
471 par
->pll_limits
.ecp_max
= 80;
472 par
->features
= ATI_CHIP_264VT
;
475 name
= "ATI264VT2 (A4) (Mach64 VT)";
476 par
->pll_limits
.pll_max
= 200;
477 par
->pll_limits
.mclk
= 67;
478 par
->pll_limits
.xclk
= 67;
479 par
->pll_limits
.ecp_max
= 80;
480 par
->features
= ATI_CHIP_264VT
| M64F_MAGIC_POSTDIV
;
485 name
= "ATI264VT3 (B1) (Mach64 VT)";
486 par
->pll_limits
.pll_max
= 200;
487 par
->pll_limits
.mclk
= 67;
488 par
->pll_limits
.xclk
= 67;
489 par
->pll_limits
.ecp_max
= 80;
490 par
->features
= ATI_CHIP_264VTB
;
493 name
= "ATI264VT3 (B2) (Mach64 VT)";
494 par
->pll_limits
.pll_max
= 200;
495 par
->pll_limits
.mclk
= 67;
496 par
->pll_limits
.xclk
= 67;
497 par
->pll_limits
.ecp_max
= 80;
498 par
->features
= ATI_CHIP_264VT3
;
502 case PCI_CHIP_MACH64GT
:
503 switch (rev
& 0x07) {
505 name
= "3D RAGE II (Mach64 GT)";
506 par
->pll_limits
.pll_max
= 170;
507 par
->pll_limits
.mclk
= 67;
508 par
->pll_limits
.xclk
= 67;
509 par
->pll_limits
.ecp_max
= 80;
510 par
->features
= ATI_CHIP_264GTB
;
513 name
= "3D RAGE II+ (Mach64 GT)";
514 par
->pll_limits
.pll_max
= 200;
515 par
->pll_limits
.mclk
= 67;
516 par
->pll_limits
.xclk
= 67;
517 par
->pll_limits
.ecp_max
= 100;
518 par
->features
= ATI_CHIP_264GTB
;
525 PRINTKI("%s [0x%04x rev 0x%02x]\n", name
, type
, rev
);
529 static char ram_dram
[] __devinitdata
= "DRAM";
530 static char ram_resv
[] __devinitdata
= "RESV";
531 #ifdef CONFIG_FB_ATY_GX
532 static char ram_vram
[] __devinitdata
= "VRAM";
533 #endif /* CONFIG_FB_ATY_GX */
534 #ifdef CONFIG_FB_ATY_CT
535 static char ram_edo
[] __devinitdata
= "EDO";
536 static char ram_sdram
[] __devinitdata
= "SDRAM (1:1)";
537 static char ram_sgram
[] __devinitdata
= "SGRAM (1:1)";
538 static char ram_sdram32
[] __devinitdata
= "SDRAM (2:1) (32-bit)";
539 static char ram_off
[] __devinitdata
= "OFF";
540 #endif /* CONFIG_FB_ATY_CT */
543 static u32 pseudo_palette
[17];
545 #ifdef CONFIG_FB_ATY_GX
546 static char *aty_gx_ram
[8] __devinitdata
= {
547 ram_dram
, ram_vram
, ram_vram
, ram_dram
,
548 ram_dram
, ram_vram
, ram_vram
, ram_resv
550 #endif /* CONFIG_FB_ATY_GX */
552 #ifdef CONFIG_FB_ATY_CT
553 static char *aty_ct_ram
[8] __devinitdata
= {
554 ram_off
, ram_dram
, ram_edo
, ram_edo
,
555 ram_sdram
, ram_sgram
, ram_sdram32
, ram_resv
557 #endif /* CONFIG_FB_ATY_CT */
559 static u32
atyfb_get_pixclock(struct fb_var_screeninfo
*var
, struct atyfb_par
*par
)
561 u32 pixclock
= var
->pixclock
;
562 #ifdef CONFIG_FB_ATY_GENERIC_LCD
564 par
->pll
.ct
.xres
= 0;
565 if (par
->lcd_table
!= 0) {
566 lcd_on_off
= aty_ld_lcd(LCD_GEN_CNTL
, par
);
567 if(lcd_on_off
& LCD_ON
) {
568 par
->pll
.ct
.xres
= var
->xres
;
569 pixclock
= par
->lcd_pixclock
;
576 #if defined(CONFIG_PPC)
579 * Apple monitor sense
582 static int __devinit
read_aty_sense(const struct atyfb_par
*par
)
586 aty_st_le32(GP_IO
, 0x31003100, par
); /* drive outputs high */
588 aty_st_le32(GP_IO
, 0, par
); /* turn off outputs */
590 i
= aty_ld_le32(GP_IO
, par
); /* get primary sense value */
591 sense
= ((i
& 0x3000) >> 3) | (i
& 0x100);
593 /* drive each sense line low in turn and collect the other 2 */
594 aty_st_le32(GP_IO
, 0x20000000, par
); /* drive A low */
596 i
= aty_ld_le32(GP_IO
, par
);
597 sense
|= ((i
& 0x1000) >> 7) | ((i
& 0x100) >> 4);
598 aty_st_le32(GP_IO
, 0x20002000, par
); /* drive A high again */
601 aty_st_le32(GP_IO
, 0x10000000, par
); /* drive B low */
603 i
= aty_ld_le32(GP_IO
, par
);
604 sense
|= ((i
& 0x2000) >> 10) | ((i
& 0x100) >> 6);
605 aty_st_le32(GP_IO
, 0x10001000, par
); /* drive B high again */
608 aty_st_le32(GP_IO
, 0x01000000, par
); /* drive C low */
610 sense
|= (aty_ld_le32(GP_IO
, par
) & 0x3000) >> 12;
611 aty_st_le32(GP_IO
, 0, par
); /* turn off outputs */
615 #endif /* defined(CONFIG_PPC) */
617 /* ------------------------------------------------------------------------- */
623 static void aty_get_crtc(const struct atyfb_par
*par
, struct crtc
*crtc
)
625 #ifdef CONFIG_FB_ATY_GENERIC_LCD
626 if (par
->lcd_table
!= 0) {
627 if(!M64_HAS(LT_LCD_REGS
)) {
628 crtc
->lcd_index
= aty_ld_le32(LCD_INDEX
, par
);
629 aty_st_le32(LCD_INDEX
, crtc
->lcd_index
, par
);
631 crtc
->lcd_config_panel
= aty_ld_lcd(CONFIG_PANEL
, par
);
632 crtc
->lcd_gen_cntl
= aty_ld_lcd(LCD_GEN_CNTL
, par
);
635 /* switch to non shadow registers */
636 aty_st_lcd(LCD_GEN_CNTL
, crtc
->lcd_gen_cntl
&
637 ~(CRTC_RW_SELECT
| SHADOW_EN
| SHADOW_RW_EN
), par
);
639 /* save stretching */
640 crtc
->horz_stretching
= aty_ld_lcd(HORZ_STRETCHING
, par
);
641 crtc
->vert_stretching
= aty_ld_lcd(VERT_STRETCHING
, par
);
642 if (!M64_HAS(LT_LCD_REGS
))
643 crtc
->ext_vert_stretch
= aty_ld_lcd(EXT_VERT_STRETCH
, par
);
646 crtc
->h_tot_disp
= aty_ld_le32(CRTC_H_TOTAL_DISP
, par
);
647 crtc
->h_sync_strt_wid
= aty_ld_le32(CRTC_H_SYNC_STRT_WID
, par
);
648 crtc
->v_tot_disp
= aty_ld_le32(CRTC_V_TOTAL_DISP
, par
);
649 crtc
->v_sync_strt_wid
= aty_ld_le32(CRTC_V_SYNC_STRT_WID
, par
);
650 crtc
->vline_crnt_vline
= aty_ld_le32(CRTC_VLINE_CRNT_VLINE
, par
);
651 crtc
->off_pitch
= aty_ld_le32(CRTC_OFF_PITCH
, par
);
652 crtc
->gen_cntl
= aty_ld_le32(CRTC_GEN_CNTL
, par
);
654 #ifdef CONFIG_FB_ATY_GENERIC_LCD
655 if (par
->lcd_table
!= 0) {
656 /* switch to shadow registers */
657 aty_st_lcd(LCD_GEN_CNTL
, (crtc
->lcd_gen_cntl
& ~CRTC_RW_SELECT
) |
658 SHADOW_EN
| SHADOW_RW_EN
, par
);
660 crtc
->shadow_h_tot_disp
= aty_ld_le32(CRTC_H_TOTAL_DISP
, par
);
661 crtc
->shadow_h_sync_strt_wid
= aty_ld_le32(CRTC_H_SYNC_STRT_WID
, par
);
662 crtc
->shadow_v_tot_disp
= aty_ld_le32(CRTC_V_TOTAL_DISP
, par
);
663 crtc
->shadow_v_sync_strt_wid
= aty_ld_le32(CRTC_V_SYNC_STRT_WID
, par
);
665 aty_st_le32(LCD_GEN_CNTL
, crtc
->lcd_gen_cntl
, par
);
667 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
670 static void aty_set_crtc(const struct atyfb_par
*par
, const struct crtc
*crtc
)
672 #ifdef CONFIG_FB_ATY_GENERIC_LCD
673 if (par
->lcd_table
!= 0) {
675 aty_st_le32(CRTC_GEN_CNTL
, crtc
->gen_cntl
& ~(CRTC_EXT_DISP_EN
| CRTC_EN
), par
);
677 /* update non-shadow registers first */
678 aty_st_lcd(CONFIG_PANEL
, crtc
->lcd_config_panel
, par
);
679 aty_st_lcd(LCD_GEN_CNTL
, crtc
->lcd_gen_cntl
&
680 ~(CRTC_RW_SELECT
| SHADOW_EN
| SHADOW_RW_EN
), par
);
682 /* temporarily disable stretching */
683 aty_st_lcd(HORZ_STRETCHING
,
684 crtc
->horz_stretching
&
685 ~(HORZ_STRETCH_MODE
| HORZ_STRETCH_EN
), par
);
686 aty_st_lcd(VERT_STRETCHING
,
687 crtc
->vert_stretching
&
688 ~(VERT_STRETCH_RATIO1
| VERT_STRETCH_RATIO2
|
689 VERT_STRETCH_USE0
| VERT_STRETCH_EN
), par
);
693 aty_st_le32(CRTC_GEN_CNTL
, crtc
->gen_cntl
& ~CRTC_EN
, par
);
695 DPRINTK("setting up CRTC\n");
696 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
697 ((((crtc
->h_tot_disp
>>16) & 0xff) + 1)<<3), (((crtc
->v_tot_disp
>>16) & 0x7ff) + 1),
698 (crtc
->h_sync_strt_wid
& 0x200000)?'N':'P', (crtc
->v_sync_strt_wid
& 0x200000)?'N':'P',
699 (crtc
->gen_cntl
& CRTC_CSYNC_EN
)?'P':'N');
701 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc
->h_tot_disp
);
702 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc
->h_sync_strt_wid
);
703 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc
->v_tot_disp
);
704 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc
->v_sync_strt_wid
);
705 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc
->off_pitch
);
706 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc
->vline_crnt_vline
);
707 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc
->gen_cntl
);
709 aty_st_le32(CRTC_H_TOTAL_DISP
, crtc
->h_tot_disp
, par
);
710 aty_st_le32(CRTC_H_SYNC_STRT_WID
, crtc
->h_sync_strt_wid
, par
);
711 aty_st_le32(CRTC_V_TOTAL_DISP
, crtc
->v_tot_disp
, par
);
712 aty_st_le32(CRTC_V_SYNC_STRT_WID
, crtc
->v_sync_strt_wid
, par
);
713 aty_st_le32(CRTC_OFF_PITCH
, crtc
->off_pitch
, par
);
714 aty_st_le32(CRTC_VLINE_CRNT_VLINE
, crtc
->vline_crnt_vline
, par
);
716 aty_st_le32(CRTC_GEN_CNTL
, crtc
->gen_cntl
, par
);
719 if (par
->accel_flags
& FB_ACCELF_TEXT
)
720 aty_init_engine(par
, info
);
722 #ifdef CONFIG_FB_ATY_GENERIC_LCD
723 /* after setting the CRTC registers we should set the LCD registers. */
724 if (par
->lcd_table
!= 0) {
725 /* switch to shadow registers */
726 aty_st_lcd(LCD_GEN_CNTL
, (crtc
->lcd_gen_cntl
& ~CRTC_RW_SELECT
) |
727 (SHADOW_EN
| SHADOW_RW_EN
), par
);
729 DPRINTK("set shadow CRT to %ix%i %c%c\n",
730 ((((crtc
->shadow_h_tot_disp
>>16) & 0xff) + 1)<<3), (((crtc
->shadow_v_tot_disp
>>16) & 0x7ff) + 1),
731 (crtc
->shadow_h_sync_strt_wid
& 0x200000)?'N':'P', (crtc
->shadow_v_sync_strt_wid
& 0x200000)?'N':'P');
733 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc
->shadow_h_tot_disp
);
734 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc
->shadow_h_sync_strt_wid
);
735 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc
->shadow_v_tot_disp
);
736 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc
->shadow_v_sync_strt_wid
);
738 aty_st_le32(CRTC_H_TOTAL_DISP
, crtc
->shadow_h_tot_disp
, par
);
739 aty_st_le32(CRTC_H_SYNC_STRT_WID
, crtc
->shadow_h_sync_strt_wid
, par
);
740 aty_st_le32(CRTC_V_TOTAL_DISP
, crtc
->shadow_v_tot_disp
, par
);
741 aty_st_le32(CRTC_V_SYNC_STRT_WID
, crtc
->shadow_v_sync_strt_wid
, par
);
743 /* restore CRTC selection & shadow state and enable stretching */
744 DPRINTK("LCD_GEN_CNTL: %x\n", crtc
->lcd_gen_cntl
);
745 DPRINTK("HORZ_STRETCHING: %x\n", crtc
->horz_stretching
);
746 DPRINTK("VERT_STRETCHING: %x\n", crtc
->vert_stretching
);
747 if(!M64_HAS(LT_LCD_REGS
))
748 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc
->ext_vert_stretch
);
750 aty_st_lcd(LCD_GEN_CNTL
, crtc
->lcd_gen_cntl
, par
);
751 aty_st_lcd(HORZ_STRETCHING
, crtc
->horz_stretching
, par
);
752 aty_st_lcd(VERT_STRETCHING
, crtc
->vert_stretching
, par
);
753 if(!M64_HAS(LT_LCD_REGS
)) {
754 aty_st_lcd(EXT_VERT_STRETCH
, crtc
->ext_vert_stretch
, par
);
755 aty_ld_le32(LCD_INDEX
, par
);
756 aty_st_le32(LCD_INDEX
, crtc
->lcd_index
, par
);
759 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
762 static int aty_var_to_crtc(const struct fb_info
*info
,
763 const struct fb_var_screeninfo
*var
, struct crtc
*crtc
)
765 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
766 u32 xres
, yres
, vxres
, vyres
, xoffset
, yoffset
, bpp
;
767 u32 sync
, vmode
, vdisplay
;
768 u32 h_total
, h_disp
, h_sync_strt
, h_sync_end
, h_sync_dly
, h_sync_wid
, h_sync_pol
;
769 u32 v_total
, v_disp
, v_sync_strt
, v_sync_end
, v_sync_wid
, v_sync_pol
, c_sync
;
770 u32 pix_width
, dp_pix_width
, dp_chain_mask
;
775 vxres
= var
->xres_virtual
;
776 vyres
= var
->yres_virtual
;
777 xoffset
= var
->xoffset
;
778 yoffset
= var
->yoffset
;
779 bpp
= var
->bits_per_pixel
;
781 bpp
= (var
->green
.length
== 5) ? 15 : 16;
785 /* convert (and round up) and validate */
786 if (vxres
< xres
+ xoffset
)
787 vxres
= xres
+ xoffset
;
790 if (vyres
< yres
+ yoffset
)
791 vyres
= yres
+ yoffset
;
796 pix_width
= CRTC_PIX_WIDTH_8BPP
;
798 HOST_8BPP
| SRC_8BPP
| DST_8BPP
|
799 BYTE_ORDER_LSB_TO_MSB
;
800 dp_chain_mask
= DP_CHAIN_8BPP
;
801 } else if (bpp
<= 15) {
803 pix_width
= CRTC_PIX_WIDTH_15BPP
;
804 dp_pix_width
= HOST_15BPP
| SRC_15BPP
| DST_15BPP
|
805 BYTE_ORDER_LSB_TO_MSB
;
806 dp_chain_mask
= DP_CHAIN_15BPP
;
807 } else if (bpp
<= 16) {
809 pix_width
= CRTC_PIX_WIDTH_16BPP
;
810 dp_pix_width
= HOST_16BPP
| SRC_16BPP
| DST_16BPP
|
811 BYTE_ORDER_LSB_TO_MSB
;
812 dp_chain_mask
= DP_CHAIN_16BPP
;
813 } else if (bpp
<= 24 && M64_HAS(INTEGRATED
)) {
815 pix_width
= CRTC_PIX_WIDTH_24BPP
;
817 HOST_8BPP
| SRC_8BPP
| DST_8BPP
|
818 BYTE_ORDER_LSB_TO_MSB
;
819 dp_chain_mask
= DP_CHAIN_24BPP
;
820 } else if (bpp
<= 32) {
822 pix_width
= CRTC_PIX_WIDTH_32BPP
;
823 dp_pix_width
= HOST_32BPP
| SRC_32BPP
| DST_32BPP
|
824 BYTE_ORDER_LSB_TO_MSB
;
825 dp_chain_mask
= DP_CHAIN_32BPP
;
829 if (vxres
* vyres
* bpp
/ 8 > info
->fix
.smem_len
)
830 FAIL("not enough video RAM");
832 h_sync_pol
= sync
& FB_SYNC_HOR_HIGH_ACT
? 0 : 1;
833 v_sync_pol
= sync
& FB_SYNC_VERT_HIGH_ACT
? 0 : 1;
835 if((xres
> 1600) || (yres
> 1200)) {
836 FAIL("MACH64 chips are designed for max 1600x1200\n"
837 "select anoter resolution.");
839 h_sync_strt
= h_disp
+ var
->right_margin
;
840 h_sync_end
= h_sync_strt
+ var
->hsync_len
;
841 h_sync_dly
= var
->right_margin
& 7;
842 h_total
= h_sync_end
+ h_sync_dly
+ var
->left_margin
;
844 v_sync_strt
= v_disp
+ var
->lower_margin
;
845 v_sync_end
= v_sync_strt
+ var
->vsync_len
;
846 v_total
= v_sync_end
+ var
->upper_margin
;
848 #ifdef CONFIG_FB_ATY_GENERIC_LCD
849 if (par
->lcd_table
!= 0) {
850 if(!M64_HAS(LT_LCD_REGS
)) {
851 u32 lcd_index
= aty_ld_le32(LCD_INDEX
, par
);
852 crtc
->lcd_index
= lcd_index
&
853 ~(LCD_INDEX_MASK
| LCD_DISPLAY_DIS
| LCD_SRC_SEL
| CRTC2_DISPLAY_DIS
);
854 aty_st_le32(LCD_INDEX
, lcd_index
, par
);
857 if (!M64_HAS(MOBIL_BUS
))
858 crtc
->lcd_index
|= CRTC2_DISPLAY_DIS
;
860 crtc
->lcd_config_panel
= aty_ld_lcd(CONFIG_PANEL
, par
) | 0x4000;
861 crtc
->lcd_gen_cntl
= aty_ld_lcd(LCD_GEN_CNTL
, par
) & ~CRTC_RW_SELECT
;
863 crtc
->lcd_gen_cntl
&=
864 ~(HORZ_DIVBY2_EN
| DIS_HOR_CRT_DIVBY2
| TVCLK_PM_EN
|
865 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
866 USE_SHADOWED_ROWCUR
| SHADOW_EN
| SHADOW_RW_EN
);
867 crtc
->lcd_gen_cntl
|= DONT_SHADOW_VPAR
| LOCK_8DOT
;
869 if((crtc
->lcd_gen_cntl
& LCD_ON
) &&
870 ((xres
> par
->lcd_width
) || (yres
> par
->lcd_height
))) {
871 /* We cannot display the mode on the LCD. If the CRT is enabled
872 we can turn off the LCD.
873 If the CRT is off, it isn't a good idea to switch it on; we don't
874 know if one is connected. So it's better to fail then.
876 if (crtc
->lcd_gen_cntl
& CRT_ON
) {
877 if (!(var
->activate
& FB_ACTIVATE_TEST
))
878 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
879 crtc
->lcd_gen_cntl
&= ~LCD_ON
;
880 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
882 if (!(var
->activate
& FB_ACTIVATE_TEST
))
883 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
889 if ((par
->lcd_table
!= 0) && (crtc
->lcd_gen_cntl
& LCD_ON
)) {
891 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
892 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
893 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
895 vmode
&= ~(FB_VMODE_DOUBLE
| FB_VMODE_INTERLACED
);
897 /* This is horror! When we simulate, say 640x480 on an 800x600
898 LCD monitor, the CRTC should be programmed 800x600 values for
899 the non visible part, but 640x480 for the visible part.
900 This code has been tested on a laptop with it's 1400x1050 LCD
901 monitor and a conventional monitor both switched on.
902 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
903 works with little glitches also with DOUBLESCAN modes
905 if (yres
< par
->lcd_height
) {
906 VScan
= par
->lcd_height
/ yres
;
909 vmode
|= FB_VMODE_DOUBLE
;
913 h_sync_strt
= h_disp
+ par
->lcd_right_margin
;
914 h_sync_end
= h_sync_strt
+ par
->lcd_hsync_len
;
915 h_sync_dly
= /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par
->lcd_hsync_dly
;
916 h_total
= h_disp
+ par
->lcd_hblank_len
;
918 v_sync_strt
= v_disp
+ par
->lcd_lower_margin
/ VScan
;
919 v_sync_end
= v_sync_strt
+ par
->lcd_vsync_len
/ VScan
;
920 v_total
= v_disp
+ par
->lcd_vblank_len
/ VScan
;
922 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
924 h_disp
= (h_disp
>> 3) - 1;
925 h_sync_strt
= (h_sync_strt
>> 3) - 1;
926 h_sync_end
= (h_sync_end
>> 3) - 1;
927 h_total
= (h_total
>> 3) - 1;
928 h_sync_wid
= h_sync_end
- h_sync_strt
;
930 FAIL_MAX("h_disp too large", h_disp
, 0xff);
931 FAIL_MAX("h_sync_strt too large", h_sync_strt
, 0x1ff);
932 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
933 if(h_sync_wid
> 0x1f)
935 FAIL_MAX("h_total too large", h_total
, 0x1ff);
937 if (vmode
& FB_VMODE_DOUBLE
) {
945 #ifdef CONFIG_FB_ATY_GENERIC_LCD
946 if ((par
->lcd_table
!= 0) && (crtc
->lcd_gen_cntl
& LCD_ON
))
947 vdisplay
= par
->lcd_height
;
954 v_sync_wid
= v_sync_end
- v_sync_strt
;
956 FAIL_MAX("v_disp too large", v_disp
, 0x7ff);
957 FAIL_MAX("v_sync_stsrt too large", v_sync_strt
, 0x7ff);
958 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
959 if(v_sync_wid
> 0x1f)
961 FAIL_MAX("v_total too large", v_total
, 0x7ff);
963 c_sync
= sync
& FB_SYNC_COMP_HIGH_ACT
? CRTC_CSYNC_EN
: 0;
968 crtc
->xoffset
= xoffset
;
969 crtc
->yoffset
= yoffset
;
971 crtc
->off_pitch
= ((yoffset
*vxres
+xoffset
)*bpp
/64) | (vxres
<<19);
972 crtc
->vline_crnt_vline
= 0;
974 crtc
->h_tot_disp
= h_total
| (h_disp
<<16);
975 crtc
->h_sync_strt_wid
= (h_sync_strt
& 0xff) | (h_sync_dly
<<8) |
976 ((h_sync_strt
& 0x100)<<4) | (h_sync_wid
<<16) | (h_sync_pol
<<21);
977 crtc
->v_tot_disp
= v_total
| (v_disp
<<16);
978 crtc
->v_sync_strt_wid
= v_sync_strt
| (v_sync_wid
<<16) | (v_sync_pol
<<21);
980 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
981 crtc
->gen_cntl
= CRTC_EXT_DISP_EN
| CRTC_EN
| pix_width
| c_sync
;
982 crtc
->gen_cntl
|= CRTC_VGA_LINEAR
;
984 /* Enable doublescan mode if requested */
985 if (vmode
& FB_VMODE_DOUBLE
)
986 crtc
->gen_cntl
|= CRTC_DBL_SCAN_EN
;
987 /* Enable interlaced mode if requested */
988 if (vmode
& FB_VMODE_INTERLACED
)
989 crtc
->gen_cntl
|= CRTC_INTERLACE_EN
;
990 #ifdef CONFIG_FB_ATY_GENERIC_LCD
991 if (par
->lcd_table
!= 0) {
993 if(vmode
& FB_VMODE_DOUBLE
)
995 crtc
->gen_cntl
&= ~(CRTC2_EN
| CRTC2_PIX_WIDTH
);
996 crtc
->lcd_gen_cntl
&= ~(HORZ_DIVBY2_EN
| DIS_HOR_CRT_DIVBY2
|
997 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
998 USE_SHADOWED_VEND
| USE_SHADOWED_ROWCUR
| SHADOW_EN
| SHADOW_RW_EN
);
999 crtc
->lcd_gen_cntl
|= (DONT_SHADOW_VPAR
/* | LOCK_8DOT*/);
1001 /* MOBILITY M1 tested, FIXME: LT */
1002 crtc
->horz_stretching
= aty_ld_lcd(HORZ_STRETCHING
, par
);
1003 if (!M64_HAS(LT_LCD_REGS
))
1004 crtc
->ext_vert_stretch
= aty_ld_lcd(EXT_VERT_STRETCH
, par
) &
1005 ~(AUTO_VERT_RATIO
| VERT_STRETCH_MODE
| VERT_STRETCH_RATIO3
);
1007 crtc
->horz_stretching
&=
1008 ~(HORZ_STRETCH_RATIO
| HORZ_STRETCH_LOOP
| AUTO_HORZ_RATIO
|
1009 HORZ_STRETCH_MODE
| HORZ_STRETCH_EN
);
1010 if (xres
< par
->lcd_width
&& crtc
->lcd_gen_cntl
& LCD_ON
) {
1013 * The horizontal blender misbehaves when HDisplay is less than a
1014 * a certain threshold (440 for a 1024-wide panel). It doesn't
1015 * stretch such modes enough. Use pixel replication instead of
1016 * blending to stretch modes that can be made to exactly fit the
1017 * panel width. The undocumented "NoLCDBlend" option allows the
1018 * pixel-replicated mode to be slightly wider or narrower than the
1019 * panel width. It also causes a mode that is exactly half as wide
1020 * as the panel to be pixel-replicated, rather than blended.
1022 int HDisplay
= xres
& ~7;
1023 int nStretch
= par
->lcd_width
/ HDisplay
;
1024 int Remainder
= par
->lcd_width
% HDisplay
;
1026 if ((!Remainder
&& ((nStretch
> 2))) ||
1027 (((HDisplay
* 16) / par
->lcd_width
) < 7)) {
1028 static const char StretchLoops
[] = {10, 12, 13, 15, 16};
1029 int horz_stretch_loop
= -1, BestRemainder
;
1030 int Numerator
= HDisplay
, Denominator
= par
->lcd_width
;
1032 ATIReduceRatio(&Numerator
, &Denominator
);
1034 BestRemainder
= (Numerator
* 16) / Denominator
;
1035 while (--Index
>= 0) {
1036 Remainder
= ((Denominator
- Numerator
) * StretchLoops
[Index
]) %
1038 if (Remainder
< BestRemainder
) {
1039 horz_stretch_loop
= Index
;
1040 if (!(BestRemainder
= Remainder
))
1045 if ((horz_stretch_loop
>= 0) && !BestRemainder
) {
1046 int horz_stretch_ratio
= 0, Accumulator
= 0;
1047 int reuse_previous
= 1;
1049 Index
= StretchLoops
[horz_stretch_loop
];
1051 while (--Index
>= 0) {
1052 if (Accumulator
> 0)
1053 horz_stretch_ratio
|= reuse_previous
;
1055 Accumulator
+= Denominator
;
1056 Accumulator
-= Numerator
;
1057 reuse_previous
<<= 1;
1060 crtc
->horz_stretching
|= (HORZ_STRETCH_EN
|
1061 ((horz_stretch_loop
& HORZ_STRETCH_LOOP
) << 16) |
1062 (horz_stretch_ratio
& HORZ_STRETCH_RATIO
));
1063 break; /* Out of the do { ... } while (0) */
1067 crtc
->horz_stretching
|= (HORZ_STRETCH_MODE
| HORZ_STRETCH_EN
|
1068 (((HDisplay
* (HORZ_STRETCH_BLEND
+ 1)) / par
->lcd_width
) & HORZ_STRETCH_BLEND
));
1072 if (vdisplay
< par
->lcd_height
&& crtc
->lcd_gen_cntl
& LCD_ON
) {
1073 crtc
->vert_stretching
= (VERT_STRETCH_USE0
| VERT_STRETCH_EN
|
1074 (((vdisplay
* (VERT_STRETCH_RATIO0
+ 1)) / par
->lcd_height
) & VERT_STRETCH_RATIO0
));
1076 if (!M64_HAS(LT_LCD_REGS
) &&
1077 xres
<= (M64_HAS(MOBIL_BUS
)?1024:800))
1078 crtc
->ext_vert_stretch
|= VERT_STRETCH_MODE
;
1081 * Don't use vertical blending if the mode is too wide or not
1082 * vertically stretched.
1084 crtc
->vert_stretching
= 0;
1086 /* copy to shadow crtc */
1087 crtc
->shadow_h_tot_disp
= crtc
->h_tot_disp
;
1088 crtc
->shadow_h_sync_strt_wid
= crtc
->h_sync_strt_wid
;
1089 crtc
->shadow_v_tot_disp
= crtc
->v_tot_disp
;
1090 crtc
->shadow_v_sync_strt_wid
= crtc
->v_sync_strt_wid
;
1092 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1094 if (M64_HAS(MAGIC_FIFO
)) {
1095 /* FIXME: display FIFO low watermark values */
1096 crtc
->gen_cntl
|= (aty_ld_le32(CRTC_GEN_CNTL
, par
) & CRTC_FIFO_LWM
);
1098 crtc
->dp_pix_width
= dp_pix_width
;
1099 crtc
->dp_chain_mask
= dp_chain_mask
;
1104 static int aty_crtc_to_var(const struct crtc
*crtc
, struct fb_var_screeninfo
*var
)
1106 u32 xres
, yres
, bpp
, left
, right
, upper
, lower
, hslen
, vslen
, sync
;
1107 u32 h_total
, h_disp
, h_sync_strt
, h_sync_dly
, h_sync_wid
,
1109 u32 v_total
, v_disp
, v_sync_strt
, v_sync_wid
, v_sync_pol
, c_sync
;
1111 u32 double_scan
, interlace
;
1114 h_total
= crtc
->h_tot_disp
& 0x1ff;
1115 h_disp
= (crtc
->h_tot_disp
>> 16) & 0xff;
1116 h_sync_strt
= (crtc
->h_sync_strt_wid
& 0xff) | ((crtc
->h_sync_strt_wid
>> 4) & 0x100);
1117 h_sync_dly
= (crtc
->h_sync_strt_wid
>> 8) & 0x7;
1118 h_sync_wid
= (crtc
->h_sync_strt_wid
>> 16) & 0x1f;
1119 h_sync_pol
= (crtc
->h_sync_strt_wid
>> 21) & 0x1;
1120 v_total
= crtc
->v_tot_disp
& 0x7ff;
1121 v_disp
= (crtc
->v_tot_disp
>> 16) & 0x7ff;
1122 v_sync_strt
= crtc
->v_sync_strt_wid
& 0x7ff;
1123 v_sync_wid
= (crtc
->v_sync_strt_wid
>> 16) & 0x1f;
1124 v_sync_pol
= (crtc
->v_sync_strt_wid
>> 21) & 0x1;
1125 c_sync
= crtc
->gen_cntl
& CRTC_CSYNC_EN
? 1 : 0;
1126 pix_width
= crtc
->gen_cntl
& CRTC_PIX_WIDTH_MASK
;
1127 double_scan
= crtc
->gen_cntl
& CRTC_DBL_SCAN_EN
;
1128 interlace
= crtc
->gen_cntl
& CRTC_INTERLACE_EN
;
1131 xres
= (h_disp
+ 1) * 8;
1133 left
= (h_total
- h_sync_strt
- h_sync_wid
) * 8 - h_sync_dly
;
1134 right
= (h_sync_strt
- h_disp
) * 8 + h_sync_dly
;
1135 hslen
= h_sync_wid
* 8;
1136 upper
= v_total
- v_sync_strt
- v_sync_wid
;
1137 lower
= v_sync_strt
- v_disp
;
1139 sync
= (h_sync_pol
? 0 : FB_SYNC_HOR_HIGH_ACT
) |
1140 (v_sync_pol
? 0 : FB_SYNC_VERT_HIGH_ACT
) |
1141 (c_sync
? FB_SYNC_COMP_HIGH_ACT
: 0);
1143 switch (pix_width
) {
1145 case CRTC_PIX_WIDTH_4BPP
:
1147 var
->red
.offset
= 0;
1148 var
->red
.length
= 8;
1149 var
->green
.offset
= 0;
1150 var
->green
.length
= 8;
1151 var
->blue
.offset
= 0;
1152 var
->blue
.length
= 8;
1153 var
->transp
.offset
= 0;
1154 var
->transp
.length
= 0;
1157 case CRTC_PIX_WIDTH_8BPP
:
1159 var
->red
.offset
= 0;
1160 var
->red
.length
= 8;
1161 var
->green
.offset
= 0;
1162 var
->green
.length
= 8;
1163 var
->blue
.offset
= 0;
1164 var
->blue
.length
= 8;
1165 var
->transp
.offset
= 0;
1166 var
->transp
.length
= 0;
1168 case CRTC_PIX_WIDTH_15BPP
: /* RGB 555 */
1170 var
->red
.offset
= 10;
1171 var
->red
.length
= 5;
1172 var
->green
.offset
= 5;
1173 var
->green
.length
= 5;
1174 var
->blue
.offset
= 0;
1175 var
->blue
.length
= 5;
1176 var
->transp
.offset
= 0;
1177 var
->transp
.length
= 0;
1179 case CRTC_PIX_WIDTH_16BPP
: /* RGB 565 */
1181 var
->red
.offset
= 11;
1182 var
->red
.length
= 5;
1183 var
->green
.offset
= 5;
1184 var
->green
.length
= 6;
1185 var
->blue
.offset
= 0;
1186 var
->blue
.length
= 5;
1187 var
->transp
.offset
= 0;
1188 var
->transp
.length
= 0;
1190 case CRTC_PIX_WIDTH_24BPP
: /* RGB 888 */
1192 var
->red
.offset
= 16;
1193 var
->red
.length
= 8;
1194 var
->green
.offset
= 8;
1195 var
->green
.length
= 8;
1196 var
->blue
.offset
= 0;
1197 var
->blue
.length
= 8;
1198 var
->transp
.offset
= 0;
1199 var
->transp
.length
= 0;
1201 case CRTC_PIX_WIDTH_32BPP
: /* ARGB 8888 */
1203 var
->red
.offset
= 16;
1204 var
->red
.length
= 8;
1205 var
->green
.offset
= 8;
1206 var
->green
.length
= 8;
1207 var
->blue
.offset
= 0;
1208 var
->blue
.length
= 8;
1209 var
->transp
.offset
= 24;
1210 var
->transp
.length
= 8;
1213 PRINTKE("Invalid pixel width\n");
1220 var
->xres_virtual
= crtc
->vxres
;
1221 var
->yres_virtual
= crtc
->vyres
;
1222 var
->bits_per_pixel
= bpp
;
1223 var
->left_margin
= left
;
1224 var
->right_margin
= right
;
1225 var
->upper_margin
= upper
;
1226 var
->lower_margin
= lower
;
1227 var
->hsync_len
= hslen
;
1228 var
->vsync_len
= vslen
;
1230 var
->vmode
= FB_VMODE_NONINTERLACED
;
1231 /* In double scan mode, the vertical parameters are doubled, so we need to
1232 half them to get the right values.
1233 In interlaced mode the values are already correct, so no correction is
1237 var
->vmode
= FB_VMODE_INTERLACED
;
1240 var
->vmode
= FB_VMODE_DOUBLE
;
1242 var
->upper_margin
>>=1;
1243 var
->lower_margin
>>=1;
1250 /* ------------------------------------------------------------------------- */
1252 static int atyfb_set_par(struct fb_info
*info
)
1254 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
1255 struct fb_var_screeninfo
*var
= &info
->var
;
1259 struct fb_var_screeninfo debug
;
1265 if ((err
= aty_var_to_crtc(info
, var
, &par
->crtc
)))
1268 pixclock
= atyfb_get_pixclock(var
, par
);
1270 if (pixclock
== 0) {
1271 PRINTKE("Invalid pixclock\n");
1274 if((err
= par
->pll_ops
->var_to_pll(info
, pixclock
, var
->bits_per_pixel
, &par
->pll
)))
1278 par
->accel_flags
= var
->accel_flags
; /* hack */
1280 if (var
->accel_flags
) {
1281 info
->fbops
->fb_sync
= atyfb_sync
;
1282 info
->flags
&= ~FBINFO_HWACCEL_DISABLED
;
1284 info
->fbops
->fb_sync
= NULL
;
1285 info
->flags
|= FBINFO_HWACCEL_DISABLED
;
1288 if (par
->blitter_may_be_busy
)
1291 aty_set_crtc(par
, &par
->crtc
);
1292 par
->dac_ops
->set_dac(info
, &par
->pll
, var
->bits_per_pixel
, par
->accel_flags
);
1293 par
->pll_ops
->set_pll(info
, &par
->pll
);
1296 if(par
->pll_ops
&& par
->pll_ops
->pll_to_var
)
1297 pixclock_in_ps
= par
->pll_ops
->pll_to_var(info
, &(par
->pll
));
1301 if(0 == pixclock_in_ps
) {
1302 PRINTKE("ALERT ops->pll_to_var get 0\n");
1303 pixclock_in_ps
= pixclock
;
1306 memset(&debug
, 0, sizeof(debug
));
1307 if(!aty_crtc_to_var(&(par
->crtc
), &debug
)) {
1308 u32 hSync
, vRefresh
;
1309 u32 h_disp
, h_sync_strt
, h_sync_end
, h_total
;
1310 u32 v_disp
, v_sync_strt
, v_sync_end
, v_total
;
1312 h_disp
= debug
.xres
;
1313 h_sync_strt
= h_disp
+ debug
.right_margin
;
1314 h_sync_end
= h_sync_strt
+ debug
.hsync_len
;
1315 h_total
= h_sync_end
+ debug
.left_margin
;
1316 v_disp
= debug
.yres
;
1317 v_sync_strt
= v_disp
+ debug
.lower_margin
;
1318 v_sync_end
= v_sync_strt
+ debug
.vsync_len
;
1319 v_total
= v_sync_end
+ debug
.upper_margin
;
1321 hSync
= 1000000000 / (pixclock_in_ps
* h_total
);
1322 vRefresh
= (hSync
* 1000) / v_total
;
1323 if (par
->crtc
.gen_cntl
& CRTC_INTERLACE_EN
)
1325 if (par
->crtc
.gen_cntl
& CRTC_DBL_SCAN_EN
)
1328 DPRINTK("atyfb_set_par\n");
1329 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var
->xres
, var
->yres
, var
->bits_per_pixel
);
1330 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1331 var
->xres_virtual
, var
->yres_virtual
, pixclock
, pixclock_in_ps
);
1332 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps
);
1333 DPRINTK(" Horizontal sync: %i kHz\n", hSync
);
1334 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh
);
1335 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1336 1000000 / pixclock_in_ps
, 1000000 % pixclock_in_ps
,
1337 h_disp
, h_sync_strt
, h_sync_end
, h_total
,
1338 v_disp
, v_sync_strt
, v_sync_end
, v_total
);
1339 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1341 debug
.left_margin
, h_disp
, debug
.right_margin
, debug
.hsync_len
,
1342 debug
.upper_margin
, v_disp
, debug
.lower_margin
, debug
.vsync_len
);
1346 if (!M64_HAS(INTEGRATED
)) {
1347 /* Don't forget MEM_CNTL */
1348 tmp
= aty_ld_le32(MEM_CNTL
, par
) & 0xf0ffffff;
1349 switch (var
->bits_per_pixel
) {
1360 aty_st_le32(MEM_CNTL
, tmp
, par
);
1362 tmp
= aty_ld_le32(MEM_CNTL
, par
) & 0xf00fffff;
1363 if (!M64_HAS(MAGIC_POSTDIV
))
1364 tmp
|= par
->mem_refresh_rate
<< 20;
1365 switch (var
->bits_per_pixel
) {
1377 if (M64_HAS(CT_BUS
)) {
1378 aty_st_le32(DAC_CNTL
, 0x87010184, par
);
1379 aty_st_le32(BUS_CNTL
, 0x680000f9, par
);
1380 } else if (M64_HAS(VT_BUS
)) {
1381 aty_st_le32(DAC_CNTL
, 0x87010184, par
);
1382 aty_st_le32(BUS_CNTL
, 0x680000f9, par
);
1383 } else if (M64_HAS(MOBIL_BUS
)) {
1384 aty_st_le32(DAC_CNTL
, 0x80010102, par
);
1385 aty_st_le32(BUS_CNTL
, 0x7b33a040 | (par
->aux_start
? BUS_APER_REG_DIS
: 0), par
);
1388 aty_st_le32(DAC_CNTL
, 0x86010102, par
);
1389 aty_st_le32(BUS_CNTL
, 0x7b23a040 | (par
->aux_start
? BUS_APER_REG_DIS
: 0), par
);
1390 aty_st_le32(EXT_MEM_CNTL
, aty_ld_le32(EXT_MEM_CNTL
, par
) | 0x5000001, par
);
1392 aty_st_le32(MEM_CNTL
, tmp
, par
);
1394 aty_st_8(DAC_MASK
, 0xff, par
);
1396 info
->fix
.line_length
= var
->xres_virtual
* var
->bits_per_pixel
/8;
1397 info
->fix
.visual
= var
->bits_per_pixel
<= 8 ?
1398 FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_DIRECTCOLOR
;
1400 /* Initialize the graphics engine */
1401 if (par
->accel_flags
& FB_ACCELF_TEXT
)
1402 aty_init_engine(par
, info
);
1404 #ifdef CONFIG_BOOTX_TEXT
1405 btext_update_display(info
->fix
.smem_start
,
1406 (((par
->crtc
.h_tot_disp
>> 16) & 0xff) + 1) * 8,
1407 ((par
->crtc
.v_tot_disp
>> 16) & 0x7ff) + 1,
1408 var
->bits_per_pixel
,
1409 par
->crtc
.vxres
* var
->bits_per_pixel
/ 8);
1410 #endif /* CONFIG_BOOTX_TEXT */
1412 /* switch to accelerator mode */
1413 if (!(par
->crtc
.gen_cntl
& CRTC_EXT_DISP_EN
))
1414 aty_st_le32(CRTC_GEN_CNTL
, par
->crtc
.gen_cntl
| CRTC_EXT_DISP_EN
, par
);
1418 /* dump non shadow CRTC, pll, LCD registers */
1421 /* CRTC registers */
1423 printk("debug atyfb: Mach64 non-shadow register values:");
1424 for (i
= 0; i
< 256; i
= i
+4) {
1425 if(i
%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base
+ i
);
1426 printk(" %08X", aty_ld_le32(i
, par
));
1430 #ifdef CONFIG_FB_ATY_CT
1433 printk("debug atyfb: Mach64 PLL register values:");
1434 for (i
= 0; i
< 64; i
++) {
1435 if(i
%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base
+ i
);
1436 if(i
%4 == 0) printk(" ");
1437 printk("%02X", aty_ld_pll_ct(i
, par
));
1440 #endif /* CONFIG_FB_ATY_CT */
1442 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1443 if (par
->lcd_table
!= 0) {
1446 printk("debug atyfb: LCD register values:");
1447 if(M64_HAS(LT_LCD_REGS
)) {
1448 for(i
= 0; i
<= POWER_MANAGEMENT
; i
++) {
1449 if(i
== EXT_VERT_STRETCH
)
1451 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs
[i
]);
1452 printk(" %08X", aty_ld_lcd(i
, par
));
1456 for (i
= 0; i
< 64; i
++) {
1457 if(i
%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base
+ i
);
1458 printk(" %08X", aty_ld_lcd(i
, par
));
1463 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1469 static int atyfb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
1471 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
1477 memcpy(&pll
, &(par
->pll
), sizeof(pll
));
1479 if((err
= aty_var_to_crtc(info
, var
, &crtc
)))
1482 pixclock
= atyfb_get_pixclock(var
, par
);
1484 if (pixclock
== 0) {
1485 if (!(var
->activate
& FB_ACTIVATE_TEST
))
1486 PRINTKE("Invalid pixclock\n");
1489 if((err
= par
->pll_ops
->var_to_pll(info
, pixclock
, var
->bits_per_pixel
, &pll
)))
1493 if (var
->accel_flags
& FB_ACCELF_TEXT
)
1494 info
->var
.accel_flags
= FB_ACCELF_TEXT
;
1496 info
->var
.accel_flags
= 0;
1498 aty_crtc_to_var(&crtc
, var
);
1499 var
->pixclock
= par
->pll_ops
->pll_to_var(info
, &pll
);
1503 static void set_off_pitch(struct atyfb_par
*par
, const struct fb_info
*info
)
1505 u32 xoffset
= info
->var
.xoffset
;
1506 u32 yoffset
= info
->var
.yoffset
;
1507 u32 vxres
= par
->crtc
.vxres
;
1508 u32 bpp
= info
->var
.bits_per_pixel
;
1510 par
->crtc
.off_pitch
= ((yoffset
* vxres
+ xoffset
) * bpp
/ 64) | (vxres
<< 19);
1515 * Open/Release the frame buffer device
1518 static int atyfb_open(struct fb_info
*info
, int user
)
1520 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
1531 static irqreturn_t
aty_irq(int irq
, void *dev_id
)
1533 struct atyfb_par
*par
= dev_id
;
1537 spin_lock(&par
->int_lock
);
1539 int_cntl
= aty_ld_le32(CRTC_INT_CNTL
, par
);
1541 if (int_cntl
& CRTC_VBLANK_INT
) {
1542 /* clear interrupt */
1543 aty_st_le32(CRTC_INT_CNTL
, (int_cntl
& CRTC_INT_EN_MASK
) | CRTC_VBLANK_INT_AK
, par
);
1544 par
->vblank
.count
++;
1545 if (par
->vblank
.pan_display
) {
1546 par
->vblank
.pan_display
= 0;
1547 aty_st_le32(CRTC_OFF_PITCH
, par
->crtc
.off_pitch
, par
);
1549 wake_up_interruptible(&par
->vblank
.wait
);
1553 spin_unlock(&par
->int_lock
);
1555 return IRQ_RETVAL(handled
);
1558 static int aty_enable_irq(struct atyfb_par
*par
, int reenable
)
1562 if (!test_and_set_bit(0, &par
->irq_flags
)) {
1563 if (request_irq(par
->irq
, aty_irq
, IRQF_SHARED
, "atyfb", par
)) {
1564 clear_bit(0, &par
->irq_flags
);
1567 spin_lock_irq(&par
->int_lock
);
1568 int_cntl
= aty_ld_le32(CRTC_INT_CNTL
, par
) & CRTC_INT_EN_MASK
;
1569 /* clear interrupt */
1570 aty_st_le32(CRTC_INT_CNTL
, int_cntl
| CRTC_VBLANK_INT_AK
, par
);
1571 /* enable interrupt */
1572 aty_st_le32(CRTC_INT_CNTL
, int_cntl
| CRTC_VBLANK_INT_EN
, par
);
1573 spin_unlock_irq(&par
->int_lock
);
1574 } else if (reenable
) {
1575 spin_lock_irq(&par
->int_lock
);
1576 int_cntl
= aty_ld_le32(CRTC_INT_CNTL
, par
) & CRTC_INT_EN_MASK
;
1577 if (!(int_cntl
& CRTC_VBLANK_INT_EN
)) {
1578 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl
);
1579 /* re-enable interrupt */
1580 aty_st_le32(CRTC_INT_CNTL
, int_cntl
| CRTC_VBLANK_INT_EN
, par
);
1582 spin_unlock_irq(&par
->int_lock
);
1588 static int aty_disable_irq(struct atyfb_par
*par
)
1592 if (test_and_clear_bit(0, &par
->irq_flags
)) {
1593 if (par
->vblank
.pan_display
) {
1594 par
->vblank
.pan_display
= 0;
1595 aty_st_le32(CRTC_OFF_PITCH
, par
->crtc
.off_pitch
, par
);
1597 spin_lock_irq(&par
->int_lock
);
1598 int_cntl
= aty_ld_le32(CRTC_INT_CNTL
, par
) & CRTC_INT_EN_MASK
;
1599 /* disable interrupt */
1600 aty_st_le32(CRTC_INT_CNTL
, int_cntl
& ~CRTC_VBLANK_INT_EN
, par
);
1601 spin_unlock_irq(&par
->int_lock
);
1602 free_irq(par
->irq
, par
);
1608 static int atyfb_release(struct fb_info
*info
, int user
)
1610 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
1617 int was_mmaped
= par
->mmaped
;
1622 struct fb_var_screeninfo var
;
1624 /* Now reset the default display config, we have no
1625 * idea what the program(s) which mmap'd the chip did
1626 * to the configuration, nor whether it restored it
1631 var
.accel_flags
&= ~FB_ACCELF_TEXT
;
1633 var
.accel_flags
|= FB_ACCELF_TEXT
;
1634 if (var
.yres
== var
.yres_virtual
) {
1635 u32 videoram
= (info
->fix
.smem_len
- (PAGE_SIZE
<< 2));
1636 var
.yres_virtual
= ((videoram
* 8) / var
.bits_per_pixel
) / var
.xres_virtual
;
1637 if (var
.yres_virtual
< var
.yres
)
1638 var
.yres_virtual
= var
.yres
;
1642 aty_disable_irq(par
);
1649 * Pan or Wrap the Display
1651 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1654 static int atyfb_pan_display(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
1656 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
1657 u32 xres
, yres
, xoffset
, yoffset
;
1659 xres
= (((par
->crtc
.h_tot_disp
>> 16) & 0xff) + 1) * 8;
1660 yres
= ((par
->crtc
.v_tot_disp
>> 16) & 0x7ff) + 1;
1661 if (par
->crtc
.gen_cntl
& CRTC_DBL_SCAN_EN
)
1663 xoffset
= (var
->xoffset
+ 7) & ~7;
1664 yoffset
= var
->yoffset
;
1665 if (xoffset
+ xres
> par
->crtc
.vxres
|| yoffset
+ yres
> par
->crtc
.vyres
)
1667 info
->var
.xoffset
= xoffset
;
1668 info
->var
.yoffset
= yoffset
;
1672 set_off_pitch(par
, info
);
1673 if ((var
->activate
& FB_ACTIVATE_VBL
) && !aty_enable_irq(par
, 0)) {
1674 par
->vblank
.pan_display
= 1;
1676 par
->vblank
.pan_display
= 0;
1677 aty_st_le32(CRTC_OFF_PITCH
, par
->crtc
.off_pitch
, par
);
1683 static int aty_waitforvblank(struct atyfb_par
*par
, u32 crtc
)
1685 struct aty_interrupt
*vbl
;
1697 ret
= aty_enable_irq(par
, 0);
1702 ret
= wait_event_interruptible_timeout(vbl
->wait
, count
!= vbl
->count
, HZ
/10);
1707 aty_enable_irq(par
, 1);
1716 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1717 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1723 u8 mclk_post_div
; /* 1,2,3,4,8 */
1724 u8 mclk_fb_mult
; /* 2 or 4 */
1725 u8 xclk_post_div
; /* 1,2,3,4,8 */
1727 u8 vclk_post_div
; /* 1,2,3,4,6,8,12 */
1728 u32 dsp_xclks_per_row
; /* 0-16383 */
1729 u32 dsp_loop_latency
; /* 0-15 */
1730 u32 dsp_precision
; /* 0-7 */
1731 u32 dsp_on
; /* 0-2047 */
1732 u32 dsp_off
; /* 0-2047 */
1735 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1736 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1739 #ifndef FBIO_WAITFORVSYNC
1740 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1743 static int atyfb_ioctl(struct fb_info
*info
, u_int cmd
, u_long arg
)
1745 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
1747 struct fbtype fbtyp
;
1753 fbtyp
.fb_type
= FBTYPE_PCI_GENERIC
;
1754 fbtyp
.fb_width
= par
->crtc
.vxres
;
1755 fbtyp
.fb_height
= par
->crtc
.vyres
;
1756 fbtyp
.fb_depth
= info
->var
.bits_per_pixel
;
1757 fbtyp
.fb_cmsize
= info
->cmap
.len
;
1758 fbtyp
.fb_size
= info
->fix
.smem_len
;
1759 if (copy_to_user((struct fbtype __user
*) arg
, &fbtyp
, sizeof(fbtyp
)))
1762 #endif /* __sparc__ */
1764 case FBIO_WAITFORVSYNC
:
1768 if (get_user(crtc
, (__u32 __user
*) arg
))
1771 return aty_waitforvblank(par
, crtc
);
1775 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1777 if (M64_HAS(INTEGRATED
)) {
1779 union aty_pll
*pll
= &(par
->pll
);
1780 u32 dsp_config
= pll
->ct
.dsp_config
;
1781 u32 dsp_on_off
= pll
->ct
.dsp_on_off
;
1782 clk
.ref_clk_per
= par
->ref_clk_per
;
1783 clk
.pll_ref_div
= pll
->ct
.pll_ref_div
;
1784 clk
.mclk_fb_div
= pll
->ct
.mclk_fb_div
;
1785 clk
.mclk_post_div
= pll
->ct
.mclk_post_div_real
;
1786 clk
.mclk_fb_mult
= pll
->ct
.mclk_fb_mult
;
1787 clk
.xclk_post_div
= pll
->ct
.xclk_post_div_real
;
1788 clk
.vclk_fb_div
= pll
->ct
.vclk_fb_div
;
1789 clk
.vclk_post_div
= pll
->ct
.vclk_post_div_real
;
1790 clk
.dsp_xclks_per_row
= dsp_config
& 0x3fff;
1791 clk
.dsp_loop_latency
= (dsp_config
>> 16) & 0xf;
1792 clk
.dsp_precision
= (dsp_config
>> 20) & 7;
1793 clk
.dsp_off
= dsp_on_off
& 0x7ff;
1794 clk
.dsp_on
= (dsp_on_off
>> 16) & 0x7ff;
1795 if (copy_to_user((struct atyclk __user
*) arg
, &clk
,
1802 if (M64_HAS(INTEGRATED
)) {
1804 union aty_pll
*pll
= &(par
->pll
);
1805 if (copy_from_user(&clk
, (struct atyclk __user
*) arg
, sizeof(clk
)))
1807 par
->ref_clk_per
= clk
.ref_clk_per
;
1808 pll
->ct
.pll_ref_div
= clk
.pll_ref_div
;
1809 pll
->ct
.mclk_fb_div
= clk
.mclk_fb_div
;
1810 pll
->ct
.mclk_post_div_real
= clk
.mclk_post_div
;
1811 pll
->ct
.mclk_fb_mult
= clk
.mclk_fb_mult
;
1812 pll
->ct
.xclk_post_div_real
= clk
.xclk_post_div
;
1813 pll
->ct
.vclk_fb_div
= clk
.vclk_fb_div
;
1814 pll
->ct
.vclk_post_div_real
= clk
.vclk_post_div
;
1815 pll
->ct
.dsp_config
= (clk
.dsp_xclks_per_row
& 0x3fff) |
1816 ((clk
.dsp_loop_latency
& 0xf)<<16)| ((clk
.dsp_precision
& 7)<<20);
1817 pll
->ct
.dsp_on_off
= (clk
.dsp_off
& 0x7ff) | ((clk
.dsp_on
& 0x7ff)<<16);
1818 /*aty_calc_pll_ct(info, &pll->ct);*/
1819 aty_set_pll_ct(info
, pll
);
1824 if (get_user(par
->features
, (u32 __user
*) arg
))
1828 if (put_user(par
->features
, (u32 __user
*) arg
))
1831 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1838 static int atyfb_sync(struct fb_info
*info
)
1840 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
1842 if (par
->blitter_may_be_busy
)
1848 static int atyfb_mmap(struct fb_info
*info
, struct vm_area_struct
*vma
)
1850 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
1851 unsigned int size
, page
, map_size
= 0;
1852 unsigned long map_offset
= 0;
1859 if (vma
->vm_pgoff
> (~0UL >> PAGE_SHIFT
))
1862 off
= vma
->vm_pgoff
<< PAGE_SHIFT
;
1863 size
= vma
->vm_end
- vma
->vm_start
;
1865 /* To stop the swapper from even considering these pages. */
1866 vma
->vm_flags
|= (VM_IO
| VM_RESERVED
);
1868 if (((vma
->vm_pgoff
== 0) && (size
== info
->fix
.smem_len
)) ||
1869 ((off
== info
->fix
.smem_len
) && (size
== PAGE_SIZE
)))
1870 off
+= 0x8000000000000000UL
;
1872 vma
->vm_pgoff
= off
>> PAGE_SHIFT
; /* propagate off changes */
1874 /* Each page, see which map applies */
1875 for (page
= 0; page
< size
;) {
1877 for (i
= 0; par
->mmap_map
[i
].size
; i
++) {
1878 unsigned long start
= par
->mmap_map
[i
].voff
;
1879 unsigned long end
= start
+ par
->mmap_map
[i
].size
;
1880 unsigned long offset
= off
+ page
;
1887 map_size
= par
->mmap_map
[i
].size
- (offset
- start
);
1889 par
->mmap_map
[i
].poff
+ (offset
- start
);
1896 if (page
+ map_size
> size
)
1897 map_size
= size
- page
;
1899 pgprot_val(vma
->vm_page_prot
) &=
1900 ~(par
->mmap_map
[i
].prot_mask
);
1901 pgprot_val(vma
->vm_page_prot
) |= par
->mmap_map
[i
].prot_flag
;
1903 if (remap_pfn_range(vma
, vma
->vm_start
+ page
,
1904 map_offset
>> PAGE_SHIFT
, map_size
, vma
->vm_page_prot
))
1925 static void atyfb_save_palette(struct atyfb_par
*par
, int enter
)
1929 for (i
= 0; i
< 256; i
++) {
1930 tmp
= aty_ld_8(DAC_CNTL
, par
) & 0xfc;
1931 if (M64_HAS(EXTRA_BRIGHT
))
1933 aty_st_8(DAC_CNTL
, tmp
, par
);
1934 aty_st_8(DAC_MASK
, 0xff, par
);
1936 aty_st_8(DAC_R_INDEX
, i
, par
);
1937 atyfb_save
.r
[enter
][i
] = aty_ld_8(DAC_DATA
, par
);
1938 atyfb_save
.g
[enter
][i
] = aty_ld_8(DAC_DATA
, par
);
1939 atyfb_save
.b
[enter
][i
] = aty_ld_8(DAC_DATA
, par
);
1940 aty_st_8(DAC_W_INDEX
, i
, par
);
1941 aty_st_8(DAC_DATA
, atyfb_save
.r
[1 - enter
][i
], par
);
1942 aty_st_8(DAC_DATA
, atyfb_save
.g
[1 - enter
][i
], par
);
1943 aty_st_8(DAC_DATA
, atyfb_save
.b
[1 - enter
][i
], par
);
1947 static void atyfb_palette(int enter
)
1949 struct atyfb_par
*par
;
1950 struct fb_info
*info
;
1953 for (i
= 0; i
< FB_MAX
; i
++) {
1954 info
= registered_fb
[i
];
1955 if (info
&& info
->fbops
== &atyfb_ops
) {
1956 par
= (struct atyfb_par
*) info
->par
;
1958 atyfb_save_palette(par
, enter
);
1960 atyfb_save
.yoffset
= info
->var
.yoffset
;
1961 info
->var
.yoffset
= 0;
1962 set_off_pitch(par
, info
);
1964 info
->var
.yoffset
= atyfb_save
.yoffset
;
1965 set_off_pitch(par
, info
);
1967 aty_st_le32(CRTC_OFF_PITCH
, par
->crtc
.off_pitch
, par
);
1972 #endif /* __sparc__ */
1976 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1978 #ifdef CONFIG_PPC_PMAC
1979 /* Power management routines. Those are used for PowerBook sleep.
1981 static int aty_power_mgmt(int sleep
, struct atyfb_par
*par
)
1986 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
1987 pm
= (pm
& ~PWR_MGT_MODE_MASK
) | PWR_MGT_MODE_REG
;
1988 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
1989 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
1995 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
1996 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
1998 pm
&= ~(PWR_BLON
| AUTO_PWR_UP
);
2000 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
2001 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
2004 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
2006 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
2008 if ((--timeout
) == 0)
2010 } while ((pm
& PWR_MGT_STATUS_MASK
) != PWR_MGT_STATUS_SUSPEND
);
2014 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
2015 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
2018 pm
|= (PWR_BLON
| AUTO_PWR_UP
);
2019 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
2020 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
2023 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
2025 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
2027 if ((--timeout
) == 0)
2029 } while ((pm
& PWR_MGT_STATUS_MASK
) != 0);
2033 return timeout
? 0 : -EIO
;
2037 static int atyfb_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2039 struct fb_info
*info
= pci_get_drvdata(pdev
);
2040 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
2042 if (state
.event
== pdev
->dev
.power
.power_state
.event
)
2045 acquire_console_sem();
2047 fb_set_suspend(info
, 1);
2049 /* Idle & reset engine */
2051 aty_reset_engine(par
);
2053 /* Blank display and LCD */
2054 atyfb_blank(FB_BLANK_POWERDOWN
, info
);
2057 par
->lock_blank
= 1;
2059 #ifdef CONFIG_PPC_PMAC
2060 /* Set chip to "suspend" mode */
2061 if (aty_power_mgmt(1, par
)) {
2063 par
->lock_blank
= 0;
2064 atyfb_blank(FB_BLANK_UNBLANK
, info
);
2065 fb_set_suspend(info
, 0);
2066 release_console_sem();
2070 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
2073 release_console_sem();
2075 pdev
->dev
.power
.power_state
= state
;
2080 static int atyfb_pci_resume(struct pci_dev
*pdev
)
2082 struct fb_info
*info
= pci_get_drvdata(pdev
);
2083 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
2085 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_ON
)
2088 acquire_console_sem();
2090 #ifdef CONFIG_PPC_PMAC
2091 if (pdev
->dev
.power
.power_state
.event
== 2)
2092 aty_power_mgmt(0, par
);
2094 pci_set_power_state(pdev
, PCI_D0
);
2097 aty_resume_chip(info
);
2101 /* Restore display */
2102 atyfb_set_par(info
);
2105 fb_set_suspend(info
, 0);
2108 par
->lock_blank
= 0;
2109 atyfb_blank(FB_BLANK_UNBLANK
, info
);
2111 release_console_sem();
2113 pdev
->dev
.power
.power_state
= PMSG_ON
;
2118 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2121 #ifdef CONFIG_FB_ATY_BACKLIGHT
2122 #define MAX_LEVEL 0xFF
2124 static int aty_bl_get_level_brightness(struct atyfb_par
*par
, int level
)
2126 struct fb_info
*info
= pci_get_drvdata(par
->pdev
);
2129 /* Get and convert the value */
2130 /* No locking of bl_curve since we read a single value */
2131 atylevel
= info
->bl_curve
[level
] * FB_BACKLIGHT_MAX
/ MAX_LEVEL
;
2135 else if (atylevel
> MAX_LEVEL
)
2136 atylevel
= MAX_LEVEL
;
2141 static int aty_bl_update_status(struct backlight_device
*bd
)
2143 struct atyfb_par
*par
= class_get_devdata(&bd
->class_dev
);
2144 unsigned int reg
= aty_ld_lcd(LCD_MISC_CNTL
, par
);
2147 if (bd
->props
.power
!= FB_BLANK_UNBLANK
||
2148 bd
->props
.fb_blank
!= FB_BLANK_UNBLANK
)
2151 level
= bd
->props
.brightness
;
2153 reg
|= (BLMOD_EN
| BIASMOD_EN
);
2155 reg
&= ~BIAS_MOD_LEVEL_MASK
;
2156 reg
|= (aty_bl_get_level_brightness(par
, level
) << BIAS_MOD_LEVEL_SHIFT
);
2158 reg
&= ~BIAS_MOD_LEVEL_MASK
;
2159 reg
|= (aty_bl_get_level_brightness(par
, 0) << BIAS_MOD_LEVEL_SHIFT
);
2161 aty_st_lcd(LCD_MISC_CNTL
, reg
, par
);
2166 static int aty_bl_get_brightness(struct backlight_device
*bd
)
2168 return bd
->props
.brightness
;
2171 static struct backlight_ops aty_bl_data
= {
2172 .get_brightness
= aty_bl_get_brightness
,
2173 .update_status
= aty_bl_update_status
,
2176 static void aty_bl_init(struct atyfb_par
*par
)
2178 struct fb_info
*info
= pci_get_drvdata(par
->pdev
);
2179 struct backlight_device
*bd
;
2182 #ifdef CONFIG_PMAC_BACKLIGHT
2183 if (!pmac_has_backlight_type("ati"))
2187 snprintf(name
, sizeof(name
), "atybl%d", info
->node
);
2189 bd
= backlight_device_register(name
, info
->dev
, par
, &aty_bl_data
);
2191 info
->bl_dev
= NULL
;
2192 printk(KERN_WARNING
"aty: Backlight registration failed\n");
2197 fb_bl_default_curve(info
, 0,
2198 0x3F * FB_BACKLIGHT_MAX
/ MAX_LEVEL
,
2199 0xFF * FB_BACKLIGHT_MAX
/ MAX_LEVEL
);
2201 bd
->props
.max_brightness
= FB_BACKLIGHT_LEVELS
- 1;
2202 bd
->props
.brightness
= bd
->props
.max_brightness
;
2203 bd
->props
.power
= FB_BLANK_UNBLANK
;
2204 backlight_update_status(bd
);
2206 printk("aty: Backlight initialized (%s)\n", name
);
2214 static void aty_bl_exit(struct backlight_device
*bd
)
2216 backlight_device_unregister(bd
);
2217 printk("aty: Backlight unloaded\n");
2220 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2222 static void __devinit
aty_calc_mem_refresh(struct atyfb_par
*par
, int xclk
)
2224 const int ragepro_tbl
[] = {
2225 44, 50, 55, 66, 75, 80, 100
2227 const int ragexl_tbl
[] = {
2228 50, 66, 75, 83, 90, 95, 100, 105,
2229 110, 115, 120, 125, 133, 143, 166
2231 const int *refresh_tbl
;
2234 if (IS_XL(par
->pci_id
) || IS_MOBILITY(par
->pci_id
)) {
2235 refresh_tbl
= ragexl_tbl
;
2236 size
= ARRAY_SIZE(ragexl_tbl
);
2238 refresh_tbl
= ragepro_tbl
;
2239 size
= ARRAY_SIZE(ragepro_tbl
);
2242 for (i
=0; i
< size
; i
++) {
2243 if (xclk
< refresh_tbl
[i
])
2246 par
->mem_refresh_rate
= i
;
2253 static struct fb_info
*fb_list
= NULL
;
2255 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2256 static int __devinit
atyfb_get_timings_from_lcd(struct atyfb_par
*par
,
2257 struct fb_var_screeninfo
*var
)
2261 if (par
->lcd_table
!= 0 && (aty_ld_lcd(LCD_GEN_CNTL
, par
) & LCD_ON
)) {
2263 var
->xres
= var
->xres_virtual
= par
->lcd_hdisp
;
2264 var
->right_margin
= par
->lcd_right_margin
;
2265 var
->left_margin
= par
->lcd_hblank_len
-
2266 (par
->lcd_right_margin
+ par
->lcd_hsync_dly
+
2267 par
->lcd_hsync_len
);
2268 var
->hsync_len
= par
->lcd_hsync_len
+ par
->lcd_hsync_dly
;
2269 var
->yres
= var
->yres_virtual
= par
->lcd_vdisp
;
2270 var
->lower_margin
= par
->lcd_lower_margin
;
2271 var
->upper_margin
= par
->lcd_vblank_len
-
2272 (par
->lcd_lower_margin
+ par
->lcd_vsync_len
);
2273 var
->vsync_len
= par
->lcd_vsync_len
;
2274 var
->pixclock
= par
->lcd_pixclock
;
2280 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2282 static int __devinit
aty_init(struct fb_info
*info
)
2284 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
2285 const char *ramname
= NULL
, *xtal
;
2286 int gtb_memsize
, has_var
= 0;
2287 struct fb_var_screeninfo var
;
2289 init_waitqueue_head(&par
->vblank
.wait
);
2290 spin_lock_init(&par
->int_lock
);
2292 #ifdef CONFIG_PPC_PMAC
2293 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2294 * and set the frequency manually. */
2295 if (machine_is_compatible("PowerBook2,1")) {
2296 par
->pll_limits
.mclk
= 70;
2297 par
->pll_limits
.xclk
= 53;
2301 #ifdef CONFIG_FB_ATY_GX
2302 if (!M64_HAS(INTEGRATED
)) {
2304 u8 dac_type
, dac_subtype
, clk_type
;
2305 stat0
= aty_ld_le32(CONFIG_STAT0
, par
);
2306 par
->bus_type
= (stat0
>> 0) & 0x07;
2307 par
->ram_type
= (stat0
>> 3) & 0x07;
2308 ramname
= aty_gx_ram
[par
->ram_type
];
2309 /* FIXME: clockchip/RAMDAC probing? */
2310 dac_type
= (aty_ld_le32(DAC_CNTL
, par
) >> 16) & 0x07;
2312 clk_type
= CLK_ATI18818_1
;
2313 dac_type
= (stat0
>> 9) & 0x07;
2314 if (dac_type
== 0x07)
2315 dac_subtype
= DAC_ATT20C408
;
2317 dac_subtype
= (aty_ld_8(SCRATCH_REG1
+ 1, par
) & 0xF0) | dac_type
;
2319 dac_type
= DAC_IBMRGB514
;
2320 dac_subtype
= DAC_IBMRGB514
;
2321 clk_type
= CLK_IBMRGB514
;
2323 switch (dac_subtype
) {
2325 par
->dac_ops
= &aty_dac_ibm514
;
2328 case DAC_ATI68860_B
:
2329 case DAC_ATI68860_C
:
2330 par
->dac_ops
= &aty_dac_ati68860b
;
2334 par
->dac_ops
= &aty_dac_att21c498
;
2338 PRINTKI("aty_init: DAC type not implemented yet!\n");
2339 par
->dac_ops
= &aty_dac_unsupported
;
2344 case CLK_ATI18818_1
:
2345 par
->pll_ops
= &aty_pll_ati18818_1
;
2349 par
->pll_ops
= &aty_pll_ibm514
;
2352 #if 0 /* dead code */
2354 par
->pll_ops
= &aty_pll_stg1703
;
2357 par
->pll_ops
= &aty_pll_ch8398
;
2360 par
->pll_ops
= &aty_pll_att20c408
;
2364 PRINTKI("aty_init: CLK type not implemented yet!");
2365 par
->pll_ops
= &aty_pll_unsupported
;
2369 #endif /* CONFIG_FB_ATY_GX */
2370 #ifdef CONFIG_FB_ATY_CT
2371 if (M64_HAS(INTEGRATED
)) {
2372 par
->dac_ops
= &aty_dac_ct
;
2373 par
->pll_ops
= &aty_pll_ct
;
2374 par
->bus_type
= PCI
;
2375 par
->ram_type
= (aty_ld_le32(CONFIG_STAT0
, par
) & 0x07);
2376 ramname
= aty_ct_ram
[par
->ram_type
];
2377 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2378 if (par
->pll_limits
.mclk
== 67 && par
->ram_type
< SDRAM
)
2379 par
->pll_limits
.mclk
= 63;
2383 /* Allow command line to override clocks. */
2385 par
->pll_limits
.pll_max
= pll
;
2387 par
->pll_limits
.mclk
= mclk
;
2389 par
->pll_limits
.xclk
= xclk
;
2391 aty_calc_mem_refresh(par
, par
->pll_limits
.xclk
);
2392 par
->pll_per
= 1000000/par
->pll_limits
.pll_max
;
2393 par
->mclk_per
= 1000000/par
->pll_limits
.mclk
;
2394 par
->xclk_per
= 1000000/par
->pll_limits
.xclk
;
2396 par
->ref_clk_per
= 1000000000000ULL / 14318180;
2399 #ifdef CONFIG_FB_ATY_CT
2400 if (M64_HAS(GTB_DSP
)) {
2401 u8 pll_ref_div
= aty_ld_pll_ct(PLL_REF_DIV
, par
);
2405 diff1
= 510 * 14 / pll_ref_div
- par
->pll_limits
.pll_max
;
2406 diff2
= 510 * 29 / pll_ref_div
- par
->pll_limits
.pll_max
;
2411 if (diff2
< diff1
) {
2412 par
->ref_clk_per
= 1000000000000ULL / 29498928;
2417 #endif /* CONFIG_FB_ATY_CT */
2419 /* save previous video mode */
2420 aty_get_crtc(par
, &saved_crtc
);
2421 if(par
->pll_ops
->get_pll
)
2422 par
->pll_ops
->get_pll(info
, &saved_pll
);
2424 par
->mem_cntl
= aty_ld_le32(MEM_CNTL
, par
);
2425 gtb_memsize
= M64_HAS(GTB_DSP
);
2427 switch (par
->mem_cntl
& 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2429 info
->fix
.smem_len
= 0x80000;
2432 info
->fix
.smem_len
= 0x100000;
2434 case MEM_SIZE_2M_GTB
:
2435 info
->fix
.smem_len
= 0x200000;
2437 case MEM_SIZE_4M_GTB
:
2438 info
->fix
.smem_len
= 0x400000;
2440 case MEM_SIZE_6M_GTB
:
2441 info
->fix
.smem_len
= 0x600000;
2443 case MEM_SIZE_8M_GTB
:
2444 info
->fix
.smem_len
= 0x800000;
2447 info
->fix
.smem_len
= 0x80000;
2449 switch (par
->mem_cntl
& MEM_SIZE_ALIAS
) {
2451 info
->fix
.smem_len
= 0x80000;
2454 info
->fix
.smem_len
= 0x100000;
2457 info
->fix
.smem_len
= 0x200000;
2460 info
->fix
.smem_len
= 0x400000;
2463 info
->fix
.smem_len
= 0x600000;
2466 info
->fix
.smem_len
= 0x800000;
2469 info
->fix
.smem_len
= 0x80000;
2472 if (M64_HAS(MAGIC_VRAM_SIZE
)) {
2473 if (aty_ld_le32(CONFIG_STAT1
, par
) & 0x40000000)
2474 info
->fix
.smem_len
+= 0x400000;
2478 info
->fix
.smem_len
= vram
* 1024;
2479 par
->mem_cntl
&= ~(gtb_memsize
? 0xF : MEM_SIZE_ALIAS
);
2480 if (info
->fix
.smem_len
<= 0x80000)
2481 par
->mem_cntl
|= MEM_SIZE_512K
;
2482 else if (info
->fix
.smem_len
<= 0x100000)
2483 par
->mem_cntl
|= MEM_SIZE_1M
;
2484 else if (info
->fix
.smem_len
<= 0x200000)
2485 par
->mem_cntl
|= gtb_memsize
? MEM_SIZE_2M_GTB
: MEM_SIZE_2M
;
2486 else if (info
->fix
.smem_len
<= 0x400000)
2487 par
->mem_cntl
|= gtb_memsize
? MEM_SIZE_4M_GTB
: MEM_SIZE_4M
;
2488 else if (info
->fix
.smem_len
<= 0x600000)
2489 par
->mem_cntl
|= gtb_memsize
? MEM_SIZE_6M_GTB
: MEM_SIZE_6M
;
2491 par
->mem_cntl
|= gtb_memsize
? MEM_SIZE_8M_GTB
: MEM_SIZE_8M
;
2492 aty_st_le32(MEM_CNTL
, par
->mem_cntl
, par
);
2496 * Reg Block 0 (CT-compatible block) is at mmio_start
2497 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2500 info
->fix
.mmio_len
= 0x400;
2501 info
->fix
.accel
= FB_ACCEL_ATI_MACH64GX
;
2502 } else if (M64_HAS(CT
)) {
2503 info
->fix
.mmio_len
= 0x400;
2504 info
->fix
.accel
= FB_ACCEL_ATI_MACH64CT
;
2505 } else if (M64_HAS(VT
)) {
2506 info
->fix
.mmio_start
-= 0x400;
2507 info
->fix
.mmio_len
= 0x800;
2508 info
->fix
.accel
= FB_ACCEL_ATI_MACH64VT
;
2510 info
->fix
.mmio_start
-= 0x400;
2511 info
->fix
.mmio_len
= 0x800;
2512 info
->fix
.accel
= FB_ACCEL_ATI_MACH64GT
;
2515 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2516 info
->fix
.smem_len
== 0x80000 ? 512 : (info
->fix
.smem_len
>> 20),
2517 info
->fix
.smem_len
== 0x80000 ? 'K' : 'M', ramname
, xtal
, par
->pll_limits
.pll_max
,
2518 par
->pll_limits
.mclk
, par
->pll_limits
.xclk
);
2520 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2521 if (M64_HAS(INTEGRATED
)) {
2523 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2524 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2525 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2527 aty_ld_le32(BUS_CNTL
, par
), aty_ld_le32(DAC_CNTL
, par
),
2528 aty_ld_le32(MEM_CNTL
, par
), aty_ld_le32(EXT_MEM_CNTL
, par
),
2529 aty_ld_le32(CRTC_GEN_CNTL
, par
), aty_ld_le32(DSP_CONFIG
, par
),
2530 aty_ld_le32(DSP_ON_OFF
, par
), aty_ld_le32(CLOCK_CNTL
, par
));
2531 for (i
= 0; i
< 40; i
++)
2532 printk(" %02x", aty_ld_pll_ct(i
, par
));
2536 if(par
->pll_ops
->init_pll
)
2537 par
->pll_ops
->init_pll(info
, &par
->pll
);
2538 if (par
->pll_ops
->resume_pll
)
2539 par
->pll_ops
->resume_pll(info
, &par
->pll
);
2542 * Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2543 * unless the auxiliary register aperture is used.
2546 if (!par
->aux_start
&&
2547 (info
->fix
.smem_len
== 0x800000 || (par
->bus_type
== ISA
&& info
->fix
.smem_len
== 0x400000)))
2548 info
->fix
.smem_len
-= GUI_RESERVE
;
2551 * Disable register access through the linear aperture
2552 * if the auxiliary aperture is used so we can access
2553 * the full 8 MB of video RAM on 8 MB boards.
2556 aty_st_le32(BUS_CNTL
, aty_ld_le32(BUS_CNTL
, par
) | BUS_APER_REG_DIS
, par
);
2559 par
->mtrr_aper
= -1;
2562 /* Cover the whole resource. */
2563 par
->mtrr_aper
= mtrr_add(par
->res_start
, par
->res_size
, MTRR_TYPE_WRCOMB
, 1);
2564 if (par
->mtrr_aper
>= 0 && !par
->aux_start
) {
2565 /* Make a hole for mmio. */
2566 par
->mtrr_reg
= mtrr_add(par
->res_start
+ 0x800000 - GUI_RESERVE
,
2567 GUI_RESERVE
, MTRR_TYPE_UNCACHABLE
, 1);
2568 if (par
->mtrr_reg
< 0) {
2569 mtrr_del(par
->mtrr_aper
, 0, 0);
2570 par
->mtrr_aper
= -1;
2576 info
->fbops
= &atyfb_ops
;
2577 info
->pseudo_palette
= pseudo_palette
;
2578 info
->flags
= FBINFO_DEFAULT
|
2579 FBINFO_HWACCEL_IMAGEBLIT
|
2580 FBINFO_HWACCEL_FILLRECT
|
2581 FBINFO_HWACCEL_COPYAREA
|
2582 FBINFO_HWACCEL_YPAN
;
2584 #ifdef CONFIG_PMAC_BACKLIGHT
2585 if (M64_HAS(G3_PB_1_1
) && machine_is_compatible("PowerBook1,1")) {
2586 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2587 aty_st_lcd(POWER_MANAGEMENT
, aty_ld_lcd(POWER_MANAGEMENT
, par
)
2588 | (USE_F32KHZ
| TRISTATE_MEM_EN
), par
);
2591 if (M64_HAS(MOBIL_BUS
) && backlight
) {
2592 #ifdef CONFIG_FB_ATY_BACKLIGHT
2597 memset(&var
, 0, sizeof(var
));
2599 if (machine_is(powermac
)) {
2601 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2602 * applies to all Mac video cards
2605 if (mac_find_mode(&var
, info
, mode
, 8))
2608 if (default_vmode
== VMODE_CHOOSE
) {
2610 if (M64_HAS(G3_PB_1024x768
))
2611 /* G3 PowerBook with 1024x768 LCD */
2612 default_vmode
= VMODE_1024_768_60
;
2613 else if (machine_is_compatible("iMac"))
2614 default_vmode
= VMODE_1024_768_75
;
2615 else if (machine_is_compatible
2617 /* iBook with 800x600 LCD */
2618 default_vmode
= VMODE_800_600_60
;
2620 default_vmode
= VMODE_640_480_67
;
2621 sense
= read_aty_sense(par
);
2622 PRINTKI("monitor sense=%x, mode %d\n",
2623 sense
, mac_map_monitor_sense(sense
));
2625 if (default_vmode
<= 0 || default_vmode
> VMODE_MAX
)
2626 default_vmode
= VMODE_640_480_60
;
2627 if (default_cmode
< CMODE_8
|| default_cmode
> CMODE_32
)
2628 default_cmode
= CMODE_8
;
2629 if (!mac_vmode_to_var(default_vmode
, default_cmode
,
2635 #endif /* !CONFIG_PPC */
2637 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2638 if (!atyfb_get_timings_from_lcd(par
, &var
))
2642 if (mode
&& fb_find_mode(&var
, info
, mode
, NULL
, 0, &defmode
, 8))
2649 var
.accel_flags
&= ~FB_ACCELF_TEXT
;
2651 var
.accel_flags
|= FB_ACCELF_TEXT
;
2653 if (comp_sync
!= -1) {
2655 var
.sync
&= ~FB_SYNC_COMP_HIGH_ACT
;
2657 var
.sync
|= FB_SYNC_COMP_HIGH_ACT
;
2660 if (var
.yres
== var
.yres_virtual
) {
2661 u32 videoram
= (info
->fix
.smem_len
- (PAGE_SIZE
<< 2));
2662 var
.yres_virtual
= ((videoram
* 8) / var
.bits_per_pixel
) / var
.xres_virtual
;
2663 if (var
.yres_virtual
< var
.yres
)
2664 var
.yres_virtual
= var
.yres
;
2667 if (atyfb_check_var(&var
, info
)) {
2668 PRINTKE("can't set default video mode\n");
2673 atyfb_save_palette(par
, 0);
2676 #ifdef CONFIG_FB_ATY_CT
2677 if (!noaccel
&& M64_HAS(INTEGRATED
))
2678 aty_init_cursor(info
);
2679 #endif /* CONFIG_FB_ATY_CT */
2682 fb_alloc_cmap(&info
->cmap
, 256, 0);
2684 if (register_framebuffer(info
) < 0)
2689 PRINTKI("fb%d: %s frame buffer device on %s\n",
2690 info
->node
, info
->fix
.id
, par
->bus_type
== ISA
? "ISA" : "PCI");
2694 /* restore video mode */
2695 aty_set_crtc(par
, &saved_crtc
);
2696 par
->pll_ops
->set_pll(info
, &saved_pll
);
2699 if (par
->mtrr_reg
>= 0) {
2700 mtrr_del(par
->mtrr_reg
, 0, 0);
2703 if (par
->mtrr_aper
>= 0) {
2704 mtrr_del(par
->mtrr_aper
, 0, 0);
2705 par
->mtrr_aper
= -1;
2711 static void aty_resume_chip(struct fb_info
*info
)
2713 struct atyfb_par
*par
= info
->par
;
2715 aty_st_le32(MEM_CNTL
, par
->mem_cntl
, par
);
2717 if (par
->pll_ops
->resume_pll
)
2718 par
->pll_ops
->resume_pll(info
, &par
->pll
);
2721 aty_st_le32(BUS_CNTL
, aty_ld_le32(BUS_CNTL
, par
) | BUS_APER_REG_DIS
, par
);
2725 static int __devinit
store_video_par(char *video_str
, unsigned char m64_num
)
2728 unsigned long vmembase
, size
, guiregbase
;
2730 PRINTKI("store_video_par() '%s' \n", video_str
);
2732 if (!(p
= strsep(&video_str
, ";")) || !*p
)
2733 goto mach64_invalid
;
2734 vmembase
= simple_strtoul(p
, NULL
, 0);
2735 if (!(p
= strsep(&video_str
, ";")) || !*p
)
2736 goto mach64_invalid
;
2737 size
= simple_strtoul(p
, NULL
, 0);
2738 if (!(p
= strsep(&video_str
, ";")) || !*p
)
2739 goto mach64_invalid
;
2740 guiregbase
= simple_strtoul(p
, NULL
, 0);
2742 phys_vmembase
[m64_num
] = vmembase
;
2743 phys_size
[m64_num
] = size
;
2744 phys_guiregbase
[m64_num
] = guiregbase
;
2745 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase
, size
,
2750 phys_vmembase
[m64_num
] = 0;
2753 #endif /* CONFIG_ATARI */
2756 * Blank the display.
2759 static int atyfb_blank(int blank
, struct fb_info
*info
)
2761 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
2764 if (par
->lock_blank
|| par
->asleep
)
2767 #ifdef CONFIG_FB_ATY_BACKLIGHT
2768 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2769 if (par
->lcd_table
&& blank
> FB_BLANK_NORMAL
&&
2770 (aty_ld_lcd(LCD_GEN_CNTL
, par
) & LCD_ON
)) {
2771 u32 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
2773 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
2777 gen_cntl
= aty_ld_le32(CRTC_GEN_CNTL
, par
);
2778 gen_cntl
&= ~0x400004c;
2780 case FB_BLANK_UNBLANK
:
2782 case FB_BLANK_NORMAL
:
2783 gen_cntl
|= 0x4000040;
2785 case FB_BLANK_VSYNC_SUSPEND
:
2786 gen_cntl
|= 0x4000048;
2788 case FB_BLANK_HSYNC_SUSPEND
:
2789 gen_cntl
|= 0x4000044;
2791 case FB_BLANK_POWERDOWN
:
2792 gen_cntl
|= 0x400004c;
2795 aty_st_le32(CRTC_GEN_CNTL
, gen_cntl
, par
);
2797 #ifdef CONFIG_FB_ATY_BACKLIGHT
2798 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2799 if (par
->lcd_table
&& blank
<= FB_BLANK_NORMAL
&&
2800 (aty_ld_lcd(LCD_GEN_CNTL
, par
) & LCD_ON
)) {
2801 u32 pm
= aty_ld_lcd(POWER_MANAGEMENT
, par
);
2803 aty_st_lcd(POWER_MANAGEMENT
, pm
, par
);
2810 static void aty_st_pal(u_int regno
, u_int red
, u_int green
, u_int blue
,
2811 const struct atyfb_par
*par
)
2813 aty_st_8(DAC_W_INDEX
, regno
, par
);
2814 aty_st_8(DAC_DATA
, red
, par
);
2815 aty_st_8(DAC_DATA
, green
, par
);
2816 aty_st_8(DAC_DATA
, blue
, par
);
2820 * Set a single color register. The values supplied are already
2821 * rounded down to the hardware's capabilities (according to the
2822 * entries in the var structure). Return != 0 for invalid regno.
2823 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2826 static int atyfb_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
2827 u_int transp
, struct fb_info
*info
)
2829 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
2831 u32
*pal
= info
->pseudo_palette
;
2833 depth
= info
->var
.bits_per_pixel
;
2835 depth
= (info
->var
.green
.length
== 5) ? 15 : 16;
2841 (depth
== 16 && regno
> 63) ||
2842 (depth
== 15 && regno
> 31))
2849 par
->palette
[regno
].red
= red
;
2850 par
->palette
[regno
].green
= green
;
2851 par
->palette
[regno
].blue
= blue
;
2856 pal
[regno
] = (regno
<< 10) | (regno
<< 5) | regno
;
2859 pal
[regno
] = (regno
<< 11) | (regno
<< 5) | regno
;
2862 pal
[regno
] = (regno
<< 16) | (regno
<< 8) | regno
;
2865 i
= (regno
<< 8) | regno
;
2866 pal
[regno
] = (i
<< 16) | i
;
2871 i
= aty_ld_8(DAC_CNTL
, par
) & 0xfc;
2872 if (M64_HAS(EXTRA_BRIGHT
))
2873 i
|= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2874 aty_st_8(DAC_CNTL
, i
, par
);
2875 aty_st_8(DAC_MASK
, 0xff, par
);
2877 if (M64_HAS(INTEGRATED
)) {
2880 aty_st_pal(regno
<< 3, red
,
2881 par
->palette
[regno
<<1].green
,
2883 red
= par
->palette
[regno
>>1].red
;
2884 blue
= par
->palette
[regno
>>1].blue
;
2886 } else if (depth
== 15) {
2888 for(i
= 0; i
< 8; i
++) {
2889 aty_st_pal(regno
+ i
, red
, green
, blue
, par
);
2893 aty_st_pal(regno
, red
, green
, blue
, par
);
2902 extern void (*prom_palette
) (int);
2904 static int __devinit
atyfb_setup_sparc(struct pci_dev
*pdev
,
2905 struct fb_info
*info
, unsigned long addr
)
2907 struct atyfb_par
*par
= info
->par
;
2908 struct device_node
*dp
;
2910 int node
, len
, i
, j
, ret
;
2913 /* Do not attach when we have a serial console. */
2914 if (!con_is_present())
2918 * Map memory-mapped registers.
2920 par
->ati_regbase
= (void *)addr
+ 0x7ffc00UL
;
2921 info
->fix
.mmio_start
= addr
+ 0x7ffc00UL
;
2924 * Map in big-endian aperture.
2926 info
->screen_base
= (char *) (addr
+ 0x800000UL
);
2927 info
->fix
.smem_start
= addr
+ 0x800000UL
;
2930 * Figure mmap addresses from PCI config space.
2931 * Split Framebuffer in big- and little-endian halfs.
2933 for (i
= 0; i
< 6 && pdev
->resource
[i
].start
; i
++)
2937 par
->mmap_map
= kmalloc(j
* sizeof(*par
->mmap_map
), GFP_ATOMIC
);
2938 if (!par
->mmap_map
) {
2939 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2942 memset(par
->mmap_map
, 0, j
* sizeof(*par
->mmap_map
));
2944 for (i
= 0, j
= 2; i
< 6 && pdev
->resource
[i
].start
; i
++) {
2945 struct resource
*rp
= &pdev
->resource
[i
];
2946 int io
, breg
= PCI_BASE_ADDRESS_0
+ (i
<< 2);
2952 io
= (rp
->flags
& IORESOURCE_IO
);
2954 size
= rp
->end
- base
+ 1;
2956 pci_read_config_dword(pdev
, breg
, &pbase
);
2962 * Map the framebuffer a second time, this time without
2963 * the braindead _PAGE_IE setting. This is used by the
2964 * fixed Xserver, but we need to maintain the old mapping
2965 * to stay compatible with older ones...
2968 par
->mmap_map
[j
].voff
= (pbase
+ 0x10000000) & PAGE_MASK
;
2969 par
->mmap_map
[j
].poff
= base
& PAGE_MASK
;
2970 par
->mmap_map
[j
].size
= (size
+ ~PAGE_MASK
) & PAGE_MASK
;
2971 par
->mmap_map
[j
].prot_mask
= _PAGE_CACHE
;
2972 par
->mmap_map
[j
].prot_flag
= _PAGE_E
;
2977 * Here comes the old framebuffer mapping with _PAGE_IE
2978 * set for the big endian half of the framebuffer...
2981 par
->mmap_map
[j
].voff
= (pbase
+ 0x800000) & PAGE_MASK
;
2982 par
->mmap_map
[j
].poff
= (base
+ 0x800000) & PAGE_MASK
;
2983 par
->mmap_map
[j
].size
= 0x800000;
2984 par
->mmap_map
[j
].prot_mask
= _PAGE_CACHE
;
2985 par
->mmap_map
[j
].prot_flag
= _PAGE_E
| _PAGE_IE
;
2990 par
->mmap_map
[j
].voff
= pbase
& PAGE_MASK
;
2991 par
->mmap_map
[j
].poff
= base
& PAGE_MASK
;
2992 par
->mmap_map
[j
].size
= (size
+ ~PAGE_MASK
) & PAGE_MASK
;
2993 par
->mmap_map
[j
].prot_mask
= _PAGE_CACHE
;
2994 par
->mmap_map
[j
].prot_flag
= _PAGE_E
;
2998 if((ret
= correct_chipset(par
)))
3001 if (IS_XL(pdev
->device
)) {
3003 * Fix PROMs idea of MEM_CNTL settings...
3005 mem
= aty_ld_le32(MEM_CNTL
, par
);
3006 chip_id
= aty_ld_le32(CONFIG_CHIP_ID
, par
);
3007 if (((chip_id
& CFG_CHIP_TYPE
) == VT_CHIP_ID
) && !((chip_id
>> 24) & 1)) {
3008 switch (mem
& 0x0f) {
3010 mem
= (mem
& ~(0x0f)) | 2;
3013 mem
= (mem
& ~(0x0f)) | 3;
3016 mem
= (mem
& ~(0x0f)) | 4;
3019 mem
= (mem
& ~(0x0f)) | 5;
3024 if ((aty_ld_le32(CONFIG_STAT0
, par
) & 7) >= SDRAM
)
3025 mem
&= ~(0x00700000);
3027 mem
&= ~(0xcf80e000); /* Turn off all undocumented bits. */
3028 aty_st_le32(MEM_CNTL
, mem
, par
);
3032 * If this is the console device, we will set default video
3033 * settings to what the PROM left us with.
3035 node
= prom_getchild(prom_root_node
);
3036 node
= prom_searchsiblings(node
, "aliases");
3038 len
= prom_getproperty(node
, "screen", prop
, sizeof(prop
));
3041 node
= prom_finddevice(prop
);
3046 dp
= pci_device_to_OF_node(pdev
);
3047 if (node
== dp
->node
) {
3048 struct fb_var_screeninfo
*var
= &default_var
;
3049 unsigned int N
, P
, Q
, M
, T
, R
;
3050 u32 v_total
, h_total
;
3055 crtc
.vxres
= prom_getintdefault(node
, "width", 1024);
3056 crtc
.vyres
= prom_getintdefault(node
, "height", 768);
3057 var
->bits_per_pixel
= prom_getintdefault(node
, "depth", 8);
3058 var
->xoffset
= var
->yoffset
= 0;
3059 crtc
.h_tot_disp
= aty_ld_le32(CRTC_H_TOTAL_DISP
, par
);
3060 crtc
.h_sync_strt_wid
= aty_ld_le32(CRTC_H_SYNC_STRT_WID
, par
);
3061 crtc
.v_tot_disp
= aty_ld_le32(CRTC_V_TOTAL_DISP
, par
);
3062 crtc
.v_sync_strt_wid
= aty_ld_le32(CRTC_V_SYNC_STRT_WID
, par
);
3063 crtc
.gen_cntl
= aty_ld_le32(CRTC_GEN_CNTL
, par
);
3064 aty_crtc_to_var(&crtc
, var
);
3066 h_total
= var
->xres
+ var
->right_margin
+ var
->hsync_len
+ var
->left_margin
;
3067 v_total
= var
->yres
+ var
->lower_margin
+ var
->vsync_len
+ var
->upper_margin
;
3070 * Read the PLL to figure actual Refresh Rate.
3072 clock_cntl
= aty_ld_8(CLOCK_CNTL
, par
);
3073 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3074 for (i
= 0; i
< 16; i
++)
3075 pll_regs
[i
] = aty_ld_pll_ct(i
, par
);
3078 * PLL Reference Divider M:
3083 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3085 N
= pll_regs
[7 + (clock_cntl
& 3)];
3088 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3090 P
= 1 << (pll_regs
[6] >> ((clock_cntl
& 3) << 1));
3104 * where R is XTALIN (= 14318 or 29498 kHz).
3106 if (IS_XL(pdev
->device
))
3113 default_var
.pixclock
= 1000000000 / T
;
3119 #else /* __sparc__ */
3122 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3123 static void __devinit
aty_init_lcd(struct atyfb_par
*par
, u32 bios_base
)
3125 u32 driv_inf_tab
, sig
;
3128 /* To support an LCD panel, we should know it's dimensions and
3129 * it's desired pixel clock.
3130 * There are two ways to do it:
3131 * - Check the startup video mode and calculate the panel
3132 * size from it. This is unreliable.
3133 * - Read it from the driver information table in the video BIOS.
3135 /* Address of driver information table is at offset 0x78. */
3136 driv_inf_tab
= bios_base
+ *((u16
*)(bios_base
+0x78));
3138 /* Check for the driver information table signature. */
3139 sig
= (*(u32
*)driv_inf_tab
);
3140 if ((sig
== 0x54504c24) || /* Rage LT pro */
3141 (sig
== 0x544d5224) || /* Rage mobility */
3142 (sig
== 0x54435824) || /* Rage XC */
3143 (sig
== 0x544c5824)) { /* Rage XL */
3144 PRINTKI("BIOS contains driver information table.\n");
3145 lcd_ofs
= (*(u16
*)(driv_inf_tab
+ 10));
3148 par
->lcd_table
= bios_base
+ lcd_ofs
;
3152 if (par
->lcd_table
!= 0) {
3155 char refresh_rates_buf
[100];
3156 int id
, tech
, f
, i
, m
, default_refresh_rate
;
3161 u16 width
, height
, panel_type
, refresh_rates
;
3164 u8 lcd_refresh_rates
[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3165 /* The most important information is the panel size at
3166 * offset 25 and 27, but there's some other nice information
3167 * which we print to the screen.
3169 id
= *(u8
*)par
->lcd_table
;
3170 strncpy(model
,(char *)par
->lcd_table
+1,24);
3173 width
= par
->lcd_width
= *(u16
*)(par
->lcd_table
+25);
3174 height
= par
->lcd_height
= *(u16
*)(par
->lcd_table
+27);
3175 panel_type
= *(u16
*)(par
->lcd_table
+29);
3177 txtcolour
= "colour";
3179 txtcolour
= "monochrome";
3181 txtdual
= "dual (split) ";
3184 tech
= (panel_type
>>2) & 63;
3187 txtmonitor
= "passive matrix";
3190 txtmonitor
= "active matrix";
3193 txtmonitor
= "active addressed STN";
3199 txtmonitor
= "plasma";
3202 txtmonitor
= "unknown";
3204 format
= *(u32
*)(par
->lcd_table
+57);
3205 if (tech
== 0 || tech
== 2) {
3206 switch (format
& 7) {
3208 txtformat
= "12 bit interface";
3211 txtformat
= "16 bit interface";
3214 txtformat
= "24 bit interface";
3217 txtformat
= "unkown format";
3220 switch (format
& 7) {
3222 txtformat
= "8 colours";
3225 txtformat
= "512 colours";
3228 txtformat
= "4096 colours";
3231 txtformat
= "262144 colours (LT mode)";
3234 txtformat
= "16777216 colours";
3237 txtformat
= "262144 colours (FDPI-2 mode)";
3240 txtformat
= "unkown format";
3243 PRINTKI("%s%s %s monitor detected: %s\n",
3244 txtdual
,txtcolour
, txtmonitor
, model
);
3245 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3246 id
, width
, height
, txtformat
);
3247 refresh_rates_buf
[0] = 0;
3248 refresh_rates
= *(u16
*)(par
->lcd_table
+62);
3251 for (i
=0;i
<16;i
++) {
3252 if (refresh_rates
& m
) {
3254 sprintf(strbuf
, "%d", lcd_refresh_rates
[i
]);
3257 sprintf(strbuf
, ",%d", lcd_refresh_rates
[i
]);
3259 strcat(refresh_rates_buf
,strbuf
);
3263 default_refresh_rate
= (*(u8
*)(par
->lcd_table
+61) & 0xf0) >> 4;
3264 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3265 refresh_rates_buf
, lcd_refresh_rates
[default_refresh_rate
]);
3266 par
->lcd_refreshrate
= lcd_refresh_rates
[default_refresh_rate
];
3267 /* We now need to determine the crtc parameters for the
3268 * LCD monitor. This is tricky, because they are not stored
3269 * individually in the BIOS. Instead, the BIOS contains a
3270 * table of display modes that work for this monitor.
3272 * The idea is that we search for a mode of the same dimensions
3273 * as the dimensions of the LCD monitor. Say our LCD monitor
3274 * is 800x600 pixels, we search for a 800x600 monitor.
3275 * The CRTC parameters we find here are the ones that we need
3276 * to use to simulate other resolutions on the LCD screen.
3278 lcdmodeptr
= (u16
*)(par
->lcd_table
+ 64);
3279 while (*lcdmodeptr
!= 0) {
3281 u16 mwidth
, mheight
, lcd_hsync_start
, lcd_vsync_start
;
3282 modeptr
= bios_base
+ *lcdmodeptr
;
3284 mwidth
= *((u16
*)(modeptr
+0));
3285 mheight
= *((u16
*)(modeptr
+2));
3287 if (mwidth
== width
&& mheight
== height
) {
3288 par
->lcd_pixclock
= 100000000 / *((u16
*)(modeptr
+9));
3289 par
->lcd_htotal
= *((u16
*)(modeptr
+17)) & 511;
3290 par
->lcd_hdisp
= *((u16
*)(modeptr
+19)) & 511;
3291 lcd_hsync_start
= *((u16
*)(modeptr
+21)) & 511;
3292 par
->lcd_hsync_dly
= (*((u16
*)(modeptr
+21)) >> 9) & 7;
3293 par
->lcd_hsync_len
= *((u8
*)(modeptr
+23)) & 63;
3295 par
->lcd_vtotal
= *((u16
*)(modeptr
+24)) & 2047;
3296 par
->lcd_vdisp
= *((u16
*)(modeptr
+26)) & 2047;
3297 lcd_vsync_start
= *((u16
*)(modeptr
+28)) & 2047;
3298 par
->lcd_vsync_len
= (*((u16
*)(modeptr
+28)) >> 11) & 31;
3300 par
->lcd_htotal
= (par
->lcd_htotal
+ 1) * 8;
3301 par
->lcd_hdisp
= (par
->lcd_hdisp
+ 1) * 8;
3302 lcd_hsync_start
= (lcd_hsync_start
+ 1) * 8;
3303 par
->lcd_hsync_len
= par
->lcd_hsync_len
* 8;
3309 par
->lcd_right_margin
= lcd_hsync_start
- par
->lcd_hdisp
;
3310 par
->lcd_lower_margin
= lcd_vsync_start
- par
->lcd_vdisp
;
3311 par
->lcd_hblank_len
= par
->lcd_htotal
- par
->lcd_hdisp
;
3312 par
->lcd_vblank_len
= par
->lcd_vtotal
- par
->lcd_vdisp
;
3318 if (*lcdmodeptr
== 0) {
3319 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3320 /* To do: Switch to CRT if possible. */
3322 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3323 1000000 / par
->lcd_pixclock
, 1000000 % par
->lcd_pixclock
,
3325 par
->lcd_hdisp
+ par
->lcd_right_margin
,
3326 par
->lcd_hdisp
+ par
->lcd_right_margin
3327 + par
->lcd_hsync_dly
+ par
->lcd_hsync_len
,
3330 par
->lcd_vdisp
+ par
->lcd_lower_margin
,
3331 par
->lcd_vdisp
+ par
->lcd_lower_margin
+ par
->lcd_vsync_len
,
3333 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3335 par
->lcd_hblank_len
- (par
->lcd_right_margin
+
3336 par
->lcd_hsync_dly
+ par
->lcd_hsync_len
),
3338 par
->lcd_right_margin
,
3340 par
->lcd_vblank_len
- (par
->lcd_lower_margin
+ par
->lcd_vsync_len
),
3342 par
->lcd_lower_margin
,
3343 par
->lcd_vsync_len
);
3347 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3349 static int __devinit
init_from_bios(struct atyfb_par
*par
)
3351 u32 bios_base
, rom_addr
;
3354 rom_addr
= 0xc0000 + ((aty_ld_le32(SCRATCH_REG1
, par
) & 0x7f) << 11);
3355 bios_base
= (unsigned long)ioremap(rom_addr
, 0x10000);
3357 /* The BIOS starts with 0xaa55. */
3358 if (*((u16
*)bios_base
) == 0xaa55) {
3361 u16 rom_table_offset
, freq_table_offset
;
3362 PLL_BLOCK_MACH64 pll_block
;
3364 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr
, bios_base
);
3366 /* check for frequncy table */
3367 bios_ptr
= (u8
*)bios_base
;
3368 rom_table_offset
= (u16
)(bios_ptr
[0x48] | (bios_ptr
[0x49] << 8));
3369 freq_table_offset
= bios_ptr
[rom_table_offset
+ 16] | (bios_ptr
[rom_table_offset
+ 17] << 8);
3370 memcpy(&pll_block
, bios_ptr
+ freq_table_offset
, sizeof(PLL_BLOCK_MACH64
));
3372 PRINTKI("BIOS frequency table:\n");
3373 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3374 pll_block
.PCLK_min_freq
, pll_block
.PCLK_max_freq
,
3375 pll_block
.ref_freq
, pll_block
.ref_divider
);
3376 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3377 pll_block
.MCLK_pwd
, pll_block
.MCLK_max_freq
,
3378 pll_block
.XCLK_max_freq
, pll_block
.SCLK_freq
);
3380 par
->pll_limits
.pll_min
= pll_block
.PCLK_min_freq
/100;
3381 par
->pll_limits
.pll_max
= pll_block
.PCLK_max_freq
/100;
3382 par
->pll_limits
.ref_clk
= pll_block
.ref_freq
/100;
3383 par
->pll_limits
.ref_div
= pll_block
.ref_divider
;
3384 par
->pll_limits
.sclk
= pll_block
.SCLK_freq
/100;
3385 par
->pll_limits
.mclk
= pll_block
.MCLK_max_freq
/100;
3386 par
->pll_limits
.mclk_pm
= pll_block
.MCLK_pwd
/100;
3387 par
->pll_limits
.xclk
= pll_block
.XCLK_max_freq
/100;
3388 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3389 aty_init_lcd(par
, bios_base
);
3393 PRINTKE("no BIOS frequency table found, use parameters\n");
3396 iounmap((void* __iomem
)bios_base
);
3400 #endif /* __i386__ */
3402 static int __devinit
atyfb_setup_generic(struct pci_dev
*pdev
, struct fb_info
*info
, unsigned long addr
)
3404 struct atyfb_par
*par
= info
->par
;
3406 unsigned long raddr
;
3407 struct resource
*rrp
;
3410 raddr
= addr
+ 0x7ff000UL
;
3411 rrp
= &pdev
->resource
[2];
3412 if ((rrp
->flags
& IORESOURCE_MEM
) && request_mem_region(rrp
->start
, rrp
->end
- rrp
->start
+ 1, "atyfb")) {
3413 par
->aux_start
= rrp
->start
;
3414 par
->aux_size
= rrp
->end
- rrp
->start
+ 1;
3416 PRINTKI("using auxiliary register aperture\n");
3419 info
->fix
.mmio_start
= raddr
;
3420 par
->ati_regbase
= ioremap(info
->fix
.mmio_start
, 0x1000);
3421 if (par
->ati_regbase
== 0)
3424 info
->fix
.mmio_start
+= par
->aux_start
? 0x400 : 0xc00;
3425 par
->ati_regbase
+= par
->aux_start
? 0x400 : 0xc00;
3428 * Enable memory-space accesses using config-space
3431 pci_read_config_word(pdev
, PCI_COMMAND
, &tmp
);
3432 if (!(tmp
& PCI_COMMAND_MEMORY
)) {
3433 tmp
|= PCI_COMMAND_MEMORY
;
3434 pci_write_config_word(pdev
, PCI_COMMAND
, tmp
);
3437 /* Use the big-endian aperture */
3441 /* Map in frame buffer */
3442 info
->fix
.smem_start
= addr
;
3443 info
->screen_base
= ioremap(addr
, 0x800000);
3444 if (info
->screen_base
== NULL
) {
3446 goto atyfb_setup_generic_fail
;
3449 if((ret
= correct_chipset(par
)))
3450 goto atyfb_setup_generic_fail
;
3452 if((ret
= init_from_bios(par
)))
3453 goto atyfb_setup_generic_fail
;
3455 if (!(aty_ld_le32(CRTC_GEN_CNTL
, par
) & CRTC_EXT_DISP_EN
))
3456 par
->clk_wr_offset
= (inb(R_GENMO
) & 0x0CU
) >> 2;
3458 par
->clk_wr_offset
= aty_ld_8(CLOCK_CNTL
, par
) & 0x03U
;
3460 /* according to ATI, we should use clock 3 for acelerated mode */
3461 par
->clk_wr_offset
= 3;
3465 atyfb_setup_generic_fail
:
3466 iounmap(par
->ati_regbase
);
3467 par
->ati_regbase
= NULL
;
3468 if (info
->screen_base
) {
3469 iounmap(info
->screen_base
);
3470 info
->screen_base
= NULL
;
3475 #endif /* !__sparc__ */
3477 static int __devinit
atyfb_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3479 unsigned long addr
, res_start
, res_size
;
3480 struct fb_info
*info
;
3481 struct resource
*rp
;
3482 struct atyfb_par
*par
;
3483 int i
, rc
= -ENOMEM
;
3485 for (i
= ARRAY_SIZE(aty_chips
) - 1; i
>= 0; i
--)
3486 if (pdev
->device
== aty_chips
[i
].pci_id
)
3492 /* Enable device in PCI config */
3493 if (pci_enable_device(pdev
)) {
3494 PRINTKE("Cannot enable PCI device\n");
3498 /* Find which resource to use */
3499 rp
= &pdev
->resource
[0];
3500 if (rp
->flags
& IORESOURCE_IO
)
3501 rp
= &pdev
->resource
[1];
3507 res_start
= rp
->start
;
3508 res_size
= rp
->end
- rp
->start
+ 1;
3509 if (!request_mem_region (res_start
, res_size
, "atyfb"))
3512 /* Allocate framebuffer */
3513 info
= framebuffer_alloc(sizeof(struct atyfb_par
), &pdev
->dev
);
3515 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3519 info
->fix
= atyfb_fix
;
3520 info
->device
= &pdev
->dev
;
3521 par
->pci_id
= aty_chips
[i
].pci_id
;
3522 par
->res_start
= res_start
;
3523 par
->res_size
= res_size
;
3524 par
->irq
= pdev
->irq
;
3527 /* Setup "info" structure */
3529 rc
= atyfb_setup_sparc(pdev
, info
, addr
);
3531 rc
= atyfb_setup_generic(pdev
, info
, addr
);
3534 goto err_release_mem
;
3536 pci_set_drvdata(pdev
, info
);
3538 /* Init chip & register framebuffer */
3540 goto err_release_io
;
3544 prom_palette
= atyfb_palette
;
3547 * Add /dev/fb mmap values.
3549 par
->mmap_map
[0].voff
= 0x8000000000000000UL
;
3550 par
->mmap_map
[0].poff
= (unsigned long) info
->screen_base
& PAGE_MASK
;
3551 par
->mmap_map
[0].size
= info
->fix
.smem_len
;
3552 par
->mmap_map
[0].prot_mask
= _PAGE_CACHE
;
3553 par
->mmap_map
[0].prot_flag
= _PAGE_E
;
3554 par
->mmap_map
[1].voff
= par
->mmap_map
[0].voff
+ info
->fix
.smem_len
;
3555 par
->mmap_map
[1].poff
= (long)par
->ati_regbase
& PAGE_MASK
;
3556 par
->mmap_map
[1].size
= PAGE_SIZE
;
3557 par
->mmap_map
[1].prot_mask
= _PAGE_CACHE
;
3558 par
->mmap_map
[1].prot_flag
= _PAGE_E
;
3559 #endif /* __sparc__ */
3565 kfree(par
->mmap_map
);
3567 if (par
->ati_regbase
)
3568 iounmap(par
->ati_regbase
);
3569 if (info
->screen_base
)
3570 iounmap(info
->screen_base
);
3574 release_mem_region(par
->aux_start
, par
->aux_size
);
3576 release_mem_region(par
->res_start
, par
->res_size
);
3577 framebuffer_release(info
);
3582 #endif /* CONFIG_PCI */
3586 static int __init
atyfb_atari_probe(void)
3588 struct atyfb_par
*par
;
3589 struct fb_info
*info
;
3594 for (m64_num
= 0; m64_num
< mach64_count
; m64_num
++) {
3595 if (!phys_vmembase
[m64_num
] || !phys_size
[m64_num
] ||
3596 !phys_guiregbase
[m64_num
]) {
3597 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num
);
3601 info
= framebuffer_alloc(sizeof(struct atyfb_par
), NULL
);
3603 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3608 info
->fix
= atyfb_fix
;
3610 par
->irq
= (unsigned int) -1; /* something invalid */
3613 * Map the video memory (physical address given) to somewhere in the
3614 * kernel address space.
3616 info
->screen_base
= ioremap(phys_vmembase
[m64_num
], phys_size
[m64_num
]);
3617 info
->fix
.smem_start
= (unsigned long)info
->screen_base
; /* Fake! */
3618 par
->ati_regbase
= ioremap(phys_guiregbase
[m64_num
], 0x10000) +
3620 info
->fix
.mmio_start
= (unsigned long)par
->ati_regbase
; /* Fake! */
3622 aty_st_le32(CLOCK_CNTL
, 0x12345678, par
);
3623 clock_r
= aty_ld_le32(CLOCK_CNTL
, par
);
3625 switch (clock_r
& 0x003F) {
3627 par
->clk_wr_offset
= 3; /* */
3630 par
->clk_wr_offset
= 2; /* Medusa ST-IO ISA Adapter etc. */
3633 par
->clk_wr_offset
= 1; /* */
3636 par
->clk_wr_offset
= 0; /* Panther 1 ISA Adapter (Gerald) */
3640 /* Fake pci_id for correct_chipset() */
3641 switch (aty_ld_le32(CONFIG_CHIP_ID
, par
) & CFG_CHIP_TYPE
) {
3643 par
->pci_id
= PCI_CHIP_MACH64GX
;
3646 par
->pci_id
= PCI_CHIP_MACH64CX
;
3652 if (correct_chipset(par
) || aty_init(info
)) {
3653 iounmap(info
->screen_base
);
3654 iounmap(par
->ati_regbase
);
3655 framebuffer_release(info
);
3661 return num_found
? 0 : -ENXIO
;
3664 #endif /* CONFIG_ATARI */
3668 static void __devexit
atyfb_remove(struct fb_info
*info
)
3670 struct atyfb_par
*par
= (struct atyfb_par
*) info
->par
;
3672 /* restore video mode */
3673 aty_set_crtc(par
, &saved_crtc
);
3674 par
->pll_ops
->set_pll(info
, &saved_pll
);
3676 unregister_framebuffer(info
);
3678 #ifdef CONFIG_FB_ATY_BACKLIGHT
3679 if (M64_HAS(MOBIL_BUS
))
3680 aty_bl_exit(info
->bl_dev
);
3684 if (par
->mtrr_reg
>= 0) {
3685 mtrr_del(par
->mtrr_reg
, 0, 0);
3688 if (par
->mtrr_aper
>= 0) {
3689 mtrr_del(par
->mtrr_aper
, 0, 0);
3690 par
->mtrr_aper
= -1;
3694 if (par
->ati_regbase
)
3695 iounmap(par
->ati_regbase
);
3696 if (info
->screen_base
)
3697 iounmap(info
->screen_base
);
3699 if (info
->sprite
.addr
)
3700 iounmap(info
->sprite
.addr
);
3704 kfree(par
->mmap_map
);
3707 release_mem_region(par
->aux_start
, par
->aux_size
);
3710 release_mem_region(par
->res_start
, par
->res_size
);
3712 framebuffer_release(info
);
3716 static void __devexit
atyfb_pci_remove(struct pci_dev
*pdev
)
3718 struct fb_info
*info
= pci_get_drvdata(pdev
);
3724 * This driver uses its own matching table. That will be more difficult
3725 * to fix, so for now, we just match against any ATI ID and let the
3726 * probe() function find out what's up. That also mean we don't have
3727 * a module ID table though.
3729 static struct pci_device_id atyfb_pci_tbl
[] = {
3730 { PCI_VENDOR_ID_ATI
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
3731 PCI_BASE_CLASS_DISPLAY
<< 16, 0xff0000, 0 },
3735 static struct pci_driver atyfb_driver
= {
3737 .id_table
= atyfb_pci_tbl
,
3738 .probe
= atyfb_pci_probe
,
3739 .remove
= __devexit_p(atyfb_pci_remove
),
3741 .suspend
= atyfb_pci_suspend
,
3742 .resume
= atyfb_pci_resume
,
3743 #endif /* CONFIG_PM */
3746 #endif /* CONFIG_PCI */
3749 static int __init
atyfb_setup(char *options
)
3753 if (!options
|| !*options
)
3756 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
3757 if (!strncmp(this_opt
, "noaccel", 7)) {
3760 } else if (!strncmp(this_opt
, "nomtrr", 6)) {
3763 } else if (!strncmp(this_opt
, "vram:", 5))
3764 vram
= simple_strtoul(this_opt
+ 5, NULL
, 0);
3765 else if (!strncmp(this_opt
, "pll:", 4))
3766 pll
= simple_strtoul(this_opt
+ 4, NULL
, 0);
3767 else if (!strncmp(this_opt
, "mclk:", 5))
3768 mclk
= simple_strtoul(this_opt
+ 5, NULL
, 0);
3769 else if (!strncmp(this_opt
, "xclk:", 5))
3770 xclk
= simple_strtoul(this_opt
+5, NULL
, 0);
3771 else if (!strncmp(this_opt
, "comp_sync:", 10))
3772 comp_sync
= simple_strtoul(this_opt
+10, NULL
, 0);
3773 else if (!strncmp(this_opt
, "backlight:", 10))
3774 backlight
= simple_strtoul(this_opt
+10, NULL
, 0);
3776 else if (!strncmp(this_opt
, "vmode:", 6)) {
3777 unsigned int vmode
=
3778 simple_strtoul(this_opt
+ 6, NULL
, 0);
3779 if (vmode
> 0 && vmode
<= VMODE_MAX
)
3780 default_vmode
= vmode
;
3781 } else if (!strncmp(this_opt
, "cmode:", 6)) {
3782 unsigned int cmode
=
3783 simple_strtoul(this_opt
+ 6, NULL
, 0);
3787 default_cmode
= CMODE_8
;
3791 default_cmode
= CMODE_16
;
3795 default_cmode
= CMODE_32
;
3802 * Why do we need this silly Mach64 argument?
3803 * We are already here because of mach64= so its redundant.
3805 else if (MACH_IS_ATARI
3806 && (!strncmp(this_opt
, "Mach64:", 7))) {
3807 static unsigned char m64_num
;
3808 static char mach64_str
[80];
3809 strlcpy(mach64_str
, this_opt
+ 7, sizeof(mach64_str
));
3810 if (!store_video_par(mach64_str
, m64_num
)) {
3812 mach64_count
= m64_num
;
3823 static int __init
atyfb_init(void)
3825 int err1
= 1, err2
= 1;
3827 char *option
= NULL
;
3829 if (fb_get_options("atyfb", &option
))
3831 atyfb_setup(option
);
3835 err1
= pci_register_driver(&atyfb_driver
);
3838 err2
= atyfb_atari_probe();
3841 return (err1
&& err2
) ? -ENODEV
: 0;
3844 static void __exit
atyfb_exit(void)
3847 pci_unregister_driver(&atyfb_driver
);
3851 module_init(atyfb_init
);
3852 module_exit(atyfb_exit
);
3854 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3855 MODULE_LICENSE("GPL");
3856 module_param(noaccel
, bool, 0);
3857 MODULE_PARM_DESC(noaccel
, "bool: disable acceleration");
3858 module_param(vram
, int, 0);
3859 MODULE_PARM_DESC(vram
, "int: override size of video ram");
3860 module_param(pll
, int, 0);
3861 MODULE_PARM_DESC(pll
, "int: override video clock");
3862 module_param(mclk
, int, 0);
3863 MODULE_PARM_DESC(mclk
, "int: override memory clock");
3864 module_param(xclk
, int, 0);
3865 MODULE_PARM_DESC(xclk
, "int: override accelerated engine clock");
3866 module_param(comp_sync
, int, 0);
3867 MODULE_PARM_DESC(comp_sync
,
3868 "Set composite sync signal to low (0) or high (1)");
3869 module_param(mode
, charp
, 0);
3870 MODULE_PARM_DESC(mode
, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3872 module_param(nomtrr
, bool, 0);
3873 MODULE_PARM_DESC(nomtrr
, "bool: disable use of MTRR registers");