projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
video: bf54x-lq043fb: fix build error
[deliverable/linux.git] / drivers / video / aty / radeon_pm.c
1 /*
2 * drivers/video/aty/radeon_pm.c
3 *
4 * Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
5 * Copyright 2004 Paul Mackerras <paulus@samba.org>
6 *
7 * This is the power management code for ATI radeon chipsets. It contains
8 * some dynamic clock PM enable/disable code similar to what X.org does,
9 * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
10 * and the necessary bits to re-initialize from scratch a few chips found
11 * on PowerMacs as well. The later could be extended to more platforms
12 * provided the memory controller configuration code be made more generic,
13 * and you can get the proper mode register commands for your RAMs.
14 * Those things may be found in the BIOS image...
15 */
16
17 #include "radeonfb.h"
18
19 #include <linux/console.h>
20 #include <linux/agp_backend.h>
21
22 #ifdef CONFIG_PPC_PMAC
23 #include <asm/machdep.h>
24 #include <asm/prom.h>
25 #include <asm/pmac_feature.h>
26 #endif
27
28 #include "ati_ids.h"
29
30 /*
31 * Workarounds for bugs in PC laptops:
32 * - enable D2 sleep in some IBM Thinkpads
33 * - special case for Samsung P35
34 *
35 * Whitelist by subsystem vendor/device because
36 * its the subsystem vendor's fault!
37 */
38
39 #if defined(CONFIG_PM) && defined(CONFIG_X86)
40 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo);
41
42 struct radeon_device_id {
43 const char *ident; /* (arbitrary) Name */
44 const unsigned short subsystem_vendor; /* Subsystem Vendor ID */
45 const unsigned short subsystem_device; /* Subsystem Device ID */
46 const enum radeon_pm_mode pm_mode_modifier; /* modify pm_mode */
47 const reinit_function_ptr new_reinit_func; /* changed reinit_func */
48 };
49
50 #define BUGFIX(model, sv, sd, pm, fn) { \
51 .ident = model, \
52 .subsystem_vendor = sv, \
53 .subsystem_device = sd, \
54 .pm_mode_modifier = pm, \
55 .new_reinit_func = fn \
56 }
57
58 static struct radeon_device_id radeon_workaround_list[] = {
59 BUGFIX("IBM Thinkpad R32",
60 PCI_VENDOR_ID_IBM, 0x1905,
61 radeon_pm_d2, NULL),
62 BUGFIX("IBM Thinkpad R40",
63 PCI_VENDOR_ID_IBM, 0x0526,
64 radeon_pm_d2, NULL),
65 BUGFIX("IBM Thinkpad R40",
66 PCI_VENDOR_ID_IBM, 0x0527,
67 radeon_pm_d2, NULL),
68 BUGFIX("IBM Thinkpad R50/R51/T40/T41",
69 PCI_VENDOR_ID_IBM, 0x0531,
70 radeon_pm_d2, NULL),
71 BUGFIX("IBM Thinkpad R51/T40/T41/T42",
72 PCI_VENDOR_ID_IBM, 0x0530,
73 radeon_pm_d2, NULL),
74 BUGFIX("IBM Thinkpad T30",
75 PCI_VENDOR_ID_IBM, 0x0517,
76 radeon_pm_d2, NULL),
77 BUGFIX("IBM Thinkpad T40p",
78 PCI_VENDOR_ID_IBM, 0x054d,
79 radeon_pm_d2, NULL),
80 BUGFIX("IBM Thinkpad T42",
81 PCI_VENDOR_ID_IBM, 0x0550,
82 radeon_pm_d2, NULL),
83 BUGFIX("IBM Thinkpad X31/X32",
84 PCI_VENDOR_ID_IBM, 0x052f,
85 radeon_pm_d2, NULL),
86 BUGFIX("Samsung P35",
87 PCI_VENDOR_ID_SAMSUNG, 0xc00c,
88 radeon_pm_off, radeon_reinitialize_M10),
89 BUGFIX("Acer Aspire 2010",
90 PCI_VENDOR_ID_AI, 0x0061,
91 radeon_pm_off, radeon_reinitialize_M10),
92 BUGFIX("Acer Travelmate 290D/292LMi",
93 PCI_VENDOR_ID_AI, 0x005a,
94 radeon_pm_off, radeon_reinitialize_M10),
95 { .ident = NULL }
96 };
97
98 static int radeon_apply_workarounds(struct radeonfb_info *rinfo)
99 {
100 struct radeon_device_id *id;
101
102 for (id = radeon_workaround_list; id->ident != NULL; id++ )
103 if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) &&
104 (id->subsystem_device == rinfo->pdev->subsystem_device )) {
105
106 /* we found a device that requires workaround */
107 printk(KERN_DEBUG "radeonfb: %s detected"
108 ", enabling workaround\n", id->ident);
109
110 rinfo->pm_mode |= id->pm_mode_modifier;
111
112 if (id->new_reinit_func != NULL)
113 rinfo->reinit_func = id->new_reinit_func;
114
115 return 1;
116 }
117 return 0; /* not found */
118 }
119
120 #else /* defined(CONFIG_PM) && defined(CONFIG_X86) */
121 static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo)
122 {
123 return 0;
124 }
125 #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
126
127
128
129 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
130 {
131 u32 tmp;
132
133 /* RV100 */
134 if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
135 if (rinfo->has_CRTC2) {
136 tmp = INPLL(pllSCLK_CNTL);
137 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
138 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
139 OUTPLL(pllSCLK_CNTL, tmp);
140 }
141 tmp = INPLL(pllMCLK_CNTL);
142 tmp |= (MCLK_CNTL__FORCE_MCLKA |
143 MCLK_CNTL__FORCE_MCLKB |
144 MCLK_CNTL__FORCE_YCLKA |
145 MCLK_CNTL__FORCE_YCLKB |
146 MCLK_CNTL__FORCE_AIC |
147 MCLK_CNTL__FORCE_MC);
148 OUTPLL(pllMCLK_CNTL, tmp);
149 return;
150 }
151 /* R100 */
152 if (!rinfo->has_CRTC2) {
153 tmp = INPLL(pllSCLK_CNTL);
154 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP |
155 SCLK_CNTL__FORCE_DISP1 | SCLK_CNTL__FORCE_TOP |
156 SCLK_CNTL__FORCE_E2 | SCLK_CNTL__FORCE_SE |
157 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_VIP |
158 SCLK_CNTL__FORCE_RE | SCLK_CNTL__FORCE_PB |
159 SCLK_CNTL__FORCE_TAM | SCLK_CNTL__FORCE_TDM |
160 SCLK_CNTL__FORCE_RB);
161 OUTPLL(pllSCLK_CNTL, tmp);
162 return;
163 }
164 /* RV350 (M10/M11) */
165 if (rinfo->family == CHIP_FAMILY_RV350) {
166 /* for RV350/M10/M11, no delays are required. */
167 tmp = INPLL(pllSCLK_CNTL2);
168 tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
169 SCLK_CNTL2__R300_FORCE_GA |
170 SCLK_CNTL2__R300_FORCE_CBA);
171 OUTPLL(pllSCLK_CNTL2, tmp);
172
173 tmp = INPLL(pllSCLK_CNTL);
174 tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
175 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
176 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
177 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
178 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
179 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
180 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
181 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
182 OUTPLL(pllSCLK_CNTL, tmp);
183
184 tmp = INPLL(pllSCLK_MORE_CNTL);
185 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI |
186 SCLK_MORE_CNTL__FORCE_MC_HOST);
187 OUTPLL(pllSCLK_MORE_CNTL, tmp);
188
189 tmp = INPLL(pllMCLK_CNTL);
190 tmp |= (MCLK_CNTL__FORCE_MCLKA |
191 MCLK_CNTL__FORCE_MCLKB |
192 MCLK_CNTL__FORCE_YCLKA |
193 MCLK_CNTL__FORCE_YCLKB |
194 MCLK_CNTL__FORCE_MC);
195 OUTPLL(pllMCLK_CNTL, tmp);
196
197 tmp = INPLL(pllVCLK_ECP_CNTL);
198 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
199 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
200 VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
201 OUTPLL(pllVCLK_ECP_CNTL, tmp);
202
203 tmp = INPLL(pllPIXCLKS_CNTL);
204 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
205 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
206 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
207 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
208 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
209 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
210 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
211 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
212 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
213 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
214 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
215 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
216 PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
217 OUTPLL(pllPIXCLKS_CNTL, tmp);
218
219 return;
220 }
221
222 /* Default */
223
224 /* Force Core Clocks */
225 tmp = INPLL(pllSCLK_CNTL);
226 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
227
228 /* XFree doesn't do that case, but we had this code from Apple and it
229 * seem necessary for proper suspend/resume operations
230 */
231 if (rinfo->is_mobility) {
232 tmp |= SCLK_CNTL__FORCE_HDP|
233 SCLK_CNTL__FORCE_DISP1|
234 SCLK_CNTL__FORCE_DISP2|
235 SCLK_CNTL__FORCE_TOP|
236 SCLK_CNTL__FORCE_SE|
237 SCLK_CNTL__FORCE_IDCT|
238 SCLK_CNTL__FORCE_VIP|
239 SCLK_CNTL__FORCE_PB|
240 SCLK_CNTL__FORCE_RE|
241 SCLK_CNTL__FORCE_TAM|
242 SCLK_CNTL__FORCE_TDM|
243 SCLK_CNTL__FORCE_RB|
244 SCLK_CNTL__FORCE_TV_SCLK|
245 SCLK_CNTL__FORCE_SUBPIC|
246 SCLK_CNTL__FORCE_OV0;
247 }
248 else if (rinfo->family == CHIP_FAMILY_R300 ||
249 rinfo->family == CHIP_FAMILY_R350) {
250 tmp |= SCLK_CNTL__FORCE_HDP |
251 SCLK_CNTL__FORCE_DISP1 |
252 SCLK_CNTL__FORCE_DISP2 |
253 SCLK_CNTL__FORCE_TOP |
254 SCLK_CNTL__FORCE_IDCT |
255 SCLK_CNTL__FORCE_VIP;
256 }
257 OUTPLL(pllSCLK_CNTL, tmp);
258 radeon_msleep(16);
259
260 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
261 tmp = INPLL(pllSCLK_CNTL2);
262 tmp |= SCLK_CNTL2__R300_FORCE_TCL |
263 SCLK_CNTL2__R300_FORCE_GA |
264 SCLK_CNTL2__R300_FORCE_CBA;
265 OUTPLL(pllSCLK_CNTL2, tmp);
266 radeon_msleep(16);
267 }
268
269 tmp = INPLL(pllCLK_PIN_CNTL);
270 tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
271 OUTPLL(pllCLK_PIN_CNTL, tmp);
272 radeon_msleep(15);
273
274 if (rinfo->is_IGP) {
275 /* Weird ... X is _un_ forcing clocks here, I think it's
276 * doing backward. Imitate it for now...
277 */
278 tmp = INPLL(pllMCLK_CNTL);
279 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
280 MCLK_CNTL__FORCE_YCLKA);
281 OUTPLL(pllMCLK_CNTL, tmp);
282 radeon_msleep(16);
283 }
284 /* Hrm... same shit, X doesn't do that but I have to */
285 else if (rinfo->is_mobility) {
286 tmp = INPLL(pllMCLK_CNTL);
287 tmp |= (MCLK_CNTL__FORCE_MCLKA |
288 MCLK_CNTL__FORCE_MCLKB |
289 MCLK_CNTL__FORCE_YCLKA |
290 MCLK_CNTL__FORCE_YCLKB);
291 OUTPLL(pllMCLK_CNTL, tmp);
292 radeon_msleep(16);
293
294 tmp = INPLL(pllMCLK_MISC);
295 tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
296 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
297 MCLK_MISC__MC_MCLK_DYN_ENABLE|
298 MCLK_MISC__IO_MCLK_DYN_ENABLE);
299 OUTPLL(pllMCLK_MISC, tmp);
300 radeon_msleep(15);
301 }
302
303 if (rinfo->is_mobility) {
304 tmp = INPLL(pllSCLK_MORE_CNTL);
305 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS|
306 SCLK_MORE_CNTL__FORCE_MC_GUI|
307 SCLK_MORE_CNTL__FORCE_MC_HOST;
308 OUTPLL(pllSCLK_MORE_CNTL, tmp);
309 radeon_msleep(16);
310 }
311
312 tmp = INPLL(pllPIXCLKS_CNTL);
313 tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
314 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
315 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
316 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
317 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
318 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
319 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
320 OUTPLL(pllPIXCLKS_CNTL, tmp);
321 radeon_msleep(16);
322
323 tmp = INPLL( pllVCLK_ECP_CNTL);
324 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
325 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
326 OUTPLL( pllVCLK_ECP_CNTL, tmp);
327 radeon_msleep(16);
328 }
329
330 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
331 {
332 u32 tmp;
333
334 /* R100 */
335 if (!rinfo->has_CRTC2) {
336 tmp = INPLL(pllSCLK_CNTL);
337
338 if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
339 tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB);
340 tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
341 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE |
342 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_RE |
343 SCLK_CNTL__FORCE_PB | SCLK_CNTL__FORCE_TAM |
344 SCLK_CNTL__FORCE_TDM);
345 OUTPLL(pllSCLK_CNTL, tmp);
346 return;
347 }
348
349 /* M10/M11 */
350 if (rinfo->family == CHIP_FAMILY_RV350) {
351 tmp = INPLL(pllSCLK_CNTL2);
352 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
353 SCLK_CNTL2__R300_FORCE_GA |
354 SCLK_CNTL2__R300_FORCE_CBA);
355 tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
356 SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT |
357 SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
358 OUTPLL(pllSCLK_CNTL2, tmp);
359
360 tmp = INPLL(pllSCLK_CNTL);
361 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
362 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
363 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
364 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
365 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
366 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
367 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
368 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
369 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
370 OUTPLL(pllSCLK_CNTL, tmp);
371
372 tmp = INPLL(pllSCLK_MORE_CNTL);
373 tmp &= ~SCLK_MORE_CNTL__FORCEON;
374 tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
375 SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
376 SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
377 OUTPLL(pllSCLK_MORE_CNTL, tmp);
378
379 tmp = INPLL(pllVCLK_ECP_CNTL);
380 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
381 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
382 OUTPLL(pllVCLK_ECP_CNTL, tmp);
383
384 tmp = INPLL(pllPIXCLKS_CNTL);
385 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
386 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
387 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
388 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
389 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
390 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
391 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
392 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
393 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
394 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
395 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
396 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
397 PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb);
398 OUTPLL(pllPIXCLKS_CNTL, tmp);
399
400 tmp = INPLL(pllMCLK_MISC);
401 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
402 MCLK_MISC__IO_MCLK_DYN_ENABLE);
403 OUTPLL(pllMCLK_MISC, tmp);
404
405 tmp = INPLL(pllMCLK_CNTL);
406 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
407 tmp &= ~(MCLK_CNTL__FORCE_YCLKA |
408 MCLK_CNTL__FORCE_YCLKB |
409 MCLK_CNTL__FORCE_MC);
410
411 /* Some releases of vbios have set DISABLE_MC_MCLKA
412 * and DISABLE_MC_MCLKB bits in the vbios table. Setting these
413 * bits will cause H/W hang when reading video memory with dynamic
414 * clocking enabled.
415 */
416 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
417 (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
418 /* If both bits are set, then check the active channels */
419 tmp = INPLL(pllMCLK_CNTL);
420 if (rinfo->vram_width == 64) {
421 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
422 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
423 else
424 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
425 } else {
426 tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
427 MCLK_CNTL__R300_DISABLE_MC_MCLKB);
428 }
429 }
430 OUTPLL(pllMCLK_CNTL, tmp);
431 return;
432 }
433
434 /* R300 */
435 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
436 tmp = INPLL(pllSCLK_CNTL);
437 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
438 tmp |= SCLK_CNTL__FORCE_CP;
439 OUTPLL(pllSCLK_CNTL, tmp);
440 radeon_msleep(15);
441
442 tmp = INPLL(pllSCLK_CNTL2);
443 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
444 SCLK_CNTL2__R300_FORCE_GA |
445 SCLK_CNTL2__R300_FORCE_CBA);
446 OUTPLL(pllSCLK_CNTL2, tmp);
447 }
448
449 /* Others */
450
451 tmp = INPLL( pllCLK_PWRMGT_CNTL);
452 tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
453 CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
454 CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
455 tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
456 (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
457 OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
458 radeon_msleep(15);
459
460 tmp = INPLL(pllCLK_PIN_CNTL);
461 tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
462 OUTPLL(pllCLK_PIN_CNTL, tmp);
463 radeon_msleep(15);
464
465 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
466 * to lockup randomly, leave them as set by BIOS.
467 */
468 tmp = INPLL(pllSCLK_CNTL);
469 tmp &= ~SCLK_CNTL__FORCEON_MASK;
470
471 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
472 if ((rinfo->family == CHIP_FAMILY_RV250 &&
473 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
474 ((rinfo->family == CHIP_FAMILY_RV100) &&
475 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
476 tmp |= SCLK_CNTL__FORCE_CP;
477 tmp |= SCLK_CNTL__FORCE_VIP;
478 }
479 OUTPLL(pllSCLK_CNTL, tmp);
480 radeon_msleep(15);
481
482 if ((rinfo->family == CHIP_FAMILY_RV200) ||
483 (rinfo->family == CHIP_FAMILY_RV250) ||
484 (rinfo->family == CHIP_FAMILY_RV280)) {
485 tmp = INPLL(pllSCLK_MORE_CNTL);
486 tmp &= ~SCLK_MORE_CNTL__FORCEON;
487
488 /* RV200::A11 A12 RV250::A11 A12 */
489 if (((rinfo->family == CHIP_FAMILY_RV200) ||
490 (rinfo->family == CHIP_FAMILY_RV250)) &&
491 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
492 tmp |= SCLK_MORE_CNTL__FORCEON;
493
494 OUTPLL(pllSCLK_MORE_CNTL, tmp);
495 radeon_msleep(15);
496 }
497
498
499 /* RV200::A11 A12, RV250::A11 A12 */
500 if (((rinfo->family == CHIP_FAMILY_RV200) ||
501 (rinfo->family == CHIP_FAMILY_RV250)) &&
502 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
503 tmp = INPLL(pllPLL_PWRMGT_CNTL);
504 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
505 OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
506 radeon_msleep(15);
507 }
508
509 tmp = INPLL(pllPIXCLKS_CNTL);
510 tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
511 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
512 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
513 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
514 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
515 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
516 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
517 OUTPLL(pllPIXCLKS_CNTL, tmp);
518 radeon_msleep(15);
519
520 tmp = INPLL(pllVCLK_ECP_CNTL);
521 tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
522 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
523 OUTPLL(pllVCLK_ECP_CNTL, tmp);
524
525 /* X doesn't do that ... hrm, we do on mobility && Macs */
526 #ifdef CONFIG_PPC_OF
527 if (rinfo->is_mobility) {
528 tmp = INPLL(pllMCLK_CNTL);
529 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
530 MCLK_CNTL__FORCE_MCLKB |
531 MCLK_CNTL__FORCE_YCLKA |
532 MCLK_CNTL__FORCE_YCLKB);
533 OUTPLL(pllMCLK_CNTL, tmp);
534 radeon_msleep(15);
535
536 tmp = INPLL(pllMCLK_MISC);
537 tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
538 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
539 MCLK_MISC__MC_MCLK_DYN_ENABLE|
540 MCLK_MISC__IO_MCLK_DYN_ENABLE;
541 OUTPLL(pllMCLK_MISC, tmp);
542 radeon_msleep(15);
543 }
544 #endif /* CONFIG_PPC_OF */
545 }
546
547 #ifdef CONFIG_PM
548
549 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
550 {
551 OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
552 OUTREG( MC_IND_DATA, value);
553 }
554
555 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
556 {
557 OUTREG( MC_IND_INDEX, indx);
558 return INREG( MC_IND_DATA);
559 }
560
561 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
562 {
563 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
564 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
565 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
566 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
567 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
568 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
569 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
570 rinfo->save_regs[7] = INPLL(MCLK_MISC);
571 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
572
573 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
574 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
575 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
576 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
577 rinfo->save_regs[14] = INREG(BUS_CNTL1);
578 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
579 rinfo->save_regs[16] = INREG(AGP_CNTL);
580 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
581 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
582 rinfo->save_regs[19] = INREG(GPIOPAD_A);
583 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
584 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
585 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
586 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
587 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
588 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
589 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
590 rinfo->save_regs[27] = INREG(GPIO_MONID);
591 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
592
593 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
594 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
595 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
596 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
597 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
598
599 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
600 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
601 rinfo->save_regs[36] = INREG(BUS_CNTL);
602 rinfo->save_regs[39] = INREG(RBBM_CNTL);
603 rinfo->save_regs[40] = INREG(DAC_CNTL);
604 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
605 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
606 rinfo->save_regs[38] = INREG(FCP_CNTL);
607
608 if (rinfo->is_mobility) {
609 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
610 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
611 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
612 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
613 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
614 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
615 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
616 }
617
618 if (rinfo->family >= CHIP_FAMILY_RV200) {
619 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
620 rinfo->save_regs[46] = INREG(MC_CNTL);
621 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
622 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
623 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
624 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
625 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
626 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
627 rinfo->save_regs[53] = INREG(MC_DEBUG);
628 }
629 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
630 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
631 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
632 rinfo->save_regs[57] = INREG(FW_CNTL);
633
634 if (rinfo->family >= CHIP_FAMILY_R300) {
635 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
636 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
637 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
638 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
639 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
640 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
641 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
642 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
643 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
644 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
645 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
646 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
647 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
648 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
649 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
650 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
651 } else {
652 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
653 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
654 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
655 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
656 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
657 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
658 }
659
660 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
661 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
662 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
663 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
664 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
665 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
666 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
667
668 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
669 rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
670 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
671 rinfo->save_regs[84] = INREG(TMDS_CNTL);
672 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
673 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
674 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
675 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
676 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
677 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
678 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
679 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
680 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
681 rinfo->save_regs[96] = INREG(HDP_DEBUG);
682 rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
683 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
684 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
685 }
686
687 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
688 {
689 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
690
691 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
692 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
693 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
694 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
695 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
696 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
697 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
698 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
699 if (rinfo->family == CHIP_FAMILY_RV350)
700 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
701
702 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
703 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
704 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
705 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
706 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
707 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
708
709 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
710 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
711 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
712 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
713 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
714 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
715 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
716 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
717 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
718 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
719 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
720
721 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
722 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
723 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
724 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
725 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
726 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
727 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
728 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
729 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
730 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
731 }
732
733 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
734 {
735 OUTREG(GPIOPAD_MASK, 0x0001ffff);
736 OUTREG(GPIOPAD_EN, 0x00000400);
737 OUTREG(GPIOPAD_A, 0x00000000);
738 OUTREG(ZV_LCDPAD_MASK, 0x00000000);
739 OUTREG(ZV_LCDPAD_EN, 0x00000000);
740 OUTREG(ZV_LCDPAD_A, 0x00000000);
741 OUTREG(GPIO_VGA_DDC, 0x00030000);
742 OUTREG(GPIO_DVI_DDC, 0x00000000);
743 OUTREG(GPIO_MONID, 0x00030000);
744 OUTREG(GPIO_CRT2_DDC, 0x00000000);
745 }
746
747 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
748 {
749 /* Set v2clk to 65MHz */
750 if (rinfo->family <= CHIP_FAMILY_RV280) {
751 OUTPLL(pllPIXCLKS_CNTL,
752 __INPLL(rinfo, pllPIXCLKS_CNTL)
753 & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
754
755 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
756 OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
757 } else {
758 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
759 INPLL(pllP2PLL_REF_DIV);
760 OUTPLL(pllP2PLL_CNTL, 0x0000a700);
761 }
762
763 OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
764
765 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
766 mdelay(1);
767
768 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
769 mdelay( 1);
770
771 OUTPLL(pllPIXCLKS_CNTL,
772 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
773 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
774 mdelay( 1);
775 }
776
777 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
778 {
779 u32 reg;
780
781 reg = INREG(BUS_CNTL1);
782 if (rinfo->family <= CHIP_FAMILY_RV280) {
783 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
784 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
785 } else {
786 reg |= 0x4080;
787 }
788 OUTREG(BUS_CNTL1, reg);
789
790 reg = INPLL(PLL_PWRMGT_CNTL);
791 reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
792 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
793 reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
794 reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
795 OUTPLL(PLL_PWRMGT_CNTL, reg);
796
797 reg = INREG(TV_DAC_CNTL);
798 reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
799 reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
800 TV_DAC_CNTL_BDACPD |
801 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
802 OUTREG(TV_DAC_CNTL, reg);
803
804 reg = INREG(TMDS_TRANSMITTER_CNTL);
805 reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
806 OUTREG(TMDS_TRANSMITTER_CNTL, reg);
807
808 reg = INREG(DAC_CNTL);
809 reg &= ~DAC_CMP_EN;
810 OUTREG(DAC_CNTL, reg);
811
812 reg = INREG(DAC_CNTL2);
813 reg &= ~DAC2_CMP_EN;
814 OUTREG(DAC_CNTL2, reg);
815
816 reg = INREG(TV_DAC_CNTL);
817 reg &= ~TV_DAC_CNTL_DETECT;
818 OUTREG(TV_DAC_CNTL, reg);
819 }
820
821 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
822 {
823
824 u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
825
826 u32 pll_pwrmgt_cntl;
827 u32 clk_pwrmgt_cntl;
828 u32 clk_pin_cntl;
829 u32 vclk_ecp_cntl;
830 u32 pixclks_cntl;
831 u32 disp_mis_cntl;
832 u32 disp_pwr_man;
833 u32 tmp;
834
835 /* Force Core Clocks */
836 sclk_cntl = INPLL( pllSCLK_CNTL);
837 sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
838 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
839 SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
840 SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
841 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
842 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
843 SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
844
845 SCLK_CNTL__FORCE_DISP2|
846 SCLK_CNTL__FORCE_CP|
847 SCLK_CNTL__FORCE_HDP|
848 SCLK_CNTL__FORCE_DISP1|
849 SCLK_CNTL__FORCE_TOP|
850 SCLK_CNTL__FORCE_E2|
851 SCLK_CNTL__FORCE_SE|
852 SCLK_CNTL__FORCE_IDCT|
853 SCLK_CNTL__FORCE_VIP|
854
855 SCLK_CNTL__FORCE_PB|
856 SCLK_CNTL__FORCE_TAM|
857 SCLK_CNTL__FORCE_TDM|
858 SCLK_CNTL__FORCE_RB|
859 SCLK_CNTL__FORCE_TV_SCLK|
860 SCLK_CNTL__FORCE_SUBPIC|
861 SCLK_CNTL__FORCE_OV0;
862 if (rinfo->family <= CHIP_FAMILY_RV280)
863 sclk_cntl |= SCLK_CNTL__FORCE_RE;
864 else
865 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
866 SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
867 SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
868 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
869 SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
870
871 OUTPLL( pllSCLK_CNTL, sclk_cntl);
872
873 sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
874 sclk_more_cntl |= SCLK_MORE_CNTL__FORCE_DISPREGS |
875 SCLK_MORE_CNTL__FORCE_MC_GUI |
876 SCLK_MORE_CNTL__FORCE_MC_HOST;
877
878 OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
879
880
881 mclk_cntl = INPLL( pllMCLK_CNTL);
882 mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
883 MCLK_CNTL__FORCE_MCLKB |
884 MCLK_CNTL__FORCE_YCLKA |
885 MCLK_CNTL__FORCE_YCLKB |
886 MCLK_CNTL__FORCE_MC
887 );
888 OUTPLL( pllMCLK_CNTL, mclk_cntl);
889
890 /* Force Display clocks */
891 vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
892 vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
893 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
894 vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
895 OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
896
897
898 pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
899 pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
900 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
901 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
902 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
903 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
904 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
905 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
906
907 OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
908
909 /* Switch off LVDS interface */
910 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
911 ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
912
913 /* Enable System power management */
914 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
915
916 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF |
917 PLL_PWRMGT_CNTL__MPLL_TURNOFF|
918 PLL_PWRMGT_CNTL__PPLL_TURNOFF|
919 PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
920 PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
921
922 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
923
924 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
925
926 clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
927 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
928 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
929 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
930 CLK_PWRMGT_CNTL__MCLK_TURNOFF|
931 CLK_PWRMGT_CNTL__SCLK_TURNOFF|
932 CLK_PWRMGT_CNTL__PCLK_TURNOFF|
933 CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
934 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
935 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
936 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
937 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
938 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
939 );
940
941 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
942 | CLK_PWRMGT_CNTL__DISP_PM;
943
944 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
945
946 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
947
948 clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
949
950 /* because both INPLL and OUTPLL take the same lock, that's why. */
951 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
952 OUTPLL( pllMCLK_MISC, tmp);
953
954 /* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
955 * and radeon chip dependent. Thus we only enable it on Mac for
956 * now (until we get more info on how to compute the correct
957 * value for various X86 bridges).
958 */
959 #ifdef CONFIG_PPC_PMAC
960 if (machine_is(powermac)) {
961 /* AGP PLL control */
962 if (rinfo->family <= CHIP_FAMILY_RV280) {
963 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID);
964 OUTREG(BUS_CNTL1,
965 (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
966 | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX
967 } else {
968 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
969 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
970 }
971 }
972 #endif
973
974 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
975 & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
976
977 clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
978 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
979 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
980
981 /* Solano2M */
982 OUTREG(AGP_CNTL,
983 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
984 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
985
986 /* ACPI mode */
987 /* because both INPLL and OUTPLL take the same lock, that's why. */
988 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
989 OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
990
991
992 disp_mis_cntl = INREG(DISP_MISC_CNTL);
993
994 disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
995 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
996 DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
997 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
998 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
999 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
1000 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
1001 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
1002 DISP_MISC_CNTL__SOFT_RESET_LVDS|
1003 DISP_MISC_CNTL__SOFT_RESET_TMDS|
1004 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
1005 DISP_MISC_CNTL__SOFT_RESET_TV);
1006
1007 OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
1008
1009 disp_pwr_man = INREG(DISP_PWR_MAN);
1010
1011 disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN |
1012 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
1013 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
1014 DISP_PWR_MAN__DISP_D3_RST|
1015 DISP_PWR_MAN__DISP_D3_REG_RST
1016 );
1017
1018 disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
1019 DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
1020 DISP_PWR_MAN__DISP_D3_OV0_RST|
1021 DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
1022 DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
1023 DISP_PWR_MAN__DISP_D1D2_OV0_RST|
1024 DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
1025 DISP_PWR_MAN__TV_ENABLE_RST|
1026 // DISP_PWR_MAN__AUTO_PWRUP_EN|
1027 0;
1028
1029 OUTREG(DISP_PWR_MAN, disp_pwr_man);
1030
1031 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
1032 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
1033 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
1034 disp_pwr_man = INREG(DISP_PWR_MAN);
1035
1036
1037 /* D2 */
1038 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
1039 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
1040 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
1041 disp_pwr_man &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
1042 | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
1043
1044 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
1045 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
1046 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
1047 OUTREG(DISP_PWR_MAN, disp_pwr_man);
1048
1049 /* disable display request & disable display */
1050 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
1051 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1052 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
1053 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1054
1055 mdelay(17);
1056
1057 }
1058
1059 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
1060 {
1061 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1062
1063 mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
1064 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1065 mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
1066 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1067
1068 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
1069 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1070 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
1071 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1072
1073 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1074 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1075
1076 mdelay( 1);
1077 }
1078
1079 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1080 {
1081 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1082
1083 mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1084 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1085 mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1086 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1087
1088 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1089 mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1090 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1091 mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1092
1093 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1094 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1095
1096 mdelay( 1);
1097 }
1098
1099 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1100 u8 delay_required)
1101 {
1102 u32 mem_sdram_mode;
1103
1104 mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG);
1105
1106 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1107 mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1108 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1109 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1110 if (delay_required >= 2)
1111 mdelay(1);
1112
1113 mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1114 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1115 if (delay_required >= 2)
1116 mdelay(1);
1117
1118 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1119 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1120 if (delay_required >= 2)
1121 mdelay(1);
1122
1123 if (delay_required) {
1124 do {
1125 if (delay_required >= 2)
1126 mdelay(1);
1127 } while ((INREG(MC_STATUS)
1128 & (MC_STATUS__MEM_PWRUP_COMPL_A |
1129 MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1130 }
1131 }
1132
1133 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1134 {
1135 int cnt;
1136
1137 for (cnt = 0; cnt < 100; ++cnt) {
1138 mdelay(1);
1139 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1140 | MC_STATUS__MEM_PWRUP_COMPL_B))
1141 break;
1142 }
1143 }
1144
1145
1146 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1147 {
1148 #define DLL_RESET_DELAY 5
1149 #define DLL_SLEEP_DELAY 1
1150
1151 u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP
1152 | MDLL_CKO__MCKOA_RESET;
1153 u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1154 | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1155 | MDLL_RDCKA__MRDCKA1_RESET;
1156 u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1157 | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1158 | MDLL_RDCKB__MRDCKB1_RESET;
1159
1160 /* Setting up the DLL range for write */
1161 OUTPLL(pllMDLL_CKO, cko);
1162 OUTPLL(pllMDLL_RDCKA, cka);
1163 OUTPLL(pllMDLL_RDCKB, ckb);
1164
1165 mdelay(DLL_RESET_DELAY*2);
1166
1167 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1168 OUTPLL(pllMDLL_CKO, cko);
1169 mdelay(DLL_SLEEP_DELAY);
1170 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1171 OUTPLL(pllMDLL_CKO, cko);
1172 mdelay(DLL_RESET_DELAY);
1173
1174 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1175 OUTPLL(pllMDLL_RDCKA, cka);
1176 mdelay(DLL_SLEEP_DELAY);
1177 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1178 OUTPLL(pllMDLL_RDCKA, cka);
1179 mdelay(DLL_RESET_DELAY);
1180
1181 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1182 OUTPLL(pllMDLL_RDCKB, ckb);
1183 mdelay(DLL_SLEEP_DELAY);
1184 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1185 OUTPLL(pllMDLL_RDCKB, ckb);
1186 mdelay(DLL_RESET_DELAY);
1187
1188
1189 #undef DLL_RESET_DELAY
1190 #undef DLL_SLEEP_DELAY
1191 }
1192
1193 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1194 {
1195 u32 dll_value;
1196 u32 dll_sleep_mask = 0;
1197 u32 dll_reset_mask = 0;
1198 u32 mc;
1199
1200 #define DLL_RESET_DELAY 5
1201 #define DLL_SLEEP_DELAY 1
1202
1203 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1204 mc = INREG(MC_CNTL);
1205 /* Check which channels are enabled */
1206 switch (mc & 0x3) {
1207 case 1:
1208 if (mc & 0x4)
1209 break;
1210 case 2:
1211 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1212 dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1213 case 0:
1214 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1215 dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1216 }
1217 switch (mc & 0x3) {
1218 case 1:
1219 if (!(mc & 0x4))
1220 break;
1221 case 2:
1222 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1223 dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1224 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1225 dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1226 }
1227
1228 dll_value = INPLL(pllMDLL_RDCKA);
1229
1230 /* Power Up */
1231 dll_value &= ~(dll_sleep_mask);
1232 OUTPLL(pllMDLL_RDCKA, dll_value);
1233 mdelay( DLL_SLEEP_DELAY);
1234
1235 dll_value &= ~(dll_reset_mask);
1236 OUTPLL(pllMDLL_RDCKA, dll_value);
1237 mdelay( DLL_RESET_DELAY);
1238
1239 #undef DLL_RESET_DELAY
1240 #undef DLL_SLEEP_DELAY
1241 }
1242
1243
1244 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1245 {
1246 u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1247 fp_gen_cntl, fp2_gen_cntl;
1248
1249 crtcGenCntl = INREG( CRTC_GEN_CNTL);
1250 crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1251
1252 crtc_more_cntl = INREG( CRTC_MORE_CNTL);
1253 fp_gen_cntl = INREG( FP_GEN_CNTL);
1254 fp2_gen_cntl = INREG( FP2_GEN_CNTL);
1255
1256
1257 OUTREG( CRTC_MORE_CNTL, 0);
1258 OUTREG( FP_GEN_CNTL, 0);
1259 OUTREG( FP2_GEN_CNTL,0);
1260
1261 OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1262 OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1263
1264 /* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */
1265 if (rinfo->family == CHIP_FAMILY_RV350) {
1266 u32 sdram_mode_reg = rinfo->save_regs[35];
1267 static const u32 default_mrtable[] =
1268 { 0x21320032,
1269 0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1270 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1271 0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1272 0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1273 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1274 0x31320032 };
1275
1276 const u32 *mrtable = default_mrtable;
1277 int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1278
1279 mdelay(30);
1280
1281 /* Disable refresh */
1282 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1283 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1284 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1285 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1286
1287 /* Configure and enable M & SPLLs */
1288 radeon_pm_enable_dll_m10(rinfo);
1289 radeon_pm_yclk_mclk_sync_m10(rinfo);
1290
1291 #ifdef CONFIG_PPC_OF
1292 if (rinfo->of_node != NULL) {
1293 int size;
1294
1295 mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size);
1296 if (mrtable)
1297 mrtable_size = size >> 2;
1298 else
1299 mrtable = default_mrtable;
1300 }
1301 #endif /* CONFIG_PPC_OF */
1302
1303 /* Program the SDRAM */
1304 sdram_mode_reg = mrtable[0];
1305 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1306 for (i = 0; i < mrtable_size; i++) {
1307 if (mrtable[i] == 0xffffffffu)
1308 radeon_pm_m10_program_mode_wait(rinfo);
1309 else {
1310 sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1311 | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1312 | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1313 sdram_mode_reg |= mrtable[i];
1314
1315 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1316 mdelay(1);
1317 }
1318 }
1319
1320 /* Restore memory refresh */
1321 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1322 mdelay(30);
1323
1324 }
1325 /* Here come the desktop RV200 "QW" card */
1326 else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1327 /* Disable refresh */
1328 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1329 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1330 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1331 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1332 mdelay(30);
1333
1334 /* Reset memory */
1335 OUTREG(MEM_SDRAM_MODE_REG,
1336 INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1337
1338 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1339 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1340 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1341
1342 OUTREG(MEM_SDRAM_MODE_REG,
1343 INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1344
1345 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1346
1347 }
1348 /* The M6 */
1349 else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1350 /* Disable refresh */
1351 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1352 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1353
1354 /* Reset memory */
1355 OUTREG( MEM_SDRAM_MODE_REG,
1356 INREG( MEM_SDRAM_MODE_REG)
1357 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1358
1359 /* DLL */
1360 radeon_pm_enable_dll(rinfo);
1361
1362 /* MLCK / YCLK sync */
1363 radeon_pm_yclk_mclk_sync(rinfo);
1364
1365 /* Program Mode Register */
1366 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1367 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1368 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1369 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1370 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1371
1372 /* Complete & re-enable refresh */
1373 OUTREG( MEM_SDRAM_MODE_REG,
1374 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1375
1376 OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1377 }
1378 /* And finally, the M7..M9 models, including M9+ (RV280) */
1379 else if (rinfo->is_mobility) {
1380
1381 /* Disable refresh */
1382 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1383 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1384 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1385 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1386
1387 /* Reset memory */
1388 OUTREG( MEM_SDRAM_MODE_REG,
1389 INREG( MEM_SDRAM_MODE_REG)
1390 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1391
1392 /* DLL */
1393 radeon_pm_enable_dll(rinfo);
1394
1395 /* MLCK / YCLK sync */
1396 radeon_pm_yclk_mclk_sync(rinfo);
1397
1398 /* M6, M7 and M9 so far ... */
1399 if (rinfo->family <= CHIP_FAMILY_RV250) {
1400 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1401 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1402 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1403 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1404 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1405 }
1406 /* M9+ (iBook G4) */
1407 else if (rinfo->family == CHIP_FAMILY_RV280) {
1408 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1409 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1410 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1411 }
1412
1413 /* Complete & re-enable refresh */
1414 OUTREG( MEM_SDRAM_MODE_REG,
1415 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1416
1417 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1418 }
1419
1420 OUTREG( CRTC_GEN_CNTL, crtcGenCntl);
1421 OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2);
1422 OUTREG( FP_GEN_CNTL, fp_gen_cntl);
1423 OUTREG( FP2_GEN_CNTL, fp2_gen_cntl);
1424
1425 OUTREG( CRTC_MORE_CNTL, crtc_more_cntl);
1426
1427 mdelay( 15);
1428 }
1429
1430 #if defined(CONFIG_PM)
1431 #if defined(CONFIG_X86) || defined(CONFIG_PPC_PMAC)
1432 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1433 {
1434 u32 tmp, tmp2;
1435 int i,j;
1436
1437 /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1438 INREG(PAD_CTLR_STRENGTH);
1439 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1440 tmp = INREG(PAD_CTLR_STRENGTH);
1441 for (i = j = 0; i < 65; ++i) {
1442 mdelay(1);
1443 tmp2 = INREG(PAD_CTLR_STRENGTH);
1444 if (tmp != tmp2) {
1445 tmp = tmp2;
1446 i = 0;
1447 j++;
1448 if (j > 10) {
1449 printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1450 "stabilize !\n");
1451 break;
1452 }
1453 }
1454 }
1455 }
1456
1457 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1458 {
1459 u32 tmp;
1460
1461 tmp = INPLL(pllPPLL_CNTL);
1462 OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1463 tmp = INPLL(pllP2PLL_CNTL);
1464 OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1465 tmp = INPLL(pllSPLL_CNTL);
1466 OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1467 tmp = INPLL(pllMPLL_CNTL);
1468 OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1469 }
1470
1471 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1472 {
1473 u32 tmp;
1474
1475 /* Switch SPLL to PCI source */
1476 tmp = INPLL(pllSCLK_CNTL);
1477 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1478
1479 /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1480 tmp = INPLL(pllSPLL_CNTL);
1481 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1482 radeon_pll_errata_after_index(rinfo);
1483 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1484 radeon_pll_errata_after_data(rinfo);
1485
1486 /* Set SPLL feedback divider */
1487 tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1488 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1489 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1490
1491 /* Power up SPLL */
1492 tmp = INPLL(pllSPLL_CNTL);
1493 OUTPLL(pllSPLL_CNTL, tmp & ~1);
1494 (void)INPLL(pllSPLL_CNTL);
1495
1496 mdelay(10);
1497
1498 /* Release SPLL reset */
1499 tmp = INPLL(pllSPLL_CNTL);
1500 OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1501 (void)INPLL(pllSPLL_CNTL);
1502
1503 mdelay(10);
1504
1505 /* Select SCLK source */
1506 tmp = INPLL(pllSCLK_CNTL);
1507 tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1508 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1509 OUTPLL(pllSCLK_CNTL, tmp);
1510 (void)INPLL(pllSCLK_CNTL);
1511
1512 mdelay(10);
1513
1514 /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1515 tmp = INPLL(pllMPLL_CNTL);
1516 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1517 radeon_pll_errata_after_index(rinfo);
1518 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1519 radeon_pll_errata_after_data(rinfo);
1520
1521 /* Set MPLL feedback divider */
1522 tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1523 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1524
1525 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1526 /* Power up MPLL */
1527 tmp = INPLL(pllMPLL_CNTL);
1528 OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1529 (void)INPLL(pllMPLL_CNTL);
1530
1531 mdelay(10);
1532
1533 /* Un-reset MPLL */
1534 tmp = INPLL(pllMPLL_CNTL);
1535 OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1536 (void)INPLL(pllMPLL_CNTL);
1537
1538 mdelay(10);
1539
1540 /* Select source for MCLK */
1541 tmp = INPLL(pllMCLK_CNTL);
1542 tmp |= rinfo->save_regs[2] & 0xffff;
1543 OUTPLL(pllMCLK_CNTL, tmp);
1544 (void)INPLL(pllMCLK_CNTL);
1545
1546 mdelay(10);
1547 }
1548
1549 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1550 {
1551 u32 r2ec;
1552
1553 /* GACK ! I though we didn't have a DDA on Radeon's anymore
1554 * here we rewrite with the same value, ... I suppose we clear
1555 * some bits that are already clear ? Or maybe this 0x2ec
1556 * register is something new ?
1557 */
1558 mdelay(20);
1559 r2ec = INREG(VGA_DDA_ON_OFF);
1560 OUTREG(VGA_DDA_ON_OFF, r2ec);
1561 mdelay(1);
1562
1563 /* Spread spectrum PLLL off */
1564 OUTPLL(pllSSPLL_CNTL, 0xbf03);
1565
1566 /* Spread spectrum disabled */
1567 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1568
1569 /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1570 * value, not sure what for...
1571 */
1572
1573 r2ec |= 0x3f0;
1574 OUTREG(VGA_DDA_ON_OFF, r2ec);
1575 mdelay(1);
1576 }
1577
1578 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1579 {
1580 u32 r2ec, tmp;
1581
1582 /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1583 * here we rewrite with the same value, ... I suppose we clear/set
1584 * some bits that are already clear/set ?
1585 */
1586 r2ec = INREG(VGA_DDA_ON_OFF);
1587 OUTREG(VGA_DDA_ON_OFF, r2ec);
1588 mdelay(1);
1589
1590 /* Enable spread spectrum */
1591 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1592 mdelay(3);
1593
1594 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1595 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1596 tmp = INPLL(pllSSPLL_CNTL);
1597 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1598 mdelay(6);
1599 tmp = INPLL(pllSSPLL_CNTL);
1600 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1601 mdelay(5);
1602
1603 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1604
1605 r2ec |= 8;
1606 OUTREG(VGA_DDA_ON_OFF, r2ec);
1607 mdelay(20);
1608
1609 /* Enable LVDS interface */
1610 tmp = INREG(LVDS_GEN_CNTL);
1611 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1612
1613 /* Enable LVDS_PLL */
1614 tmp = INREG(LVDS_PLL_CNTL);
1615 tmp &= ~0x30000;
1616 tmp |= 0x10000;
1617 OUTREG(LVDS_PLL_CNTL, tmp);
1618
1619 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1620 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1621
1622 /* The trace reads that one here, waiting for something to settle down ? */
1623 INREG(RBBM_STATUS);
1624
1625 /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1626 * R300 register spec at least...
1627 */
1628 tmp = INPLL(pllSS_TST_CNTL);
1629 tmp |= 0x00400000;
1630 OUTPLL(pllSS_TST_CNTL, tmp);
1631 }
1632
1633 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1634 {
1635 u32 tmp;
1636
1637 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1638 radeon_pll_errata_after_index(rinfo);
1639 OUTREG8(CLOCK_CNTL_DATA, 0);
1640 radeon_pll_errata_after_data(rinfo);
1641
1642 tmp = INPLL(pllVCLK_ECP_CNTL);
1643 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1644 mdelay(5);
1645
1646 tmp = INPLL(pllPPLL_REF_DIV);
1647 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1648 OUTPLL(pllPPLL_REF_DIV, tmp);
1649 INPLL(pllPPLL_REF_DIV);
1650
1651 /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1652 * probably useless since we already did it ...
1653 */
1654 tmp = INPLL(pllPPLL_CNTL);
1655 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1656 radeon_pll_errata_after_index(rinfo);
1657 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1658 radeon_pll_errata_after_data(rinfo);
1659
1660 /* Restore our "reference" PPLL divider set by firmware
1661 * according to proper spread spectrum calculations
1662 */
1663 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1664
1665 tmp = INPLL(pllPPLL_CNTL);
1666 OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1667 mdelay(5);
1668
1669 tmp = INPLL(pllPPLL_CNTL);
1670 OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1671 mdelay(5);
1672
1673 tmp = INPLL(pllVCLK_ECP_CNTL);
1674 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1675 mdelay(5);
1676
1677 tmp = INPLL(pllVCLK_ECP_CNTL);
1678 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1679 mdelay(5);
1680
1681 /* Switch pixel clock to firmware default div 0 */
1682 OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1683 radeon_pll_errata_after_index(rinfo);
1684 radeon_pll_errata_after_data(rinfo);
1685 }
1686
1687 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1688 {
1689 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1690 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1691 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1692 OUTREG(MEM_SDRAM_MODE_REG,
1693 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1694 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1695 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1696 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1697 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1698 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1699 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1700
1701 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1702 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1703 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1704 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1705 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1706 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1707 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1708 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1709 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1710 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1711 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1712 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1713 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1714 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1715 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1716 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1717 OUTREG(MC_IND_INDEX, 0);
1718 }
1719
1720 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1721 {
1722 u32 tmp, i;
1723
1724 /* Restore a bunch of registers first */
1725 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1726 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1727 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1728 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1729 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1730 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1731 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1732 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1733 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1734 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1735 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1736 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1737 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1738 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1739
1740 /* Hrm... */
1741 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1742
1743 /* Reset the PAD CTLR */
1744 radeon_pm_reset_pad_ctlr_strength(rinfo);
1745
1746 /* Some PLLs are Read & written identically in the trace here...
1747 * I suppose it's actually to switch them all off & reset,
1748 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1749 */
1750 radeon_pm_all_ppls_off(rinfo);
1751
1752 /* Clear tiling, reset swappers */
1753 INREG(SURFACE_CNTL);
1754 OUTREG(SURFACE_CNTL, 0);
1755
1756 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1757 * rather than hard coding...
1758 */
1759 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1760 tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1761 OUTREG(TV_DAC_CNTL, tmp);
1762
1763 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1764 tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1765 OUTREG(TV_DAC_CNTL, tmp);
1766
1767 /* More registers restored */
1768 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1769 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1770 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1771
1772 /* Hrmmm ... What is that ? */
1773 tmp = rinfo->save_regs[1]
1774 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1775 CLK_PWRMGT_CNTL__MC_BUSY);
1776 OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1777
1778 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1779 OUTREG(FW_CNTL, rinfo->save_regs[57]);
1780 OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1781 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1782 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1783 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1784
1785 /* Restore Memory Controller configuration */
1786 radeon_pm_m10_reconfigure_mc(rinfo);
1787
1788 /* Make sure CRTC's dont touch memory */
1789 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1790 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1791 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1792 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1793 mdelay(30);
1794
1795 /* Disable SDRAM refresh */
1796 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1797 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1798
1799 /* Restore XTALIN routing (CLK_PIN_CNTL) */
1800 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1801
1802 /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1803 tmp = rinfo->save_regs[2] & 0xff000000;
1804 tmp |= MCLK_CNTL__FORCE_MCLKA |
1805 MCLK_CNTL__FORCE_MCLKB |
1806 MCLK_CNTL__FORCE_YCLKA |
1807 MCLK_CNTL__FORCE_YCLKB |
1808 MCLK_CNTL__FORCE_MC;
1809 OUTPLL(pllMCLK_CNTL, tmp);
1810
1811 /* Force all clocks on in SCLK */
1812 tmp = INPLL(pllSCLK_CNTL);
1813 tmp |= SCLK_CNTL__FORCE_DISP2|
1814 SCLK_CNTL__FORCE_CP|
1815 SCLK_CNTL__FORCE_HDP|
1816 SCLK_CNTL__FORCE_DISP1|
1817 SCLK_CNTL__FORCE_TOP|
1818 SCLK_CNTL__FORCE_E2|
1819 SCLK_CNTL__FORCE_SE|
1820 SCLK_CNTL__FORCE_IDCT|
1821 SCLK_CNTL__FORCE_VIP|
1822 SCLK_CNTL__FORCE_PB|
1823 SCLK_CNTL__FORCE_TAM|
1824 SCLK_CNTL__FORCE_TDM|
1825 SCLK_CNTL__FORCE_RB|
1826 SCLK_CNTL__FORCE_TV_SCLK|
1827 SCLK_CNTL__FORCE_SUBPIC|
1828 SCLK_CNTL__FORCE_OV0;
1829 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT |
1830 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1831 SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
1832 SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
1833 SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
1834 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1835 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1836 SCLK_CNTL__RE_MAX_DYN_STOP_LAT |
1837 SCLK_CNTL__PB_MAX_DYN_STOP_LAT |
1838 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1839 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1840 SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1841 OUTPLL(pllSCLK_CNTL, tmp);
1842
1843 OUTPLL(pllVCLK_ECP_CNTL, 0);
1844 OUTPLL(pllPIXCLKS_CNTL, 0);
1845 OUTPLL(pllMCLK_MISC,
1846 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1847 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1848
1849 mdelay(5);
1850
1851 /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1852 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1853 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1854 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1855
1856 /* Now restore the major PLLs settings, keeping them off & reset though */
1857 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1858 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1859 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1860 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1861
1862 /* Restore MC DLL state and switch it off/reset too */
1863 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1864
1865 /* Switch MDLL off & reset */
1866 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1867 mdelay(5);
1868
1869 /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1870 * 0xa1100007... and MacOS writes 0xa1000007 ..
1871 */
1872 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1873
1874 /* Restore more stuffs */
1875 OUTPLL(pllHTOTAL_CNTL, 0);
1876 OUTPLL(pllHTOTAL2_CNTL, 0);
1877
1878 /* More PLL initial configuration */
1879 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
1880 OUTPLL(pllSCLK_CNTL2, tmp);
1881
1882 tmp = INPLL(pllSCLK_MORE_CNTL);
1883 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */
1884 SCLK_MORE_CNTL__FORCE_MC_GUI |
1885 SCLK_MORE_CNTL__FORCE_MC_HOST;
1886 OUTPLL(pllSCLK_MORE_CNTL, tmp);
1887
1888 /* Now we actually start MCLK and SCLK */
1889 radeon_pm_start_mclk_sclk(rinfo);
1890
1891 /* Full reset sdrams, this also re-inits the MDLL */
1892 radeon_pm_full_reset_sdram(rinfo);
1893
1894 /* Fill palettes */
1895 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
1896 for (i=0; i<256; i++)
1897 OUTREG(PALETTE_30_DATA, 0x15555555);
1898 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
1899 udelay(20);
1900 for (i=0; i<256; i++)
1901 OUTREG(PALETTE_30_DATA, 0x15555555);
1902
1903 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
1904 mdelay(3);
1905
1906 /* Restore TMDS */
1907 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1908 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1909
1910 /* Set LVDS registers but keep interface & pll down */
1911 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1912 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
1913 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1914
1915 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1916
1917 /* Restore GPIOPAD state */
1918 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1919 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1920 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1921
1922 /* write some stuff to the framebuffer... */
1923 for (i = 0; i < 0x8000; ++i)
1924 writeb(0, rinfo->fb_base + i);
1925
1926 mdelay(40);
1927 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
1928 mdelay(40);
1929
1930 /* Restore a few more things */
1931 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1932 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1933
1934 /* Take care of spread spectrum & PPLLs now */
1935 radeon_pm_m10_disable_spread_spectrum(rinfo);
1936 radeon_pm_restore_pixel_pll(rinfo);
1937
1938 /* GRRRR... I can't figure out the proper LVDS power sequence, and the
1939 * code I have for blank/unblank doesn't quite work on some laptop models
1940 * it seems ... Hrm. What I have here works most of the time ...
1941 */
1942 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1943 }
1944 #endif
1945
1946 #ifdef CONFIG_PPC_OF
1947 #ifdef CONFIG_PPC_PMAC
1948 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1949 {
1950 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1951 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1952 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1953 OUTREG(MEM_SDRAM_MODE_REG,
1954 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1955 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1956 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1957 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1958 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1959 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1960 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1961
1962 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1963 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1964 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1965 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1966 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1967 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1968 OUTREG(MC_IND_INDEX, 0);
1969 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1970
1971 mdelay(20);
1972 }
1973
1974 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1975 {
1976 u32 tmp, i;
1977
1978 /* Restore a bunch of registers first */
1979 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1980 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1981 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1982 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1983 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1984 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1985 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1986 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1987 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1988 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1989 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1990
1991 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1992 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1993
1994 /* Reset the PAD CTLR */
1995 radeon_pm_reset_pad_ctlr_strength(rinfo);
1996
1997 /* Some PLLs are Read & written identically in the trace here...
1998 * I suppose it's actually to switch them all off & reset,
1999 * let's assume off is what we want. I'm just doing that for all major PLLs now.
2000 */
2001 radeon_pm_all_ppls_off(rinfo);
2002
2003 /* Clear tiling, reset swappers */
2004 INREG(SURFACE_CNTL);
2005 OUTREG(SURFACE_CNTL, 0);
2006
2007 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
2008 * rather than hard coding...
2009 */
2010 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
2011 tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
2012 OUTREG(TV_DAC_CNTL, tmp);
2013
2014 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
2015 tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
2016 OUTREG(TV_DAC_CNTL, tmp);
2017
2018 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
2019
2020 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
2021 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
2022 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
2023
2024 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2025 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
2026 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2027
2028 tmp = rinfo->save_regs[1]
2029 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
2030 CLK_PWRMGT_CNTL__MC_BUSY);
2031 OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
2032
2033 OUTREG(FW_CNTL, rinfo->save_regs[57]);
2034
2035 /* Disable SDRAM refresh */
2036 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
2037 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
2038
2039 /* Restore XTALIN routing (CLK_PIN_CNTL) */
2040 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
2041
2042 /* Force MCLK to be PCI sourced and forced ON */
2043 tmp = rinfo->save_regs[2] & 0xff000000;
2044 tmp |= MCLK_CNTL__FORCE_MCLKA |
2045 MCLK_CNTL__FORCE_MCLKB |
2046 MCLK_CNTL__FORCE_YCLKA |
2047 MCLK_CNTL__FORCE_YCLKB |
2048 MCLK_CNTL__FORCE_MC |
2049 MCLK_CNTL__FORCE_AIC;
2050 OUTPLL(pllMCLK_CNTL, tmp);
2051
2052 /* Force SCLK to be PCI sourced with a bunch forced */
2053 tmp = 0 |
2054 SCLK_CNTL__FORCE_DISP2|
2055 SCLK_CNTL__FORCE_CP|
2056 SCLK_CNTL__FORCE_HDP|
2057 SCLK_CNTL__FORCE_DISP1|
2058 SCLK_CNTL__FORCE_TOP|
2059 SCLK_CNTL__FORCE_E2|
2060 SCLK_CNTL__FORCE_SE|
2061 SCLK_CNTL__FORCE_IDCT|
2062 SCLK_CNTL__FORCE_VIP|
2063 SCLK_CNTL__FORCE_RE|
2064 SCLK_CNTL__FORCE_PB|
2065 SCLK_CNTL__FORCE_TAM|
2066 SCLK_CNTL__FORCE_TDM|
2067 SCLK_CNTL__FORCE_RB;
2068 OUTPLL(pllSCLK_CNTL, tmp);
2069
2070 /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */
2071 OUTPLL(pllVCLK_ECP_CNTL, 0);
2072 OUTPLL(pllPIXCLKS_CNTL, 0);
2073
2074 /* Setup MCLK_MISC, non dynamic mode */
2075 OUTPLL(pllMCLK_MISC,
2076 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
2077 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
2078
2079 mdelay(5);
2080
2081 /* Set back the default clock dividers */
2082 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2083 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2084 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2085
2086 /* PPLL and P2PLL default values & off */
2087 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2088 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2089
2090 /* S and M PLLs are reset & off, configure them */
2091 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2092 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2093
2094 /* Default values for MDLL ... fixme */
2095 OUTPLL(pllMDLL_CKO, 0x9c009c);
2096 OUTPLL(pllMDLL_RDCKA, 0x08830883);
2097 OUTPLL(pllMDLL_RDCKB, 0x08830883);
2098 mdelay(5);
2099
2100 /* Restore PLL_PWRMGT_CNTL */ // XXXX
2101 tmp = rinfo->save_regs[0];
2102 tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
2103 tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2104 OUTPLL(PLL_PWRMGT_CNTL, tmp);
2105
2106 /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
2107 OUTPLL(pllHTOTAL_CNTL, 0);
2108 OUTPLL(pllHTOTAL2_CNTL, 0);
2109
2110 /* All outputs off */
2111 OUTREG(CRTC_GEN_CNTL, 0x04000000);
2112 OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2113 OUTREG(FP_GEN_CNTL, 0x00004008);
2114 OUTREG(FP2_GEN_CNTL, 0x00000008);
2115 OUTREG(LVDS_GEN_CNTL, 0x08000008);
2116
2117 /* Restore Memory Controller configuration */
2118 radeon_pm_m9p_reconfigure_mc(rinfo);
2119
2120 /* Now we actually start MCLK and SCLK */
2121 radeon_pm_start_mclk_sclk(rinfo);
2122
2123 /* Full reset sdrams, this also re-inits the MDLL */
2124 radeon_pm_full_reset_sdram(rinfo);
2125
2126 /* Fill palettes */
2127 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2128 for (i=0; i<256; i++)
2129 OUTREG(PALETTE_30_DATA, 0x15555555);
2130 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2131 udelay(20);
2132 for (i=0; i<256; i++)
2133 OUTREG(PALETTE_30_DATA, 0x15555555);
2134
2135 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2136 mdelay(3);
2137
2138 /* Restore TV stuff, make sure TV DAC is down */
2139 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2140 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2141
2142 /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2143 * possibly related to the weird PLL related workarounds and to the
2144 * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2145 * but we keep things the simple way here
2146 */
2147 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2148 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2149 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2150
2151 /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2152 * high bits from backup
2153 */
2154 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2155 tmp |= rinfo->save_regs[34] & 0xffff0000;
2156 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2157 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2158
2159 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2160 tmp |= rinfo->save_regs[34] & 0xffff0000;
2161 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2162 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2163
2164 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2165 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2166 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2167 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2168 mdelay(20);
2169
2170 /* write some stuff to the framebuffer... */
2171 for (i = 0; i < 0x8000; ++i)
2172 writeb(0, rinfo->fb_base + i);
2173
2174 OUTREG(0x2ec, 0x6332a020);
2175 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2176 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2177 tmp = INPLL(pllSSPLL_CNTL);
2178 tmp &= ~2;
2179 OUTPLL(pllSSPLL_CNTL, tmp);
2180 mdelay(6);
2181 tmp &= ~1;
2182 OUTPLL(pllSSPLL_CNTL, tmp);
2183 mdelay(5);
2184 tmp |= 3;
2185 OUTPLL(pllSSPLL_CNTL, tmp);
2186 mdelay(5);
2187
2188 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2189 OUTREG(0x2ec, 0x6332a3f0);
2190 mdelay(17);
2191
2192 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
2193 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2194
2195 mdelay(40);
2196 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2197 mdelay(40);
2198
2199 /* Restore a few more things */
2200 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2201 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2202
2203 /* Restore PPLL, spread spectrum & LVDS */
2204 radeon_pm_m10_disable_spread_spectrum(rinfo);
2205 radeon_pm_restore_pixel_pll(rinfo);
2206 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2207 }
2208 #endif
2209 #endif
2210
2211 #if 0 /* Not ready yet */
2212 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2213 {
2214 int i;
2215 u32 tmp, tmp2;
2216 u32 cko, cka, ckb;
2217 u32 cgc, cec, c2gc;
2218
2219 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2220 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2221 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2222 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2223 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2224 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2225
2226 INREG(PAD_CTLR_STRENGTH);
2227 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2228 for (i = 0; i < 65; ++i) {
2229 mdelay(1);
2230 INREG(PAD_CTLR_STRENGTH);
2231 }
2232
2233 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2234 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2235 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2236 OUTREG(DAC_CNTL, 0xff00410a);
2237 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2238 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2239
2240 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2241 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2242 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2243 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2244
2245 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2246 OUTREG(MC_IND_INDEX, 0);
2247 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2248 OUTREG(MC_IND_INDEX, 0);
2249
2250 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2251
2252 tmp = INPLL(pllVCLK_ECP_CNTL);
2253 OUTPLL(pllVCLK_ECP_CNTL, tmp);
2254 tmp = INPLL(pllPIXCLKS_CNTL);
2255 OUTPLL(pllPIXCLKS_CNTL, tmp);
2256
2257 OUTPLL(MCLK_CNTL, 0xaa3f0000);
2258 OUTPLL(SCLK_CNTL, 0xffff0000);
2259 OUTPLL(pllMPLL_AUX_CNTL, 6);
2260 OUTPLL(pllSPLL_AUX_CNTL, 1);
2261 OUTPLL(MDLL_CKO, 0x9f009f);
2262 OUTPLL(MDLL_RDCKA, 0x830083);
2263 OUTPLL(pllMDLL_RDCKB, 0x830083);
2264 OUTPLL(PPLL_CNTL, 0xa433);
2265 OUTPLL(P2PLL_CNTL, 0xa433);
2266 OUTPLL(MPLL_CNTL, 0x0400a403);
2267 OUTPLL(SPLL_CNTL, 0x0400a433);
2268
2269 tmp = INPLL(M_SPLL_REF_FB_DIV);
2270 OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2271 tmp = INPLL(M_SPLL_REF_FB_DIV);
2272 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2273 INPLL(M_SPLL_REF_FB_DIV);
2274
2275 tmp = INPLL(MPLL_CNTL);
2276 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2277 radeon_pll_errata_after_index(rinfo);
2278 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2279 radeon_pll_errata_after_data(rinfo);
2280
2281 tmp = INPLL(M_SPLL_REF_FB_DIV);
2282 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2283
2284 tmp = INPLL(MPLL_CNTL);
2285 OUTPLL(MPLL_CNTL, tmp & ~0x2);
2286 mdelay(1);
2287 tmp = INPLL(MPLL_CNTL);
2288 OUTPLL(MPLL_CNTL, tmp & ~0x1);
2289 mdelay(10);
2290
2291 OUTPLL(MCLK_CNTL, 0xaa3f1212);
2292 mdelay(1);
2293
2294 INPLL(M_SPLL_REF_FB_DIV);
2295 INPLL(MCLK_CNTL);
2296 INPLL(M_SPLL_REF_FB_DIV);
2297
2298 tmp = INPLL(SPLL_CNTL);
2299 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2300 radeon_pll_errata_after_index(rinfo);
2301 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2302 radeon_pll_errata_after_data(rinfo);
2303
2304 tmp = INPLL(M_SPLL_REF_FB_DIV);
2305 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2306
2307 tmp = INPLL(SPLL_CNTL);
2308 OUTPLL(SPLL_CNTL, tmp & ~0x1);
2309 mdelay(1);
2310 tmp = INPLL(SPLL_CNTL);
2311 OUTPLL(SPLL_CNTL, tmp & ~0x2);
2312 mdelay(10);
2313
2314 tmp = INPLL(SCLK_CNTL);
2315 OUTPLL(SCLK_CNTL, tmp | 2);
2316 mdelay(1);
2317
2318 cko = INPLL(pllMDLL_CKO);
2319 cka = INPLL(pllMDLL_RDCKA);
2320 ckb = INPLL(pllMDLL_RDCKB);
2321
2322 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2323 OUTPLL(pllMDLL_CKO, cko);
2324 mdelay(1);
2325 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2326 OUTPLL(pllMDLL_CKO, cko);
2327 mdelay(5);
2328
2329 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2330 OUTPLL(pllMDLL_RDCKA, cka);
2331 mdelay(1);
2332 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2333 OUTPLL(pllMDLL_RDCKA, cka);
2334 mdelay(5);
2335
2336 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2337 OUTPLL(pllMDLL_RDCKB, ckb);
2338 mdelay(1);
2339 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2340 OUTPLL(pllMDLL_RDCKB, ckb);
2341 mdelay(5);
2342
2343 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2344 OUTREG(MC_IND_INDEX, 0);
2345 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2346 OUTREG(MC_IND_INDEX, 0);
2347 mdelay(1);
2348 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2349 OUTREG(MC_IND_INDEX, 0);
2350 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2351 OUTREG(MC_IND_INDEX, 0);
2352 mdelay(1);
2353
2354 OUTPLL(pllHTOTAL_CNTL, 0);
2355 OUTPLL(pllHTOTAL2_CNTL, 0);
2356
2357 OUTREG(MEM_CNTL, 0x29002901);
2358 OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2359 OUTREG(EXT_MEM_CNTL, 0x1a394333);
2360 OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2361 OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2362 OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */
2363 OUTREG(MC_DEBUG, 0);
2364 OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2365
2366 OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2367 OUTREG(MC_IND_INDEX, 0);
2368 OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2369 OUTREG(MC_IND_INDEX, 0);
2370
2371 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2372
2373 radeon_pm_full_reset_sdram(rinfo);
2374
2375 INREG(FP_GEN_CNTL);
2376 OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */
2377 tmp = INREG(FP_GEN_CNTL);
2378 tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2379 OUTREG(FP_GEN_CNTL, tmp);
2380
2381 tmp = INREG(DISP_OUTPUT_CNTL);
2382 tmp &= ~0x400;
2383 OUTREG(DISP_OUTPUT_CNTL, tmp);
2384
2385 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2386 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2387 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2388
2389 tmp = INPLL(MCLK_MISC);
2390 tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2391 OUTPLL(MCLK_MISC, tmp);
2392
2393 tmp = INPLL(SCLK_CNTL);
2394 OUTPLL(SCLK_CNTL, tmp);
2395
2396 OUTREG(CRTC_MORE_CNTL, 0);
2397 OUTREG8(CRTC_GEN_CNTL+1, 6);
2398 OUTREG8(CRTC_GEN_CNTL+3, 1);
2399 OUTREG(CRTC_PITCH, 32);
2400
2401 tmp = INPLL(VCLK_ECP_CNTL);
2402 OUTPLL(VCLK_ECP_CNTL, tmp);
2403
2404 tmp = INPLL(PPLL_CNTL);
2405 OUTPLL(PPLL_CNTL, tmp);
2406
2407 /* palette stuff and BIOS_1_SCRATCH... */
2408
2409 tmp = INREG(FP_GEN_CNTL);
2410 tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2411 tmp |= 2;
2412 OUTREG(FP_GEN_CNTL, tmp);
2413 mdelay(5);
2414 OUTREG(FP_GEN_CNTL, tmp);
2415 mdelay(5);
2416 OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2417 OUTREG(CRTC_MORE_CNTL, 0);
2418 mdelay(20);
2419
2420 tmp = INREG(CRTC_MORE_CNTL);
2421 OUTREG(CRTC_MORE_CNTL, tmp);
2422
2423 cgc = INREG(CRTC_GEN_CNTL);
2424 cec = INREG(CRTC_EXT_CNTL);
2425 c2gc = INREG(CRTC2_GEN_CNTL);
2426
2427 OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2428 OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2429 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2430 radeon_pll_errata_after_index(rinfo);
2431 OUTREG8(CLOCK_CNTL_DATA, 0);
2432 radeon_pll_errata_after_data(rinfo);
2433 OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2434 OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2435 OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2436 OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2437 OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2438 OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2439 OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2440 OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2441 OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2442 OUTREG(FP_HORZ_STRETCH, 0);
2443 OUTREG(FP_VERT_STRETCH, 0);
2444 OUTREG(OVR_CLR, 0);
2445 OUTREG(OVR_WID_LEFT_RIGHT, 0);
2446 OUTREG(OVR_WID_TOP_BOTTOM, 0);
2447
2448 tmp = INPLL(PPLL_REF_DIV);
2449 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2450 OUTPLL(PPLL_REF_DIV, tmp);
2451 INPLL(PPLL_REF_DIV);
2452
2453 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2454 radeon_pll_errata_after_index(rinfo);
2455 OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2456 radeon_pll_errata_after_data(rinfo);
2457
2458 tmp = INREG(CLOCK_CNTL_INDEX);
2459 radeon_pll_errata_after_index(rinfo);
2460 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2461 radeon_pll_errata_after_index(rinfo);
2462 radeon_pll_errata_after_data(rinfo);
2463
2464 OUTPLL(PPLL_DIV_0, 0x48090);
2465
2466 tmp = INPLL(PPLL_CNTL);
2467 OUTPLL(PPLL_CNTL, tmp & ~0x2);
2468 mdelay(1);
2469 tmp = INPLL(PPLL_CNTL);
2470 OUTPLL(PPLL_CNTL, tmp & ~0x1);
2471 mdelay(10);
2472
2473 tmp = INPLL(VCLK_ECP_CNTL);
2474 OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2475 mdelay(1);
2476
2477 tmp = INPLL(VCLK_ECP_CNTL);
2478 OUTPLL(VCLK_ECP_CNTL, tmp);
2479
2480 c2gc |= CRTC2_DISP_REQ_EN_B;
2481 OUTREG(CRTC2_GEN_CNTL, c2gc);
2482 cgc |= CRTC_EN;
2483 OUTREG(CRTC_GEN_CNTL, cgc);
2484 OUTREG(CRTC_EXT_CNTL, cec);
2485 OUTREG(CRTC_PITCH, 0xa0);
2486 OUTREG(CRTC_OFFSET, 0);
2487 OUTREG(CRTC_OFFSET_CNTL, 0);
2488
2489 OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2490 OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2491
2492 tmp2 = INREG(FP_GEN_CNTL);
2493 tmp = INREG(TMDS_TRANSMITTER_CNTL);
2494 OUTREG(0x2a8, 0x0000061b);
2495 tmp |= TMDS_PLL_EN;
2496 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2497 mdelay(1);
2498 tmp &= ~TMDS_PLLRST;
2499 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2500 tmp2 &= ~2;
2501 tmp2 |= FP_TMDS_EN;
2502 OUTREG(FP_GEN_CNTL, tmp2);
2503 mdelay(5);
2504 tmp2 |= FP_FPON;
2505 OUTREG(FP_GEN_CNTL, tmp2);
2506
2507 OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2508 cgc = INREG(CRTC_GEN_CNTL);
2509 OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2510 cgc |= 0x10000;
2511 OUTREG(CUR_OFFSET, 0);
2512 }
2513 #endif /* 0 */
2514
2515 #endif /* CONFIG_PPC_OF */
2516
2517 static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state)
2518 {
2519 u16 pwr_cmd;
2520
2521 for (;;) {
2522 pci_read_config_word(rinfo->pdev,
2523 rinfo->pdev->pm_cap + PCI_PM_CTRL,
2524 &pwr_cmd);
2525 if (pwr_cmd & state)
2526 break;
2527 pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | state;
2528 pci_write_config_word(rinfo->pdev,
2529 rinfo->pdev->pm_cap + PCI_PM_CTRL,
2530 pwr_cmd);
2531 msleep(500);
2532 }
2533 rinfo->pdev->current_state = state;
2534 }
2535
2536 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2537 {
2538 u32 tmp;
2539
2540 if (!rinfo->pdev->pm_cap)
2541 return;
2542
2543 /* Set the chip into appropriate suspend mode (we use D2,
2544 * D3 would require a compete re-initialization of the chip,
2545 * including PCI config registers, clocks, AGP conf, ...)
2546 */
2547 if (suspend) {
2548 printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2549 pci_name(rinfo->pdev));
2550
2551 /* Disable dynamic power management of clocks for the
2552 * duration of the suspend/resume process
2553 */
2554 radeon_pm_disable_dynamic_mode(rinfo);
2555
2556 /* Save some registers */
2557 radeon_pm_save_regs(rinfo, 0);
2558
2559 /* Prepare mobility chips for suspend.
2560 */
2561 if (rinfo->is_mobility) {
2562 /* Program V2CLK */
2563 radeon_pm_program_v2clk(rinfo);
2564
2565 /* Disable IO PADs */
2566 radeon_pm_disable_iopad(rinfo);
2567
2568 /* Set low current */
2569 radeon_pm_low_current(rinfo);
2570
2571 /* Prepare chip for power management */
2572 radeon_pm_setup_for_suspend(rinfo);
2573
2574 if (rinfo->family <= CHIP_FAMILY_RV280) {
2575 /* Reset the MDLL */
2576 /* because both INPLL and OUTPLL take the same
2577 * lock, that's why. */
2578 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2579 | MDLL_CKO__MCKOB_RESET;
2580 OUTPLL( pllMDLL_CKO, tmp );
2581 }
2582 }
2583
2584 /* Switch PCI power management to D2. */
2585 pci_disable_device(rinfo->pdev);
2586 pci_save_state(rinfo->pdev);
2587 /* The chip seems to need us to whack the PM register
2588 * repeatedly until it sticks. We do that -prior- to
2589 * calling pci_set_power_state()
2590 */
2591 radeonfb_whack_power_state(rinfo, PCI_D2);
2592 __pci_complete_power_transition(rinfo->pdev, PCI_D2);
2593 } else {
2594 printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2595 pci_name(rinfo->pdev));
2596
2597 if (rinfo->family <= CHIP_FAMILY_RV250) {
2598 /* Reset the SDRAM controller */
2599 radeon_pm_full_reset_sdram(rinfo);
2600
2601 /* Restore some registers */
2602 radeon_pm_restore_regs(rinfo);
2603 } else {
2604 /* Restore registers first */
2605 radeon_pm_restore_regs(rinfo);
2606 /* init sdram controller */
2607 radeon_pm_full_reset_sdram(rinfo);
2608 }
2609 }
2610 }
2611
2612 int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
2613 {
2614 struct fb_info *info = pci_get_drvdata(pdev);
2615 struct radeonfb_info *rinfo = info->par;
2616
2617 if (mesg.event == pdev->dev.power.power_state.event)
2618 return 0;
2619
2620 printk(KERN_DEBUG "radeonfb (%s): suspending for event: %d...\n",
2621 pci_name(pdev), mesg.event);
2622
2623 /* For suspend-to-disk, we cheat here. We don't suspend anything and
2624 * let fbcon continue drawing until we are all set. That shouldn't
2625 * really cause any problem at this point, provided that the wakeup
2626 * code knows that any state in memory may not match the HW
2627 */
2628 switch (mesg.event) {
2629 case PM_EVENT_FREEZE: /* about to take snapshot */
2630 case PM_EVENT_PRETHAW: /* before restoring snapshot */
2631 goto done;
2632 }
2633
2634 console_lock();
2635
2636 fb_set_suspend(info, 1);
2637
2638 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2639 /* Make sure engine is reset */
2640 radeon_engine_idle();
2641 radeonfb_engine_reset(rinfo);
2642 radeon_engine_idle();
2643 }
2644
2645 /* Blank display and LCD */
2646 radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2647
2648 /* Sleep */
2649 rinfo->asleep = 1;
2650 rinfo->lock_blank = 1;
2651 del_timer_sync(&rinfo->lvds_timer);
2652
2653 #ifdef CONFIG_PPC_PMAC
2654 /* On powermac, we have hooks to properly suspend/resume AGP now,
2655 * use them here. We'll ultimately need some generic support here,
2656 * but the generic code isn't quite ready for that yet
2657 */
2658 pmac_suspend_agp_for_card(pdev);
2659 #endif /* CONFIG_PPC_PMAC */
2660
2661 /* It's unclear whether or when the generic code will do that, so let's
2662 * do it ourselves. We save state before we do any power management
2663 */
2664 pci_save_state(pdev);
2665
2666 /* If we support wakeup from poweroff, we save all regs we can including cfg
2667 * space
2668 */
2669 if (rinfo->pm_mode & radeon_pm_off) {
2670 /* Always disable dynamic clocks or weird things are happening when
2671 * the chip goes off (basically the panel doesn't shut down properly
2672 * and we crash on wakeup),
2673 * also, we want the saved regs context to have no dynamic clocks in
2674 * it, we'll restore the dynamic clocks state on wakeup
2675 */
2676 radeon_pm_disable_dynamic_mode(rinfo);
2677 mdelay(50);
2678 radeon_pm_save_regs(rinfo, 1);
2679
2680 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2681 /* Switch off LVDS interface */
2682 mdelay(1);
2683 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2684 mdelay(1);
2685 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2686 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2687 mdelay(20);
2688 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2689 }
2690 pci_disable_device(pdev);
2691 }
2692 /* If we support D2, we go to it (should be fixed later with a flag forcing
2693 * D3 only for some laptops)
2694 */
2695 if (rinfo->pm_mode & radeon_pm_d2)
2696 radeon_set_suspend(rinfo, 1);
2697
2698 console_unlock();
2699
2700 done:
2701 pdev->dev.power.power_state = mesg;
2702
2703 return 0;
2704 }
2705
2706 static int radeon_check_power_loss(struct radeonfb_info *rinfo)
2707 {
2708 return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) ||
2709 rinfo->save_regs[2] != INPLL(MCLK_CNTL) ||
2710 rinfo->save_regs[3] != INPLL(SCLK_CNTL);
2711 }
2712
2713 int radeonfb_pci_resume(struct pci_dev *pdev)
2714 {
2715 struct fb_info *info = pci_get_drvdata(pdev);
2716 struct radeonfb_info *rinfo = info->par;
2717 int rc = 0;
2718
2719 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2720 return 0;
2721
2722 if (rinfo->no_schedule) {
2723 if (!console_trylock())
2724 return 0;
2725 } else
2726 console_lock();
2727
2728 printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2729 pci_name(pdev), pdev->dev.power.power_state.event);
2730
2731 /* PCI state will have been restored by the core, so
2732 * we should be in D0 now with our config space fully
2733 * restored
2734 */
2735 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2736 /* Wakeup chip */
2737 if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) {
2738 if (rinfo->reinit_func != NULL)
2739 rinfo->reinit_func(rinfo);
2740 else {
2741 printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2742 " D3 cold, need softboot !", pci_name(pdev));
2743 rc = -EIO;
2744 goto bail;
2745 }
2746 }
2747 /* If we support D2, try to resume... we should check what was our
2748 * state though... (were we really in D2 state ?). Right now, this code
2749 * is only enable on Macs so it's fine.
2750 */
2751 else if (rinfo->pm_mode & radeon_pm_d2)
2752 radeon_set_suspend(rinfo, 0);
2753
2754 rinfo->asleep = 0;
2755 } else
2756 radeon_engine_idle();
2757
2758 /* Restore display & engine */
2759 radeon_write_mode (rinfo, &rinfo->state, 1);
2760 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2761 radeonfb_engine_init (rinfo);
2762
2763 fb_pan_display(info, &info->var);
2764 fb_set_cmap(&info->cmap, info);
2765
2766 /* Refresh */
2767 fb_set_suspend(info, 0);
2768
2769 /* Unblank */
2770 rinfo->lock_blank = 0;
2771 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2772
2773 #ifdef CONFIG_PPC_PMAC
2774 /* On powermac, we have hooks to properly suspend/resume AGP now,
2775 * use them here. We'll ultimately need some generic support here,
2776 * but the generic code isn't quite ready for that yet
2777 */
2778 pmac_resume_agp_for_card(pdev);
2779 #endif /* CONFIG_PPC_PMAC */
2780
2781
2782 /* Check status of dynclk */
2783 if (rinfo->dynclk == 1)
2784 radeon_pm_enable_dynamic_mode(rinfo);
2785 else if (rinfo->dynclk == 0)
2786 radeon_pm_disable_dynamic_mode(rinfo);
2787
2788 pdev->dev.power.power_state = PMSG_ON;
2789
2790 bail:
2791 console_unlock();
2792
2793 return rc;
2794 }
2795
2796 #ifdef CONFIG_PPC_OF__disabled
2797 static void radeonfb_early_resume(void *data)
2798 {
2799 struct radeonfb_info *rinfo = data;
2800
2801 rinfo->no_schedule = 1;
2802 pci_restore_state(rinfo->pdev);
2803 radeonfb_pci_resume(rinfo->pdev);
2804 rinfo->no_schedule = 0;
2805 }
2806 #endif /* CONFIG_PPC_OF */
2807
2808 #endif /* CONFIG_PM */
2809
2810 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep)
2811 {
2812 /* Enable/Disable dynamic clocks: TODO add sysfs access */
2813 if (rinfo->family == CHIP_FAMILY_RS480)
2814 rinfo->dynclk = -1;
2815 else
2816 rinfo->dynclk = dynclk;
2817
2818 if (rinfo->dynclk == 1) {
2819 radeon_pm_enable_dynamic_mode(rinfo);
2820 printk("radeonfb: Dynamic Clock Power Management enabled\n");
2821 } else if (rinfo->dynclk == 0) {
2822 radeon_pm_disable_dynamic_mode(rinfo);
2823 printk("radeonfb: Dynamic Clock Power Management disabled\n");
2824 }
2825
2826 #if defined(CONFIG_PM)
2827 #if defined(CONFIG_PPC_PMAC)
2828 /* Check if we can power manage on suspend/resume. We can do
2829 * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2830 * "Mac" cards, but that's all. We need more infos about what the
2831 * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2832 * reason. --BenH
2833 */
2834 if (machine_is(powermac) && rinfo->of_node) {
2835 if (rinfo->is_mobility && rinfo->pdev->pm_cap &&
2836 rinfo->family <= CHIP_FAMILY_RV250)
2837 rinfo->pm_mode |= radeon_pm_d2;
2838
2839 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2840 * in some desktop G4s), Via (M9+ chip on iBook G4) and
2841 * Snowy (M11 chip on iBook G4 manufactured after July 2005)
2842 */
2843 if (!strcmp(rinfo->of_node->name, "ATY,JasperParent") ||
2844 !strcmp(rinfo->of_node->name, "ATY,SnowyParent")) {
2845 rinfo->reinit_func = radeon_reinitialize_M10;
2846 rinfo->pm_mode |= radeon_pm_off;
2847 }
2848 #if 0 /* Not ready yet */
2849 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2850 rinfo->reinit_func = radeon_reinitialize_QW;
2851 rinfo->pm_mode |= radeon_pm_off;
2852 }
2853 #endif
2854 if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
2855 rinfo->reinit_func = radeon_reinitialize_M9P;
2856 rinfo->pm_mode |= radeon_pm_off;
2857 }
2858
2859 /* If any of the above is set, we assume the machine can sleep/resume.
2860 * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2861 * from the platform about what happens to the chip...
2862 * Now we tell the platform about our capability
2863 */
2864 if (rinfo->pm_mode != radeon_pm_none) {
2865 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2866 #if 0 /* Disable the early video resume hack for now as it's causing problems, among
2867 * others we now rely on the PCI core restoring the config space for us, which
2868 * isn't the case with that hack, and that code path causes various things to
2869 * be called with interrupts off while they shouldn't. I'm leaving the code in
2870 * as it can be useful for debugging purposes
2871 */
2872 pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2873 #endif
2874 }
2875
2876 #if 0
2877 /* Power down TV DAC, that saves a significant amount of power,
2878 * we'll have something better once we actually have some TVOut
2879 * support
2880 */
2881 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2882 #endif
2883 }
2884 #endif /* defined(CONFIG_PPC_PMAC) */
2885 #endif /* defined(CONFIG_PM) */
2886
2887 if (ignore_devlist)
2888 printk(KERN_DEBUG
2889 "radeonfb: skipping test for device workarounds\n");
2890 else
2891 radeon_apply_workarounds(rinfo);
2892
2893 if (force_sleep) {
2894 printk(KERN_DEBUG
2895 "radeonfb: forcefully enabling D2 sleep mode\n");
2896 rinfo->pm_mode |= radeon_pm_d2;
2897 }
2898 }
2899
2900 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2901 {
2902 #if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC)
2903 if (rinfo->pm_mode != radeon_pm_none)
2904 pmac_set_early_video_resume(NULL, NULL);
2905 #endif
2906 }
Linux kernel - Deliverables
This page took 0.093105 seconds and 5 git commands to generate.